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Commit | Line | Data |
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8977f3c1 | 1 | /* |
890fa6be | 2 | * QEMU Floppy disk emulator (Intel 82078) |
5fafdf24 | 3 | * |
3ccacc4a | 4 | * Copyright (c) 2003, 2007 Jocelyn Mayer |
bcc4e41f | 5 | * Copyright (c) 2008 Hervé Poussineau |
5fafdf24 | 6 | * |
8977f3c1 FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
e80cfcfc FB |
25 | /* |
26 | * The controller is used in Sun4m systems in a slightly different | |
27 | * way. There are changes in DOR register and DMA is not available. | |
28 | */ | |
f64ab228 | 29 | |
80c71a24 | 30 | #include "qemu/osdep.h" |
83c9f4ca | 31 | #include "hw/hw.h" |
0d09e41a | 32 | #include "hw/block/fdc.h" |
1de7afc9 PB |
33 | #include "qemu/error-report.h" |
34 | #include "qemu/timer.h" | |
0d09e41a | 35 | #include "hw/isa/isa.h" |
83c9f4ca | 36 | #include "hw/sysbus.h" |
fa1d36df | 37 | #include "sysemu/block-backend.h" |
9c17d615 PB |
38 | #include "sysemu/blockdev.h" |
39 | #include "sysemu/sysemu.h" | |
1de7afc9 | 40 | #include "qemu/log.h" |
8977f3c1 FB |
41 | |
42 | /********************************************************/ | |
43 | /* debug Floppy devices */ | |
44 | //#define DEBUG_FLOPPY | |
45 | ||
46 | #ifdef DEBUG_FLOPPY | |
001faf32 BS |
47 | #define FLOPPY_DPRINTF(fmt, ...) \ |
48 | do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0) | |
8977f3c1 | 49 | #else |
001faf32 | 50 | #define FLOPPY_DPRINTF(fmt, ...) |
8977f3c1 FB |
51 | #endif |
52 | ||
8977f3c1 FB |
53 | /********************************************************/ |
54 | /* Floppy drive emulation */ | |
55 | ||
61a8d649 MA |
56 | typedef enum FDriveRate { |
57 | FDRIVE_RATE_500K = 0x00, /* 500 Kbps */ | |
58 | FDRIVE_RATE_300K = 0x01, /* 300 Kbps */ | |
59 | FDRIVE_RATE_250K = 0x02, /* 250 Kbps */ | |
60 | FDRIVE_RATE_1M = 0x03, /* 1 Mbps */ | |
61 | } FDriveRate; | |
62 | ||
63 | typedef struct FDFormat { | |
2da44dd0 | 64 | FloppyDriveType drive; |
61a8d649 MA |
65 | uint8_t last_sect; |
66 | uint8_t max_track; | |
67 | uint8_t max_head; | |
68 | FDriveRate rate; | |
69 | } FDFormat; | |
70 | ||
71 | static const FDFormat fd_formats[] = { | |
72 | /* First entry is default format */ | |
73 | /* 1.44 MB 3"1/2 floppy disks */ | |
2da44dd0 JS |
74 | { FLOPPY_DRIVE_TYPE_144, 18, 80, 1, FDRIVE_RATE_500K, }, |
75 | { FLOPPY_DRIVE_TYPE_144, 20, 80, 1, FDRIVE_RATE_500K, }, | |
76 | { FLOPPY_DRIVE_TYPE_144, 21, 80, 1, FDRIVE_RATE_500K, }, | |
77 | { FLOPPY_DRIVE_TYPE_144, 21, 82, 1, FDRIVE_RATE_500K, }, | |
78 | { FLOPPY_DRIVE_TYPE_144, 21, 83, 1, FDRIVE_RATE_500K, }, | |
79 | { FLOPPY_DRIVE_TYPE_144, 22, 80, 1, FDRIVE_RATE_500K, }, | |
80 | { FLOPPY_DRIVE_TYPE_144, 23, 80, 1, FDRIVE_RATE_500K, }, | |
81 | { FLOPPY_DRIVE_TYPE_144, 24, 80, 1, FDRIVE_RATE_500K, }, | |
61a8d649 | 82 | /* 2.88 MB 3"1/2 floppy disks */ |
2da44dd0 JS |
83 | { FLOPPY_DRIVE_TYPE_288, 36, 80, 1, FDRIVE_RATE_1M, }, |
84 | { FLOPPY_DRIVE_TYPE_288, 39, 80, 1, FDRIVE_RATE_1M, }, | |
85 | { FLOPPY_DRIVE_TYPE_288, 40, 80, 1, FDRIVE_RATE_1M, }, | |
86 | { FLOPPY_DRIVE_TYPE_288, 44, 80, 1, FDRIVE_RATE_1M, }, | |
87 | { FLOPPY_DRIVE_TYPE_288, 48, 80, 1, FDRIVE_RATE_1M, }, | |
61a8d649 | 88 | /* 720 kB 3"1/2 floppy disks */ |
2da44dd0 JS |
89 | { FLOPPY_DRIVE_TYPE_144, 9, 80, 1, FDRIVE_RATE_250K, }, |
90 | { FLOPPY_DRIVE_TYPE_144, 10, 80, 1, FDRIVE_RATE_250K, }, | |
91 | { FLOPPY_DRIVE_TYPE_144, 10, 82, 1, FDRIVE_RATE_250K, }, | |
92 | { FLOPPY_DRIVE_TYPE_144, 10, 83, 1, FDRIVE_RATE_250K, }, | |
93 | { FLOPPY_DRIVE_TYPE_144, 13, 80, 1, FDRIVE_RATE_250K, }, | |
94 | { FLOPPY_DRIVE_TYPE_144, 14, 80, 1, FDRIVE_RATE_250K, }, | |
61a8d649 | 95 | /* 1.2 MB 5"1/4 floppy disks */ |
2da44dd0 JS |
96 | { FLOPPY_DRIVE_TYPE_120, 15, 80, 1, FDRIVE_RATE_500K, }, |
97 | { FLOPPY_DRIVE_TYPE_120, 18, 80, 1, FDRIVE_RATE_500K, }, | |
98 | { FLOPPY_DRIVE_TYPE_120, 18, 82, 1, FDRIVE_RATE_500K, }, | |
99 | { FLOPPY_DRIVE_TYPE_120, 18, 83, 1, FDRIVE_RATE_500K, }, | |
100 | { FLOPPY_DRIVE_TYPE_120, 20, 80, 1, FDRIVE_RATE_500K, }, | |
61a8d649 | 101 | /* 720 kB 5"1/4 floppy disks */ |
2da44dd0 JS |
102 | { FLOPPY_DRIVE_TYPE_120, 9, 80, 1, FDRIVE_RATE_250K, }, |
103 | { FLOPPY_DRIVE_TYPE_120, 11, 80, 1, FDRIVE_RATE_250K, }, | |
61a8d649 | 104 | /* 360 kB 5"1/4 floppy disks */ |
2da44dd0 JS |
105 | { FLOPPY_DRIVE_TYPE_120, 9, 40, 1, FDRIVE_RATE_300K, }, |
106 | { FLOPPY_DRIVE_TYPE_120, 9, 40, 0, FDRIVE_RATE_300K, }, | |
107 | { FLOPPY_DRIVE_TYPE_120, 10, 41, 1, FDRIVE_RATE_300K, }, | |
108 | { FLOPPY_DRIVE_TYPE_120, 10, 42, 1, FDRIVE_RATE_300K, }, | |
61a8d649 | 109 | /* 320 kB 5"1/4 floppy disks */ |
2da44dd0 JS |
110 | { FLOPPY_DRIVE_TYPE_120, 8, 40, 1, FDRIVE_RATE_250K, }, |
111 | { FLOPPY_DRIVE_TYPE_120, 8, 40, 0, FDRIVE_RATE_250K, }, | |
61a8d649 | 112 | /* 360 kB must match 5"1/4 better than 3"1/2... */ |
2da44dd0 | 113 | { FLOPPY_DRIVE_TYPE_144, 9, 80, 0, FDRIVE_RATE_250K, }, |
61a8d649 | 114 | /* end */ |
2da44dd0 | 115 | { FLOPPY_DRIVE_TYPE_NONE, -1, -1, 0, 0, }, |
61a8d649 MA |
116 | }; |
117 | ||
cefec4f5 BS |
118 | #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv) |
119 | #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive)) | |
120 | ||
8977f3c1 | 121 | /* Will always be a fixed parameter for us */ |
f2d81b33 BS |
122 | #define FD_SECTOR_LEN 512 |
123 | #define FD_SECTOR_SC 2 /* Sector size code */ | |
124 | #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */ | |
8977f3c1 | 125 | |
844f65d6 HP |
126 | typedef struct FDCtrl FDCtrl; |
127 | ||
8977f3c1 | 128 | /* Floppy disk drive emulation */ |
5c02c033 | 129 | typedef enum FDiskFlags { |
baca51fa | 130 | FDISK_DBL_SIDES = 0x01, |
5c02c033 | 131 | } FDiskFlags; |
baca51fa | 132 | |
5c02c033 | 133 | typedef struct FDrive { |
844f65d6 | 134 | FDCtrl *fdctrl; |
4be74634 | 135 | BlockBackend *blk; |
8977f3c1 | 136 | /* Drive status */ |
2da44dd0 | 137 | FloppyDriveType drive; /* CMOS drive type */ |
8977f3c1 | 138 | uint8_t perpendicular; /* 2.88 MB access mode */ |
8977f3c1 FB |
139 | /* Position */ |
140 | uint8_t head; | |
141 | uint8_t track; | |
142 | uint8_t sect; | |
8977f3c1 | 143 | /* Media */ |
16c1e3ec | 144 | FloppyDriveType disk; /* Current disk type */ |
5c02c033 | 145 | FDiskFlags flags; |
8977f3c1 FB |
146 | uint8_t last_sect; /* Nb sector per track */ |
147 | uint8_t max_track; /* Nb of tracks */ | |
baca51fa | 148 | uint16_t bps; /* Bytes per sector */ |
8977f3c1 | 149 | uint8_t ro; /* Is read-only */ |
7d905f71 | 150 | uint8_t media_changed; /* Is media changed */ |
844f65d6 | 151 | uint8_t media_rate; /* Data rate of medium */ |
2e1280e8 HR |
152 | |
153 | bool media_inserted; /* Is there a medium in the tray */ | |
5c02c033 | 154 | } FDrive; |
8977f3c1 | 155 | |
5c02c033 | 156 | static void fd_init(FDrive *drv) |
8977f3c1 FB |
157 | { |
158 | /* Drive */ | |
2da44dd0 | 159 | drv->drive = FLOPPY_DRIVE_TYPE_NONE; |
8977f3c1 | 160 | drv->perpendicular = 0; |
8977f3c1 | 161 | /* Disk */ |
16c1e3ec | 162 | drv->disk = FLOPPY_DRIVE_TYPE_NONE; |
baca51fa | 163 | drv->last_sect = 0; |
8977f3c1 FB |
164 | drv->max_track = 0; |
165 | } | |
166 | ||
08388273 HP |
167 | #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1) |
168 | ||
7859cb98 | 169 | static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect, |
08388273 | 170 | uint8_t last_sect, uint8_t num_sides) |
8977f3c1 | 171 | { |
08388273 | 172 | return (((track * num_sides) + head) * last_sect) + sect - 1; |
8977f3c1 FB |
173 | } |
174 | ||
175 | /* Returns current position, in sectors, for given drive */ | |
5c02c033 | 176 | static int fd_sector(FDrive *drv) |
8977f3c1 | 177 | { |
08388273 HP |
178 | return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect, |
179 | NUM_SIDES(drv)); | |
8977f3c1 FB |
180 | } |
181 | ||
77370520 BS |
182 | /* Seek to a new position: |
183 | * returns 0 if already on right track | |
184 | * returns 1 if track changed | |
185 | * returns 2 if track is invalid | |
186 | * returns 3 if sector is invalid | |
187 | * returns 4 if seek is disabled | |
188 | */ | |
5c02c033 BS |
189 | static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect, |
190 | int enable_seek) | |
8977f3c1 FB |
191 | { |
192 | uint32_t sector; | |
baca51fa FB |
193 | int ret; |
194 | ||
195 | if (track > drv->max_track || | |
4f431960 | 196 | (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) { |
ed5fd2cc FB |
197 | FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n", |
198 | head, track, sect, 1, | |
199 | (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, | |
200 | drv->max_track, drv->last_sect); | |
8977f3c1 FB |
201 | return 2; |
202 | } | |
203 | if (sect > drv->last_sect) { | |
ed5fd2cc FB |
204 | FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n", |
205 | head, track, sect, 1, | |
206 | (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, | |
207 | drv->max_track, drv->last_sect); | |
8977f3c1 FB |
208 | return 3; |
209 | } | |
08388273 | 210 | sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv)); |
baca51fa | 211 | ret = 0; |
8977f3c1 FB |
212 | if (sector != fd_sector(drv)) { |
213 | #if 0 | |
214 | if (!enable_seek) { | |
cced7a13 BS |
215 | FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x" |
216 | " (max=%d %02x %02x)\n", | |
217 | head, track, sect, 1, drv->max_track, | |
218 | drv->last_sect); | |
8977f3c1 FB |
219 | return 4; |
220 | } | |
221 | #endif | |
222 | drv->head = head; | |
6be01b1e | 223 | if (drv->track != track) { |
2e1280e8 | 224 | if (drv->media_inserted) { |
6be01b1e PH |
225 | drv->media_changed = 0; |
226 | } | |
4f431960 | 227 | ret = 1; |
6be01b1e | 228 | } |
8977f3c1 FB |
229 | drv->track = track; |
230 | drv->sect = sect; | |
8977f3c1 FB |
231 | } |
232 | ||
2e1280e8 | 233 | if (!drv->media_inserted) { |
c52acf60 PH |
234 | ret = 2; |
235 | } | |
236 | ||
baca51fa | 237 | return ret; |
8977f3c1 FB |
238 | } |
239 | ||
240 | /* Set drive back to track 0 */ | |
5c02c033 | 241 | static void fd_recalibrate(FDrive *drv) |
8977f3c1 FB |
242 | { |
243 | FLOPPY_DPRINTF("recalibrate\n"); | |
6be01b1e | 244 | fd_seek(drv, 0, 0, 1, 1); |
8977f3c1 FB |
245 | } |
246 | ||
21862658 | 247 | static void pick_geometry(FDrive *drv) |
9a972233 | 248 | { |
21862658 | 249 | BlockBackend *blk = drv->blk; |
9a972233 JS |
250 | const FDFormat *parse; |
251 | uint64_t nb_sectors, size; | |
252 | int i, first_match, match; | |
253 | ||
254 | blk_get_geometry(blk, &nb_sectors); | |
255 | match = -1; | |
256 | first_match = -1; | |
257 | for (i = 0; ; i++) { | |
258 | parse = &fd_formats[i]; | |
2da44dd0 | 259 | if (parse->drive == FLOPPY_DRIVE_TYPE_NONE) { |
9a972233 JS |
260 | break; |
261 | } | |
21862658 | 262 | if (drv->drive == parse->drive || |
2da44dd0 | 263 | drv->drive == FLOPPY_DRIVE_TYPE_NONE) { |
9a972233 JS |
264 | size = (parse->max_head + 1) * parse->max_track * |
265 | parse->last_sect; | |
266 | if (nb_sectors == size) { | |
267 | match = i; | |
268 | break; | |
269 | } | |
270 | if (first_match == -1) { | |
271 | first_match = i; | |
272 | } | |
273 | } | |
274 | } | |
275 | if (match == -1) { | |
276 | if (first_match == -1) { | |
69ce1ac2 JS |
277 | error_setg(&error_abort, "No candidate geometries present in table " |
278 | " for floppy drive type '%s'", | |
279 | FloppyDriveType_lookup[drv->drive]); | |
9a972233 JS |
280 | } else { |
281 | match = first_match; | |
282 | } | |
283 | parse = &fd_formats[match]; | |
284 | } | |
21862658 JS |
285 | |
286 | if (parse->max_head == 0) { | |
287 | drv->flags &= ~FDISK_DBL_SIDES; | |
288 | } else { | |
289 | drv->flags |= FDISK_DBL_SIDES; | |
290 | } | |
291 | drv->max_track = parse->max_track; | |
292 | drv->last_sect = parse->last_sect; | |
293 | drv->drive = parse->drive; | |
16c1e3ec | 294 | drv->disk = drv->media_inserted ? parse->drive : FLOPPY_DRIVE_TYPE_NONE; |
21862658 | 295 | drv->media_rate = parse->rate; |
9a972233 JS |
296 | } |
297 | ||
8977f3c1 | 298 | /* Revalidate a disk drive after a disk change */ |
5c02c033 | 299 | static void fd_revalidate(FDrive *drv) |
8977f3c1 | 300 | { |
8977f3c1 | 301 | FLOPPY_DPRINTF("revalidate\n"); |
4be74634 | 302 | if (drv->blk != NULL) { |
21862658 JS |
303 | drv->ro = blk_is_read_only(drv->blk); |
304 | pick_geometry(drv); | |
2e1280e8 | 305 | if (!drv->media_inserted) { |
cfb08fba | 306 | FLOPPY_DPRINTF("No disk in drive\n"); |
4f431960 | 307 | } else { |
21862658 JS |
308 | FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", |
309 | (drv->flags & FDISK_DBL_SIDES) ? 2 : 1, | |
310 | drv->max_track, drv->last_sect, | |
311 | drv->ro ? "ro" : "rw"); | |
4f431960 | 312 | } |
8977f3c1 | 313 | } else { |
cfb08fba | 314 | FLOPPY_DPRINTF("No drive connected\n"); |
baca51fa | 315 | drv->last_sect = 0; |
4f431960 JM |
316 | drv->max_track = 0; |
317 | drv->flags &= ~FDISK_DBL_SIDES; | |
8977f3c1 | 318 | } |
caed8802 FB |
319 | } |
320 | ||
8977f3c1 | 321 | /********************************************************/ |
4b19ec0c | 322 | /* Intel 82078 floppy disk controller emulation */ |
8977f3c1 | 323 | |
5c02c033 | 324 | static void fdctrl_reset(FDCtrl *fdctrl, int do_irq); |
07e415f2 | 325 | static void fdctrl_to_command_phase(FDCtrl *fdctrl); |
85571bc7 | 326 | static int fdctrl_transfer_handler (void *opaque, int nchan, |
c227f099 | 327 | int dma_pos, int dma_len); |
d497d534 | 328 | static void fdctrl_raise_irq(FDCtrl *fdctrl); |
a2df5fa3 | 329 | static FDrive *get_cur_drv(FDCtrl *fdctrl); |
5c02c033 BS |
330 | |
331 | static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl); | |
332 | static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl); | |
333 | static uint32_t fdctrl_read_dor(FDCtrl *fdctrl); | |
334 | static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value); | |
335 | static uint32_t fdctrl_read_tape(FDCtrl *fdctrl); | |
336 | static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value); | |
337 | static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl); | |
338 | static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value); | |
339 | static uint32_t fdctrl_read_data(FDCtrl *fdctrl); | |
340 | static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value); | |
341 | static uint32_t fdctrl_read_dir(FDCtrl *fdctrl); | |
a758f8f4 | 342 | static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value); |
8977f3c1 | 343 | |
8977f3c1 FB |
344 | enum { |
345 | FD_DIR_WRITE = 0, | |
346 | FD_DIR_READ = 1, | |
347 | FD_DIR_SCANE = 2, | |
348 | FD_DIR_SCANL = 3, | |
349 | FD_DIR_SCANH = 4, | |
7ea004ed | 350 | FD_DIR_VERIFY = 5, |
8977f3c1 FB |
351 | }; |
352 | ||
353 | enum { | |
b9b3d225 BS |
354 | FD_STATE_MULTI = 0x01, /* multi track flag */ |
355 | FD_STATE_FORMAT = 0x02, /* format flag */ | |
8977f3c1 FB |
356 | }; |
357 | ||
9fea808a | 358 | enum { |
8c6a4d77 BS |
359 | FD_REG_SRA = 0x00, |
360 | FD_REG_SRB = 0x01, | |
9fea808a BS |
361 | FD_REG_DOR = 0x02, |
362 | FD_REG_TDR = 0x03, | |
363 | FD_REG_MSR = 0x04, | |
364 | FD_REG_DSR = 0x04, | |
365 | FD_REG_FIFO = 0x05, | |
366 | FD_REG_DIR = 0x07, | |
a758f8f4 | 367 | FD_REG_CCR = 0x07, |
9fea808a BS |
368 | }; |
369 | ||
370 | enum { | |
65cef780 | 371 | FD_CMD_READ_TRACK = 0x02, |
9fea808a BS |
372 | FD_CMD_SPECIFY = 0x03, |
373 | FD_CMD_SENSE_DRIVE_STATUS = 0x04, | |
65cef780 BS |
374 | FD_CMD_WRITE = 0x05, |
375 | FD_CMD_READ = 0x06, | |
9fea808a BS |
376 | FD_CMD_RECALIBRATE = 0x07, |
377 | FD_CMD_SENSE_INTERRUPT_STATUS = 0x08, | |
65cef780 BS |
378 | FD_CMD_WRITE_DELETED = 0x09, |
379 | FD_CMD_READ_ID = 0x0a, | |
380 | FD_CMD_READ_DELETED = 0x0c, | |
381 | FD_CMD_FORMAT_TRACK = 0x0d, | |
9fea808a BS |
382 | FD_CMD_DUMPREG = 0x0e, |
383 | FD_CMD_SEEK = 0x0f, | |
384 | FD_CMD_VERSION = 0x10, | |
65cef780 | 385 | FD_CMD_SCAN_EQUAL = 0x11, |
9fea808a BS |
386 | FD_CMD_PERPENDICULAR_MODE = 0x12, |
387 | FD_CMD_CONFIGURE = 0x13, | |
65cef780 BS |
388 | FD_CMD_LOCK = 0x14, |
389 | FD_CMD_VERIFY = 0x16, | |
9fea808a BS |
390 | FD_CMD_POWERDOWN_MODE = 0x17, |
391 | FD_CMD_PART_ID = 0x18, | |
65cef780 BS |
392 | FD_CMD_SCAN_LOW_OR_EQUAL = 0x19, |
393 | FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d, | |
bb350a5e | 394 | FD_CMD_SAVE = 0x2e, |
9fea808a | 395 | FD_CMD_OPTION = 0x33, |
bb350a5e | 396 | FD_CMD_RESTORE = 0x4e, |
9fea808a BS |
397 | FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e, |
398 | FD_CMD_RELATIVE_SEEK_OUT = 0x8f, | |
9fea808a BS |
399 | FD_CMD_FORMAT_AND_WRITE = 0xcd, |
400 | FD_CMD_RELATIVE_SEEK_IN = 0xcf, | |
401 | }; | |
402 | ||
403 | enum { | |
404 | FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */ | |
405 | FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */ | |
406 | FD_CONFIG_POLL = 0x10, /* Poll enabled */ | |
407 | FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */ | |
408 | FD_CONFIG_EIS = 0x40, /* No implied seeks */ | |
409 | }; | |
410 | ||
411 | enum { | |
2fee0088 PH |
412 | FD_SR0_DS0 = 0x01, |
413 | FD_SR0_DS1 = 0x02, | |
414 | FD_SR0_HEAD = 0x04, | |
9fea808a BS |
415 | FD_SR0_EQPMT = 0x10, |
416 | FD_SR0_SEEK = 0x20, | |
417 | FD_SR0_ABNTERM = 0x40, | |
418 | FD_SR0_INVCMD = 0x80, | |
419 | FD_SR0_RDYCHG = 0xc0, | |
420 | }; | |
421 | ||
77370520 | 422 | enum { |
844f65d6 | 423 | FD_SR1_MA = 0x01, /* Missing address mark */ |
8510854e | 424 | FD_SR1_NW = 0x02, /* Not writable */ |
77370520 BS |
425 | FD_SR1_EC = 0x80, /* End of cylinder */ |
426 | }; | |
427 | ||
428 | enum { | |
429 | FD_SR2_SNS = 0x04, /* Scan not satisfied */ | |
430 | FD_SR2_SEH = 0x08, /* Scan equal hit */ | |
431 | }; | |
432 | ||
8c6a4d77 BS |
433 | enum { |
434 | FD_SRA_DIR = 0x01, | |
435 | FD_SRA_nWP = 0x02, | |
436 | FD_SRA_nINDX = 0x04, | |
437 | FD_SRA_HDSEL = 0x08, | |
438 | FD_SRA_nTRK0 = 0x10, | |
439 | FD_SRA_STEP = 0x20, | |
440 | FD_SRA_nDRV2 = 0x40, | |
441 | FD_SRA_INTPEND = 0x80, | |
442 | }; | |
443 | ||
444 | enum { | |
445 | FD_SRB_MTR0 = 0x01, | |
446 | FD_SRB_MTR1 = 0x02, | |
447 | FD_SRB_WGATE = 0x04, | |
448 | FD_SRB_RDATA = 0x08, | |
449 | FD_SRB_WDATA = 0x10, | |
450 | FD_SRB_DR0 = 0x20, | |
451 | }; | |
452 | ||
9fea808a | 453 | enum { |
78ae820c BS |
454 | #if MAX_FD == 4 |
455 | FD_DOR_SELMASK = 0x03, | |
456 | #else | |
9fea808a | 457 | FD_DOR_SELMASK = 0x01, |
78ae820c | 458 | #endif |
9fea808a BS |
459 | FD_DOR_nRESET = 0x04, |
460 | FD_DOR_DMAEN = 0x08, | |
461 | FD_DOR_MOTEN0 = 0x10, | |
462 | FD_DOR_MOTEN1 = 0x20, | |
463 | FD_DOR_MOTEN2 = 0x40, | |
464 | FD_DOR_MOTEN3 = 0x80, | |
465 | }; | |
466 | ||
467 | enum { | |
78ae820c | 468 | #if MAX_FD == 4 |
9fea808a | 469 | FD_TDR_BOOTSEL = 0x0c, |
78ae820c BS |
470 | #else |
471 | FD_TDR_BOOTSEL = 0x04, | |
472 | #endif | |
9fea808a BS |
473 | }; |
474 | ||
475 | enum { | |
476 | FD_DSR_DRATEMASK= 0x03, | |
477 | FD_DSR_PWRDOWN = 0x40, | |
478 | FD_DSR_SWRESET = 0x80, | |
479 | }; | |
480 | ||
481 | enum { | |
482 | FD_MSR_DRV0BUSY = 0x01, | |
483 | FD_MSR_DRV1BUSY = 0x02, | |
484 | FD_MSR_DRV2BUSY = 0x04, | |
485 | FD_MSR_DRV3BUSY = 0x08, | |
486 | FD_MSR_CMDBUSY = 0x10, | |
487 | FD_MSR_NONDMA = 0x20, | |
488 | FD_MSR_DIO = 0x40, | |
489 | FD_MSR_RQM = 0x80, | |
490 | }; | |
491 | ||
492 | enum { | |
493 | FD_DIR_DSKCHG = 0x80, | |
494 | }; | |
495 | ||
85d291a0 KW |
496 | /* |
497 | * See chapter 5.0 "Controller phases" of the spec: | |
498 | * | |
499 | * Command phase: | |
500 | * The host writes a command and its parameters into the FIFO. The command | |
501 | * phase is completed when all parameters for the command have been supplied, | |
502 | * and execution phase is entered. | |
503 | * | |
504 | * Execution phase: | |
505 | * Data transfers, either DMA or non-DMA. For non-DMA transfers, the FIFO | |
506 | * contains the payload now, otherwise it's unused. When all bytes of the | |
507 | * required data have been transferred, the state is switched to either result | |
508 | * phase (if the command produces status bytes) or directly back into the | |
509 | * command phase for the next command. | |
510 | * | |
511 | * Result phase: | |
512 | * The host reads out the FIFO, which contains one or more result bytes now. | |
513 | */ | |
514 | enum { | |
515 | /* Only for migration: reconstruct phase from registers like qemu 2.3 */ | |
516 | FD_PHASE_RECONSTRUCT = 0, | |
517 | ||
518 | FD_PHASE_COMMAND = 1, | |
519 | FD_PHASE_EXECUTION = 2, | |
520 | FD_PHASE_RESULT = 3, | |
521 | }; | |
522 | ||
8977f3c1 | 523 | #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI) |
baca51fa | 524 | #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT) |
8977f3c1 | 525 | |
5c02c033 | 526 | struct FDCtrl { |
dc6c1b37 | 527 | MemoryRegion iomem; |
d537cf6c | 528 | qemu_irq irq; |
4b19ec0c | 529 | /* Controller state */ |
ed5fd2cc | 530 | QEMUTimer *result_timer; |
242cca4f | 531 | int dma_chann; |
85d291a0 | 532 | uint8_t phase; |
242cca4f BS |
533 | /* Controller's identification */ |
534 | uint8_t version; | |
535 | /* HW */ | |
8c6a4d77 BS |
536 | uint8_t sra; |
537 | uint8_t srb; | |
368df94d | 538 | uint8_t dor; |
d7a6c270 | 539 | uint8_t dor_vmstate; /* only used as temp during vmstate */ |
46d3233b | 540 | uint8_t tdr; |
b9b3d225 | 541 | uint8_t dsr; |
368df94d | 542 | uint8_t msr; |
8977f3c1 | 543 | uint8_t cur_drv; |
77370520 BS |
544 | uint8_t status0; |
545 | uint8_t status1; | |
546 | uint8_t status2; | |
8977f3c1 | 547 | /* Command FIFO */ |
33f00271 | 548 | uint8_t *fifo; |
d7a6c270 | 549 | int32_t fifo_size; |
8977f3c1 FB |
550 | uint32_t data_pos; |
551 | uint32_t data_len; | |
552 | uint8_t data_state; | |
553 | uint8_t data_dir; | |
890fa6be | 554 | uint8_t eot; /* last wanted sector */ |
8977f3c1 | 555 | /* States kept only to be returned back */ |
8977f3c1 FB |
556 | /* precompensation */ |
557 | uint8_t precomp_trk; | |
558 | uint8_t config; | |
559 | uint8_t lock; | |
560 | /* Power down config (also with status regB access mode */ | |
561 | uint8_t pwrd; | |
562 | /* Floppy drives */ | |
d7a6c270 | 563 | uint8_t num_floppies; |
5c02c033 | 564 | FDrive drives[MAX_FD]; |
f2d81b33 | 565 | int reset_sensei; |
09c6d585 | 566 | uint32_t check_media_rate; |
242cca4f BS |
567 | /* Timers state */ |
568 | uint8_t timer0; | |
569 | uint8_t timer1; | |
baca51fa FB |
570 | }; |
571 | ||
19d46d71 | 572 | #define TYPE_SYSBUS_FDC "base-sysbus-fdc" |
dd3be742 HT |
573 | #define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC) |
574 | ||
5c02c033 | 575 | typedef struct FDCtrlSysBus { |
dd3be742 HT |
576 | /*< private >*/ |
577 | SysBusDevice parent_obj; | |
578 | /*< public >*/ | |
579 | ||
5c02c033 BS |
580 | struct FDCtrl state; |
581 | } FDCtrlSysBus; | |
8baf73ad | 582 | |
020c8e76 AF |
583 | #define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC) |
584 | ||
5c02c033 | 585 | typedef struct FDCtrlISABus { |
020c8e76 AF |
586 | ISADevice parent_obj; |
587 | ||
c9ae703d HP |
588 | uint32_t iobase; |
589 | uint32_t irq; | |
590 | uint32_t dma; | |
5c02c033 | 591 | struct FDCtrl state; |
1ca4d09a GN |
592 | int32_t bootindexA; |
593 | int32_t bootindexB; | |
5c02c033 | 594 | } FDCtrlISABus; |
8baf73ad | 595 | |
baca51fa FB |
596 | static uint32_t fdctrl_read (void *opaque, uint32_t reg) |
597 | { | |
5c02c033 | 598 | FDCtrl *fdctrl = opaque; |
baca51fa FB |
599 | uint32_t retval; |
600 | ||
a18e67f5 | 601 | reg &= 7; |
e64d7d59 | 602 | switch (reg) { |
8c6a4d77 BS |
603 | case FD_REG_SRA: |
604 | retval = fdctrl_read_statusA(fdctrl); | |
4f431960 | 605 | break; |
8c6a4d77 | 606 | case FD_REG_SRB: |
4f431960 JM |
607 | retval = fdctrl_read_statusB(fdctrl); |
608 | break; | |
9fea808a | 609 | case FD_REG_DOR: |
4f431960 JM |
610 | retval = fdctrl_read_dor(fdctrl); |
611 | break; | |
9fea808a | 612 | case FD_REG_TDR: |
baca51fa | 613 | retval = fdctrl_read_tape(fdctrl); |
4f431960 | 614 | break; |
9fea808a | 615 | case FD_REG_MSR: |
baca51fa | 616 | retval = fdctrl_read_main_status(fdctrl); |
4f431960 | 617 | break; |
9fea808a | 618 | case FD_REG_FIFO: |
baca51fa | 619 | retval = fdctrl_read_data(fdctrl); |
4f431960 | 620 | break; |
9fea808a | 621 | case FD_REG_DIR: |
baca51fa | 622 | retval = fdctrl_read_dir(fdctrl); |
4f431960 | 623 | break; |
a541f297 | 624 | default: |
4f431960 JM |
625 | retval = (uint32_t)(-1); |
626 | break; | |
a541f297 | 627 | } |
ed5fd2cc | 628 | FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval); |
baca51fa FB |
629 | |
630 | return retval; | |
631 | } | |
632 | ||
633 | static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value) | |
634 | { | |
5c02c033 | 635 | FDCtrl *fdctrl = opaque; |
baca51fa | 636 | |
ed5fd2cc FB |
637 | FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value); |
638 | ||
a18e67f5 | 639 | reg &= 7; |
e64d7d59 | 640 | switch (reg) { |
9fea808a | 641 | case FD_REG_DOR: |
4f431960 JM |
642 | fdctrl_write_dor(fdctrl, value); |
643 | break; | |
9fea808a | 644 | case FD_REG_TDR: |
baca51fa | 645 | fdctrl_write_tape(fdctrl, value); |
4f431960 | 646 | break; |
9fea808a | 647 | case FD_REG_DSR: |
baca51fa | 648 | fdctrl_write_rate(fdctrl, value); |
4f431960 | 649 | break; |
9fea808a | 650 | case FD_REG_FIFO: |
baca51fa | 651 | fdctrl_write_data(fdctrl, value); |
4f431960 | 652 | break; |
a758f8f4 HP |
653 | case FD_REG_CCR: |
654 | fdctrl_write_ccr(fdctrl, value); | |
655 | break; | |
a541f297 | 656 | default: |
4f431960 | 657 | break; |
a541f297 | 658 | } |
baca51fa FB |
659 | } |
660 | ||
a8170e5e | 661 | static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg, |
dc6c1b37 | 662 | unsigned ize) |
62a46c61 | 663 | { |
5dcb6b91 | 664 | return fdctrl_read(opaque, (uint32_t)reg); |
62a46c61 FB |
665 | } |
666 | ||
a8170e5e | 667 | static void fdctrl_write_mem (void *opaque, hwaddr reg, |
dc6c1b37 | 668 | uint64_t value, unsigned size) |
62a46c61 | 669 | { |
5dcb6b91 | 670 | fdctrl_write(opaque, (uint32_t)reg, value); |
62a46c61 FB |
671 | } |
672 | ||
dc6c1b37 AK |
673 | static const MemoryRegionOps fdctrl_mem_ops = { |
674 | .read = fdctrl_read_mem, | |
675 | .write = fdctrl_write_mem, | |
676 | .endianness = DEVICE_NATIVE_ENDIAN, | |
e80cfcfc FB |
677 | }; |
678 | ||
dc6c1b37 AK |
679 | static const MemoryRegionOps fdctrl_mem_strict_ops = { |
680 | .read = fdctrl_read_mem, | |
681 | .write = fdctrl_write_mem, | |
682 | .endianness = DEVICE_NATIVE_ENDIAN, | |
683 | .valid = { | |
684 | .min_access_size = 1, | |
685 | .max_access_size = 1, | |
686 | }, | |
7c560456 BS |
687 | }; |
688 | ||
7d905f71 JW |
689 | static bool fdrive_media_changed_needed(void *opaque) |
690 | { | |
691 | FDrive *drive = opaque; | |
692 | ||
2e1280e8 | 693 | return (drive->media_inserted && drive->media_changed != 1); |
7d905f71 JW |
694 | } |
695 | ||
696 | static const VMStateDescription vmstate_fdrive_media_changed = { | |
697 | .name = "fdrive/media_changed", | |
698 | .version_id = 1, | |
699 | .minimum_version_id = 1, | |
5cd8cada | 700 | .needed = fdrive_media_changed_needed, |
d49805ae | 701 | .fields = (VMStateField[]) { |
7d905f71 JW |
702 | VMSTATE_UINT8(media_changed, FDrive), |
703 | VMSTATE_END_OF_LIST() | |
704 | } | |
705 | }; | |
706 | ||
844f65d6 HP |
707 | static bool fdrive_media_rate_needed(void *opaque) |
708 | { | |
709 | FDrive *drive = opaque; | |
710 | ||
711 | return drive->fdctrl->check_media_rate; | |
712 | } | |
713 | ||
714 | static const VMStateDescription vmstate_fdrive_media_rate = { | |
715 | .name = "fdrive/media_rate", | |
716 | .version_id = 1, | |
717 | .minimum_version_id = 1, | |
5cd8cada | 718 | .needed = fdrive_media_rate_needed, |
d49805ae | 719 | .fields = (VMStateField[]) { |
844f65d6 HP |
720 | VMSTATE_UINT8(media_rate, FDrive), |
721 | VMSTATE_END_OF_LIST() | |
722 | } | |
723 | }; | |
724 | ||
c0b92f30 PD |
725 | static bool fdrive_perpendicular_needed(void *opaque) |
726 | { | |
727 | FDrive *drive = opaque; | |
728 | ||
729 | return drive->perpendicular != 0; | |
730 | } | |
731 | ||
732 | static const VMStateDescription vmstate_fdrive_perpendicular = { | |
733 | .name = "fdrive/perpendicular", | |
734 | .version_id = 1, | |
735 | .minimum_version_id = 1, | |
5cd8cada | 736 | .needed = fdrive_perpendicular_needed, |
c0b92f30 PD |
737 | .fields = (VMStateField[]) { |
738 | VMSTATE_UINT8(perpendicular, FDrive), | |
739 | VMSTATE_END_OF_LIST() | |
740 | } | |
741 | }; | |
742 | ||
743 | static int fdrive_post_load(void *opaque, int version_id) | |
744 | { | |
745 | fd_revalidate(opaque); | |
746 | return 0; | |
747 | } | |
748 | ||
d7a6c270 JQ |
749 | static const VMStateDescription vmstate_fdrive = { |
750 | .name = "fdrive", | |
751 | .version_id = 1, | |
752 | .minimum_version_id = 1, | |
c0b92f30 | 753 | .post_load = fdrive_post_load, |
d49805ae | 754 | .fields = (VMStateField[]) { |
5c02c033 BS |
755 | VMSTATE_UINT8(head, FDrive), |
756 | VMSTATE_UINT8(track, FDrive), | |
757 | VMSTATE_UINT8(sect, FDrive), | |
d7a6c270 | 758 | VMSTATE_END_OF_LIST() |
7d905f71 | 759 | }, |
5cd8cada JQ |
760 | .subsections = (const VMStateDescription*[]) { |
761 | &vmstate_fdrive_media_changed, | |
762 | &vmstate_fdrive_media_rate, | |
763 | &vmstate_fdrive_perpendicular, | |
764 | NULL | |
d7a6c270 JQ |
765 | } |
766 | }; | |
3ccacc4a | 767 | |
85d291a0 KW |
768 | /* |
769 | * Reconstructs the phase from register values according to the logic that was | |
770 | * implemented in qemu 2.3. This is the default value that is used if the phase | |
771 | * subsection is not present on migration. | |
772 | * | |
773 | * Don't change this function to reflect newer qemu versions, it is part of | |
774 | * the migration ABI. | |
775 | */ | |
776 | static int reconstruct_phase(FDCtrl *fdctrl) | |
777 | { | |
778 | if (fdctrl->msr & FD_MSR_NONDMA) { | |
779 | return FD_PHASE_EXECUTION; | |
780 | } else if ((fdctrl->msr & FD_MSR_RQM) == 0) { | |
781 | /* qemu 2.3 disabled RQM only during DMA transfers */ | |
782 | return FD_PHASE_EXECUTION; | |
783 | } else if (fdctrl->msr & FD_MSR_DIO) { | |
784 | return FD_PHASE_RESULT; | |
785 | } else { | |
786 | return FD_PHASE_COMMAND; | |
787 | } | |
788 | } | |
789 | ||
d4bfa4d7 | 790 | static void fdc_pre_save(void *opaque) |
3ccacc4a | 791 | { |
5c02c033 | 792 | FDCtrl *s = opaque; |
3ccacc4a | 793 | |
d7a6c270 | 794 | s->dor_vmstate = s->dor | GET_CUR_DRV(s); |
3ccacc4a BS |
795 | } |
796 | ||
85d291a0 KW |
797 | static int fdc_pre_load(void *opaque) |
798 | { | |
799 | FDCtrl *s = opaque; | |
800 | s->phase = FD_PHASE_RECONSTRUCT; | |
801 | return 0; | |
802 | } | |
803 | ||
e59fb374 | 804 | static int fdc_post_load(void *opaque, int version_id) |
3ccacc4a | 805 | { |
5c02c033 | 806 | FDCtrl *s = opaque; |
3ccacc4a | 807 | |
d7a6c270 JQ |
808 | SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK); |
809 | s->dor = s->dor_vmstate & ~FD_DOR_SELMASK; | |
85d291a0 KW |
810 | |
811 | if (s->phase == FD_PHASE_RECONSTRUCT) { | |
812 | s->phase = reconstruct_phase(s); | |
813 | } | |
814 | ||
3ccacc4a BS |
815 | return 0; |
816 | } | |
817 | ||
c0b92f30 PD |
818 | static bool fdc_reset_sensei_needed(void *opaque) |
819 | { | |
820 | FDCtrl *s = opaque; | |
821 | ||
822 | return s->reset_sensei != 0; | |
823 | } | |
824 | ||
825 | static const VMStateDescription vmstate_fdc_reset_sensei = { | |
826 | .name = "fdc/reset_sensei", | |
827 | .version_id = 1, | |
828 | .minimum_version_id = 1, | |
5cd8cada | 829 | .needed = fdc_reset_sensei_needed, |
c0b92f30 PD |
830 | .fields = (VMStateField[]) { |
831 | VMSTATE_INT32(reset_sensei, FDCtrl), | |
832 | VMSTATE_END_OF_LIST() | |
833 | } | |
834 | }; | |
835 | ||
836 | static bool fdc_result_timer_needed(void *opaque) | |
837 | { | |
838 | FDCtrl *s = opaque; | |
839 | ||
840 | return timer_pending(s->result_timer); | |
841 | } | |
842 | ||
843 | static const VMStateDescription vmstate_fdc_result_timer = { | |
844 | .name = "fdc/result_timer", | |
845 | .version_id = 1, | |
846 | .minimum_version_id = 1, | |
5cd8cada | 847 | .needed = fdc_result_timer_needed, |
c0b92f30 | 848 | .fields = (VMStateField[]) { |
e720677e | 849 | VMSTATE_TIMER_PTR(result_timer, FDCtrl), |
c0b92f30 PD |
850 | VMSTATE_END_OF_LIST() |
851 | } | |
852 | }; | |
853 | ||
85d291a0 KW |
854 | static bool fdc_phase_needed(void *opaque) |
855 | { | |
856 | FDCtrl *fdctrl = opaque; | |
857 | ||
858 | return reconstruct_phase(fdctrl) != fdctrl->phase; | |
859 | } | |
860 | ||
861 | static const VMStateDescription vmstate_fdc_phase = { | |
862 | .name = "fdc/phase", | |
863 | .version_id = 1, | |
864 | .minimum_version_id = 1, | |
5cd8cada | 865 | .needed = fdc_phase_needed, |
85d291a0 KW |
866 | .fields = (VMStateField[]) { |
867 | VMSTATE_UINT8(phase, FDCtrl), | |
868 | VMSTATE_END_OF_LIST() | |
869 | } | |
870 | }; | |
871 | ||
d7a6c270 | 872 | static const VMStateDescription vmstate_fdc = { |
aef30c3c | 873 | .name = "fdc", |
d7a6c270 JQ |
874 | .version_id = 2, |
875 | .minimum_version_id = 2, | |
d7a6c270 | 876 | .pre_save = fdc_pre_save, |
85d291a0 | 877 | .pre_load = fdc_pre_load, |
d7a6c270 | 878 | .post_load = fdc_post_load, |
d49805ae | 879 | .fields = (VMStateField[]) { |
d7a6c270 | 880 | /* Controller State */ |
5c02c033 BS |
881 | VMSTATE_UINT8(sra, FDCtrl), |
882 | VMSTATE_UINT8(srb, FDCtrl), | |
883 | VMSTATE_UINT8(dor_vmstate, FDCtrl), | |
884 | VMSTATE_UINT8(tdr, FDCtrl), | |
885 | VMSTATE_UINT8(dsr, FDCtrl), | |
886 | VMSTATE_UINT8(msr, FDCtrl), | |
887 | VMSTATE_UINT8(status0, FDCtrl), | |
888 | VMSTATE_UINT8(status1, FDCtrl), | |
889 | VMSTATE_UINT8(status2, FDCtrl), | |
d7a6c270 | 890 | /* Command FIFO */ |
8ec68b06 BS |
891 | VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8, |
892 | uint8_t), | |
5c02c033 BS |
893 | VMSTATE_UINT32(data_pos, FDCtrl), |
894 | VMSTATE_UINT32(data_len, FDCtrl), | |
895 | VMSTATE_UINT8(data_state, FDCtrl), | |
896 | VMSTATE_UINT8(data_dir, FDCtrl), | |
897 | VMSTATE_UINT8(eot, FDCtrl), | |
d7a6c270 | 898 | /* States kept only to be returned back */ |
5c02c033 BS |
899 | VMSTATE_UINT8(timer0, FDCtrl), |
900 | VMSTATE_UINT8(timer1, FDCtrl), | |
901 | VMSTATE_UINT8(precomp_trk, FDCtrl), | |
902 | VMSTATE_UINT8(config, FDCtrl), | |
903 | VMSTATE_UINT8(lock, FDCtrl), | |
904 | VMSTATE_UINT8(pwrd, FDCtrl), | |
905 | VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl), | |
906 | VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1, | |
907 | vmstate_fdrive, FDrive), | |
d7a6c270 | 908 | VMSTATE_END_OF_LIST() |
c0b92f30 | 909 | }, |
5cd8cada JQ |
910 | .subsections = (const VMStateDescription*[]) { |
911 | &vmstate_fdc_reset_sensei, | |
912 | &vmstate_fdc_result_timer, | |
913 | &vmstate_fdc_phase, | |
914 | NULL | |
78ae820c | 915 | } |
d7a6c270 | 916 | }; |
3ccacc4a | 917 | |
2be37833 | 918 | static void fdctrl_external_reset_sysbus(DeviceState *d) |
3ccacc4a | 919 | { |
dd3be742 | 920 | FDCtrlSysBus *sys = SYSBUS_FDC(d); |
5c02c033 | 921 | FDCtrl *s = &sys->state; |
2be37833 BS |
922 | |
923 | fdctrl_reset(s, 0); | |
924 | } | |
925 | ||
926 | static void fdctrl_external_reset_isa(DeviceState *d) | |
927 | { | |
020c8e76 | 928 | FDCtrlISABus *isa = ISA_FDC(d); |
5c02c033 | 929 | FDCtrl *s = &isa->state; |
3ccacc4a BS |
930 | |
931 | fdctrl_reset(s, 0); | |
932 | } | |
933 | ||
2be17ebd BS |
934 | static void fdctrl_handle_tc(void *opaque, int irq, int level) |
935 | { | |
5c02c033 | 936 | //FDCtrl *s = opaque; |
2be17ebd BS |
937 | |
938 | if (level) { | |
939 | // XXX | |
940 | FLOPPY_DPRINTF("TC pulsed\n"); | |
941 | } | |
942 | } | |
943 | ||
8977f3c1 | 944 | /* Change IRQ state */ |
5c02c033 | 945 | static void fdctrl_reset_irq(FDCtrl *fdctrl) |
8977f3c1 | 946 | { |
d497d534 | 947 | fdctrl->status0 = 0; |
8c6a4d77 BS |
948 | if (!(fdctrl->sra & FD_SRA_INTPEND)) |
949 | return; | |
ed5fd2cc | 950 | FLOPPY_DPRINTF("Reset interrupt\n"); |
d537cf6c | 951 | qemu_set_irq(fdctrl->irq, 0); |
8c6a4d77 | 952 | fdctrl->sra &= ~FD_SRA_INTPEND; |
8977f3c1 FB |
953 | } |
954 | ||
d497d534 | 955 | static void fdctrl_raise_irq(FDCtrl *fdctrl) |
8977f3c1 | 956 | { |
8c6a4d77 | 957 | if (!(fdctrl->sra & FD_SRA_INTPEND)) { |
d537cf6c | 958 | qemu_set_irq(fdctrl->irq, 1); |
8c6a4d77 | 959 | fdctrl->sra |= FD_SRA_INTPEND; |
8977f3c1 | 960 | } |
21fcf360 | 961 | |
f2d81b33 | 962 | fdctrl->reset_sensei = 0; |
77370520 | 963 | FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0); |
8977f3c1 FB |
964 | } |
965 | ||
4b19ec0c | 966 | /* Reset controller */ |
5c02c033 | 967 | static void fdctrl_reset(FDCtrl *fdctrl, int do_irq) |
8977f3c1 FB |
968 | { |
969 | int i; | |
970 | ||
4b19ec0c | 971 | FLOPPY_DPRINTF("reset controller\n"); |
baca51fa | 972 | fdctrl_reset_irq(fdctrl); |
4b19ec0c | 973 | /* Initialise controller */ |
8c6a4d77 BS |
974 | fdctrl->sra = 0; |
975 | fdctrl->srb = 0xc0; | |
4be74634 | 976 | if (!fdctrl->drives[1].blk) { |
8c6a4d77 | 977 | fdctrl->sra |= FD_SRA_nDRV2; |
4be74634 | 978 | } |
baca51fa | 979 | fdctrl->cur_drv = 0; |
1c346df2 | 980 | fdctrl->dor = FD_DOR_nRESET; |
368df94d | 981 | fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0; |
b9b3d225 | 982 | fdctrl->msr = FD_MSR_RQM; |
c0b92f30 PD |
983 | fdctrl->reset_sensei = 0; |
984 | timer_del(fdctrl->result_timer); | |
8977f3c1 | 985 | /* FIFO state */ |
baca51fa FB |
986 | fdctrl->data_pos = 0; |
987 | fdctrl->data_len = 0; | |
b9b3d225 | 988 | fdctrl->data_state = 0; |
baca51fa | 989 | fdctrl->data_dir = FD_DIR_WRITE; |
8977f3c1 | 990 | for (i = 0; i < MAX_FD; i++) |
1c346df2 | 991 | fd_recalibrate(&fdctrl->drives[i]); |
07e415f2 | 992 | fdctrl_to_command_phase(fdctrl); |
77370520 | 993 | if (do_irq) { |
d497d534 HP |
994 | fdctrl->status0 |= FD_SR0_RDYCHG; |
995 | fdctrl_raise_irq(fdctrl); | |
f2d81b33 | 996 | fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT; |
77370520 | 997 | } |
baca51fa FB |
998 | } |
999 | ||
5c02c033 | 1000 | static inline FDrive *drv0(FDCtrl *fdctrl) |
baca51fa | 1001 | { |
46d3233b | 1002 | return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2]; |
baca51fa FB |
1003 | } |
1004 | ||
5c02c033 | 1005 | static inline FDrive *drv1(FDCtrl *fdctrl) |
baca51fa | 1006 | { |
46d3233b BS |
1007 | if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2)) |
1008 | return &fdctrl->drives[1]; | |
1009 | else | |
1010 | return &fdctrl->drives[0]; | |
baca51fa FB |
1011 | } |
1012 | ||
78ae820c | 1013 | #if MAX_FD == 4 |
5c02c033 | 1014 | static inline FDrive *drv2(FDCtrl *fdctrl) |
78ae820c BS |
1015 | { |
1016 | if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2)) | |
1017 | return &fdctrl->drives[2]; | |
1018 | else | |
1019 | return &fdctrl->drives[1]; | |
1020 | } | |
1021 | ||
5c02c033 | 1022 | static inline FDrive *drv3(FDCtrl *fdctrl) |
78ae820c BS |
1023 | { |
1024 | if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2)) | |
1025 | return &fdctrl->drives[3]; | |
1026 | else | |
1027 | return &fdctrl->drives[2]; | |
1028 | } | |
1029 | #endif | |
1030 | ||
5c02c033 | 1031 | static FDrive *get_cur_drv(FDCtrl *fdctrl) |
baca51fa | 1032 | { |
78ae820c BS |
1033 | switch (fdctrl->cur_drv) { |
1034 | case 0: return drv0(fdctrl); | |
1035 | case 1: return drv1(fdctrl); | |
1036 | #if MAX_FD == 4 | |
1037 | case 2: return drv2(fdctrl); | |
1038 | case 3: return drv3(fdctrl); | |
1039 | #endif | |
1040 | default: return NULL; | |
1041 | } | |
8977f3c1 FB |
1042 | } |
1043 | ||
8c6a4d77 | 1044 | /* Status A register : 0x00 (read-only) */ |
5c02c033 | 1045 | static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl) |
8c6a4d77 BS |
1046 | { |
1047 | uint32_t retval = fdctrl->sra; | |
1048 | ||
1049 | FLOPPY_DPRINTF("status register A: 0x%02x\n", retval); | |
1050 | ||
1051 | return retval; | |
1052 | } | |
1053 | ||
8977f3c1 | 1054 | /* Status B register : 0x01 (read-only) */ |
5c02c033 | 1055 | static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl) |
8977f3c1 | 1056 | { |
8c6a4d77 BS |
1057 | uint32_t retval = fdctrl->srb; |
1058 | ||
1059 | FLOPPY_DPRINTF("status register B: 0x%02x\n", retval); | |
1060 | ||
1061 | return retval; | |
8977f3c1 FB |
1062 | } |
1063 | ||
1064 | /* Digital output register : 0x02 */ | |
5c02c033 | 1065 | static uint32_t fdctrl_read_dor(FDCtrl *fdctrl) |
8977f3c1 | 1066 | { |
1c346df2 | 1067 | uint32_t retval = fdctrl->dor; |
8977f3c1 | 1068 | |
8977f3c1 | 1069 | /* Selected drive */ |
baca51fa | 1070 | retval |= fdctrl->cur_drv; |
8977f3c1 FB |
1071 | FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval); |
1072 | ||
1073 | return retval; | |
1074 | } | |
1075 | ||
5c02c033 | 1076 | static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value) |
8977f3c1 | 1077 | { |
8977f3c1 | 1078 | FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value); |
8c6a4d77 BS |
1079 | |
1080 | /* Motors */ | |
1081 | if (value & FD_DOR_MOTEN0) | |
1082 | fdctrl->srb |= FD_SRB_MTR0; | |
1083 | else | |
1084 | fdctrl->srb &= ~FD_SRB_MTR0; | |
1085 | if (value & FD_DOR_MOTEN1) | |
1086 | fdctrl->srb |= FD_SRB_MTR1; | |
1087 | else | |
1088 | fdctrl->srb &= ~FD_SRB_MTR1; | |
1089 | ||
1090 | /* Drive */ | |
1091 | if (value & 1) | |
1092 | fdctrl->srb |= FD_SRB_DR0; | |
1093 | else | |
1094 | fdctrl->srb &= ~FD_SRB_DR0; | |
1095 | ||
8977f3c1 | 1096 | /* Reset */ |
9fea808a | 1097 | if (!(value & FD_DOR_nRESET)) { |
1c346df2 | 1098 | if (fdctrl->dor & FD_DOR_nRESET) { |
4b19ec0c | 1099 | FLOPPY_DPRINTF("controller enter RESET state\n"); |
8977f3c1 FB |
1100 | } |
1101 | } else { | |
1c346df2 | 1102 | if (!(fdctrl->dor & FD_DOR_nRESET)) { |
4b19ec0c | 1103 | FLOPPY_DPRINTF("controller out of RESET state\n"); |
fb6cf1d0 | 1104 | fdctrl_reset(fdctrl, 1); |
b9b3d225 | 1105 | fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
8977f3c1 FB |
1106 | } |
1107 | } | |
1108 | /* Selected drive */ | |
9fea808a | 1109 | fdctrl->cur_drv = value & FD_DOR_SELMASK; |
368df94d BS |
1110 | |
1111 | fdctrl->dor = value; | |
8977f3c1 FB |
1112 | } |
1113 | ||
1114 | /* Tape drive register : 0x03 */ | |
5c02c033 | 1115 | static uint32_t fdctrl_read_tape(FDCtrl *fdctrl) |
8977f3c1 | 1116 | { |
46d3233b | 1117 | uint32_t retval = fdctrl->tdr; |
8977f3c1 | 1118 | |
8977f3c1 FB |
1119 | FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval); |
1120 | ||
1121 | return retval; | |
1122 | } | |
1123 | ||
5c02c033 | 1124 | static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value) |
8977f3c1 | 1125 | { |
8977f3c1 | 1126 | /* Reset mode */ |
1c346df2 | 1127 | if (!(fdctrl->dor & FD_DOR_nRESET)) { |
4b19ec0c | 1128 | FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); |
8977f3c1 FB |
1129 | return; |
1130 | } | |
1131 | FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value); | |
1132 | /* Disk boot selection indicator */ | |
46d3233b | 1133 | fdctrl->tdr = value & FD_TDR_BOOTSEL; |
8977f3c1 FB |
1134 | /* Tape indicators: never allow */ |
1135 | } | |
1136 | ||
1137 | /* Main status register : 0x04 (read) */ | |
5c02c033 | 1138 | static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl) |
8977f3c1 | 1139 | { |
b9b3d225 | 1140 | uint32_t retval = fdctrl->msr; |
8977f3c1 | 1141 | |
b9b3d225 | 1142 | fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
1c346df2 | 1143 | fdctrl->dor |= FD_DOR_nRESET; |
b9b3d225 | 1144 | |
8977f3c1 FB |
1145 | FLOPPY_DPRINTF("main status register: 0x%02x\n", retval); |
1146 | ||
1147 | return retval; | |
1148 | } | |
1149 | ||
1150 | /* Data select rate register : 0x04 (write) */ | |
5c02c033 | 1151 | static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value) |
8977f3c1 | 1152 | { |
8977f3c1 | 1153 | /* Reset mode */ |
1c346df2 | 1154 | if (!(fdctrl->dor & FD_DOR_nRESET)) { |
4f431960 JM |
1155 | FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); |
1156 | return; | |
1157 | } | |
8977f3c1 FB |
1158 | FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value); |
1159 | /* Reset: autoclear */ | |
9fea808a | 1160 | if (value & FD_DSR_SWRESET) { |
1c346df2 | 1161 | fdctrl->dor &= ~FD_DOR_nRESET; |
baca51fa | 1162 | fdctrl_reset(fdctrl, 1); |
1c346df2 | 1163 | fdctrl->dor |= FD_DOR_nRESET; |
8977f3c1 | 1164 | } |
9fea808a | 1165 | if (value & FD_DSR_PWRDOWN) { |
baca51fa | 1166 | fdctrl_reset(fdctrl, 1); |
8977f3c1 | 1167 | } |
b9b3d225 | 1168 | fdctrl->dsr = value; |
8977f3c1 FB |
1169 | } |
1170 | ||
a758f8f4 HP |
1171 | /* Configuration control register: 0x07 (write) */ |
1172 | static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value) | |
1173 | { | |
1174 | /* Reset mode */ | |
1175 | if (!(fdctrl->dor & FD_DOR_nRESET)) { | |
1176 | FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); | |
1177 | return; | |
1178 | } | |
1179 | FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value); | |
1180 | ||
1181 | /* Only the rate selection bits used in AT mode, and we | |
1182 | * store those in the DSR. | |
1183 | */ | |
1184 | fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) | | |
1185 | (value & FD_DSR_DRATEMASK); | |
1186 | } | |
1187 | ||
5c02c033 | 1188 | static int fdctrl_media_changed(FDrive *drv) |
ea185bbd | 1189 | { |
21fcf360 | 1190 | return drv->media_changed; |
ea185bbd FB |
1191 | } |
1192 | ||
8977f3c1 | 1193 | /* Digital input register : 0x07 (read-only) */ |
5c02c033 | 1194 | static uint32_t fdctrl_read_dir(FDCtrl *fdctrl) |
8977f3c1 | 1195 | { |
8977f3c1 FB |
1196 | uint32_t retval = 0; |
1197 | ||
a2df5fa3 | 1198 | if (fdctrl_media_changed(get_cur_drv(fdctrl))) { |
9fea808a | 1199 | retval |= FD_DIR_DSKCHG; |
a2df5fa3 | 1200 | } |
3c83eb4f | 1201 | if (retval != 0) { |
baca51fa | 1202 | FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval); |
3c83eb4f | 1203 | } |
8977f3c1 FB |
1204 | |
1205 | return retval; | |
1206 | } | |
1207 | ||
07e415f2 KW |
1208 | /* Clear the FIFO and update the state for receiving the next command */ |
1209 | static void fdctrl_to_command_phase(FDCtrl *fdctrl) | |
8977f3c1 | 1210 | { |
85d291a0 | 1211 | fdctrl->phase = FD_PHASE_COMMAND; |
baca51fa FB |
1212 | fdctrl->data_dir = FD_DIR_WRITE; |
1213 | fdctrl->data_pos = 0; | |
6cc8a11c | 1214 | fdctrl->data_len = 1; /* Accept command byte, adjust for params later */ |
b9b3d225 | 1215 | fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO); |
6cc8a11c | 1216 | fdctrl->msr |= FD_MSR_RQM; |
8977f3c1 FB |
1217 | } |
1218 | ||
83a26013 KW |
1219 | /* Update the state to allow the guest to read out the command status. |
1220 | * @fifo_len is the number of result bytes to be read out. */ | |
1221 | static void fdctrl_to_result_phase(FDCtrl *fdctrl, int fifo_len) | |
8977f3c1 | 1222 | { |
85d291a0 | 1223 | fdctrl->phase = FD_PHASE_RESULT; |
baca51fa FB |
1224 | fdctrl->data_dir = FD_DIR_READ; |
1225 | fdctrl->data_len = fifo_len; | |
1226 | fdctrl->data_pos = 0; | |
b9b3d225 | 1227 | fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO; |
8977f3c1 FB |
1228 | } |
1229 | ||
1230 | /* Set an error: unimplemented/unknown command */ | |
5c02c033 | 1231 | static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction) |
8977f3c1 | 1232 | { |
cced7a13 BS |
1233 | qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n", |
1234 | fdctrl->fifo[0]); | |
9fea808a | 1235 | fdctrl->fifo[0] = FD_SR0_INVCMD; |
83a26013 | 1236 | fdctrl_to_result_phase(fdctrl, 1); |
8977f3c1 FB |
1237 | } |
1238 | ||
6be01b1e PH |
1239 | /* Seek to next sector |
1240 | * returns 0 when end of track reached (for DBL_SIDES on head 1) | |
1241 | * otherwise returns 1 | |
1242 | */ | |
5c02c033 | 1243 | static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv) |
746d6de7 BS |
1244 | { |
1245 | FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n", | |
1246 | cur_drv->head, cur_drv->track, cur_drv->sect, | |
1247 | fd_sector(cur_drv)); | |
1248 | /* XXX: cur_drv->sect >= cur_drv->last_sect should be an | |
1249 | error in fact */ | |
6be01b1e PH |
1250 | uint8_t new_head = cur_drv->head; |
1251 | uint8_t new_track = cur_drv->track; | |
1252 | uint8_t new_sect = cur_drv->sect; | |
1253 | ||
1254 | int ret = 1; | |
1255 | ||
1256 | if (new_sect >= cur_drv->last_sect || | |
1257 | new_sect == fdctrl->eot) { | |
1258 | new_sect = 1; | |
746d6de7 | 1259 | if (FD_MULTI_TRACK(fdctrl->data_state)) { |
6be01b1e | 1260 | if (new_head == 0 && |
746d6de7 | 1261 | (cur_drv->flags & FDISK_DBL_SIDES) != 0) { |
6be01b1e | 1262 | new_head = 1; |
746d6de7 | 1263 | } else { |
6be01b1e PH |
1264 | new_head = 0; |
1265 | new_track++; | |
c5139bd9 | 1266 | fdctrl->status0 |= FD_SR0_SEEK; |
6be01b1e PH |
1267 | if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) { |
1268 | ret = 0; | |
1269 | } | |
746d6de7 BS |
1270 | } |
1271 | } else { | |
c5139bd9 | 1272 | fdctrl->status0 |= FD_SR0_SEEK; |
6be01b1e PH |
1273 | new_track++; |
1274 | ret = 0; | |
1275 | } | |
1276 | if (ret == 1) { | |
1277 | FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n", | |
1278 | new_head, new_track, new_sect, fd_sector(cur_drv)); | |
746d6de7 | 1279 | } |
746d6de7 | 1280 | } else { |
6be01b1e | 1281 | new_sect++; |
746d6de7 | 1282 | } |
6be01b1e PH |
1283 | fd_seek(cur_drv, new_head, new_track, new_sect, 1); |
1284 | return ret; | |
746d6de7 BS |
1285 | } |
1286 | ||
8977f3c1 | 1287 | /* Callback for transfer end (stop or abort) */ |
5c02c033 BS |
1288 | static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0, |
1289 | uint8_t status1, uint8_t status2) | |
8977f3c1 | 1290 | { |
5c02c033 | 1291 | FDrive *cur_drv; |
baca51fa | 1292 | cur_drv = get_cur_drv(fdctrl); |
075f5532 HP |
1293 | |
1294 | fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD); | |
1295 | fdctrl->status0 |= GET_CUR_DRV(fdctrl); | |
1296 | if (cur_drv->head) { | |
1297 | fdctrl->status0 |= FD_SR0_HEAD; | |
1298 | } | |
1299 | fdctrl->status0 |= status0; | |
2fee0088 | 1300 | |
8977f3c1 | 1301 | FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n", |
2fee0088 PH |
1302 | status0, status1, status2, fdctrl->status0); |
1303 | fdctrl->fifo[0] = fdctrl->status0; | |
baca51fa FB |
1304 | fdctrl->fifo[1] = status1; |
1305 | fdctrl->fifo[2] = status2; | |
1306 | fdctrl->fifo[3] = cur_drv->track; | |
1307 | fdctrl->fifo[4] = cur_drv->head; | |
1308 | fdctrl->fifo[5] = cur_drv->sect; | |
1309 | fdctrl->fifo[6] = FD_SECTOR_SC; | |
1310 | fdctrl->data_dir = FD_DIR_READ; | |
368df94d | 1311 | if (!(fdctrl->msr & FD_MSR_NONDMA)) { |
baca51fa | 1312 | DMA_release_DREQ(fdctrl->dma_chann); |
ed5fd2cc | 1313 | } |
b9b3d225 | 1314 | fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO; |
368df94d | 1315 | fdctrl->msr &= ~FD_MSR_NONDMA; |
34abf9a7 | 1316 | |
83a26013 | 1317 | fdctrl_to_result_phase(fdctrl, 7); |
d497d534 | 1318 | fdctrl_raise_irq(fdctrl); |
8977f3c1 FB |
1319 | } |
1320 | ||
1321 | /* Prepare a data transfer (either DMA or FIFO) */ | |
5c02c033 | 1322 | static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction) |
8977f3c1 | 1323 | { |
5c02c033 | 1324 | FDrive *cur_drv; |
8977f3c1 | 1325 | uint8_t kh, kt, ks; |
8977f3c1 | 1326 | |
cefec4f5 | 1327 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); |
baca51fa FB |
1328 | cur_drv = get_cur_drv(fdctrl); |
1329 | kt = fdctrl->fifo[2]; | |
1330 | kh = fdctrl->fifo[3]; | |
1331 | ks = fdctrl->fifo[4]; | |
4b19ec0c | 1332 | FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n", |
cefec4f5 | 1333 | GET_CUR_DRV(fdctrl), kh, kt, ks, |
08388273 HP |
1334 | fd_sector_calc(kh, kt, ks, cur_drv->last_sect, |
1335 | NUM_SIDES(cur_drv))); | |
77370520 | 1336 | switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) { |
8977f3c1 FB |
1337 | case 2: |
1338 | /* sect too big */ | |
9fea808a | 1339 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
baca51fa FB |
1340 | fdctrl->fifo[3] = kt; |
1341 | fdctrl->fifo[4] = kh; | |
1342 | fdctrl->fifo[5] = ks; | |
8977f3c1 FB |
1343 | return; |
1344 | case 3: | |
1345 | /* track too big */ | |
77370520 | 1346 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00); |
baca51fa FB |
1347 | fdctrl->fifo[3] = kt; |
1348 | fdctrl->fifo[4] = kh; | |
1349 | fdctrl->fifo[5] = ks; | |
8977f3c1 FB |
1350 | return; |
1351 | case 4: | |
1352 | /* No seek enabled */ | |
9fea808a | 1353 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
baca51fa FB |
1354 | fdctrl->fifo[3] = kt; |
1355 | fdctrl->fifo[4] = kh; | |
1356 | fdctrl->fifo[5] = ks; | |
8977f3c1 FB |
1357 | return; |
1358 | case 1: | |
d6ed4e21 | 1359 | fdctrl->status0 |= FD_SR0_SEEK; |
8977f3c1 FB |
1360 | break; |
1361 | default: | |
1362 | break; | |
1363 | } | |
b9b3d225 | 1364 | |
844f65d6 HP |
1365 | /* Check the data rate. If the programmed data rate does not match |
1366 | * the currently inserted medium, the operation has to fail. */ | |
1367 | if (fdctrl->check_media_rate && | |
1368 | (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) { | |
1369 | FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n", | |
1370 | fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate); | |
1371 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00); | |
1372 | fdctrl->fifo[3] = kt; | |
1373 | fdctrl->fifo[4] = kh; | |
1374 | fdctrl->fifo[5] = ks; | |
1375 | return; | |
1376 | } | |
1377 | ||
8977f3c1 | 1378 | /* Set the FIFO state */ |
baca51fa FB |
1379 | fdctrl->data_dir = direction; |
1380 | fdctrl->data_pos = 0; | |
27c86e24 | 1381 | assert(fdctrl->msr & FD_MSR_CMDBUSY); |
baca51fa FB |
1382 | if (fdctrl->fifo[0] & 0x80) |
1383 | fdctrl->data_state |= FD_STATE_MULTI; | |
1384 | else | |
1385 | fdctrl->data_state &= ~FD_STATE_MULTI; | |
c83f97b5 | 1386 | if (fdctrl->fifo[5] == 0) { |
baca51fa FB |
1387 | fdctrl->data_len = fdctrl->fifo[8]; |
1388 | } else { | |
4f431960 | 1389 | int tmp; |
3bcb80f1 | 1390 | fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]); |
771effeb | 1391 | tmp = (fdctrl->fifo[6] - ks + 1); |
baca51fa | 1392 | if (fdctrl->fifo[0] & 0x80) |
771effeb | 1393 | tmp += fdctrl->fifo[6]; |
4f431960 | 1394 | fdctrl->data_len *= tmp; |
baca51fa | 1395 | } |
890fa6be | 1396 | fdctrl->eot = fdctrl->fifo[6]; |
368df94d | 1397 | if (fdctrl->dor & FD_DOR_DMAEN) { |
8977f3c1 FB |
1398 | int dma_mode; |
1399 | /* DMA transfer are enabled. Check if DMA channel is well programmed */ | |
baca51fa | 1400 | dma_mode = DMA_get_channel_mode(fdctrl->dma_chann); |
8977f3c1 | 1401 | dma_mode = (dma_mode >> 2) & 3; |
baca51fa | 1402 | FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n", |
4f431960 | 1403 | dma_mode, direction, |
baca51fa | 1404 | (128 << fdctrl->fifo[5]) * |
4f431960 | 1405 | (cur_drv->last_sect - ks + 1), fdctrl->data_len); |
8977f3c1 FB |
1406 | if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL || |
1407 | direction == FD_DIR_SCANH) && dma_mode == 0) || | |
1408 | (direction == FD_DIR_WRITE && dma_mode == 2) || | |
7ea004ed HP |
1409 | (direction == FD_DIR_READ && dma_mode == 1) || |
1410 | (direction == FD_DIR_VERIFY)) { | |
8977f3c1 | 1411 | /* No access is allowed until DMA transfer has completed */ |
b9b3d225 | 1412 | fdctrl->msr &= ~FD_MSR_RQM; |
7ea004ed HP |
1413 | if (direction != FD_DIR_VERIFY) { |
1414 | /* Now, we just have to wait for the DMA controller to | |
1415 | * recall us... | |
1416 | */ | |
1417 | DMA_hold_DREQ(fdctrl->dma_chann); | |
19d2b5e6 | 1418 | DMA_schedule(); |
7ea004ed HP |
1419 | } else { |
1420 | /* Start transfer */ | |
1421 | fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0, | |
1422 | fdctrl->data_len); | |
1423 | } | |
8977f3c1 | 1424 | return; |
baca51fa | 1425 | } else { |
cced7a13 BS |
1426 | FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode, |
1427 | direction); | |
8977f3c1 FB |
1428 | } |
1429 | } | |
1430 | FLOPPY_DPRINTF("start non-DMA transfer\n"); | |
6cc8a11c | 1431 | fdctrl->msr |= FD_MSR_NONDMA | FD_MSR_RQM; |
b9b3d225 BS |
1432 | if (direction != FD_DIR_WRITE) |
1433 | fdctrl->msr |= FD_MSR_DIO; | |
8977f3c1 | 1434 | /* IO based transfer: calculate len */ |
d497d534 | 1435 | fdctrl_raise_irq(fdctrl); |
8977f3c1 FB |
1436 | } |
1437 | ||
1438 | /* Prepare a transfer of deleted data */ | |
5c02c033 | 1439 | static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction) |
8977f3c1 | 1440 | { |
cced7a13 | 1441 | qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n"); |
77370520 | 1442 | |
8977f3c1 FB |
1443 | /* We don't handle deleted data, |
1444 | * so we don't return *ANYTHING* | |
1445 | */ | |
9fea808a | 1446 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
8977f3c1 FB |
1447 | } |
1448 | ||
1449 | /* handlers for DMA transfers */ | |
85571bc7 FB |
1450 | static int fdctrl_transfer_handler (void *opaque, int nchan, |
1451 | int dma_pos, int dma_len) | |
8977f3c1 | 1452 | { |
5c02c033 BS |
1453 | FDCtrl *fdctrl; |
1454 | FDrive *cur_drv; | |
baca51fa | 1455 | int len, start_pos, rel_pos; |
8977f3c1 FB |
1456 | uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00; |
1457 | ||
baca51fa | 1458 | fdctrl = opaque; |
b9b3d225 | 1459 | if (fdctrl->msr & FD_MSR_RQM) { |
8977f3c1 FB |
1460 | FLOPPY_DPRINTF("Not in DMA transfer mode !\n"); |
1461 | return 0; | |
1462 | } | |
baca51fa FB |
1463 | cur_drv = get_cur_drv(fdctrl); |
1464 | if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL || | |
1465 | fdctrl->data_dir == FD_DIR_SCANH) | |
77370520 | 1466 | status2 = FD_SR2_SNS; |
85571bc7 FB |
1467 | if (dma_len > fdctrl->data_len) |
1468 | dma_len = fdctrl->data_len; | |
4be74634 | 1469 | if (cur_drv->blk == NULL) { |
4f431960 | 1470 | if (fdctrl->data_dir == FD_DIR_WRITE) |
9fea808a | 1471 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
4f431960 | 1472 | else |
9fea808a | 1473 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
4f431960 | 1474 | len = 0; |
890fa6be FB |
1475 | goto transfer_error; |
1476 | } | |
baca51fa | 1477 | rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; |
85571bc7 FB |
1478 | for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) { |
1479 | len = dma_len - fdctrl->data_pos; | |
baca51fa FB |
1480 | if (len + rel_pos > FD_SECTOR_LEN) |
1481 | len = FD_SECTOR_LEN - rel_pos; | |
6f7e9aec FB |
1482 | FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x " |
1483 | "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos, | |
cefec4f5 | 1484 | fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head, |
baca51fa | 1485 | cur_drv->track, cur_drv->sect, fd_sector(cur_drv), |
9fea808a | 1486 | fd_sector(cur_drv) * FD_SECTOR_LEN); |
baca51fa | 1487 | if (fdctrl->data_dir != FD_DIR_WRITE || |
4f431960 | 1488 | len < FD_SECTOR_LEN || rel_pos != 0) { |
baca51fa | 1489 | /* READ & SCAN commands and realign to a sector for WRITE */ |
4be74634 MA |
1490 | if (blk_read(cur_drv->blk, fd_sector(cur_drv), |
1491 | fdctrl->fifo, 1) < 0) { | |
8977f3c1 FB |
1492 | FLOPPY_DPRINTF("Floppy: error getting sector %d\n", |
1493 | fd_sector(cur_drv)); | |
1494 | /* Sure, image size is too small... */ | |
baca51fa | 1495 | memset(fdctrl->fifo, 0, FD_SECTOR_LEN); |
8977f3c1 | 1496 | } |
890fa6be | 1497 | } |
4f431960 JM |
1498 | switch (fdctrl->data_dir) { |
1499 | case FD_DIR_READ: | |
1500 | /* READ commands */ | |
85571bc7 FB |
1501 | DMA_write_memory (nchan, fdctrl->fifo + rel_pos, |
1502 | fdctrl->data_pos, len); | |
4f431960 JM |
1503 | break; |
1504 | case FD_DIR_WRITE: | |
baca51fa | 1505 | /* WRITE commands */ |
8510854e HP |
1506 | if (cur_drv->ro) { |
1507 | /* Handle readonly medium early, no need to do DMA, touch the | |
1508 | * LED or attempt any writes. A real floppy doesn't attempt | |
1509 | * to write to readonly media either. */ | |
1510 | fdctrl_stop_transfer(fdctrl, | |
1511 | FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW, | |
1512 | 0x00); | |
1513 | goto transfer_error; | |
1514 | } | |
1515 | ||
85571bc7 FB |
1516 | DMA_read_memory (nchan, fdctrl->fifo + rel_pos, |
1517 | fdctrl->data_pos, len); | |
4be74634 MA |
1518 | if (blk_write(cur_drv->blk, fd_sector(cur_drv), |
1519 | fdctrl->fifo, 1) < 0) { | |
cced7a13 BS |
1520 | FLOPPY_DPRINTF("error writing sector %d\n", |
1521 | fd_sector(cur_drv)); | |
9fea808a | 1522 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
baca51fa | 1523 | goto transfer_error; |
890fa6be | 1524 | } |
4f431960 | 1525 | break; |
7ea004ed HP |
1526 | case FD_DIR_VERIFY: |
1527 | /* VERIFY commands */ | |
1528 | break; | |
4f431960 JM |
1529 | default: |
1530 | /* SCAN commands */ | |
baca51fa | 1531 | { |
4f431960 | 1532 | uint8_t tmpbuf[FD_SECTOR_LEN]; |
baca51fa | 1533 | int ret; |
85571bc7 | 1534 | DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len); |
baca51fa | 1535 | ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len); |
8977f3c1 | 1536 | if (ret == 0) { |
77370520 | 1537 | status2 = FD_SR2_SEH; |
8977f3c1 FB |
1538 | goto end_transfer; |
1539 | } | |
baca51fa FB |
1540 | if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) || |
1541 | (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) { | |
8977f3c1 FB |
1542 | status2 = 0x00; |
1543 | goto end_transfer; | |
1544 | } | |
1545 | } | |
4f431960 | 1546 | break; |
8977f3c1 | 1547 | } |
4f431960 JM |
1548 | fdctrl->data_pos += len; |
1549 | rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; | |
baca51fa | 1550 | if (rel_pos == 0) { |
8977f3c1 | 1551 | /* Seek to next sector */ |
746d6de7 BS |
1552 | if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) |
1553 | break; | |
8977f3c1 FB |
1554 | } |
1555 | } | |
4f431960 | 1556 | end_transfer: |
baca51fa FB |
1557 | len = fdctrl->data_pos - start_pos; |
1558 | FLOPPY_DPRINTF("end transfer %d %d %d\n", | |
4f431960 | 1559 | fdctrl->data_pos, len, fdctrl->data_len); |
baca51fa FB |
1560 | if (fdctrl->data_dir == FD_DIR_SCANE || |
1561 | fdctrl->data_dir == FD_DIR_SCANL || | |
1562 | fdctrl->data_dir == FD_DIR_SCANH) | |
77370520 | 1563 | status2 = FD_SR2_SEH; |
baca51fa | 1564 | fdctrl->data_len -= len; |
890fa6be | 1565 | fdctrl_stop_transfer(fdctrl, status0, status1, status2); |
4f431960 | 1566 | transfer_error: |
8977f3c1 | 1567 | |
baca51fa | 1568 | return len; |
8977f3c1 FB |
1569 | } |
1570 | ||
8977f3c1 | 1571 | /* Data register : 0x05 */ |
5c02c033 | 1572 | static uint32_t fdctrl_read_data(FDCtrl *fdctrl) |
8977f3c1 | 1573 | { |
5c02c033 | 1574 | FDrive *cur_drv; |
8977f3c1 | 1575 | uint32_t retval = 0; |
e9077462 | 1576 | uint32_t pos; |
8977f3c1 | 1577 | |
baca51fa | 1578 | cur_drv = get_cur_drv(fdctrl); |
b9b3d225 BS |
1579 | fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
1580 | if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) { | |
cced7a13 | 1581 | FLOPPY_DPRINTF("error: controller not ready for reading\n"); |
8977f3c1 FB |
1582 | return 0; |
1583 | } | |
f6c2d1d8 KW |
1584 | |
1585 | /* If data_len spans multiple sectors, the current position in the FIFO | |
1586 | * wraps around while fdctrl->data_pos is the real position in the whole | |
1587 | * request. */ | |
baca51fa | 1588 | pos = fdctrl->data_pos; |
e9077462 | 1589 | pos %= FD_SECTOR_LEN; |
f6c2d1d8 KW |
1590 | |
1591 | switch (fdctrl->phase) { | |
1592 | case FD_PHASE_EXECUTION: | |
1593 | assert(fdctrl->msr & FD_MSR_NONDMA); | |
8977f3c1 | 1594 | if (pos == 0) { |
746d6de7 BS |
1595 | if (fdctrl->data_pos != 0) |
1596 | if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) { | |
1597 | FLOPPY_DPRINTF("error seeking to next sector %d\n", | |
1598 | fd_sector(cur_drv)); | |
1599 | return 0; | |
1600 | } | |
4be74634 MA |
1601 | if (blk_read(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1) |
1602 | < 0) { | |
77370520 BS |
1603 | FLOPPY_DPRINTF("error getting sector %d\n", |
1604 | fd_sector(cur_drv)); | |
1605 | /* Sure, image size is too small... */ | |
1606 | memset(fdctrl->fifo, 0, FD_SECTOR_LEN); | |
1607 | } | |
8977f3c1 | 1608 | } |
f6c2d1d8 KW |
1609 | |
1610 | if (++fdctrl->data_pos == fdctrl->data_len) { | |
6cc8a11c | 1611 | fdctrl->msr &= ~FD_MSR_RQM; |
c5139bd9 | 1612 | fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); |
f6c2d1d8 KW |
1613 | } |
1614 | break; | |
1615 | ||
1616 | case FD_PHASE_RESULT: | |
1617 | assert(!(fdctrl->msr & FD_MSR_NONDMA)); | |
1618 | if (++fdctrl->data_pos == fdctrl->data_len) { | |
6cc8a11c | 1619 | fdctrl->msr &= ~FD_MSR_RQM; |
07e415f2 | 1620 | fdctrl_to_command_phase(fdctrl); |
ed5fd2cc FB |
1621 | fdctrl_reset_irq(fdctrl); |
1622 | } | |
f6c2d1d8 KW |
1623 | break; |
1624 | ||
1625 | case FD_PHASE_COMMAND: | |
1626 | default: | |
1627 | abort(); | |
8977f3c1 | 1628 | } |
f6c2d1d8 KW |
1629 | |
1630 | retval = fdctrl->fifo[pos]; | |
8977f3c1 FB |
1631 | FLOPPY_DPRINTF("data register: 0x%02x\n", retval); |
1632 | ||
1633 | return retval; | |
1634 | } | |
1635 | ||
5c02c033 | 1636 | static void fdctrl_format_sector(FDCtrl *fdctrl) |
8977f3c1 | 1637 | { |
5c02c033 | 1638 | FDrive *cur_drv; |
baca51fa | 1639 | uint8_t kh, kt, ks; |
8977f3c1 | 1640 | |
cefec4f5 | 1641 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); |
baca51fa FB |
1642 | cur_drv = get_cur_drv(fdctrl); |
1643 | kt = fdctrl->fifo[6]; | |
1644 | kh = fdctrl->fifo[7]; | |
1645 | ks = fdctrl->fifo[8]; | |
1646 | FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n", | |
cefec4f5 | 1647 | GET_CUR_DRV(fdctrl), kh, kt, ks, |
08388273 HP |
1648 | fd_sector_calc(kh, kt, ks, cur_drv->last_sect, |
1649 | NUM_SIDES(cur_drv))); | |
9fea808a | 1650 | switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) { |
baca51fa FB |
1651 | case 2: |
1652 | /* sect too big */ | |
9fea808a | 1653 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
baca51fa FB |
1654 | fdctrl->fifo[3] = kt; |
1655 | fdctrl->fifo[4] = kh; | |
1656 | fdctrl->fifo[5] = ks; | |
1657 | return; | |
1658 | case 3: | |
1659 | /* track too big */ | |
77370520 | 1660 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00); |
baca51fa FB |
1661 | fdctrl->fifo[3] = kt; |
1662 | fdctrl->fifo[4] = kh; | |
1663 | fdctrl->fifo[5] = ks; | |
1664 | return; | |
1665 | case 4: | |
1666 | /* No seek enabled */ | |
9fea808a | 1667 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
baca51fa FB |
1668 | fdctrl->fifo[3] = kt; |
1669 | fdctrl->fifo[4] = kh; | |
1670 | fdctrl->fifo[5] = ks; | |
1671 | return; | |
1672 | case 1: | |
cd30b53d | 1673 | fdctrl->status0 |= FD_SR0_SEEK; |
baca51fa FB |
1674 | break; |
1675 | default: | |
1676 | break; | |
1677 | } | |
1678 | memset(fdctrl->fifo, 0, FD_SECTOR_LEN); | |
4be74634 MA |
1679 | if (cur_drv->blk == NULL || |
1680 | blk_write(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { | |
cced7a13 | 1681 | FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv)); |
9fea808a | 1682 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
baca51fa | 1683 | } else { |
4f431960 JM |
1684 | if (cur_drv->sect == cur_drv->last_sect) { |
1685 | fdctrl->data_state &= ~FD_STATE_FORMAT; | |
1686 | /* Last sector done */ | |
cd30b53d | 1687 | fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); |
4f431960 JM |
1688 | } else { |
1689 | /* More to do */ | |
1690 | fdctrl->data_pos = 0; | |
1691 | fdctrl->data_len = 4; | |
1692 | } | |
baca51fa FB |
1693 | } |
1694 | } | |
1695 | ||
5c02c033 | 1696 | static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction) |
65cef780 BS |
1697 | { |
1698 | fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0; | |
1699 | fdctrl->fifo[0] = fdctrl->lock << 4; | |
83a26013 | 1700 | fdctrl_to_result_phase(fdctrl, 1); |
65cef780 BS |
1701 | } |
1702 | ||
5c02c033 | 1703 | static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction) |
65cef780 | 1704 | { |
5c02c033 | 1705 | FDrive *cur_drv = get_cur_drv(fdctrl); |
65cef780 BS |
1706 | |
1707 | /* Drives position */ | |
1708 | fdctrl->fifo[0] = drv0(fdctrl)->track; | |
1709 | fdctrl->fifo[1] = drv1(fdctrl)->track; | |
78ae820c BS |
1710 | #if MAX_FD == 4 |
1711 | fdctrl->fifo[2] = drv2(fdctrl)->track; | |
1712 | fdctrl->fifo[3] = drv3(fdctrl)->track; | |
1713 | #else | |
65cef780 BS |
1714 | fdctrl->fifo[2] = 0; |
1715 | fdctrl->fifo[3] = 0; | |
78ae820c | 1716 | #endif |
65cef780 BS |
1717 | /* timers */ |
1718 | fdctrl->fifo[4] = fdctrl->timer0; | |
368df94d | 1719 | fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0); |
65cef780 BS |
1720 | fdctrl->fifo[6] = cur_drv->last_sect; |
1721 | fdctrl->fifo[7] = (fdctrl->lock << 7) | | |
1722 | (cur_drv->perpendicular << 2); | |
1723 | fdctrl->fifo[8] = fdctrl->config; | |
1724 | fdctrl->fifo[9] = fdctrl->precomp_trk; | |
83a26013 | 1725 | fdctrl_to_result_phase(fdctrl, 10); |
65cef780 BS |
1726 | } |
1727 | ||
5c02c033 | 1728 | static void fdctrl_handle_version(FDCtrl *fdctrl, int direction) |
65cef780 BS |
1729 | { |
1730 | /* Controller's version */ | |
1731 | fdctrl->fifo[0] = fdctrl->version; | |
83a26013 | 1732 | fdctrl_to_result_phase(fdctrl, 1); |
65cef780 BS |
1733 | } |
1734 | ||
5c02c033 | 1735 | static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction) |
65cef780 BS |
1736 | { |
1737 | fdctrl->fifo[0] = 0x41; /* Stepping 1 */ | |
83a26013 | 1738 | fdctrl_to_result_phase(fdctrl, 1); |
65cef780 BS |
1739 | } |
1740 | ||
5c02c033 | 1741 | static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction) |
65cef780 | 1742 | { |
5c02c033 | 1743 | FDrive *cur_drv = get_cur_drv(fdctrl); |
65cef780 BS |
1744 | |
1745 | /* Drives position */ | |
1746 | drv0(fdctrl)->track = fdctrl->fifo[3]; | |
1747 | drv1(fdctrl)->track = fdctrl->fifo[4]; | |
78ae820c BS |
1748 | #if MAX_FD == 4 |
1749 | drv2(fdctrl)->track = fdctrl->fifo[5]; | |
1750 | drv3(fdctrl)->track = fdctrl->fifo[6]; | |
1751 | #endif | |
65cef780 BS |
1752 | /* timers */ |
1753 | fdctrl->timer0 = fdctrl->fifo[7]; | |
1754 | fdctrl->timer1 = fdctrl->fifo[8]; | |
1755 | cur_drv->last_sect = fdctrl->fifo[9]; | |
1756 | fdctrl->lock = fdctrl->fifo[10] >> 7; | |
1757 | cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF; | |
1758 | fdctrl->config = fdctrl->fifo[11]; | |
1759 | fdctrl->precomp_trk = fdctrl->fifo[12]; | |
1760 | fdctrl->pwrd = fdctrl->fifo[13]; | |
07e415f2 | 1761 | fdctrl_to_command_phase(fdctrl); |
65cef780 BS |
1762 | } |
1763 | ||
5c02c033 | 1764 | static void fdctrl_handle_save(FDCtrl *fdctrl, int direction) |
65cef780 | 1765 | { |
5c02c033 | 1766 | FDrive *cur_drv = get_cur_drv(fdctrl); |
65cef780 BS |
1767 | |
1768 | fdctrl->fifo[0] = 0; | |
1769 | fdctrl->fifo[1] = 0; | |
1770 | /* Drives position */ | |
1771 | fdctrl->fifo[2] = drv0(fdctrl)->track; | |
1772 | fdctrl->fifo[3] = drv1(fdctrl)->track; | |
78ae820c BS |
1773 | #if MAX_FD == 4 |
1774 | fdctrl->fifo[4] = drv2(fdctrl)->track; | |
1775 | fdctrl->fifo[5] = drv3(fdctrl)->track; | |
1776 | #else | |
65cef780 BS |
1777 | fdctrl->fifo[4] = 0; |
1778 | fdctrl->fifo[5] = 0; | |
78ae820c | 1779 | #endif |
65cef780 BS |
1780 | /* timers */ |
1781 | fdctrl->fifo[6] = fdctrl->timer0; | |
1782 | fdctrl->fifo[7] = fdctrl->timer1; | |
1783 | fdctrl->fifo[8] = cur_drv->last_sect; | |
1784 | fdctrl->fifo[9] = (fdctrl->lock << 7) | | |
1785 | (cur_drv->perpendicular << 2); | |
1786 | fdctrl->fifo[10] = fdctrl->config; | |
1787 | fdctrl->fifo[11] = fdctrl->precomp_trk; | |
1788 | fdctrl->fifo[12] = fdctrl->pwrd; | |
1789 | fdctrl->fifo[13] = 0; | |
1790 | fdctrl->fifo[14] = 0; | |
83a26013 | 1791 | fdctrl_to_result_phase(fdctrl, 15); |
65cef780 BS |
1792 | } |
1793 | ||
5c02c033 | 1794 | static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction) |
65cef780 | 1795 | { |
5c02c033 | 1796 | FDrive *cur_drv = get_cur_drv(fdctrl); |
65cef780 | 1797 | |
65cef780 | 1798 | cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; |
bc72ad67 AB |
1799 | timer_mod(fdctrl->result_timer, |
1800 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 50)); | |
65cef780 BS |
1801 | } |
1802 | ||
5c02c033 | 1803 | static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction) |
65cef780 | 1804 | { |
5c02c033 | 1805 | FDrive *cur_drv; |
65cef780 | 1806 | |
cefec4f5 | 1807 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); |
65cef780 BS |
1808 | cur_drv = get_cur_drv(fdctrl); |
1809 | fdctrl->data_state |= FD_STATE_FORMAT; | |
1810 | if (fdctrl->fifo[0] & 0x80) | |
1811 | fdctrl->data_state |= FD_STATE_MULTI; | |
1812 | else | |
1813 | fdctrl->data_state &= ~FD_STATE_MULTI; | |
65cef780 BS |
1814 | cur_drv->bps = |
1815 | fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2]; | |
1816 | #if 0 | |
1817 | cur_drv->last_sect = | |
1818 | cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] : | |
1819 | fdctrl->fifo[3] / 2; | |
1820 | #else | |
1821 | cur_drv->last_sect = fdctrl->fifo[3]; | |
1822 | #endif | |
1823 | /* TODO: implement format using DMA expected by the Bochs BIOS | |
1824 | * and Linux fdformat (read 3 bytes per sector via DMA and fill | |
1825 | * the sector with the specified fill byte | |
1826 | */ | |
1827 | fdctrl->data_state &= ~FD_STATE_FORMAT; | |
1828 | fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); | |
1829 | } | |
1830 | ||
5c02c033 | 1831 | static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction) |
65cef780 BS |
1832 | { |
1833 | fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF; | |
1834 | fdctrl->timer1 = fdctrl->fifo[2] >> 1; | |
368df94d BS |
1835 | if (fdctrl->fifo[2] & 1) |
1836 | fdctrl->dor &= ~FD_DOR_DMAEN; | |
1837 | else | |
1838 | fdctrl->dor |= FD_DOR_DMAEN; | |
65cef780 | 1839 | /* No result back */ |
07e415f2 | 1840 | fdctrl_to_command_phase(fdctrl); |
65cef780 BS |
1841 | } |
1842 | ||
5c02c033 | 1843 | static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction) |
65cef780 | 1844 | { |
5c02c033 | 1845 | FDrive *cur_drv; |
65cef780 | 1846 | |
cefec4f5 | 1847 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); |
65cef780 BS |
1848 | cur_drv = get_cur_drv(fdctrl); |
1849 | cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; | |
1850 | /* 1 Byte status back */ | |
1851 | fdctrl->fifo[0] = (cur_drv->ro << 6) | | |
1852 | (cur_drv->track == 0 ? 0x10 : 0x00) | | |
1853 | (cur_drv->head << 2) | | |
cefec4f5 | 1854 | GET_CUR_DRV(fdctrl) | |
65cef780 | 1855 | 0x28; |
83a26013 | 1856 | fdctrl_to_result_phase(fdctrl, 1); |
65cef780 BS |
1857 | } |
1858 | ||
5c02c033 | 1859 | static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction) |
65cef780 | 1860 | { |
5c02c033 | 1861 | FDrive *cur_drv; |
65cef780 | 1862 | |
cefec4f5 | 1863 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); |
65cef780 BS |
1864 | cur_drv = get_cur_drv(fdctrl); |
1865 | fd_recalibrate(cur_drv); | |
07e415f2 | 1866 | fdctrl_to_command_phase(fdctrl); |
65cef780 | 1867 | /* Raise Interrupt */ |
d497d534 HP |
1868 | fdctrl->status0 |= FD_SR0_SEEK; |
1869 | fdctrl_raise_irq(fdctrl); | |
65cef780 BS |
1870 | } |
1871 | ||
5c02c033 | 1872 | static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction) |
65cef780 | 1873 | { |
5c02c033 | 1874 | FDrive *cur_drv = get_cur_drv(fdctrl); |
65cef780 | 1875 | |
2fee0088 | 1876 | if (fdctrl->reset_sensei > 0) { |
f2d81b33 BS |
1877 | fdctrl->fifo[0] = |
1878 | FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei; | |
1879 | fdctrl->reset_sensei--; | |
2fee0088 PH |
1880 | } else if (!(fdctrl->sra & FD_SRA_INTPEND)) { |
1881 | fdctrl->fifo[0] = FD_SR0_INVCMD; | |
83a26013 | 1882 | fdctrl_to_result_phase(fdctrl, 1); |
2fee0088 | 1883 | return; |
f2d81b33 | 1884 | } else { |
f2d81b33 | 1885 | fdctrl->fifo[0] = |
2fee0088 PH |
1886 | (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0)) |
1887 | | GET_CUR_DRV(fdctrl); | |
f2d81b33 BS |
1888 | } |
1889 | ||
65cef780 | 1890 | fdctrl->fifo[1] = cur_drv->track; |
83a26013 | 1891 | fdctrl_to_result_phase(fdctrl, 2); |
65cef780 | 1892 | fdctrl_reset_irq(fdctrl); |
77370520 | 1893 | fdctrl->status0 = FD_SR0_RDYCHG; |
65cef780 BS |
1894 | } |
1895 | ||
5c02c033 | 1896 | static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction) |
65cef780 | 1897 | { |
5c02c033 | 1898 | FDrive *cur_drv; |
65cef780 | 1899 | |
cefec4f5 | 1900 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); |
65cef780 | 1901 | cur_drv = get_cur_drv(fdctrl); |
07e415f2 | 1902 | fdctrl_to_command_phase(fdctrl); |
b072a3c8 HP |
1903 | /* The seek command just sends step pulses to the drive and doesn't care if |
1904 | * there is a medium inserted of if it's banging the head against the drive. | |
1905 | */ | |
6be01b1e | 1906 | fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1); |
b072a3c8 | 1907 | /* Raise Interrupt */ |
d497d534 HP |
1908 | fdctrl->status0 |= FD_SR0_SEEK; |
1909 | fdctrl_raise_irq(fdctrl); | |
65cef780 BS |
1910 | } |
1911 | ||
5c02c033 | 1912 | static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction) |
65cef780 | 1913 | { |
5c02c033 | 1914 | FDrive *cur_drv = get_cur_drv(fdctrl); |
65cef780 BS |
1915 | |
1916 | if (fdctrl->fifo[1] & 0x80) | |
1917 | cur_drv->perpendicular = fdctrl->fifo[1] & 0x7; | |
1918 | /* No result back */ | |
07e415f2 | 1919 | fdctrl_to_command_phase(fdctrl); |
65cef780 BS |
1920 | } |
1921 | ||
5c02c033 | 1922 | static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction) |
65cef780 BS |
1923 | { |
1924 | fdctrl->config = fdctrl->fifo[2]; | |
1925 | fdctrl->precomp_trk = fdctrl->fifo[3]; | |
1926 | /* No result back */ | |
07e415f2 | 1927 | fdctrl_to_command_phase(fdctrl); |
65cef780 BS |
1928 | } |
1929 | ||
5c02c033 | 1930 | static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction) |
65cef780 BS |
1931 | { |
1932 | fdctrl->pwrd = fdctrl->fifo[1]; | |
1933 | fdctrl->fifo[0] = fdctrl->fifo[1]; | |
83a26013 | 1934 | fdctrl_to_result_phase(fdctrl, 1); |
65cef780 BS |
1935 | } |
1936 | ||
5c02c033 | 1937 | static void fdctrl_handle_option(FDCtrl *fdctrl, int direction) |
65cef780 BS |
1938 | { |
1939 | /* No result back */ | |
07e415f2 | 1940 | fdctrl_to_command_phase(fdctrl); |
65cef780 BS |
1941 | } |
1942 | ||
5c02c033 | 1943 | static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction) |
65cef780 | 1944 | { |
5c02c033 | 1945 | FDrive *cur_drv = get_cur_drv(fdctrl); |
e9077462 | 1946 | uint32_t pos; |
65cef780 | 1947 | |
e9077462 PM |
1948 | pos = fdctrl->data_pos - 1; |
1949 | pos %= FD_SECTOR_LEN; | |
1950 | if (fdctrl->fifo[pos] & 0x80) { | |
65cef780 | 1951 | /* Command parameters done */ |
e9077462 | 1952 | if (fdctrl->fifo[pos] & 0x40) { |
65cef780 BS |
1953 | fdctrl->fifo[0] = fdctrl->fifo[1]; |
1954 | fdctrl->fifo[2] = 0; | |
1955 | fdctrl->fifo[3] = 0; | |
83a26013 | 1956 | fdctrl_to_result_phase(fdctrl, 4); |
65cef780 | 1957 | } else { |
07e415f2 | 1958 | fdctrl_to_command_phase(fdctrl); |
65cef780 BS |
1959 | } |
1960 | } else if (fdctrl->data_len > 7) { | |
1961 | /* ERROR */ | |
1962 | fdctrl->fifo[0] = 0x80 | | |
cefec4f5 | 1963 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl); |
83a26013 | 1964 | fdctrl_to_result_phase(fdctrl, 1); |
65cef780 BS |
1965 | } |
1966 | } | |
1967 | ||
6d013772 | 1968 | static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction) |
65cef780 | 1969 | { |
5c02c033 | 1970 | FDrive *cur_drv; |
65cef780 | 1971 | |
cefec4f5 | 1972 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); |
65cef780 | 1973 | cur_drv = get_cur_drv(fdctrl); |
65cef780 | 1974 | if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) { |
6be01b1e PH |
1975 | fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1, |
1976 | cur_drv->sect, 1); | |
65cef780 | 1977 | } else { |
6d013772 PH |
1978 | fd_seek(cur_drv, cur_drv->head, |
1979 | cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1); | |
65cef780 | 1980 | } |
07e415f2 | 1981 | fdctrl_to_command_phase(fdctrl); |
77370520 | 1982 | /* Raise Interrupt */ |
d497d534 HP |
1983 | fdctrl->status0 |= FD_SR0_SEEK; |
1984 | fdctrl_raise_irq(fdctrl); | |
65cef780 BS |
1985 | } |
1986 | ||
6d013772 | 1987 | static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction) |
65cef780 | 1988 | { |
5c02c033 | 1989 | FDrive *cur_drv; |
65cef780 | 1990 | |
cefec4f5 | 1991 | SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK); |
65cef780 | 1992 | cur_drv = get_cur_drv(fdctrl); |
65cef780 | 1993 | if (fdctrl->fifo[2] > cur_drv->track) { |
6be01b1e | 1994 | fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1); |
65cef780 | 1995 | } else { |
6d013772 PH |
1996 | fd_seek(cur_drv, cur_drv->head, |
1997 | cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1); | |
65cef780 | 1998 | } |
07e415f2 | 1999 | fdctrl_to_command_phase(fdctrl); |
65cef780 | 2000 | /* Raise Interrupt */ |
d497d534 HP |
2001 | fdctrl->status0 |= FD_SR0_SEEK; |
2002 | fdctrl_raise_irq(fdctrl); | |
65cef780 BS |
2003 | } |
2004 | ||
85d291a0 KW |
2005 | /* |
2006 | * Handlers for the execution phase of each command | |
2007 | */ | |
d275b33d | 2008 | typedef struct FDCtrlCommand { |
678803ab BS |
2009 | uint8_t value; |
2010 | uint8_t mask; | |
2011 | const char* name; | |
2012 | int parameters; | |
5c02c033 | 2013 | void (*handler)(FDCtrl *fdctrl, int direction); |
678803ab | 2014 | int direction; |
d275b33d KW |
2015 | } FDCtrlCommand; |
2016 | ||
2017 | static const FDCtrlCommand handlers[] = { | |
678803ab BS |
2018 | { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ }, |
2019 | { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE }, | |
2020 | { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek }, | |
2021 | { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status }, | |
2022 | { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate }, | |
2023 | { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track }, | |
2024 | { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ }, | |
2025 | { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */ | |
2026 | { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */ | |
2027 | { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ }, | |
2028 | { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE }, | |
7ea004ed | 2029 | { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY }, |
678803ab BS |
2030 | { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL }, |
2031 | { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH }, | |
2032 | { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE }, | |
2033 | { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid }, | |
2034 | { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify }, | |
2035 | { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status }, | |
2036 | { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode }, | |
2037 | { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure }, | |
2038 | { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode }, | |
2039 | { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option }, | |
2040 | { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command }, | |
2041 | { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out }, | |
2042 | { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented }, | |
2043 | { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in }, | |
2044 | { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock }, | |
2045 | { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg }, | |
2046 | { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version }, | |
2047 | { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid }, | |
2048 | { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */ | |
2049 | { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */ | |
2050 | }; | |
2051 | /* Associate command to an index in the 'handlers' array */ | |
2052 | static uint8_t command_to_handler[256]; | |
2053 | ||
d275b33d KW |
2054 | static const FDCtrlCommand *get_command(uint8_t cmd) |
2055 | { | |
2056 | int idx; | |
2057 | ||
2058 | idx = command_to_handler[cmd]; | |
2059 | FLOPPY_DPRINTF("%s command\n", handlers[idx].name); | |
2060 | return &handlers[idx]; | |
2061 | } | |
2062 | ||
5c02c033 | 2063 | static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value) |
baca51fa | 2064 | { |
5c02c033 | 2065 | FDrive *cur_drv; |
d275b33d | 2066 | const FDCtrlCommand *cmd; |
e9077462 | 2067 | uint32_t pos; |
baca51fa | 2068 | |
8977f3c1 | 2069 | /* Reset mode */ |
1c346df2 | 2070 | if (!(fdctrl->dor & FD_DOR_nRESET)) { |
4b19ec0c | 2071 | FLOPPY_DPRINTF("Floppy controller in RESET state !\n"); |
8977f3c1 FB |
2072 | return; |
2073 | } | |
b9b3d225 | 2074 | if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) { |
cced7a13 | 2075 | FLOPPY_DPRINTF("error: controller not ready for writing\n"); |
8977f3c1 FB |
2076 | return; |
2077 | } | |
b9b3d225 | 2078 | fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
5b0a25e8 | 2079 | |
d275b33d KW |
2080 | FLOPPY_DPRINTF("%s: %02x\n", __func__, value); |
2081 | ||
2082 | /* If data_len spans multiple sectors, the current position in the FIFO | |
2083 | * wraps around while fdctrl->data_pos is the real position in the whole | |
2084 | * request. */ | |
2085 | pos = fdctrl->data_pos++; | |
2086 | pos %= FD_SECTOR_LEN; | |
2087 | fdctrl->fifo[pos] = value; | |
2088 | ||
6cc8a11c KW |
2089 | if (fdctrl->data_pos == fdctrl->data_len) { |
2090 | fdctrl->msr &= ~FD_MSR_RQM; | |
2091 | } | |
2092 | ||
5b0a25e8 KW |
2093 | switch (fdctrl->phase) { |
2094 | case FD_PHASE_EXECUTION: | |
2095 | /* For DMA requests, RQM should be cleared during execution phase, so | |
2096 | * we would have errored out above. */ | |
2097 | assert(fdctrl->msr & FD_MSR_NONDMA); | |
d275b33d | 2098 | |
8977f3c1 | 2099 | /* FIFO data write */ |
b3bc1540 | 2100 | if (pos == FD_SECTOR_LEN - 1 || |
baca51fa | 2101 | fdctrl->data_pos == fdctrl->data_len) { |
77370520 | 2102 | cur_drv = get_cur_drv(fdctrl); |
4be74634 MA |
2103 | if (blk_write(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1) |
2104 | < 0) { | |
cced7a13 BS |
2105 | FLOPPY_DPRINTF("error writing sector %d\n", |
2106 | fd_sector(cur_drv)); | |
5b0a25e8 | 2107 | break; |
77370520 | 2108 | } |
746d6de7 BS |
2109 | if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) { |
2110 | FLOPPY_DPRINTF("error seeking to next sector %d\n", | |
2111 | fd_sector(cur_drv)); | |
5b0a25e8 | 2112 | break; |
746d6de7 | 2113 | } |
8977f3c1 | 2114 | } |
d275b33d KW |
2115 | |
2116 | /* Switch to result phase when done with the transfer */ | |
2117 | if (fdctrl->data_pos == fdctrl->data_len) { | |
c5139bd9 | 2118 | fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); |
d275b33d | 2119 | } |
5b0a25e8 | 2120 | break; |
678803ab | 2121 | |
5b0a25e8 KW |
2122 | case FD_PHASE_COMMAND: |
2123 | assert(!(fdctrl->msr & FD_MSR_NONDMA)); | |
d275b33d | 2124 | assert(fdctrl->data_pos < FD_SECTOR_LEN); |
5b0a25e8 | 2125 | |
d275b33d KW |
2126 | if (pos == 0) { |
2127 | /* The first byte specifies the command. Now we start reading | |
2128 | * as many parameters as this command requires. */ | |
2129 | cmd = get_command(value); | |
2130 | fdctrl->data_len = cmd->parameters + 1; | |
6cc8a11c KW |
2131 | if (cmd->parameters) { |
2132 | fdctrl->msr |= FD_MSR_RQM; | |
2133 | } | |
5b0a25e8 | 2134 | fdctrl->msr |= FD_MSR_CMDBUSY; |
8977f3c1 | 2135 | } |
65cef780 | 2136 | |
5b0a25e8 | 2137 | if (fdctrl->data_pos == fdctrl->data_len) { |
d275b33d | 2138 | /* We have all parameters now, execute the command */ |
5b0a25e8 | 2139 | fdctrl->phase = FD_PHASE_EXECUTION; |
d275b33d | 2140 | |
5b0a25e8 KW |
2141 | if (fdctrl->data_state & FD_STATE_FORMAT) { |
2142 | fdctrl_format_sector(fdctrl); | |
2143 | break; | |
2144 | } | |
2145 | ||
d275b33d KW |
2146 | cmd = get_command(fdctrl->fifo[0]); |
2147 | FLOPPY_DPRINTF("Calling handler for '%s'\n", cmd->name); | |
2148 | cmd->handler(fdctrl, cmd->direction); | |
5b0a25e8 KW |
2149 | } |
2150 | break; | |
2151 | ||
2152 | case FD_PHASE_RESULT: | |
2153 | default: | |
2154 | abort(); | |
8977f3c1 FB |
2155 | } |
2156 | } | |
ed5fd2cc FB |
2157 | |
2158 | static void fdctrl_result_timer(void *opaque) | |
2159 | { | |
5c02c033 BS |
2160 | FDCtrl *fdctrl = opaque; |
2161 | FDrive *cur_drv = get_cur_drv(fdctrl); | |
4f431960 | 2162 | |
b7ffa3b1 TS |
2163 | /* Pretend we are spinning. |
2164 | * This is needed for Coherent, which uses READ ID to check for | |
2165 | * sector interleaving. | |
2166 | */ | |
2167 | if (cur_drv->last_sect != 0) { | |
2168 | cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1; | |
2169 | } | |
844f65d6 HP |
2170 | /* READ_ID can't automatically succeed! */ |
2171 | if (fdctrl->check_media_rate && | |
2172 | (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) { | |
2173 | FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n", | |
2174 | fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate); | |
2175 | fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00); | |
2176 | } else { | |
2177 | fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); | |
2178 | } | |
ed5fd2cc | 2179 | } |
678803ab | 2180 | |
7d4b4ba5 | 2181 | static void fdctrl_change_cb(void *opaque, bool load) |
8e49ca46 MA |
2182 | { |
2183 | FDrive *drive = opaque; | |
2184 | ||
2e1280e8 HR |
2185 | drive->media_inserted = load && drive->blk && blk_is_inserted(drive->blk); |
2186 | ||
8e49ca46 | 2187 | drive->media_changed = 1; |
21fcf360 | 2188 | fd_revalidate(drive); |
8e49ca46 MA |
2189 | } |
2190 | ||
2e1280e8 HR |
2191 | static bool fdctrl_is_tray_open(void *opaque) |
2192 | { | |
2193 | FDrive *drive = opaque; | |
2194 | return !drive->media_inserted; | |
2195 | } | |
2196 | ||
8e49ca46 MA |
2197 | static const BlockDevOps fdctrl_block_ops = { |
2198 | .change_media_cb = fdctrl_change_cb, | |
2e1280e8 | 2199 | .is_tray_open = fdctrl_is_tray_open, |
8e49ca46 MA |
2200 | }; |
2201 | ||
678803ab | 2202 | /* Init functions */ |
a3ef7a61 | 2203 | static void fdctrl_connect_drives(FDCtrl *fdctrl, Error **errp) |
678803ab | 2204 | { |
12a71a02 | 2205 | unsigned int i; |
7d0d6950 | 2206 | FDrive *drive; |
678803ab | 2207 | |
678803ab | 2208 | for (i = 0; i < MAX_FD; i++) { |
7d0d6950 | 2209 | drive = &fdctrl->drives[i]; |
844f65d6 | 2210 | drive->fdctrl = fdctrl; |
7d0d6950 | 2211 | |
4be74634 MA |
2212 | if (drive->blk) { |
2213 | if (blk_get_on_error(drive->blk, 0) != BLOCKDEV_ON_ERROR_ENOSPC) { | |
a3ef7a61 AF |
2214 | error_setg(errp, "fdc doesn't support drive option werror"); |
2215 | return; | |
b47b3525 | 2216 | } |
4be74634 | 2217 | if (blk_get_on_error(drive->blk, 1) != BLOCKDEV_ON_ERROR_REPORT) { |
a3ef7a61 AF |
2218 | error_setg(errp, "fdc doesn't support drive option rerror"); |
2219 | return; | |
b47b3525 MA |
2220 | } |
2221 | } | |
2222 | ||
7d0d6950 | 2223 | fd_init(drive); |
cfb08fba | 2224 | fdctrl_change_cb(drive, 0); |
4be74634 MA |
2225 | if (drive->blk) { |
2226 | blk_set_dev_ops(drive->blk, &fdctrl_block_ops, drive); | |
2e1280e8 | 2227 | drive->media_inserted = blk_is_inserted(drive->blk); |
7d0d6950 | 2228 | } |
678803ab | 2229 | } |
678803ab BS |
2230 | } |
2231 | ||
dfc65f1f MA |
2232 | ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds) |
2233 | { | |
4a17cc4f AF |
2234 | DeviceState *dev; |
2235 | ISADevice *isadev; | |
dfc65f1f | 2236 | |
4a17cc4f AF |
2237 | isadev = isa_try_create(bus, TYPE_ISA_FDC); |
2238 | if (!isadev) { | |
dfc65f1f MA |
2239 | return NULL; |
2240 | } | |
4a17cc4f | 2241 | dev = DEVICE(isadev); |
dfc65f1f MA |
2242 | |
2243 | if (fds[0]) { | |
6231a6da MA |
2244 | qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]), |
2245 | &error_fatal); | |
dfc65f1f MA |
2246 | } |
2247 | if (fds[1]) { | |
6231a6da MA |
2248 | qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]), |
2249 | &error_fatal); | |
dfc65f1f | 2250 | } |
4a17cc4f | 2251 | qdev_init_nofail(dev); |
dfc65f1f | 2252 | |
4a17cc4f | 2253 | return isadev; |
dfc65f1f MA |
2254 | } |
2255 | ||
63ffb564 | 2256 | void fdctrl_init_sysbus(qemu_irq irq, int dma_chann, |
a8170e5e | 2257 | hwaddr mmio_base, DriveInfo **fds) |
2091ba23 | 2258 | { |
5c02c033 | 2259 | FDCtrl *fdctrl; |
2091ba23 | 2260 | DeviceState *dev; |
dd3be742 | 2261 | SysBusDevice *sbd; |
5c02c033 | 2262 | FDCtrlSysBus *sys; |
2091ba23 | 2263 | |
19d46d71 | 2264 | dev = qdev_create(NULL, "sysbus-fdc"); |
dd3be742 | 2265 | sys = SYSBUS_FDC(dev); |
99244fa1 GH |
2266 | fdctrl = &sys->state; |
2267 | fdctrl->dma_chann = dma_chann; /* FIXME */ | |
995bf0ca | 2268 | if (fds[0]) { |
6231a6da MA |
2269 | qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]), |
2270 | &error_fatal); | |
995bf0ca GH |
2271 | } |
2272 | if (fds[1]) { | |
6231a6da MA |
2273 | qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]), |
2274 | &error_fatal); | |
995bf0ca | 2275 | } |
e23a1b33 | 2276 | qdev_init_nofail(dev); |
dd3be742 HT |
2277 | sbd = SYS_BUS_DEVICE(dev); |
2278 | sysbus_connect_irq(sbd, 0, irq); | |
2279 | sysbus_mmio_map(sbd, 0, mmio_base); | |
678803ab BS |
2280 | } |
2281 | ||
a8170e5e | 2282 | void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base, |
63ffb564 | 2283 | DriveInfo **fds, qemu_irq *fdc_tc) |
678803ab | 2284 | { |
f64ab228 | 2285 | DeviceState *dev; |
5c02c033 | 2286 | FDCtrlSysBus *sys; |
678803ab | 2287 | |
12a71a02 | 2288 | dev = qdev_create(NULL, "SUNW,fdtwo"); |
995bf0ca | 2289 | if (fds[0]) { |
6231a6da MA |
2290 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(fds[0]), |
2291 | &error_fatal); | |
995bf0ca | 2292 | } |
e23a1b33 | 2293 | qdev_init_nofail(dev); |
dd3be742 HT |
2294 | sys = SYSBUS_FDC(dev); |
2295 | sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq); | |
2296 | sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base); | |
f64ab228 | 2297 | *fdc_tc = qdev_get_gpio_in(dev, 0); |
678803ab | 2298 | } |
f64ab228 | 2299 | |
a3ef7a61 | 2300 | static void fdctrl_realize_common(FDCtrl *fdctrl, Error **errp) |
f64ab228 | 2301 | { |
12a71a02 BS |
2302 | int i, j; |
2303 | static int command_tables_inited = 0; | |
f64ab228 | 2304 | |
12a71a02 BS |
2305 | /* Fill 'command_to_handler' lookup table */ |
2306 | if (!command_tables_inited) { | |
2307 | command_tables_inited = 1; | |
2308 | for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) { | |
2309 | for (j = 0; j < sizeof(command_to_handler); j++) { | |
2310 | if ((j & handlers[i].mask) == handlers[i].value) { | |
2311 | command_to_handler[j] = i; | |
2312 | } | |
2313 | } | |
2314 | } | |
2315 | } | |
2316 | ||
2317 | FLOPPY_DPRINTF("init controller\n"); | |
2318 | fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN); | |
d7a6c270 | 2319 | fdctrl->fifo_size = 512; |
bc72ad67 | 2320 | fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, |
a3ef7a61 | 2321 | fdctrl_result_timer, fdctrl); |
12a71a02 BS |
2322 | |
2323 | fdctrl->version = 0x90; /* Intel 82078 controller */ | |
2324 | fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */ | |
d7a6c270 | 2325 | fdctrl->num_floppies = MAX_FD; |
12a71a02 | 2326 | |
a3ef7a61 | 2327 | if (fdctrl->dma_chann != -1) { |
99244fa1 | 2328 | DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl); |
a3ef7a61 AF |
2329 | } |
2330 | fdctrl_connect_drives(fdctrl, errp); | |
f64ab228 BS |
2331 | } |
2332 | ||
212ec7ba | 2333 | static const MemoryRegionPortio fdc_portio_list[] = { |
2f290a8c | 2334 | { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write }, |
212ec7ba RH |
2335 | { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write }, |
2336 | PORTIO_END_OF_LIST(), | |
2f290a8c RH |
2337 | }; |
2338 | ||
db895a1e | 2339 | static void isabus_fdc_realize(DeviceState *dev, Error **errp) |
8baf73ad | 2340 | { |
db895a1e | 2341 | ISADevice *isadev = ISA_DEVICE(dev); |
020c8e76 | 2342 | FDCtrlISABus *isa = ISA_FDC(dev); |
5c02c033 | 2343 | FDCtrl *fdctrl = &isa->state; |
a3ef7a61 | 2344 | Error *err = NULL; |
8baf73ad | 2345 | |
db895a1e AF |
2346 | isa_register_portio_list(isadev, isa->iobase, fdc_portio_list, fdctrl, |
2347 | "fdc"); | |
dee41d58 | 2348 | |
db895a1e | 2349 | isa_init_irq(isadev, &fdctrl->irq, isa->irq); |
c9ae703d | 2350 | fdctrl->dma_chann = isa->dma; |
8baf73ad | 2351 | |
db895a1e | 2352 | qdev_set_legacy_instance_id(dev, isa->iobase, 2); |
a3ef7a61 AF |
2353 | fdctrl_realize_common(fdctrl, &err); |
2354 | if (err != NULL) { | |
2355 | error_propagate(errp, err); | |
db895a1e AF |
2356 | return; |
2357 | } | |
8baf73ad GH |
2358 | } |
2359 | ||
940194c2 | 2360 | static void sysbus_fdc_initfn(Object *obj) |
12a71a02 | 2361 | { |
19d46d71 | 2362 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
940194c2 | 2363 | FDCtrlSysBus *sys = SYSBUS_FDC(obj); |
5c02c033 | 2364 | FDCtrl *fdctrl = &sys->state; |
12a71a02 | 2365 | |
19d46d71 AF |
2366 | fdctrl->dma_chann = -1; |
2367 | ||
940194c2 | 2368 | memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl, |
2d256e6f | 2369 | "fdc", 0x08); |
19d46d71 | 2370 | sysbus_init_mmio(sbd, &fdctrl->iomem); |
940194c2 HT |
2371 | } |
2372 | ||
19d46d71 | 2373 | static void sun4m_fdc_initfn(Object *obj) |
940194c2 | 2374 | { |
19d46d71 AF |
2375 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
2376 | FDCtrlSysBus *sys = SYSBUS_FDC(obj); | |
940194c2 | 2377 | FDCtrl *fdctrl = &sys->state; |
940194c2 | 2378 | |
19d46d71 AF |
2379 | memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops, |
2380 | fdctrl, "fdctrl", 0x08); | |
2381 | sysbus_init_mmio(sbd, &fdctrl->iomem); | |
940194c2 | 2382 | } |
2be37833 | 2383 | |
19d46d71 | 2384 | static void sysbus_fdc_common_initfn(Object *obj) |
940194c2 | 2385 | { |
19d46d71 AF |
2386 | DeviceState *dev = DEVICE(obj); |
2387 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
940194c2 HT |
2388 | FDCtrlSysBus *sys = SYSBUS_FDC(obj); |
2389 | FDCtrl *fdctrl = &sys->state; | |
2390 | ||
19d46d71 AF |
2391 | qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */ |
2392 | ||
2393 | sysbus_init_irq(sbd, &fdctrl->irq); | |
2394 | qdev_init_gpio_in(dev, fdctrl_handle_tc, 1); | |
12a71a02 BS |
2395 | } |
2396 | ||
19d46d71 | 2397 | static void sysbus_fdc_common_realize(DeviceState *dev, Error **errp) |
12a71a02 | 2398 | { |
dd3be742 HT |
2399 | FDCtrlSysBus *sys = SYSBUS_FDC(dev); |
2400 | FDCtrl *fdctrl = &sys->state; | |
12a71a02 | 2401 | |
19d46d71 | 2402 | fdctrl_realize_common(fdctrl, errp); |
12a71a02 | 2403 | } |
f64ab228 | 2404 | |
2da44dd0 | 2405 | FloppyDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i) |
34d4260e | 2406 | { |
020c8e76 | 2407 | FDCtrlISABus *isa = ISA_FDC(fdc); |
34d4260e | 2408 | |
61a8d649 | 2409 | return isa->state.drives[i].drive; |
34d4260e KW |
2410 | } |
2411 | ||
a64405d1 JK |
2412 | static const VMStateDescription vmstate_isa_fdc ={ |
2413 | .name = "fdc", | |
2414 | .version_id = 2, | |
2415 | .minimum_version_id = 2, | |
d49805ae | 2416 | .fields = (VMStateField[]) { |
a64405d1 JK |
2417 | VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl), |
2418 | VMSTATE_END_OF_LIST() | |
2419 | } | |
2420 | }; | |
2421 | ||
39bffca2 | 2422 | static Property isa_fdc_properties[] = { |
c7bcc85d | 2423 | DEFINE_PROP_UINT32("iobase", FDCtrlISABus, iobase, 0x3f0), |
c9ae703d HP |
2424 | DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6), |
2425 | DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2), | |
4be74634 MA |
2426 | DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].blk), |
2427 | DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].blk), | |
09c6d585 HP |
2428 | DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate, |
2429 | 0, true), | |
39bffca2 AL |
2430 | DEFINE_PROP_END_OF_LIST(), |
2431 | }; | |
2432 | ||
020c8e76 | 2433 | static void isabus_fdc_class_init(ObjectClass *klass, void *data) |
8f04ee08 | 2434 | { |
39bffca2 | 2435 | DeviceClass *dc = DEVICE_CLASS(klass); |
db895a1e AF |
2436 | |
2437 | dc->realize = isabus_fdc_realize; | |
39bffca2 | 2438 | dc->fw_name = "fdc"; |
39bffca2 AL |
2439 | dc->reset = fdctrl_external_reset_isa; |
2440 | dc->vmsd = &vmstate_isa_fdc; | |
2441 | dc->props = isa_fdc_properties; | |
125ee0ed | 2442 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
39bffca2 AL |
2443 | } |
2444 | ||
81782b6a GA |
2445 | static void isabus_fdc_instance_init(Object *obj) |
2446 | { | |
2447 | FDCtrlISABus *isa = ISA_FDC(obj); | |
2448 | ||
2449 | device_add_bootindex_property(obj, &isa->bootindexA, | |
2450 | "bootindexA", "/floppy@0", | |
2451 | DEVICE(obj), NULL); | |
2452 | device_add_bootindex_property(obj, &isa->bootindexB, | |
2453 | "bootindexB", "/floppy@1", | |
2454 | DEVICE(obj), NULL); | |
2455 | } | |
2456 | ||
8c43a6f0 | 2457 | static const TypeInfo isa_fdc_info = { |
020c8e76 | 2458 | .name = TYPE_ISA_FDC, |
39bffca2 AL |
2459 | .parent = TYPE_ISA_DEVICE, |
2460 | .instance_size = sizeof(FDCtrlISABus), | |
020c8e76 | 2461 | .class_init = isabus_fdc_class_init, |
81782b6a | 2462 | .instance_init = isabus_fdc_instance_init, |
8baf73ad GH |
2463 | }; |
2464 | ||
a64405d1 JK |
2465 | static const VMStateDescription vmstate_sysbus_fdc ={ |
2466 | .name = "fdc", | |
2467 | .version_id = 2, | |
2468 | .minimum_version_id = 2, | |
d49805ae | 2469 | .fields = (VMStateField[]) { |
a64405d1 JK |
2470 | VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl), |
2471 | VMSTATE_END_OF_LIST() | |
2472 | } | |
2473 | }; | |
2474 | ||
999e12bb | 2475 | static Property sysbus_fdc_properties[] = { |
4be74634 MA |
2476 | DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].blk), |
2477 | DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].blk), | |
999e12bb | 2478 | DEFINE_PROP_END_OF_LIST(), |
12a71a02 BS |
2479 | }; |
2480 | ||
999e12bb AL |
2481 | static void sysbus_fdc_class_init(ObjectClass *klass, void *data) |
2482 | { | |
39bffca2 | 2483 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 2484 | |
39bffca2 | 2485 | dc->props = sysbus_fdc_properties; |
125ee0ed | 2486 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
999e12bb AL |
2487 | } |
2488 | ||
8c43a6f0 | 2489 | static const TypeInfo sysbus_fdc_info = { |
19d46d71 AF |
2490 | .name = "sysbus-fdc", |
2491 | .parent = TYPE_SYSBUS_FDC, | |
940194c2 | 2492 | .instance_init = sysbus_fdc_initfn, |
39bffca2 | 2493 | .class_init = sysbus_fdc_class_init, |
999e12bb AL |
2494 | }; |
2495 | ||
2496 | static Property sun4m_fdc_properties[] = { | |
4be74634 | 2497 | DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].blk), |
999e12bb AL |
2498 | DEFINE_PROP_END_OF_LIST(), |
2499 | }; | |
2500 | ||
2501 | static void sun4m_fdc_class_init(ObjectClass *klass, void *data) | |
2502 | { | |
39bffca2 | 2503 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 2504 | |
39bffca2 | 2505 | dc->props = sun4m_fdc_properties; |
125ee0ed | 2506 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
999e12bb AL |
2507 | } |
2508 | ||
8c43a6f0 | 2509 | static const TypeInfo sun4m_fdc_info = { |
39bffca2 | 2510 | .name = "SUNW,fdtwo", |
19d46d71 | 2511 | .parent = TYPE_SYSBUS_FDC, |
940194c2 | 2512 | .instance_init = sun4m_fdc_initfn, |
39bffca2 | 2513 | .class_init = sun4m_fdc_class_init, |
f64ab228 BS |
2514 | }; |
2515 | ||
19d46d71 AF |
2516 | static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data) |
2517 | { | |
2518 | DeviceClass *dc = DEVICE_CLASS(klass); | |
2519 | ||
2520 | dc->realize = sysbus_fdc_common_realize; | |
2521 | dc->reset = fdctrl_external_reset_sysbus; | |
2522 | dc->vmsd = &vmstate_sysbus_fdc; | |
2523 | } | |
2524 | ||
2525 | static const TypeInfo sysbus_fdc_type_info = { | |
2526 | .name = TYPE_SYSBUS_FDC, | |
2527 | .parent = TYPE_SYS_BUS_DEVICE, | |
2528 | .instance_size = sizeof(FDCtrlSysBus), | |
2529 | .instance_init = sysbus_fdc_common_initfn, | |
2530 | .abstract = true, | |
2531 | .class_init = sysbus_fdc_common_class_init, | |
2532 | }; | |
2533 | ||
83f7d43a | 2534 | static void fdc_register_types(void) |
f64ab228 | 2535 | { |
39bffca2 | 2536 | type_register_static(&isa_fdc_info); |
19d46d71 | 2537 | type_register_static(&sysbus_fdc_type_info); |
39bffca2 AL |
2538 | type_register_static(&sysbus_fdc_info); |
2539 | type_register_static(&sun4m_fdc_info); | |
f64ab228 BS |
2540 | } |
2541 | ||
83f7d43a | 2542 | type_init(fdc_register_types) |