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fdc: Switch to byte-based block access
[mirror_qemu.git] / hw / block / fdc.c
CommitLineData
8977f3c1 1/*
890fa6be 2 * QEMU Floppy disk emulator (Intel 82078)
5fafdf24 3 *
3ccacc4a 4 * Copyright (c) 2003, 2007 Jocelyn Mayer
bcc4e41f 5 * Copyright (c) 2008 Hervé Poussineau
5fafdf24 6 *
8977f3c1
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
e80cfcfc
FB		 25/*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
f64ab228 29
80c71a24 30#include "qemu/osdep.h"
83c9f4ca 31#include "hw/hw.h"
0d09e41a 32#include "hw/block/fdc.h"
da34e65c 33#include "qapi/error.h"
1de7afc9
PB		 34#include "qemu/error-report.h"
35#include "qemu/timer.h"
0d09e41a 36#include "hw/isa/isa.h"
83c9f4ca 37#include "hw/sysbus.h"
fa1d36df 38#include "sysemu/block-backend.h"
9c17d615
PB		 39#include "sysemu/blockdev.h"
40#include "sysemu/sysemu.h"
1de7afc9 41#include "qemu/log.h"
8977f3c1
FB		 42
43/********************************************************/
44/* debug Floppy devices */
8977f3c1 45
c691320f
JS		 46#define DEBUG_FLOPPY 0
47
001faf32 48#define FLOPPY_DPRINTF(fmt, ...) \
c691320f
JS		 49 do { \
50 if (DEBUG_FLOPPY) { \
51 fprintf(stderr, "FLOPPY: " fmt , ## __VA_ARGS__); \
52 } \
53 } while (0)
8977f3c1 54
8977f3c1
FB		 55/********************************************************/
56/* Floppy drive emulation */
57
61a8d649
MA		 58typedef enum FDriveRate {
59 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */
60 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */
61 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */
62 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */
63} FDriveRate;
64
109c17bc
JS		 65typedef enum FDriveSize {
66 FDRIVE_SIZE_UNKNOWN,
67 FDRIVE_SIZE_350,
68 FDRIVE_SIZE_525,
69} FDriveSize;
70
61a8d649 71typedef struct FDFormat {
2da44dd0 72 FloppyDriveType drive;
61a8d649
MA		 73 uint8_t last_sect;
74 uint8_t max_track;
75 uint8_t max_head;
76 FDriveRate rate;
77} FDFormat;
78
109c17bc
JS		 79/* In many cases, the total sector size of a format is enough to uniquely
80 * identify it. However, there are some total sector collisions between
81 * formats of different physical size, and these are noted below by
82 * highlighting the total sector size for entries with collisions. */
61a8d649
MA		 83static const FDFormat fd_formats[] = {
84 /* First entry is default format */
85 /* 1.44 MB 3"1/2 floppy disks */
109c17bc
JS		 86 { FLOPPY_DRIVE_TYPE_144, 18, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 2880 */
87 { FLOPPY_DRIVE_TYPE_144, 20, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 3200 */
2da44dd0
JS		 88 { FLOPPY_DRIVE_TYPE_144, 21, 80, 1, FDRIVE_RATE_500K, },
89 { FLOPPY_DRIVE_TYPE_144, 21, 82, 1, FDRIVE_RATE_500K, },
90 { FLOPPY_DRIVE_TYPE_144, 21, 83, 1, FDRIVE_RATE_500K, },
91 { FLOPPY_DRIVE_TYPE_144, 22, 80, 1, FDRIVE_RATE_500K, },
92 { FLOPPY_DRIVE_TYPE_144, 23, 80, 1, FDRIVE_RATE_500K, },
93 { FLOPPY_DRIVE_TYPE_144, 24, 80, 1, FDRIVE_RATE_500K, },
61a8d649 94 /* 2.88 MB 3"1/2 floppy disks */
2da44dd0
JS		 95 { FLOPPY_DRIVE_TYPE_288, 36, 80, 1, FDRIVE_RATE_1M, },
96 { FLOPPY_DRIVE_TYPE_288, 39, 80, 1, FDRIVE_RATE_1M, },
97 { FLOPPY_DRIVE_TYPE_288, 40, 80, 1, FDRIVE_RATE_1M, },
98 { FLOPPY_DRIVE_TYPE_288, 44, 80, 1, FDRIVE_RATE_1M, },
99 { FLOPPY_DRIVE_TYPE_288, 48, 80, 1, FDRIVE_RATE_1M, },
61a8d649 100 /* 720 kB 3"1/2 floppy disks */
109c17bc 101 { FLOPPY_DRIVE_TYPE_144, 9, 80, 1, FDRIVE_RATE_250K, }, /* 3.5" 1440 */
2da44dd0
JS		 102 { FLOPPY_DRIVE_TYPE_144, 10, 80, 1, FDRIVE_RATE_250K, },
103 { FLOPPY_DRIVE_TYPE_144, 10, 82, 1, FDRIVE_RATE_250K, },
104 { FLOPPY_DRIVE_TYPE_144, 10, 83, 1, FDRIVE_RATE_250K, },
105 { FLOPPY_DRIVE_TYPE_144, 13, 80, 1, FDRIVE_RATE_250K, },
106 { FLOPPY_DRIVE_TYPE_144, 14, 80, 1, FDRIVE_RATE_250K, },
61a8d649 107 /* 1.2 MB 5"1/4 floppy disks */
2da44dd0 108 { FLOPPY_DRIVE_TYPE_120, 15, 80, 1, FDRIVE_RATE_500K, },
109c17bc 109 { FLOPPY_DRIVE_TYPE_120, 18, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 2880 */
2da44dd0
JS		 110 { FLOPPY_DRIVE_TYPE_120, 18, 82, 1, FDRIVE_RATE_500K, },
111 { FLOPPY_DRIVE_TYPE_120, 18, 83, 1, FDRIVE_RATE_500K, },
109c17bc 112 { FLOPPY_DRIVE_TYPE_120, 20, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 3200 */
61a8d649 113 /* 720 kB 5"1/4 floppy disks */
109c17bc 114 { FLOPPY_DRIVE_TYPE_120, 9, 80, 1, FDRIVE_RATE_250K, }, /* 5.25" 1440 */
2da44dd0 115 { FLOPPY_DRIVE_TYPE_120, 11, 80, 1, FDRIVE_RATE_250K, },
61a8d649 116 /* 360 kB 5"1/4 floppy disks */
109c17bc 117 { FLOPPY_DRIVE_TYPE_120, 9, 40, 1, FDRIVE_RATE_300K, }, /* 5.25" 720 */
2da44dd0
JS		 118 { FLOPPY_DRIVE_TYPE_120, 9, 40, 0, FDRIVE_RATE_300K, },
119 { FLOPPY_DRIVE_TYPE_120, 10, 41, 1, FDRIVE_RATE_300K, },
120 { FLOPPY_DRIVE_TYPE_120, 10, 42, 1, FDRIVE_RATE_300K, },
61a8d649 121 /* 320 kB 5"1/4 floppy disks */
2da44dd0
JS		 122 { FLOPPY_DRIVE_TYPE_120, 8, 40, 1, FDRIVE_RATE_250K, },
123 { FLOPPY_DRIVE_TYPE_120, 8, 40, 0, FDRIVE_RATE_250K, },
61a8d649 124 /* 360 kB must match 5"1/4 better than 3"1/2... */
109c17bc 125 { FLOPPY_DRIVE_TYPE_144, 9, 80, 0, FDRIVE_RATE_250K, }, /* 3.5" 720 */
61a8d649 126 /* end */
2da44dd0 127 { FLOPPY_DRIVE_TYPE_NONE, -1, -1, 0, 0, },
61a8d649
MA		 128};
129
109c17bc
JS		 130static FDriveSize drive_size(FloppyDriveType drive)
131{
132 switch (drive) {
133 case FLOPPY_DRIVE_TYPE_120:
134 return FDRIVE_SIZE_525;
135 case FLOPPY_DRIVE_TYPE_144:
136 case FLOPPY_DRIVE_TYPE_288:
137 return FDRIVE_SIZE_350;
138 default:
139 return FDRIVE_SIZE_UNKNOWN;
140 }
141}
142
cefec4f5
BS		 143#define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
144#define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
145
8977f3c1 146/* Will always be a fixed parameter for us */
f2d81b33
BS		 147#define FD_SECTOR_LEN 512
148#define FD_SECTOR_SC 2 /* Sector size code */
149#define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
8977f3c1 150
844f65d6
HP		 151typedef struct FDCtrl FDCtrl;
152
8977f3c1 153/* Floppy disk drive emulation */
5c02c033 154typedef enum FDiskFlags {
baca51fa 155 FDISK_DBL_SIDES = 0x01,
5c02c033 156} FDiskFlags;
baca51fa 157
5c02c033 158typedef struct FDrive {
844f65d6 159 FDCtrl *fdctrl;
4be74634 160 BlockBackend *blk;
8977f3c1 161 /* Drive status */
2da44dd0 162 FloppyDriveType drive; /* CMOS drive type */
8977f3c1 163 uint8_t perpendicular; /* 2.88 MB access mode */
8977f3c1
FB		 164 /* Position */
165 uint8_t head;
166 uint8_t track;
167 uint8_t sect;
8977f3c1 168 /* Media */
16c1e3ec 169 FloppyDriveType disk; /* Current disk type */
5c02c033 170 FDiskFlags flags;
8977f3c1
FB		 171 uint8_t last_sect; /* Nb sector per track */
172 uint8_t max_track; /* Nb of tracks */
baca51fa 173 uint16_t bps; /* Bytes per sector */
8977f3c1 174 uint8_t ro; /* Is read-only */
7d905f71 175 uint8_t media_changed; /* Is media changed */
844f65d6 176 uint8_t media_rate; /* Data rate of medium */
2e1280e8 177
d5d47efc 178 bool media_validated; /* Have we validated the media? */
5c02c033 179} FDrive;
8977f3c1 180
a73275dd
JS		 181
182static FloppyDriveType get_fallback_drive_type(FDrive *drv);
183
fd9bdbd3
JS		 184/* Hack: FD_SEEK is expected to work on empty drives. However, QEMU
185 * currently goes through some pains to keep seeks within the bounds
186 * established by last_sect and max_track. Correcting this is difficult,
187 * as refactoring FDC code tends to expose nasty bugs in the Linux kernel.
188 *
189 * For now: allow empty drives to have large bounds so we can seek around,
190 * with the understanding that when a diskette is inserted, the bounds will
191 * properly tighten to match the geometry of that inserted medium.
192 */
193static void fd_empty_seek_hack(FDrive *drv)
194{
195 drv->last_sect = 0xFF;
196 drv->max_track = 0xFF;
197}
198
5c02c033 199static void fd_init(FDrive *drv)
8977f3c1
FB		 200{
201 /* Drive */
8977f3c1 202 drv->perpendicular = 0;
8977f3c1 203 /* Disk */
16c1e3ec 204 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
baca51fa 205 drv->last_sect = 0;
8977f3c1 206 drv->max_track = 0;
d5d47efc
JS		 207 drv->ro = true;
208 drv->media_changed = 1;
8977f3c1
FB		 209}
210
08388273
HP		 211#define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
212
7859cb98 213static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
08388273 214 uint8_t last_sect, uint8_t num_sides)
8977f3c1 215{
08388273 216 return (((track * num_sides) + head) * last_sect) + sect - 1;
8977f3c1
FB		 217}
218
219/* Returns current position, in sectors, for given drive */
5c02c033 220static int fd_sector(FDrive *drv)
8977f3c1 221{
08388273
HP		 222 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
223 NUM_SIDES(drv));
8977f3c1
FB		 224}
225
a7a5b7c0
EB		 226/* Returns current position, in bytes, for given drive */
227static int fd_offset(FDrive *drv)
228{
229 g_assert(fd_sector(drv) < INT_MAX >> BDRV_SECTOR_BITS);
230 return fd_sector(drv) << BDRV_SECTOR_BITS;
231}
232
77370520
BS		 233/* Seek to a new position:
234 * returns 0 if already on right track
235 * returns 1 if track changed
236 * returns 2 if track is invalid
237 * returns 3 if sector is invalid
238 * returns 4 if seek is disabled
239 */
5c02c033
BS		 240static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
241 int enable_seek)
8977f3c1
FB		 242{
243 uint32_t sector;
baca51fa
FB		 244 int ret;
245
246 if (track > drv->max_track ||
4f431960 247 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
ed5fd2cc
FB		 248 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
249 head, track, sect, 1,
250 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
251 drv->max_track, drv->last_sect);
8977f3c1
FB		 252 return 2;
253 }
254 if (sect > drv->last_sect) {
ed5fd2cc
FB		 255 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
256 head, track, sect, 1,
257 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
258 drv->max_track, drv->last_sect);
8977f3c1
FB		 259 return 3;
260 }
08388273 261 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
baca51fa 262 ret = 0;
8977f3c1
FB		 263 if (sector != fd_sector(drv)) {
264#if 0
265 if (!enable_seek) {
cced7a13
BS		 266 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x"
267 " (max=%d %02x %02x)\n",
268 head, track, sect, 1, drv->max_track,
269 drv->last_sect);
8977f3c1
FB		 270 return 4;
271 }
272#endif
273 drv->head = head;
6be01b1e 274 if (drv->track != track) {
abb3e55b 275 if (drv->blk != NULL && blk_is_inserted(drv->blk)) {
6be01b1e
PH		 276 drv->media_changed = 0;
277 }
4f431960 278 ret = 1;
6be01b1e 279 }
8977f3c1
FB		 280 drv->track = track;
281 drv->sect = sect;
8977f3c1
FB		 282 }
283
abb3e55b 284 if (drv->blk == NULL || !blk_is_inserted(drv->blk)) {
c52acf60
PH		 285 ret = 2;
286 }
287
baca51fa 288 return ret;
8977f3c1
FB		 289}
290
291/* Set drive back to track 0 */
5c02c033 292static void fd_recalibrate(FDrive *drv)
8977f3c1
FB		 293{
294 FLOPPY_DPRINTF("recalibrate\n");
6be01b1e 295 fd_seek(drv, 0, 0, 1, 1);
8977f3c1
FB		 296}
297
d5d47efc
JS		 298/**
299 * Determine geometry based on inserted diskette.
300 * Will not operate on an empty drive.
301 *
302 * @return: 0 on success, -1 if the drive is empty.
303 */
304static int pick_geometry(FDrive *drv)
9a972233 305{
21862658 306 BlockBackend *blk = drv->blk;
9a972233
JS		 307 const FDFormat *parse;
308 uint64_t nb_sectors, size;
f31937aa
JS		 309 int i;
310 int match, size_match, type_match;
311 bool magic = drv->drive == FLOPPY_DRIVE_TYPE_AUTO;
9a972233 312
d5d47efc 313 /* We can only pick a geometry if we have a diskette. */
abb3e55b
HR		 314 if (!drv->blk || !blk_is_inserted(drv->blk) ||
315 drv->drive == FLOPPY_DRIVE_TYPE_NONE)
316 {
d5d47efc
JS		 317 return -1;
318 }
319
f31937aa
JS		 320 /* We need to determine the likely geometry of the inserted medium.
321 * In order of preference, we look for:
322 * (1) The same drive type and number of sectors,
323 * (2) The same diskette size and number of sectors,
324 * (3) The same drive type.
325 *
326 * In all cases, matches that occur higher in the drive table will take
327 * precedence over matches that occur later in the table.
328 */
9a972233 329 blk_get_geometry(blk, &nb_sectors);
f31937aa 330 match = size_match = type_match = -1;
9a972233
JS		 331 for (i = 0; ; i++) {
332 parse = &fd_formats[i];
2da44dd0 333 if (parse->drive == FLOPPY_DRIVE_TYPE_NONE) {
9a972233
JS		 334 break;
335 }
f31937aa
JS		 336 size = (parse->max_head + 1) * parse->max_track * parse->last_sect;
337 if (nb_sectors == size) {
338 if (magic || parse->drive == drv->drive) {
339 /* (1) perfect match -- nb_sectors and drive type */
340 goto out;
341 } else if (drive_size(parse->drive) == drive_size(drv->drive)) {
342 /* (2) size match -- nb_sectors and physical medium size */
343 match = (match == -1) ? i : match;
344 } else {
345 /* This is suspicious -- Did the user misconfigure? */
346 size_match = (size_match == -1) ? i : size_match;
9a972233 347 }
f31937aa
JS		 348 } else if (type_match == -1) {
349 if ((parse->drive == drv->drive) ||
350 (magic && (parse->drive == get_fallback_drive_type(drv)))) {
351 /* (3) type match -- nb_sectors mismatch, but matches the type
352 * specified explicitly by the user, or matches the fallback
353 * default type when using the drive autodetect mechanism */
354 type_match = i;
9a972233
JS		 355 }
356 }
357 }
f31937aa
JS		 358
359 /* No exact match found */
9a972233 360 if (match == -1) {
f31937aa
JS		 361 if (size_match != -1) {
362 parse = &fd_formats[size_match];
363 FLOPPY_DPRINTF("User requested floppy drive type '%s', "
364 "but inserted medium appears to be a "
c691320f 365 "%"PRId64" sector '%s' type\n",
f31937aa
JS		 366 FloppyDriveType_lookup[drv->drive],
367 nb_sectors,
368 FloppyDriveType_lookup[parse->drive]);
9a972233 369 }
f31937aa 370 match = type_match;
9a972233 371 }
21862658 372
f31937aa
JS		 373 /* No match of any kind found -- fd_format is misconfigured, abort. */
374 if (match == -1) {
375 error_setg(&error_abort, "No candidate geometries present in table "
376 " for floppy drive type '%s'",
377 FloppyDriveType_lookup[drv->drive]);
378 }
379
380 parse = &(fd_formats[match]);
381
382 out:
21862658
JS		 383 if (parse->max_head == 0) {
384 drv->flags &= ~FDISK_DBL_SIDES;
385 } else {
386 drv->flags |= FDISK_DBL_SIDES;
387 }
388 drv->max_track = parse->max_track;
389 drv->last_sect = parse->last_sect;
d5d47efc 390 drv->disk = parse->drive;
21862658 391 drv->media_rate = parse->rate;
d5d47efc
JS		 392 return 0;
393}
394
395static void pick_drive_type(FDrive *drv)
396{
fff4687b
JS		 397 if (drv->drive != FLOPPY_DRIVE_TYPE_AUTO) {
398 return;
399 }
400
d5d47efc
JS		 401 if (pick_geometry(drv) == 0) {
402 drv->drive = drv->disk;
403 } else {
a73275dd 404 drv->drive = get_fallback_drive_type(drv);
d5d47efc 405 }
fff4687b
JS		 406
407 g_assert(drv->drive != FLOPPY_DRIVE_TYPE_AUTO);
9a972233
JS		 408}
409
8977f3c1 410/* Revalidate a disk drive after a disk change */
5c02c033 411static void fd_revalidate(FDrive *drv)
8977f3c1 412{
d5d47efc
JS		 413 int rc;
414
8977f3c1 415 FLOPPY_DPRINTF("revalidate\n");
4be74634 416 if (drv->blk != NULL) {
21862658 417 drv->ro = blk_is_read_only(drv->blk);
abb3e55b 418 if (!blk_is_inserted(drv->blk)) {
cfb08fba 419 FLOPPY_DPRINTF("No disk in drive\n");
d5d47efc 420 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
fd9bdbd3 421 fd_empty_seek_hack(drv);
d5d47efc
JS		 422 } else if (!drv->media_validated) {
423 rc = pick_geometry(drv);
424 if (rc) {
425 FLOPPY_DPRINTF("Could not validate floppy drive media");
426 } else {
427 drv->media_validated = true;
428 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n",
429 (drv->flags & FDISK_DBL_SIDES) ? 2 : 1,
430 drv->max_track, drv->last_sect,
431 drv->ro ? "ro" : "rw");
432 }
4f431960 433 }
8977f3c1 434 } else {
cfb08fba 435 FLOPPY_DPRINTF("No drive connected\n");
baca51fa 436 drv->last_sect = 0;
4f431960
JM		 437 drv->max_track = 0;
438 drv->flags &= ~FDISK_DBL_SIDES;
d5d47efc
JS		 439 drv->drive = FLOPPY_DRIVE_TYPE_NONE;
440 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
8977f3c1 441 }
caed8802
FB		 442}
443
8977f3c1 444/********************************************************/
4b19ec0c 445/* Intel 82078 floppy disk controller emulation */
8977f3c1 446
5c02c033 447static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
07e415f2 448static void fdctrl_to_command_phase(FDCtrl *fdctrl);
85571bc7 449static int fdctrl_transfer_handler (void *opaque, int nchan,
c227f099 450 int dma_pos, int dma_len);
d497d534 451static void fdctrl_raise_irq(FDCtrl *fdctrl);
a2df5fa3 452static FDrive *get_cur_drv(FDCtrl *fdctrl);
5c02c033
BS		 453
454static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
455static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
456static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
457static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
458static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
459static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
460static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
461static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
462static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
463static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
464static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
a758f8f4 465static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
8977f3c1 466
8977f3c1
FB		 467enum {
468 FD_DIR_WRITE = 0,
469 FD_DIR_READ = 1,
470 FD_DIR_SCANE = 2,
471 FD_DIR_SCANL = 3,
472 FD_DIR_SCANH = 4,
7ea004ed 473 FD_DIR_VERIFY = 5,
8977f3c1
FB		 474};
475
476enum {
b9b3d225
BS		 477 FD_STATE_MULTI = 0x01, /* multi track flag */
478 FD_STATE_FORMAT = 0x02, /* format flag */
8977f3c1
FB		 479};
480
9fea808a 481enum {
8c6a4d77
BS		 482 FD_REG_SRA = 0x00,
483 FD_REG_SRB = 0x01,
9fea808a
BS		 484 FD_REG_DOR = 0x02,
485 FD_REG_TDR = 0x03,
486 FD_REG_MSR = 0x04,
487 FD_REG_DSR = 0x04,
488 FD_REG_FIFO = 0x05,
489 FD_REG_DIR = 0x07,
a758f8f4 490 FD_REG_CCR = 0x07,
9fea808a
BS		 491};
492
493enum {
65cef780 494 FD_CMD_READ_TRACK = 0x02,
9fea808a
BS		 495 FD_CMD_SPECIFY = 0x03,
496 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
65cef780
BS		 497 FD_CMD_WRITE = 0x05,
498 FD_CMD_READ = 0x06,
9fea808a
BS		 499 FD_CMD_RECALIBRATE = 0x07,
500 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
65cef780
BS		 501 FD_CMD_WRITE_DELETED = 0x09,
502 FD_CMD_READ_ID = 0x0a,
503 FD_CMD_READ_DELETED = 0x0c,
504 FD_CMD_FORMAT_TRACK = 0x0d,
9fea808a
BS		 505 FD_CMD_DUMPREG = 0x0e,
506 FD_CMD_SEEK = 0x0f,
507 FD_CMD_VERSION = 0x10,
65cef780 508 FD_CMD_SCAN_EQUAL = 0x11,
9fea808a
BS		 509 FD_CMD_PERPENDICULAR_MODE = 0x12,
510 FD_CMD_CONFIGURE = 0x13,
65cef780
BS		 511 FD_CMD_LOCK = 0x14,
512 FD_CMD_VERIFY = 0x16,
9fea808a
BS		 513 FD_CMD_POWERDOWN_MODE = 0x17,
514 FD_CMD_PART_ID = 0x18,
65cef780
BS		 515 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
516 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
bb350a5e 517 FD_CMD_SAVE = 0x2e,
9fea808a 518 FD_CMD_OPTION = 0x33,
bb350a5e 519 FD_CMD_RESTORE = 0x4e,
9fea808a
BS		 520 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
521 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
9fea808a
BS		 522 FD_CMD_FORMAT_AND_WRITE = 0xcd,
523 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
524};
525
526enum {
527 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
528 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
529 FD_CONFIG_POLL = 0x10, /* Poll enabled */
530 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
531 FD_CONFIG_EIS = 0x40, /* No implied seeks */
532};
533
534enum {
2fee0088
PH		 535 FD_SR0_DS0 = 0x01,
536 FD_SR0_DS1 = 0x02,
537 FD_SR0_HEAD = 0x04,
9fea808a
BS		 538 FD_SR0_EQPMT = 0x10,
539 FD_SR0_SEEK = 0x20,
540 FD_SR0_ABNTERM = 0x40,
541 FD_SR0_INVCMD = 0x80,
542 FD_SR0_RDYCHG = 0xc0,
543};
544
77370520 545enum {
844f65d6 546 FD_SR1_MA = 0x01, /* Missing address mark */
8510854e 547 FD_SR1_NW = 0x02, /* Not writable */
77370520
BS		 548 FD_SR1_EC = 0x80, /* End of cylinder */
549};
550
551enum {
552 FD_SR2_SNS = 0x04, /* Scan not satisfied */
553 FD_SR2_SEH = 0x08, /* Scan equal hit */
554};
555
8c6a4d77
BS		 556enum {
557 FD_SRA_DIR = 0x01,
558 FD_SRA_nWP = 0x02,
559 FD_SRA_nINDX = 0x04,
560 FD_SRA_HDSEL = 0x08,
561 FD_SRA_nTRK0 = 0x10,
562 FD_SRA_STEP = 0x20,
563 FD_SRA_nDRV2 = 0x40,
564 FD_SRA_INTPEND = 0x80,
565};
566
567enum {
568 FD_SRB_MTR0 = 0x01,
569 FD_SRB_MTR1 = 0x02,
570 FD_SRB_WGATE = 0x04,
571 FD_SRB_RDATA = 0x08,
572 FD_SRB_WDATA = 0x10,
573 FD_SRB_DR0 = 0x20,
574};
575
9fea808a 576enum {
78ae820c
BS		 577#if MAX_FD == 4
578 FD_DOR_SELMASK = 0x03,
579#else
9fea808a 580 FD_DOR_SELMASK = 0x01,
78ae820c 581#endif
9fea808a
BS		 582 FD_DOR_nRESET = 0x04,
583 FD_DOR_DMAEN = 0x08,
584 FD_DOR_MOTEN0 = 0x10,
585 FD_DOR_MOTEN1 = 0x20,
586 FD_DOR_MOTEN2 = 0x40,
587 FD_DOR_MOTEN3 = 0x80,
588};
589
590enum {
78ae820c 591#if MAX_FD == 4
9fea808a 592 FD_TDR_BOOTSEL = 0x0c,
78ae820c
BS		 593#else
594 FD_TDR_BOOTSEL = 0x04,
595#endif
9fea808a
BS		 596};
597
598enum {
599 FD_DSR_DRATEMASK= 0x03,
600 FD_DSR_PWRDOWN = 0x40,
601 FD_DSR_SWRESET = 0x80,
602};
603
604enum {
605 FD_MSR_DRV0BUSY = 0x01,
606 FD_MSR_DRV1BUSY = 0x02,
607 FD_MSR_DRV2BUSY = 0x04,
608 FD_MSR_DRV3BUSY = 0x08,
609 FD_MSR_CMDBUSY = 0x10,
610 FD_MSR_NONDMA = 0x20,
611 FD_MSR_DIO = 0x40,
612 FD_MSR_RQM = 0x80,
613};
614
615enum {
616 FD_DIR_DSKCHG = 0x80,
617};
618
85d291a0
KW		 619/*
620 * See chapter 5.0 "Controller phases" of the spec:
621 *
622 * Command phase:
623 * The host writes a command and its parameters into the FIFO. The command
624 * phase is completed when all parameters for the command have been supplied,
625 * and execution phase is entered.
626 *
627 * Execution phase:
628 * Data transfers, either DMA or non-DMA. For non-DMA transfers, the FIFO
629 * contains the payload now, otherwise it's unused. When all bytes of the
630 * required data have been transferred, the state is switched to either result
631 * phase (if the command produces status bytes) or directly back into the
632 * command phase for the next command.
633 *
634 * Result phase:
635 * The host reads out the FIFO, which contains one or more result bytes now.
636 */
637enum {
638 /* Only for migration: reconstruct phase from registers like qemu 2.3 */
639 FD_PHASE_RECONSTRUCT = 0,
640
641 FD_PHASE_COMMAND = 1,
642 FD_PHASE_EXECUTION = 2,
643 FD_PHASE_RESULT = 3,
644};
645
8977f3c1 646#define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
baca51fa 647#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
8977f3c1 648
5c02c033 649struct FDCtrl {
dc6c1b37 650 MemoryRegion iomem;
d537cf6c 651 qemu_irq irq;
4b19ec0c 652 /* Controller state */
ed5fd2cc 653 QEMUTimer *result_timer;
242cca4f 654 int dma_chann;
85d291a0 655 uint8_t phase;
c8a35f1c 656 IsaDma *dma;
242cca4f
BS		 657 /* Controller's identification */
658 uint8_t version;
659 /* HW */
8c6a4d77
BS		 660 uint8_t sra;
661 uint8_t srb;
368df94d 662 uint8_t dor;
d7a6c270 663 uint8_t dor_vmstate; /* only used as temp during vmstate */
46d3233b 664 uint8_t tdr;
b9b3d225 665 uint8_t dsr;
368df94d 666 uint8_t msr;
8977f3c1 667 uint8_t cur_drv;
77370520
BS		 668 uint8_t status0;
669 uint8_t status1;
670 uint8_t status2;
8977f3c1 671 /* Command FIFO */
33f00271 672 uint8_t *fifo;
d7a6c270 673 int32_t fifo_size;
8977f3c1
FB		 674 uint32_t data_pos;
675 uint32_t data_len;
676 uint8_t data_state;
677 uint8_t data_dir;
890fa6be 678 uint8_t eot; /* last wanted sector */
8977f3c1 679 /* States kept only to be returned back */
8977f3c1
FB		 680 /* precompensation */
681 uint8_t precomp_trk;
682 uint8_t config;
683 uint8_t lock;
684 /* Power down config (also with status regB access mode */
685 uint8_t pwrd;
686 /* Floppy drives */
d7a6c270 687 uint8_t num_floppies;
5c02c033 688 FDrive drives[MAX_FD];
f2d81b33 689 int reset_sensei;
09c6d585 690 uint32_t check_media_rate;
a73275dd 691 FloppyDriveType fallback; /* type=auto failure fallback */
242cca4f
BS		 692 /* Timers state */
693 uint8_t timer0;
694 uint8_t timer1;
baca51fa
FB		 695};
696
a73275dd
JS		 697static FloppyDriveType get_fallback_drive_type(FDrive *drv)
698{
699 return drv->fdctrl->fallback;
700}
701
19d46d71 702#define TYPE_SYSBUS_FDC "base-sysbus-fdc"
dd3be742
HT		 703#define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC)
704
5c02c033 705typedef struct FDCtrlSysBus {
dd3be742
HT		 706 /*< private >*/
707 SysBusDevice parent_obj;
708 /*< public >*/
709
5c02c033
BS		 710 struct FDCtrl state;
711} FDCtrlSysBus;
8baf73ad 712
020c8e76
AF		 713#define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC)
714
5c02c033 715typedef struct FDCtrlISABus {
020c8e76
AF		 716 ISADevice parent_obj;
717
c9ae703d
HP		 718 uint32_t iobase;
719 uint32_t irq;
720 uint32_t dma;
5c02c033 721 struct FDCtrl state;
1ca4d09a
GN		 722 int32_t bootindexA;
723 int32_t bootindexB;
5c02c033 724} FDCtrlISABus;
8baf73ad 725
baca51fa
FB		 726static uint32_t fdctrl_read (void *opaque, uint32_t reg)
727{
5c02c033 728 FDCtrl *fdctrl = opaque;
baca51fa
FB		 729 uint32_t retval;
730
a18e67f5 731 reg &= 7;
e64d7d59 732 switch (reg) {
8c6a4d77
BS		 733 case FD_REG_SRA:
734 retval = fdctrl_read_statusA(fdctrl);
4f431960 735 break;
8c6a4d77 736 case FD_REG_SRB:
4f431960
JM		 737 retval = fdctrl_read_statusB(fdctrl);
738 break;
9fea808a 739 case FD_REG_DOR:
4f431960
JM		 740 retval = fdctrl_read_dor(fdctrl);
741 break;
9fea808a 742 case FD_REG_TDR:
baca51fa 743 retval = fdctrl_read_tape(fdctrl);
4f431960 744 break;
9fea808a 745 case FD_REG_MSR:
baca51fa 746 retval = fdctrl_read_main_status(fdctrl);
4f431960 747 break;
9fea808a 748 case FD_REG_FIFO:
baca51fa 749 retval = fdctrl_read_data(fdctrl);
4f431960 750 break;
9fea808a 751 case FD_REG_DIR:
baca51fa 752 retval = fdctrl_read_dir(fdctrl);
4f431960 753 break;
a541f297 754 default:
4f431960
JM		 755 retval = (uint32_t)(-1);
756 break;
a541f297 757 }
ed5fd2cc 758 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
baca51fa
FB		 759
760 return retval;
761}
762
763static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
764{
5c02c033 765 FDCtrl *fdctrl = opaque;
baca51fa 766
ed5fd2cc
FB		 767 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
768
a18e67f5 769 reg &= 7;
e64d7d59 770 switch (reg) {
9fea808a 771 case FD_REG_DOR:
4f431960
JM		 772 fdctrl_write_dor(fdctrl, value);
773 break;
9fea808a 774 case FD_REG_TDR:
baca51fa 775 fdctrl_write_tape(fdctrl, value);
4f431960 776 break;
9fea808a 777 case FD_REG_DSR:
baca51fa 778 fdctrl_write_rate(fdctrl, value);
4f431960 779 break;
9fea808a 780 case FD_REG_FIFO:
baca51fa 781 fdctrl_write_data(fdctrl, value);
4f431960 782 break;
a758f8f4
HP		 783 case FD_REG_CCR:
784 fdctrl_write_ccr(fdctrl, value);
785 break;
a541f297 786 default:
4f431960 787 break;
a541f297 788 }
baca51fa
FB		 789}
790
a8170e5e 791static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg,
dc6c1b37 792 unsigned ize)
62a46c61 793{
5dcb6b91 794 return fdctrl_read(opaque, (uint32_t)reg);
62a46c61
FB		 795}
796
a8170e5e 797static void fdctrl_write_mem (void *opaque, hwaddr reg,
dc6c1b37 798 uint64_t value, unsigned size)
62a46c61 799{
5dcb6b91 800 fdctrl_write(opaque, (uint32_t)reg, value);
62a46c61
FB		 801}
802
dc6c1b37
AK		 803static const MemoryRegionOps fdctrl_mem_ops = {
804 .read = fdctrl_read_mem,
805 .write = fdctrl_write_mem,
806 .endianness = DEVICE_NATIVE_ENDIAN,
e80cfcfc
FB		 807};
808
dc6c1b37
AK		 809static const MemoryRegionOps fdctrl_mem_strict_ops = {
810 .read = fdctrl_read_mem,
811 .write = fdctrl_write_mem,
812 .endianness = DEVICE_NATIVE_ENDIAN,
813 .valid = {
814 .min_access_size = 1,
815 .max_access_size = 1,
816 },
7c560456
BS		 817};
818
7d905f71
JW		 819static bool fdrive_media_changed_needed(void *opaque)
820{
821 FDrive *drive = opaque;
822
abb3e55b 823 return (drive->blk != NULL && drive->media_changed != 1);
7d905f71
JW		 824}
825
826static const VMStateDescription vmstate_fdrive_media_changed = {
827 .name = "fdrive/media_changed",
828 .version_id = 1,
829 .minimum_version_id = 1,
5cd8cada 830 .needed = fdrive_media_changed_needed,
d49805ae 831 .fields = (VMStateField[]) {
7d905f71
JW		 832 VMSTATE_UINT8(media_changed, FDrive),
833 VMSTATE_END_OF_LIST()
834 }
835};
836
844f65d6
HP		 837static bool fdrive_media_rate_needed(void *opaque)
838{
839 FDrive *drive = opaque;
840
841 return drive->fdctrl->check_media_rate;
842}
843
844static const VMStateDescription vmstate_fdrive_media_rate = {
845 .name = "fdrive/media_rate",
846 .version_id = 1,
847 .minimum_version_id = 1,
5cd8cada 848 .needed = fdrive_media_rate_needed,
d49805ae 849 .fields = (VMStateField[]) {
844f65d6
HP		 850 VMSTATE_UINT8(media_rate, FDrive),
851 VMSTATE_END_OF_LIST()
852 }
853};
854
c0b92f30
PD		 855static bool fdrive_perpendicular_needed(void *opaque)
856{
857 FDrive *drive = opaque;
858
859 return drive->perpendicular != 0;
860}
861
862static const VMStateDescription vmstate_fdrive_perpendicular = {
863 .name = "fdrive/perpendicular",
864 .version_id = 1,
865 .minimum_version_id = 1,
5cd8cada 866 .needed = fdrive_perpendicular_needed,
c0b92f30
PD		 867 .fields = (VMStateField[]) {
868 VMSTATE_UINT8(perpendicular, FDrive),
869 VMSTATE_END_OF_LIST()
870 }
871};
872
873static int fdrive_post_load(void *opaque, int version_id)
874{
875 fd_revalidate(opaque);
876 return 0;
877}
878
d7a6c270
JQ		 879static const VMStateDescription vmstate_fdrive = {
880 .name = "fdrive",
881 .version_id = 1,
882 .minimum_version_id = 1,
c0b92f30 883 .post_load = fdrive_post_load,
d49805ae 884 .fields = (VMStateField[]) {
5c02c033
BS		 885 VMSTATE_UINT8(head, FDrive),
886 VMSTATE_UINT8(track, FDrive),
887 VMSTATE_UINT8(sect, FDrive),
d7a6c270 888 VMSTATE_END_OF_LIST()
7d905f71 889 },
5cd8cada
JQ		 890 .subsections = (const VMStateDescription*[]) {
891 &vmstate_fdrive_media_changed,
892 &vmstate_fdrive_media_rate,
893 &vmstate_fdrive_perpendicular,
894 NULL
d7a6c270
JQ		 895 }
896};
3ccacc4a 897
85d291a0
KW		 898/*
899 * Reconstructs the phase from register values according to the logic that was
900 * implemented in qemu 2.3. This is the default value that is used if the phase
901 * subsection is not present on migration.
902 *
903 * Don't change this function to reflect newer qemu versions, it is part of
904 * the migration ABI.
905 */
906static int reconstruct_phase(FDCtrl *fdctrl)
907{
908 if (fdctrl->msr & FD_MSR_NONDMA) {
909 return FD_PHASE_EXECUTION;
910 } else if ((fdctrl->msr & FD_MSR_RQM) == 0) {
911 /* qemu 2.3 disabled RQM only during DMA transfers */
912 return FD_PHASE_EXECUTION;
913 } else if (fdctrl->msr & FD_MSR_DIO) {
914 return FD_PHASE_RESULT;
915 } else {
916 return FD_PHASE_COMMAND;
917 }
918}
919
d4bfa4d7 920static void fdc_pre_save(void *opaque)
3ccacc4a 921{
5c02c033 922 FDCtrl *s = opaque;
3ccacc4a 923
d7a6c270 924 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
3ccacc4a
BS		 925}
926
85d291a0
KW		 927static int fdc_pre_load(void *opaque)
928{
929 FDCtrl *s = opaque;
930 s->phase = FD_PHASE_RECONSTRUCT;
931 return 0;
932}
933
e59fb374 934static int fdc_post_load(void *opaque, int version_id)
3ccacc4a 935{
5c02c033 936 FDCtrl *s = opaque;
3ccacc4a 937
d7a6c270
JQ		 938 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
939 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
85d291a0
KW		 940
941 if (s->phase == FD_PHASE_RECONSTRUCT) {
942 s->phase = reconstruct_phase(s);
943 }
944
3ccacc4a
BS		 945 return 0;
946}
947
c0b92f30
PD		 948static bool fdc_reset_sensei_needed(void *opaque)
949{
950 FDCtrl *s = opaque;
951
952 return s->reset_sensei != 0;
953}
954
955static const VMStateDescription vmstate_fdc_reset_sensei = {
956 .name = "fdc/reset_sensei",
957 .version_id = 1,
958 .minimum_version_id = 1,
5cd8cada 959 .needed = fdc_reset_sensei_needed,
c0b92f30
PD		 960 .fields = (VMStateField[]) {
961 VMSTATE_INT32(reset_sensei, FDCtrl),
962 VMSTATE_END_OF_LIST()
963 }
964};
965
966static bool fdc_result_timer_needed(void *opaque)
967{
968 FDCtrl *s = opaque;
969
970 return timer_pending(s->result_timer);
971}
972
973static const VMStateDescription vmstate_fdc_result_timer = {
974 .name = "fdc/result_timer",
975 .version_id = 1,
976 .minimum_version_id = 1,
5cd8cada 977 .needed = fdc_result_timer_needed,
c0b92f30 978 .fields = (VMStateField[]) {
e720677e 979 VMSTATE_TIMER_PTR(result_timer, FDCtrl),
c0b92f30
PD		 980 VMSTATE_END_OF_LIST()
981 }
982};
983
85d291a0
KW		 984static bool fdc_phase_needed(void *opaque)
985{
986 FDCtrl *fdctrl = opaque;
987
988 return reconstruct_phase(fdctrl) != fdctrl->phase;
989}
990
991static const VMStateDescription vmstate_fdc_phase = {
992 .name = "fdc/phase",
993 .version_id = 1,
994 .minimum_version_id = 1,
5cd8cada 995 .needed = fdc_phase_needed,
85d291a0
KW		 996 .fields = (VMStateField[]) {
997 VMSTATE_UINT8(phase, FDCtrl),
998 VMSTATE_END_OF_LIST()
999 }
1000};
1001
d7a6c270 1002static const VMStateDescription vmstate_fdc = {
aef30c3c 1003 .name = "fdc",
d7a6c270
JQ		 1004 .version_id = 2,
1005 .minimum_version_id = 2,
d7a6c270 1006 .pre_save = fdc_pre_save,
85d291a0 1007 .pre_load = fdc_pre_load,
d7a6c270 1008 .post_load = fdc_post_load,
d49805ae 1009 .fields = (VMStateField[]) {
d7a6c270 1010 /* Controller State */
5c02c033
BS		 1011 VMSTATE_UINT8(sra, FDCtrl),
1012 VMSTATE_UINT8(srb, FDCtrl),
1013 VMSTATE_UINT8(dor_vmstate, FDCtrl),
1014 VMSTATE_UINT8(tdr, FDCtrl),
1015 VMSTATE_UINT8(dsr, FDCtrl),
1016 VMSTATE_UINT8(msr, FDCtrl),
1017 VMSTATE_UINT8(status0, FDCtrl),
1018 VMSTATE_UINT8(status1, FDCtrl),
1019 VMSTATE_UINT8(status2, FDCtrl),
d7a6c270 1020 /* Command FIFO */
8ec68b06
BS		 1021 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
1022 uint8_t),
5c02c033
BS		 1023 VMSTATE_UINT32(data_pos, FDCtrl),
1024 VMSTATE_UINT32(data_len, FDCtrl),
1025 VMSTATE_UINT8(data_state, FDCtrl),
1026 VMSTATE_UINT8(data_dir, FDCtrl),
1027 VMSTATE_UINT8(eot, FDCtrl),
d7a6c270 1028 /* States kept only to be returned back */
5c02c033
BS		 1029 VMSTATE_UINT8(timer0, FDCtrl),
1030 VMSTATE_UINT8(timer1, FDCtrl),
1031 VMSTATE_UINT8(precomp_trk, FDCtrl),
1032 VMSTATE_UINT8(config, FDCtrl),
1033 VMSTATE_UINT8(lock, FDCtrl),
1034 VMSTATE_UINT8(pwrd, FDCtrl),
1035 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
1036 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
1037 vmstate_fdrive, FDrive),
d7a6c270 1038 VMSTATE_END_OF_LIST()
c0b92f30 1039 },
5cd8cada
JQ		 1040 .subsections = (const VMStateDescription*[]) {
1041 &vmstate_fdc_reset_sensei,
1042 &vmstate_fdc_result_timer,
1043 &vmstate_fdc_phase,
1044 NULL
78ae820c 1045 }
d7a6c270 1046};
3ccacc4a 1047
2be37833 1048static void fdctrl_external_reset_sysbus(DeviceState *d)
3ccacc4a 1049{
dd3be742 1050 FDCtrlSysBus *sys = SYSBUS_FDC(d);
5c02c033 1051 FDCtrl *s = &sys->state;
2be37833
BS		 1052
1053 fdctrl_reset(s, 0);
1054}
1055
1056static void fdctrl_external_reset_isa(DeviceState *d)
1057{
020c8e76 1058 FDCtrlISABus *isa = ISA_FDC(d);
5c02c033 1059 FDCtrl *s = &isa->state;
3ccacc4a
BS		 1060
1061 fdctrl_reset(s, 0);
1062}
1063
2be17ebd
BS		 1064static void fdctrl_handle_tc(void *opaque, int irq, int level)
1065{
5c02c033 1066 //FDCtrl *s = opaque;
2be17ebd
BS		 1067
1068 if (level) {
1069 // XXX
1070 FLOPPY_DPRINTF("TC pulsed\n");
1071 }
1072}
1073
8977f3c1 1074/* Change IRQ state */
5c02c033 1075static void fdctrl_reset_irq(FDCtrl *fdctrl)
8977f3c1 1076{
d497d534 1077 fdctrl->status0 = 0;
8c6a4d77
BS		 1078 if (!(fdctrl->sra & FD_SRA_INTPEND))
1079 return;
ed5fd2cc 1080 FLOPPY_DPRINTF("Reset interrupt\n");
d537cf6c 1081 qemu_set_irq(fdctrl->irq, 0);
8c6a4d77 1082 fdctrl->sra &= ~FD_SRA_INTPEND;
8977f3c1
FB		 1083}
1084
d497d534 1085static void fdctrl_raise_irq(FDCtrl *fdctrl)
8977f3c1 1086{
8c6a4d77 1087 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
d537cf6c 1088 qemu_set_irq(fdctrl->irq, 1);
8c6a4d77 1089 fdctrl->sra |= FD_SRA_INTPEND;
8977f3c1 1090 }
21fcf360 1091
f2d81b33 1092 fdctrl->reset_sensei = 0;
77370520 1093 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
8977f3c1
FB		 1094}
1095
4b19ec0c 1096/* Reset controller */
5c02c033 1097static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
8977f3c1
FB		 1098{
1099 int i;
1100
4b19ec0c 1101 FLOPPY_DPRINTF("reset controller\n");
baca51fa 1102 fdctrl_reset_irq(fdctrl);
4b19ec0c 1103 /* Initialise controller */
8c6a4d77
BS		 1104 fdctrl->sra = 0;
1105 fdctrl->srb = 0xc0;
4be74634 1106 if (!fdctrl->drives[1].blk) {
8c6a4d77 1107 fdctrl->sra |= FD_SRA_nDRV2;
4be74634 1108 }
baca51fa 1109 fdctrl->cur_drv = 0;
1c346df2 1110 fdctrl->dor = FD_DOR_nRESET;
368df94d 1111 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
b9b3d225 1112 fdctrl->msr = FD_MSR_RQM;
c0b92f30
PD		 1113 fdctrl->reset_sensei = 0;
1114 timer_del(fdctrl->result_timer);
8977f3c1 1115 /* FIFO state */
baca51fa
FB		 1116 fdctrl->data_pos = 0;
1117 fdctrl->data_len = 0;
b9b3d225 1118 fdctrl->data_state = 0;
baca51fa 1119 fdctrl->data_dir = FD_DIR_WRITE;
8977f3c1 1120 for (i = 0; i < MAX_FD; i++)
1c346df2 1121 fd_recalibrate(&fdctrl->drives[i]);
07e415f2 1122 fdctrl_to_command_phase(fdctrl);
77370520 1123 if (do_irq) {
d497d534
HP		 1124 fdctrl->status0 |= FD_SR0_RDYCHG;
1125 fdctrl_raise_irq(fdctrl);
f2d81b33 1126 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
77370520 1127 }
baca51fa
FB		 1128}
1129
5c02c033 1130static inline FDrive *drv0(FDCtrl *fdctrl)
baca51fa 1131{
46d3233b 1132 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
baca51fa
FB		 1133}
1134
5c02c033 1135static inline FDrive *drv1(FDCtrl *fdctrl)
baca51fa 1136{
46d3233b
BS		 1137 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
1138 return &fdctrl->drives[1];
1139 else
1140 return &fdctrl->drives[0];
baca51fa
FB		 1141}
1142
78ae820c 1143#if MAX_FD == 4
5c02c033 1144static inline FDrive *drv2(FDCtrl *fdctrl)
78ae820c
BS		 1145{
1146 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
1147 return &fdctrl->drives[2];
1148 else
1149 return &fdctrl->drives[1];
1150}
1151
5c02c033 1152static inline FDrive *drv3(FDCtrl *fdctrl)
78ae820c
BS		 1153{
1154 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
1155 return &fdctrl->drives[3];
1156 else
1157 return &fdctrl->drives[2];
1158}
1159#endif
1160
5c02c033 1161static FDrive *get_cur_drv(FDCtrl *fdctrl)
baca51fa 1162{
78ae820c
BS		 1163 switch (fdctrl->cur_drv) {
1164 case 0: return drv0(fdctrl);
1165 case 1: return drv1(fdctrl);
1166#if MAX_FD == 4
1167 case 2: return drv2(fdctrl);
1168 case 3: return drv3(fdctrl);
1169#endif
1170 default: return NULL;
1171 }
8977f3c1
FB		 1172}
1173
8c6a4d77 1174/* Status A register : 0x00 (read-only) */
5c02c033 1175static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
8c6a4d77
BS		 1176{
1177 uint32_t retval = fdctrl->sra;
1178
1179 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
1180
1181 return retval;
1182}
1183
8977f3c1 1184/* Status B register : 0x01 (read-only) */
5c02c033 1185static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
8977f3c1 1186{
8c6a4d77
BS		 1187 uint32_t retval = fdctrl->srb;
1188
1189 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
1190
1191 return retval;
8977f3c1
FB		 1192}
1193
1194/* Digital output register : 0x02 */
5c02c033 1195static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
8977f3c1 1196{
1c346df2 1197 uint32_t retval = fdctrl->dor;
8977f3c1 1198
8977f3c1 1199 /* Selected drive */
baca51fa 1200 retval |= fdctrl->cur_drv;
8977f3c1
FB		 1201 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
1202
1203 return retval;
1204}
1205
5c02c033 1206static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
8977f3c1 1207{
8977f3c1 1208 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
8c6a4d77
BS		 1209
1210 /* Motors */
1211 if (value & FD_DOR_MOTEN0)
1212 fdctrl->srb |= FD_SRB_MTR0;
1213 else
1214 fdctrl->srb &= ~FD_SRB_MTR0;
1215 if (value & FD_DOR_MOTEN1)
1216 fdctrl->srb |= FD_SRB_MTR1;
1217 else
1218 fdctrl->srb &= ~FD_SRB_MTR1;
1219
1220 /* Drive */
1221 if (value & 1)
1222 fdctrl->srb |= FD_SRB_DR0;
1223 else
1224 fdctrl->srb &= ~FD_SRB_DR0;
1225
8977f3c1 1226 /* Reset */
9fea808a 1227 if (!(value & FD_DOR_nRESET)) {
1c346df2 1228 if (fdctrl->dor & FD_DOR_nRESET) {
4b19ec0c 1229 FLOPPY_DPRINTF("controller enter RESET state\n");
8977f3c1
FB		 1230 }
1231 } else {
1c346df2 1232 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4b19ec0c 1233 FLOPPY_DPRINTF("controller out of RESET state\n");
fb6cf1d0 1234 fdctrl_reset(fdctrl, 1);
b9b3d225 1235 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
8977f3c1
FB		 1236 }
1237 }
1238 /* Selected drive */
9fea808a 1239 fdctrl->cur_drv = value & FD_DOR_SELMASK;
368df94d
BS		 1240
1241 fdctrl->dor = value;
8977f3c1
FB		 1242}
1243
1244/* Tape drive register : 0x03 */
5c02c033 1245static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
8977f3c1 1246{
46d3233b 1247 uint32_t retval = fdctrl->tdr;
8977f3c1 1248
8977f3c1
FB		 1249 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
1250
1251 return retval;
1252}
1253
5c02c033 1254static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
8977f3c1 1255{
8977f3c1 1256 /* Reset mode */
1c346df2 1257 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4b19ec0c 1258 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
8977f3c1
FB		 1259 return;
1260 }
1261 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
1262 /* Disk boot selection indicator */
46d3233b 1263 fdctrl->tdr = value & FD_TDR_BOOTSEL;
8977f3c1
FB		 1264 /* Tape indicators: never allow */
1265}
1266
1267/* Main status register : 0x04 (read) */
5c02c033 1268static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
8977f3c1 1269{
b9b3d225 1270 uint32_t retval = fdctrl->msr;
8977f3c1 1271
b9b3d225 1272 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1c346df2 1273 fdctrl->dor |= FD_DOR_nRESET;
b9b3d225 1274
8977f3c1
FB		 1275 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
1276
1277 return retval;
1278}
1279
1280/* Data select rate register : 0x04 (write) */
5c02c033 1281static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
8977f3c1 1282{
8977f3c1 1283 /* Reset mode */
1c346df2 1284 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4f431960
JM		 1285 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1286 return;
1287 }
8977f3c1
FB		 1288 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
1289 /* Reset: autoclear */
9fea808a 1290 if (value & FD_DSR_SWRESET) {
1c346df2 1291 fdctrl->dor &= ~FD_DOR_nRESET;
baca51fa 1292 fdctrl_reset(fdctrl, 1);
1c346df2 1293 fdctrl->dor |= FD_DOR_nRESET;
8977f3c1 1294 }
9fea808a 1295 if (value & FD_DSR_PWRDOWN) {
baca51fa 1296 fdctrl_reset(fdctrl, 1);
8977f3c1 1297 }
b9b3d225 1298 fdctrl->dsr = value;
8977f3c1
FB		 1299}
1300
a758f8f4
HP		 1301/* Configuration control register: 0x07 (write) */
1302static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
1303{
1304 /* Reset mode */
1305 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1306 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1307 return;
1308 }
1309 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
1310
1311 /* Only the rate selection bits used in AT mode, and we
1312 * store those in the DSR.
1313 */
1314 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
1315 (value & FD_DSR_DRATEMASK);
1316}
1317
5c02c033 1318static int fdctrl_media_changed(FDrive *drv)
ea185bbd 1319{
21fcf360 1320 return drv->media_changed;
ea185bbd
FB		 1321}
1322
8977f3c1 1323/* Digital input register : 0x07 (read-only) */
5c02c033 1324static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
8977f3c1 1325{
8977f3c1
FB		 1326 uint32_t retval = 0;
1327
a2df5fa3 1328 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
9fea808a 1329 retval |= FD_DIR_DSKCHG;
a2df5fa3 1330 }
3c83eb4f 1331 if (retval != 0) {
baca51fa 1332 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
3c83eb4f 1333 }
8977f3c1
FB		 1334
1335 return retval;
1336}
1337
07e415f2
KW		 1338/* Clear the FIFO and update the state for receiving the next command */
1339static void fdctrl_to_command_phase(FDCtrl *fdctrl)
8977f3c1 1340{
85d291a0 1341 fdctrl->phase = FD_PHASE_COMMAND;
baca51fa
FB		 1342 fdctrl->data_dir = FD_DIR_WRITE;
1343 fdctrl->data_pos = 0;
6cc8a11c 1344 fdctrl->data_len = 1; /* Accept command byte, adjust for params later */
b9b3d225 1345 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
6cc8a11c 1346 fdctrl->msr |= FD_MSR_RQM;
8977f3c1
FB		 1347}
1348
83a26013
KW		 1349/* Update the state to allow the guest to read out the command status.
1350 * @fifo_len is the number of result bytes to be read out. */
1351static void fdctrl_to_result_phase(FDCtrl *fdctrl, int fifo_len)
8977f3c1 1352{
85d291a0 1353 fdctrl->phase = FD_PHASE_RESULT;
baca51fa
FB		 1354 fdctrl->data_dir = FD_DIR_READ;
1355 fdctrl->data_len = fifo_len;
1356 fdctrl->data_pos = 0;
b9b3d225 1357 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
8977f3c1
FB		 1358}
1359
1360/* Set an error: unimplemented/unknown command */
5c02c033 1361static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
8977f3c1 1362{
cced7a13
BS		 1363 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n",
1364 fdctrl->fifo[0]);
9fea808a 1365 fdctrl->fifo[0] = FD_SR0_INVCMD;
83a26013 1366 fdctrl_to_result_phase(fdctrl, 1);
8977f3c1
FB		 1367}
1368
6be01b1e
PH		 1369/* Seek to next sector
1370 * returns 0 when end of track reached (for DBL_SIDES on head 1)
1371 * otherwise returns 1
1372 */
5c02c033 1373static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
746d6de7
BS		 1374{
1375 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1376 cur_drv->head, cur_drv->track, cur_drv->sect,
1377 fd_sector(cur_drv));
1378 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1379 error in fact */
6be01b1e
PH		 1380 uint8_t new_head = cur_drv->head;
1381 uint8_t new_track = cur_drv->track;
1382 uint8_t new_sect = cur_drv->sect;
1383
1384 int ret = 1;
1385
1386 if (new_sect >= cur_drv->last_sect ||
1387 new_sect == fdctrl->eot) {
1388 new_sect = 1;
746d6de7 1389 if (FD_MULTI_TRACK(fdctrl->data_state)) {
6be01b1e 1390 if (new_head == 0 &&
746d6de7 1391 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
6be01b1e 1392 new_head = 1;
746d6de7 1393 } else {
6be01b1e
PH		 1394 new_head = 0;
1395 new_track++;
c5139bd9 1396 fdctrl->status0 |= FD_SR0_SEEK;
6be01b1e
PH		 1397 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) {
1398 ret = 0;
1399 }
746d6de7
BS		 1400 }
1401 } else {
c5139bd9 1402 fdctrl->status0 |= FD_SR0_SEEK;
6be01b1e
PH		 1403 new_track++;
1404 ret = 0;
1405 }
1406 if (ret == 1) {
1407 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1408 new_head, new_track, new_sect, fd_sector(cur_drv));
746d6de7 1409 }
746d6de7 1410 } else {
6be01b1e 1411 new_sect++;
746d6de7 1412 }
6be01b1e
PH		 1413 fd_seek(cur_drv, new_head, new_track, new_sect, 1);
1414 return ret;
746d6de7
BS		 1415}
1416
8977f3c1 1417/* Callback for transfer end (stop or abort) */
5c02c033
BS		 1418static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1419 uint8_t status1, uint8_t status2)
8977f3c1 1420{
5c02c033 1421 FDrive *cur_drv;
baca51fa 1422 cur_drv = get_cur_drv(fdctrl);
075f5532
HP		 1423
1424 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD);
1425 fdctrl->status0 |= GET_CUR_DRV(fdctrl);
1426 if (cur_drv->head) {
1427 fdctrl->status0 |= FD_SR0_HEAD;
1428 }
1429 fdctrl->status0 |= status0;
2fee0088 1430
8977f3c1 1431 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
2fee0088
PH		 1432 status0, status1, status2, fdctrl->status0);
1433 fdctrl->fifo[0] = fdctrl->status0;
baca51fa
FB		 1434 fdctrl->fifo[1] = status1;
1435 fdctrl->fifo[2] = status2;
1436 fdctrl->fifo[3] = cur_drv->track;
1437 fdctrl->fifo[4] = cur_drv->head;
1438 fdctrl->fifo[5] = cur_drv->sect;
1439 fdctrl->fifo[6] = FD_SECTOR_SC;
1440 fdctrl->data_dir = FD_DIR_READ;
368df94d 1441 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
c8a35f1c
HP		 1442 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma);
1443 k->release_DREQ(fdctrl->dma, fdctrl->dma_chann);
ed5fd2cc 1444 }
b9b3d225 1445 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
368df94d 1446 fdctrl->msr &= ~FD_MSR_NONDMA;
34abf9a7 1447
83a26013 1448 fdctrl_to_result_phase(fdctrl, 7);
d497d534 1449 fdctrl_raise_irq(fdctrl);
8977f3c1
FB		 1450}
1451
1452/* Prepare a data transfer (either DMA or FIFO) */
5c02c033 1453static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
8977f3c1 1454{
5c02c033 1455 FDrive *cur_drv;
8977f3c1 1456 uint8_t kh, kt, ks;
8977f3c1 1457
cefec4f5 1458 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
baca51fa
FB		 1459 cur_drv = get_cur_drv(fdctrl);
1460 kt = fdctrl->fifo[2];
1461 kh = fdctrl->fifo[3];
1462 ks = fdctrl->fifo[4];
4b19ec0c 1463 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
cefec4f5 1464 GET_CUR_DRV(fdctrl), kh, kt, ks,
08388273
HP		 1465 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1466 NUM_SIDES(cur_drv)));
77370520 1467 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
8977f3c1
FB		 1468 case 2:
1469 /* sect too big */
9fea808a 1470 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1471 fdctrl->fifo[3] = kt;
1472 fdctrl->fifo[4] = kh;
1473 fdctrl->fifo[5] = ks;
8977f3c1
FB		 1474 return;
1475 case 3:
1476 /* track too big */
77370520 1477 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
baca51fa
FB		 1478 fdctrl->fifo[3] = kt;
1479 fdctrl->fifo[4] = kh;
1480 fdctrl->fifo[5] = ks;
8977f3c1
FB		 1481 return;
1482 case 4:
1483 /* No seek enabled */
9fea808a 1484 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1485 fdctrl->fifo[3] = kt;
1486 fdctrl->fifo[4] = kh;
1487 fdctrl->fifo[5] = ks;
8977f3c1
FB		 1488 return;
1489 case 1:
d6ed4e21 1490 fdctrl->status0 |= FD_SR0_SEEK;
8977f3c1
FB		 1491 break;
1492 default:
1493 break;
1494 }
b9b3d225 1495
844f65d6
HP		 1496 /* Check the data rate. If the programmed data rate does not match
1497 * the currently inserted medium, the operation has to fail. */
1498 if (fdctrl->check_media_rate &&
1499 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1500 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1501 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1502 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1503 fdctrl->fifo[3] = kt;
1504 fdctrl->fifo[4] = kh;
1505 fdctrl->fifo[5] = ks;
1506 return;
1507 }
1508
8977f3c1 1509 /* Set the FIFO state */
baca51fa
FB		 1510 fdctrl->data_dir = direction;
1511 fdctrl->data_pos = 0;
27c86e24 1512 assert(fdctrl->msr & FD_MSR_CMDBUSY);
baca51fa
FB		 1513 if (fdctrl->fifo[0] & 0x80)
1514 fdctrl->data_state |= FD_STATE_MULTI;
1515 else
1516 fdctrl->data_state &= ~FD_STATE_MULTI;
c83f97b5 1517 if (fdctrl->fifo[5] == 0) {
baca51fa
FB		 1518 fdctrl->data_len = fdctrl->fifo[8];
1519 } else {
4f431960 1520 int tmp;
3bcb80f1 1521 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
771effeb 1522 tmp = (fdctrl->fifo[6] - ks + 1);
baca51fa 1523 if (fdctrl->fifo[0] & 0x80)
771effeb 1524 tmp += fdctrl->fifo[6];
4f431960 1525 fdctrl->data_len *= tmp;
baca51fa 1526 }
890fa6be 1527 fdctrl->eot = fdctrl->fifo[6];
368df94d 1528 if (fdctrl->dor & FD_DOR_DMAEN) {
c8a35f1c
HP		 1529 IsaDmaTransferMode dma_mode;
1530 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma);
1531 bool dma_mode_ok;
8977f3c1 1532 /* DMA transfer are enabled. Check if DMA channel is well programmed */
c8a35f1c 1533 dma_mode = k->get_transfer_mode(fdctrl->dma, fdctrl->dma_chann);
baca51fa 1534 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
4f431960 1535 dma_mode, direction,
baca51fa 1536 (128 << fdctrl->fifo[5]) *
4f431960 1537 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
c8a35f1c
HP		 1538 switch (direction) {
1539 case FD_DIR_SCANE:
1540 case FD_DIR_SCANL:
1541 case FD_DIR_SCANH:
1542 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_VERIFY);
1543 break;
1544 case FD_DIR_WRITE:
1545 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_WRITE);
1546 break;
1547 case FD_DIR_READ:
1548 dma_mode_ok = (dma_mode == ISADMA_TRANSFER_READ);
1549 break;
1550 case FD_DIR_VERIFY:
1551 dma_mode_ok = true;
1552 break;
1553 default:
1554 dma_mode_ok = false;
1555 break;
1556 }
1557 if (dma_mode_ok) {
8977f3c1 1558 /* No access is allowed until DMA transfer has completed */
b9b3d225 1559 fdctrl->msr &= ~FD_MSR_RQM;
7ea004ed
HP		 1560 if (direction != FD_DIR_VERIFY) {
1561 /* Now, we just have to wait for the DMA controller to
1562 * recall us...
1563 */
c8a35f1c
HP		 1564 k->hold_DREQ(fdctrl->dma, fdctrl->dma_chann);
1565 k->schedule(fdctrl->dma);
7ea004ed
HP		 1566 } else {
1567 /* Start transfer */
1568 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0,
1569 fdctrl->data_len);
1570 }
8977f3c1 1571 return;
baca51fa 1572 } else {
cced7a13
BS		 1573 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode,
1574 direction);
8977f3c1
FB		 1575 }
1576 }
1577 FLOPPY_DPRINTF("start non-DMA transfer\n");
6cc8a11c 1578 fdctrl->msr |= FD_MSR_NONDMA | FD_MSR_RQM;
b9b3d225
BS		 1579 if (direction != FD_DIR_WRITE)
1580 fdctrl->msr |= FD_MSR_DIO;
8977f3c1 1581 /* IO based transfer: calculate len */
d497d534 1582 fdctrl_raise_irq(fdctrl);
8977f3c1
FB		 1583}
1584
1585/* Prepare a transfer of deleted data */
5c02c033 1586static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
8977f3c1 1587{
cced7a13 1588 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n");
77370520 1589
8977f3c1
FB		 1590 /* We don't handle deleted data,
1591 * so we don't return *ANYTHING*
1592 */
9fea808a 1593 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
8977f3c1
FB		 1594}
1595
1596/* handlers for DMA transfers */
85571bc7
FB		 1597static int fdctrl_transfer_handler (void *opaque, int nchan,
1598 int dma_pos, int dma_len)
8977f3c1 1599{
5c02c033
BS		 1600 FDCtrl *fdctrl;
1601 FDrive *cur_drv;
baca51fa 1602 int len, start_pos, rel_pos;
8977f3c1 1603 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
c8a35f1c 1604 IsaDmaClass *k;
8977f3c1 1605
baca51fa 1606 fdctrl = opaque;
b9b3d225 1607 if (fdctrl->msr & FD_MSR_RQM) {
8977f3c1
FB		 1608 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1609 return 0;
1610 }
c8a35f1c 1611 k = ISADMA_GET_CLASS(fdctrl->dma);
baca51fa
FB		 1612 cur_drv = get_cur_drv(fdctrl);
1613 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1614 fdctrl->data_dir == FD_DIR_SCANH)
77370520 1615 status2 = FD_SR2_SNS;
85571bc7
FB		 1616 if (dma_len > fdctrl->data_len)
1617 dma_len = fdctrl->data_len;
4be74634 1618 if (cur_drv->blk == NULL) {
4f431960 1619 if (fdctrl->data_dir == FD_DIR_WRITE)
9fea808a 1620 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
4f431960 1621 else
9fea808a 1622 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
4f431960 1623 len = 0;
890fa6be
FB		 1624 goto transfer_error;
1625 }
baca51fa 1626 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
85571bc7
FB		 1627 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1628 len = dma_len - fdctrl->data_pos;
baca51fa
FB		 1629 if (len + rel_pos > FD_SECTOR_LEN)
1630 len = FD_SECTOR_LEN - rel_pos;
6f7e9aec
FB		 1631 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1632 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
cefec4f5 1633 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
baca51fa 1634 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
9fea808a 1635 fd_sector(cur_drv) * FD_SECTOR_LEN);
baca51fa 1636 if (fdctrl->data_dir != FD_DIR_WRITE ||
4f431960 1637 len < FD_SECTOR_LEN || rel_pos != 0) {
baca51fa 1638 /* READ & SCAN commands and realign to a sector for WRITE */
a7a5b7c0
EB		 1639 if (blk_pread(cur_drv->blk, fd_offset(cur_drv),
1640 fdctrl->fifo, BDRV_SECTOR_SIZE) < 0) {
8977f3c1
FB		 1641 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1642 fd_sector(cur_drv));
1643 /* Sure, image size is too small... */
baca51fa 1644 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
8977f3c1 1645 }
890fa6be 1646 }
4f431960
JM		 1647 switch (fdctrl->data_dir) {
1648 case FD_DIR_READ:
1649 /* READ commands */
c8a35f1c
HP		 1650 k->write_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos,
1651 fdctrl->data_pos, len);
4f431960
JM		 1652 break;
1653 case FD_DIR_WRITE:
baca51fa 1654 /* WRITE commands */
8510854e
HP		 1655 if (cur_drv->ro) {
1656 /* Handle readonly medium early, no need to do DMA, touch the
1657 * LED or attempt any writes. A real floppy doesn't attempt
1658 * to write to readonly media either. */
1659 fdctrl_stop_transfer(fdctrl,
1660 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1661 0x00);
1662 goto transfer_error;
1663 }
1664
c8a35f1c
HP		 1665 k->read_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos,
1666 fdctrl->data_pos, len);
a7a5b7c0
EB		 1667 if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv),
1668 fdctrl->fifo, BDRV_SECTOR_SIZE, 0) < 0) {
cced7a13
BS		 1669 FLOPPY_DPRINTF("error writing sector %d\n",
1670 fd_sector(cur_drv));
9fea808a 1671 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
baca51fa 1672 goto transfer_error;
890fa6be 1673 }
4f431960 1674 break;
7ea004ed
HP		 1675 case FD_DIR_VERIFY:
1676 /* VERIFY commands */
1677 break;
4f431960
JM		 1678 default:
1679 /* SCAN commands */
baca51fa 1680 {
4f431960 1681 uint8_t tmpbuf[FD_SECTOR_LEN];
baca51fa 1682 int ret;
c8a35f1c
HP		 1683 k->read_memory(fdctrl->dma, nchan, tmpbuf, fdctrl->data_pos,
1684 len);
baca51fa 1685 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
8977f3c1 1686 if (ret == 0) {
77370520 1687 status2 = FD_SR2_SEH;
8977f3c1
FB		 1688 goto end_transfer;
1689 }
baca51fa
FB		 1690 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1691 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
8977f3c1
FB		 1692 status2 = 0x00;
1693 goto end_transfer;
1694 }
1695 }
4f431960 1696 break;
8977f3c1 1697 }
4f431960
JM		 1698 fdctrl->data_pos += len;
1699 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
baca51fa 1700 if (rel_pos == 0) {
8977f3c1 1701 /* Seek to next sector */
746d6de7
BS		 1702 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1703 break;
8977f3c1
FB		 1704 }
1705 }
4f431960 1706 end_transfer:
baca51fa
FB		 1707 len = fdctrl->data_pos - start_pos;
1708 FLOPPY_DPRINTF("end transfer %d %d %d\n",
4f431960 1709 fdctrl->data_pos, len, fdctrl->data_len);
baca51fa
FB		 1710 if (fdctrl->data_dir == FD_DIR_SCANE ||
1711 fdctrl->data_dir == FD_DIR_SCANL ||
1712 fdctrl->data_dir == FD_DIR_SCANH)
77370520 1713 status2 = FD_SR2_SEH;
baca51fa 1714 fdctrl->data_len -= len;
890fa6be 1715 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
4f431960 1716 transfer_error:
8977f3c1 1717
baca51fa 1718 return len;
8977f3c1
FB		 1719}
1720
8977f3c1 1721/* Data register : 0x05 */
5c02c033 1722static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
8977f3c1 1723{
5c02c033 1724 FDrive *cur_drv;
8977f3c1 1725 uint32_t retval = 0;
e9077462 1726 uint32_t pos;
8977f3c1 1727
baca51fa 1728 cur_drv = get_cur_drv(fdctrl);
b9b3d225
BS		 1729 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1730 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
cced7a13 1731 FLOPPY_DPRINTF("error: controller not ready for reading\n");
8977f3c1
FB		 1732 return 0;
1733 }
f6c2d1d8
KW		 1734
1735 /* If data_len spans multiple sectors, the current position in the FIFO
1736 * wraps around while fdctrl->data_pos is the real position in the whole
1737 * request. */
baca51fa 1738 pos = fdctrl->data_pos;
e9077462 1739 pos %= FD_SECTOR_LEN;
f6c2d1d8
KW		 1740
1741 switch (fdctrl->phase) {
1742 case FD_PHASE_EXECUTION:
1743 assert(fdctrl->msr & FD_MSR_NONDMA);
8977f3c1 1744 if (pos == 0) {
746d6de7
BS		 1745 if (fdctrl->data_pos != 0)
1746 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1747 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1748 fd_sector(cur_drv));
1749 return 0;
1750 }
a7a5b7c0
EB		 1751 if (blk_pread(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
1752 BDRV_SECTOR_SIZE)
4be74634 1753 < 0) {
77370520
BS		 1754 FLOPPY_DPRINTF("error getting sector %d\n",
1755 fd_sector(cur_drv));
1756 /* Sure, image size is too small... */
1757 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1758 }
8977f3c1 1759 }
f6c2d1d8
KW		 1760
1761 if (++fdctrl->data_pos == fdctrl->data_len) {
6cc8a11c 1762 fdctrl->msr &= ~FD_MSR_RQM;
c5139bd9 1763 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
f6c2d1d8
KW		 1764 }
1765 break;
1766
1767 case FD_PHASE_RESULT:
1768 assert(!(fdctrl->msr & FD_MSR_NONDMA));
1769 if (++fdctrl->data_pos == fdctrl->data_len) {
6cc8a11c 1770 fdctrl->msr &= ~FD_MSR_RQM;
07e415f2 1771 fdctrl_to_command_phase(fdctrl);
ed5fd2cc
FB		 1772 fdctrl_reset_irq(fdctrl);
1773 }
f6c2d1d8
KW		 1774 break;
1775
1776 case FD_PHASE_COMMAND:
1777 default:
1778 abort();
8977f3c1 1779 }
f6c2d1d8
KW		 1780
1781 retval = fdctrl->fifo[pos];
8977f3c1
FB		 1782 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1783
1784 return retval;
1785}
1786
5c02c033 1787static void fdctrl_format_sector(FDCtrl *fdctrl)
8977f3c1 1788{
5c02c033 1789 FDrive *cur_drv;
baca51fa 1790 uint8_t kh, kt, ks;
8977f3c1 1791
cefec4f5 1792 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
baca51fa
FB		 1793 cur_drv = get_cur_drv(fdctrl);
1794 kt = fdctrl->fifo[6];
1795 kh = fdctrl->fifo[7];
1796 ks = fdctrl->fifo[8];
1797 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
cefec4f5 1798 GET_CUR_DRV(fdctrl), kh, kt, ks,
08388273
HP		 1799 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1800 NUM_SIDES(cur_drv)));
9fea808a 1801 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
baca51fa
FB		 1802 case 2:
1803 /* sect too big */
9fea808a 1804 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1805 fdctrl->fifo[3] = kt;
1806 fdctrl->fifo[4] = kh;
1807 fdctrl->fifo[5] = ks;
1808 return;
1809 case 3:
1810 /* track too big */
77370520 1811 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
baca51fa
FB		 1812 fdctrl->fifo[3] = kt;
1813 fdctrl->fifo[4] = kh;
1814 fdctrl->fifo[5] = ks;
1815 return;
1816 case 4:
1817 /* No seek enabled */
9fea808a 1818 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
baca51fa
FB		 1819 fdctrl->fifo[3] = kt;
1820 fdctrl->fifo[4] = kh;
1821 fdctrl->fifo[5] = ks;
1822 return;
1823 case 1:
cd30b53d 1824 fdctrl->status0 |= FD_SR0_SEEK;
baca51fa
FB		 1825 break;
1826 default:
1827 break;
1828 }
1829 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
4be74634 1830 if (cur_drv->blk == NULL ||
a7a5b7c0
EB		 1831 blk_pwrite(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
1832 BDRV_SECTOR_SIZE, 0) < 0) {
cced7a13 1833 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv));
9fea808a 1834 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
baca51fa 1835 } else {
4f431960
JM		 1836 if (cur_drv->sect == cur_drv->last_sect) {
1837 fdctrl->data_state &= ~FD_STATE_FORMAT;
1838 /* Last sector done */
cd30b53d 1839 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
4f431960
JM		 1840 } else {
1841 /* More to do */
1842 fdctrl->data_pos = 0;
1843 fdctrl->data_len = 4;
1844 }
baca51fa
FB		 1845 }
1846}
1847
5c02c033 1848static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
65cef780
BS		 1849{
1850 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1851 fdctrl->fifo[0] = fdctrl->lock << 4;
83a26013 1852 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 1853}
1854
5c02c033 1855static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
65cef780 1856{
5c02c033 1857 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 1858
1859 /* Drives position */
1860 fdctrl->fifo[0] = drv0(fdctrl)->track;
1861 fdctrl->fifo[1] = drv1(fdctrl)->track;
78ae820c
BS		 1862#if MAX_FD == 4
1863 fdctrl->fifo[2] = drv2(fdctrl)->track;
1864 fdctrl->fifo[3] = drv3(fdctrl)->track;
1865#else
65cef780
BS		 1866 fdctrl->fifo[2] = 0;
1867 fdctrl->fifo[3] = 0;
78ae820c 1868#endif
65cef780
BS		 1869 /* timers */
1870 fdctrl->fifo[4] = fdctrl->timer0;
368df94d 1871 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
65cef780
BS		 1872 fdctrl->fifo[6] = cur_drv->last_sect;
1873 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1874 (cur_drv->perpendicular << 2);
1875 fdctrl->fifo[8] = fdctrl->config;
1876 fdctrl->fifo[9] = fdctrl->precomp_trk;
83a26013 1877 fdctrl_to_result_phase(fdctrl, 10);
65cef780
BS		 1878}
1879
5c02c033 1880static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
65cef780
BS		 1881{
1882 /* Controller's version */
1883 fdctrl->fifo[0] = fdctrl->version;
83a26013 1884 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 1885}
1886
5c02c033 1887static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
65cef780
BS		 1888{
1889 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
83a26013 1890 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 1891}
1892
5c02c033 1893static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
65cef780 1894{
5c02c033 1895 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 1896
1897 /* Drives position */
1898 drv0(fdctrl)->track = fdctrl->fifo[3];
1899 drv1(fdctrl)->track = fdctrl->fifo[4];
78ae820c
BS		 1900#if MAX_FD == 4
1901 drv2(fdctrl)->track = fdctrl->fifo[5];
1902 drv3(fdctrl)->track = fdctrl->fifo[6];
1903#endif
65cef780
BS		 1904 /* timers */
1905 fdctrl->timer0 = fdctrl->fifo[7];
1906 fdctrl->timer1 = fdctrl->fifo[8];
1907 cur_drv->last_sect = fdctrl->fifo[9];
1908 fdctrl->lock = fdctrl->fifo[10] >> 7;
1909 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1910 fdctrl->config = fdctrl->fifo[11];
1911 fdctrl->precomp_trk = fdctrl->fifo[12];
1912 fdctrl->pwrd = fdctrl->fifo[13];
07e415f2 1913 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 1914}
1915
5c02c033 1916static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
65cef780 1917{
5c02c033 1918 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 1919
1920 fdctrl->fifo[0] = 0;
1921 fdctrl->fifo[1] = 0;
1922 /* Drives position */
1923 fdctrl->fifo[2] = drv0(fdctrl)->track;
1924 fdctrl->fifo[3] = drv1(fdctrl)->track;
78ae820c
BS		 1925#if MAX_FD == 4
1926 fdctrl->fifo[4] = drv2(fdctrl)->track;
1927 fdctrl->fifo[5] = drv3(fdctrl)->track;
1928#else
65cef780
BS		 1929 fdctrl->fifo[4] = 0;
1930 fdctrl->fifo[5] = 0;
78ae820c 1931#endif
65cef780
BS		 1932 /* timers */
1933 fdctrl->fifo[6] = fdctrl->timer0;
1934 fdctrl->fifo[7] = fdctrl->timer1;
1935 fdctrl->fifo[8] = cur_drv->last_sect;
1936 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1937 (cur_drv->perpendicular << 2);
1938 fdctrl->fifo[10] = fdctrl->config;
1939 fdctrl->fifo[11] = fdctrl->precomp_trk;
1940 fdctrl->fifo[12] = fdctrl->pwrd;
1941 fdctrl->fifo[13] = 0;
1942 fdctrl->fifo[14] = 0;
83a26013 1943 fdctrl_to_result_phase(fdctrl, 15);
65cef780
BS		 1944}
1945
5c02c033 1946static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
65cef780 1947{
5c02c033 1948 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780 1949
65cef780 1950 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
73bcb24d
RS		 1951 timer_mod(fdctrl->result_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
1952 (NANOSECONDS_PER_SECOND / 50));
65cef780
BS		 1953}
1954
5c02c033 1955static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
65cef780 1956{
5c02c033 1957 FDrive *cur_drv;
65cef780 1958
cefec4f5 1959 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780
BS		 1960 cur_drv = get_cur_drv(fdctrl);
1961 fdctrl->data_state |= FD_STATE_FORMAT;
1962 if (fdctrl->fifo[0] & 0x80)
1963 fdctrl->data_state |= FD_STATE_MULTI;
1964 else
1965 fdctrl->data_state &= ~FD_STATE_MULTI;
65cef780
BS		 1966 cur_drv->bps =
1967 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1968#if 0
1969 cur_drv->last_sect =
1970 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1971 fdctrl->fifo[3] / 2;
1972#else
1973 cur_drv->last_sect = fdctrl->fifo[3];
1974#endif
1975 /* TODO: implement format using DMA expected by the Bochs BIOS
1976 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1977 * the sector with the specified fill byte
1978 */
1979 fdctrl->data_state &= ~FD_STATE_FORMAT;
1980 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1981}
1982
5c02c033 1983static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
65cef780
BS		 1984{
1985 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1986 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
368df94d
BS		 1987 if (fdctrl->fifo[2] & 1)
1988 fdctrl->dor &= ~FD_DOR_DMAEN;
1989 else
1990 fdctrl->dor |= FD_DOR_DMAEN;
65cef780 1991 /* No result back */
07e415f2 1992 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 1993}
1994
5c02c033 1995static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
65cef780 1996{
5c02c033 1997 FDrive *cur_drv;
65cef780 1998
cefec4f5 1999 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780
BS		 2000 cur_drv = get_cur_drv(fdctrl);
2001 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
2002 /* 1 Byte status back */
2003 fdctrl->fifo[0] = (cur_drv->ro << 6) |
2004 (cur_drv->track == 0 ? 0x10 : 0x00) |
2005 (cur_drv->head << 2) |
cefec4f5 2006 GET_CUR_DRV(fdctrl) |
65cef780 2007 0x28;
83a26013 2008 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2009}
2010
5c02c033 2011static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
65cef780 2012{
5c02c033 2013 FDrive *cur_drv;
65cef780 2014
cefec4f5 2015 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780
BS		 2016 cur_drv = get_cur_drv(fdctrl);
2017 fd_recalibrate(cur_drv);
07e415f2 2018 fdctrl_to_command_phase(fdctrl);
65cef780 2019 /* Raise Interrupt */
d497d534
HP		 2020 fdctrl->status0 |= FD_SR0_SEEK;
2021 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2022}
2023
5c02c033 2024static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
65cef780 2025{
5c02c033 2026 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780 2027
2fee0088 2028 if (fdctrl->reset_sensei > 0) {
f2d81b33
BS		 2029 fdctrl->fifo[0] =
2030 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
2031 fdctrl->reset_sensei--;
2fee0088
PH		 2032 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) {
2033 fdctrl->fifo[0] = FD_SR0_INVCMD;
83a26013 2034 fdctrl_to_result_phase(fdctrl, 1);
2fee0088 2035 return;
f2d81b33 2036 } else {
f2d81b33 2037 fdctrl->fifo[0] =
2fee0088
PH		 2038 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0))
2039 | GET_CUR_DRV(fdctrl);
f2d81b33
BS		 2040 }
2041
65cef780 2042 fdctrl->fifo[1] = cur_drv->track;
83a26013 2043 fdctrl_to_result_phase(fdctrl, 2);
65cef780 2044 fdctrl_reset_irq(fdctrl);
77370520 2045 fdctrl->status0 = FD_SR0_RDYCHG;
65cef780
BS		 2046}
2047
5c02c033 2048static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
65cef780 2049{
5c02c033 2050 FDrive *cur_drv;
65cef780 2051
cefec4f5 2052 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780 2053 cur_drv = get_cur_drv(fdctrl);
07e415f2 2054 fdctrl_to_command_phase(fdctrl);
b072a3c8
HP		 2055 /* The seek command just sends step pulses to the drive and doesn't care if
2056 * there is a medium inserted of if it's banging the head against the drive.
2057 */
6be01b1e 2058 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1);
b072a3c8 2059 /* Raise Interrupt */
d497d534
HP		 2060 fdctrl->status0 |= FD_SR0_SEEK;
2061 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2062}
2063
5c02c033 2064static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
65cef780 2065{
5c02c033 2066 FDrive *cur_drv = get_cur_drv(fdctrl);
65cef780
BS		 2067
2068 if (fdctrl->fifo[1] & 0x80)
2069 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
2070 /* No result back */
07e415f2 2071 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2072}
2073
5c02c033 2074static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
65cef780
BS		 2075{
2076 fdctrl->config = fdctrl->fifo[2];
2077 fdctrl->precomp_trk = fdctrl->fifo[3];
2078 /* No result back */
07e415f2 2079 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2080}
2081
5c02c033 2082static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
65cef780
BS		 2083{
2084 fdctrl->pwrd = fdctrl->fifo[1];
2085 fdctrl->fifo[0] = fdctrl->fifo[1];
83a26013 2086 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2087}
2088
5c02c033 2089static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
65cef780
BS		 2090{
2091 /* No result back */
07e415f2 2092 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2093}
2094
5c02c033 2095static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
65cef780 2096{
5c02c033 2097 FDrive *cur_drv = get_cur_drv(fdctrl);
e9077462 2098 uint32_t pos;
65cef780 2099
e9077462
PM		 2100 pos = fdctrl->data_pos - 1;
2101 pos %= FD_SECTOR_LEN;
2102 if (fdctrl->fifo[pos] & 0x80) {
65cef780 2103 /* Command parameters done */
e9077462 2104 if (fdctrl->fifo[pos] & 0x40) {
65cef780
BS		 2105 fdctrl->fifo[0] = fdctrl->fifo[1];
2106 fdctrl->fifo[2] = 0;
2107 fdctrl->fifo[3] = 0;
83a26013 2108 fdctrl_to_result_phase(fdctrl, 4);
65cef780 2109 } else {
07e415f2 2110 fdctrl_to_command_phase(fdctrl);
65cef780
BS		 2111 }
2112 } else if (fdctrl->data_len > 7) {
2113 /* ERROR */
2114 fdctrl->fifo[0] = 0x80 |
cefec4f5 2115 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
83a26013 2116 fdctrl_to_result_phase(fdctrl, 1);
65cef780
BS		 2117 }
2118}
2119
6d013772 2120static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
65cef780 2121{
5c02c033 2122 FDrive *cur_drv;
65cef780 2123
cefec4f5 2124 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780 2125 cur_drv = get_cur_drv(fdctrl);
65cef780 2126 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
6be01b1e
PH		 2127 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1,
2128 cur_drv->sect, 1);
65cef780 2129 } else {
6d013772
PH		 2130 fd_seek(cur_drv, cur_drv->head,
2131 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1);
65cef780 2132 }
07e415f2 2133 fdctrl_to_command_phase(fdctrl);
77370520 2134 /* Raise Interrupt */
d497d534
HP		 2135 fdctrl->status0 |= FD_SR0_SEEK;
2136 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2137}
2138
6d013772 2139static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
65cef780 2140{
5c02c033 2141 FDrive *cur_drv;
65cef780 2142
cefec4f5 2143 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
65cef780 2144 cur_drv = get_cur_drv(fdctrl);
65cef780 2145 if (fdctrl->fifo[2] > cur_drv->track) {
6be01b1e 2146 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1);
65cef780 2147 } else {
6d013772
PH		 2148 fd_seek(cur_drv, cur_drv->head,
2149 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1);
65cef780 2150 }
07e415f2 2151 fdctrl_to_command_phase(fdctrl);
65cef780 2152 /* Raise Interrupt */
d497d534
HP		 2153 fdctrl->status0 |= FD_SR0_SEEK;
2154 fdctrl_raise_irq(fdctrl);
65cef780
BS		 2155}
2156
85d291a0
KW		 2157/*
2158 * Handlers for the execution phase of each command
2159 */
d275b33d 2160typedef struct FDCtrlCommand {
678803ab
BS		 2161 uint8_t value;
2162 uint8_t mask;
2163 const char* name;
2164 int parameters;
5c02c033 2165 void (*handler)(FDCtrl *fdctrl, int direction);
678803ab 2166 int direction;
d275b33d
KW		 2167} FDCtrlCommand;
2168
2169static const FDCtrlCommand handlers[] = {
678803ab
BS		 2170 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
2171 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
2172 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
2173 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
2174 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
2175 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
2176 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
2177 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
2178 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
2179 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
2180 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
7ea004ed 2181 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY },
678803ab
BS		 2182 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
2183 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
2184 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
2185 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
2186 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
2187 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
2188 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
2189 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
2190 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
2191 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
2192 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
2193 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
2194 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
2195 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
2196 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
2197 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
2198 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
2199 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
2200 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
2201 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
2202};
2203/* Associate command to an index in the 'handlers' array */
2204static uint8_t command_to_handler[256];
2205
d275b33d
KW		 2206static const FDCtrlCommand *get_command(uint8_t cmd)
2207{
2208 int idx;
2209
2210 idx = command_to_handler[cmd];
2211 FLOPPY_DPRINTF("%s command\n", handlers[idx].name);
2212 return &handlers[idx];
2213}
2214
5c02c033 2215static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
baca51fa 2216{
5c02c033 2217 FDrive *cur_drv;
d275b33d 2218 const FDCtrlCommand *cmd;
e9077462 2219 uint32_t pos;
baca51fa 2220
8977f3c1 2221 /* Reset mode */
1c346df2 2222 if (!(fdctrl->dor & FD_DOR_nRESET)) {
4b19ec0c 2223 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
8977f3c1
FB		 2224 return;
2225 }
b9b3d225 2226 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
cced7a13 2227 FLOPPY_DPRINTF("error: controller not ready for writing\n");
8977f3c1
FB		 2228 return;
2229 }
b9b3d225 2230 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
5b0a25e8 2231
d275b33d
KW		 2232 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
2233
2234 /* If data_len spans multiple sectors, the current position in the FIFO
2235 * wraps around while fdctrl->data_pos is the real position in the whole
2236 * request. */
2237 pos = fdctrl->data_pos++;
2238 pos %= FD_SECTOR_LEN;
2239 fdctrl->fifo[pos] = value;
2240
6cc8a11c
KW		 2241 if (fdctrl->data_pos == fdctrl->data_len) {
2242 fdctrl->msr &= ~FD_MSR_RQM;
2243 }
2244
5b0a25e8
KW		 2245 switch (fdctrl->phase) {
2246 case FD_PHASE_EXECUTION:
2247 /* For DMA requests, RQM should be cleared during execution phase, so
2248 * we would have errored out above. */
2249 assert(fdctrl->msr & FD_MSR_NONDMA);
d275b33d 2250
8977f3c1 2251 /* FIFO data write */
b3bc1540 2252 if (pos == FD_SECTOR_LEN - 1 ||
baca51fa 2253 fdctrl->data_pos == fdctrl->data_len) {
77370520 2254 cur_drv = get_cur_drv(fdctrl);
a7a5b7c0
EB		 2255 if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
2256 BDRV_SECTOR_SIZE, 0) < 0) {
cced7a13
BS		 2257 FLOPPY_DPRINTF("error writing sector %d\n",
2258 fd_sector(cur_drv));
5b0a25e8 2259 break;
77370520 2260 }
746d6de7
BS		 2261 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
2262 FLOPPY_DPRINTF("error seeking to next sector %d\n",
2263 fd_sector(cur_drv));
5b0a25e8 2264 break;
746d6de7 2265 }
8977f3c1 2266 }
d275b33d
KW		 2267
2268 /* Switch to result phase when done with the transfer */
2269 if (fdctrl->data_pos == fdctrl->data_len) {
c5139bd9 2270 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
d275b33d 2271 }
5b0a25e8 2272 break;
678803ab 2273
5b0a25e8
KW		 2274 case FD_PHASE_COMMAND:
2275 assert(!(fdctrl->msr & FD_MSR_NONDMA));
d275b33d 2276 assert(fdctrl->data_pos < FD_SECTOR_LEN);
5b0a25e8 2277
d275b33d
KW		 2278 if (pos == 0) {
2279 /* The first byte specifies the command. Now we start reading
2280 * as many parameters as this command requires. */
2281 cmd = get_command(value);
2282 fdctrl->data_len = cmd->parameters + 1;
6cc8a11c
KW		 2283 if (cmd->parameters) {
2284 fdctrl->msr |= FD_MSR_RQM;
2285 }
5b0a25e8 2286 fdctrl->msr |= FD_MSR_CMDBUSY;
8977f3c1 2287 }
65cef780 2288
5b0a25e8 2289 if (fdctrl->data_pos == fdctrl->data_len) {
d275b33d 2290 /* We have all parameters now, execute the command */
5b0a25e8 2291 fdctrl->phase = FD_PHASE_EXECUTION;
d275b33d 2292
5b0a25e8
KW		 2293 if (fdctrl->data_state & FD_STATE_FORMAT) {
2294 fdctrl_format_sector(fdctrl);
2295 break;
2296 }
2297
d275b33d
KW		 2298 cmd = get_command(fdctrl->fifo[0]);
2299 FLOPPY_DPRINTF("Calling handler for '%s'\n", cmd->name);
2300 cmd->handler(fdctrl, cmd->direction);
5b0a25e8
KW		 2301 }
2302 break;
2303
2304 case FD_PHASE_RESULT:
2305 default:
2306 abort();
8977f3c1
FB		 2307 }
2308}
ed5fd2cc
FB		 2309
2310static void fdctrl_result_timer(void *opaque)
2311{
5c02c033
BS		 2312 FDCtrl *fdctrl = opaque;
2313 FDrive *cur_drv = get_cur_drv(fdctrl);
4f431960 2314
b7ffa3b1
TS		 2315 /* Pretend we are spinning.
2316 * This is needed for Coherent, which uses READ ID to check for
2317 * sector interleaving.
2318 */
2319 if (cur_drv->last_sect != 0) {
2320 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
2321 }
844f65d6
HP		 2322 /* READ_ID can't automatically succeed! */
2323 if (fdctrl->check_media_rate &&
2324 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
2325 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
2326 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
2327 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
2328 } else {
2329 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2330 }
ed5fd2cc 2331}
678803ab 2332
7d4b4ba5 2333static void fdctrl_change_cb(void *opaque, bool load)
8e49ca46
MA		 2334{
2335 FDrive *drive = opaque;
2336
2337 drive->media_changed = 1;
d5d47efc 2338 drive->media_validated = false;
21fcf360 2339 fd_revalidate(drive);
8e49ca46
MA		 2340}
2341
2342static const BlockDevOps fdctrl_block_ops = {
2343 .change_media_cb = fdctrl_change_cb,
2344};
2345
678803ab 2346/* Init functions */
a3ef7a61 2347static void fdctrl_connect_drives(FDCtrl *fdctrl, Error **errp)
678803ab 2348{
12a71a02 2349 unsigned int i;
7d0d6950 2350 FDrive *drive;
678803ab 2351
678803ab 2352 for (i = 0; i < MAX_FD; i++) {
7d0d6950 2353 drive = &fdctrl->drives[i];
844f65d6 2354 drive->fdctrl = fdctrl;
7d0d6950 2355
4be74634
MA		 2356 if (drive->blk) {
2357 if (blk_get_on_error(drive->blk, 0) != BLOCKDEV_ON_ERROR_ENOSPC) {
a3ef7a61
AF		 2358 error_setg(errp, "fdc doesn't support drive option werror");
2359 return;
b47b3525 2360 }
4be74634 2361 if (blk_get_on_error(drive->blk, 1) != BLOCKDEV_ON_ERROR_REPORT) {
a3ef7a61
AF		 2362 error_setg(errp, "fdc doesn't support drive option rerror");
2363 return;
b47b3525
MA		 2364 }
2365 }
2366
7d0d6950 2367 fd_init(drive);
4be74634
MA		 2368 if (drive->blk) {
2369 blk_set_dev_ops(drive->blk, &fdctrl_block_ops, drive);
d5d47efc 2370 pick_drive_type(drive);
7d0d6950 2371 }
d5d47efc 2372 fd_revalidate(drive);
678803ab 2373 }
678803ab
BS		 2374}
2375
dfc65f1f
MA		 2376ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds)
2377{
4a17cc4f
AF		 2378 DeviceState *dev;
2379 ISADevice *isadev;
dfc65f1f 2380
4a17cc4f
AF		 2381 isadev = isa_try_create(bus, TYPE_ISA_FDC);
2382 if (!isadev) {
dfc65f1f
MA		 2383 return NULL;
2384 }
4a17cc4f 2385 dev = DEVICE(isadev);
dfc65f1f
MA		 2386
2387 if (fds[0]) {
6231a6da
MA		 2388 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]),
2389 &error_fatal);
dfc65f1f
MA		 2390 }
2391 if (fds[1]) {
6231a6da
MA		 2392 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
2393 &error_fatal);
dfc65f1f 2394 }
4a17cc4f 2395 qdev_init_nofail(dev);
dfc65f1f 2396
4a17cc4f 2397 return isadev;
dfc65f1f
MA		 2398}
2399
63ffb564 2400void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
a8170e5e 2401 hwaddr mmio_base, DriveInfo **fds)
2091ba23 2402{
5c02c033 2403 FDCtrl *fdctrl;
2091ba23 2404 DeviceState *dev;
dd3be742 2405 SysBusDevice *sbd;
5c02c033 2406 FDCtrlSysBus *sys;
2091ba23 2407
19d46d71 2408 dev = qdev_create(NULL, "sysbus-fdc");
dd3be742 2409 sys = SYSBUS_FDC(dev);
99244fa1
GH		 2410 fdctrl = &sys->state;
2411 fdctrl->dma_chann = dma_chann; /* FIXME */
995bf0ca 2412 if (fds[0]) {
6231a6da
MA		 2413 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fds[0]),
2414 &error_fatal);
995bf0ca
GH		 2415 }
2416 if (fds[1]) {
6231a6da
MA		 2417 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fds[1]),
2418 &error_fatal);
995bf0ca 2419 }
e23a1b33 2420 qdev_init_nofail(dev);
dd3be742
HT		 2421 sbd = SYS_BUS_DEVICE(dev);
2422 sysbus_connect_irq(sbd, 0, irq);
2423 sysbus_mmio_map(sbd, 0, mmio_base);
678803ab
BS		 2424}
2425
a8170e5e 2426void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
63ffb564 2427 DriveInfo **fds, qemu_irq *fdc_tc)
678803ab 2428{
f64ab228 2429 DeviceState *dev;
5c02c033 2430 FDCtrlSysBus *sys;
678803ab 2431
12a71a02 2432 dev = qdev_create(NULL, "SUNW,fdtwo");
995bf0ca 2433 if (fds[0]) {
6231a6da
MA		 2434 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(fds[0]),
2435 &error_fatal);
995bf0ca 2436 }
e23a1b33 2437 qdev_init_nofail(dev);
dd3be742
HT		 2438 sys = SYSBUS_FDC(dev);
2439 sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq);
2440 sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base);
f64ab228 2441 *fdc_tc = qdev_get_gpio_in(dev, 0);
678803ab 2442}
f64ab228 2443
a3ef7a61 2444static void fdctrl_realize_common(FDCtrl *fdctrl, Error **errp)
f64ab228 2445{
12a71a02
BS		 2446 int i, j;
2447 static int command_tables_inited = 0;
f64ab228 2448
a73275dd
JS		 2449 if (fdctrl->fallback == FLOPPY_DRIVE_TYPE_AUTO) {
2450 error_setg(errp, "Cannot choose a fallback FDrive type of 'auto'");
2451 }
2452
12a71a02
BS		 2453 /* Fill 'command_to_handler' lookup table */
2454 if (!command_tables_inited) {
2455 command_tables_inited = 1;
2456 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
2457 for (j = 0; j < sizeof(command_to_handler); j++) {
2458 if ((j & handlers[i].mask) == handlers[i].value) {
2459 command_to_handler[j] = i;
2460 }
2461 }
2462 }
2463 }
2464
2465 FLOPPY_DPRINTF("init controller\n");
2466 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
d7a6c270 2467 fdctrl->fifo_size = 512;
bc72ad67 2468 fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
a3ef7a61 2469 fdctrl_result_timer, fdctrl);
12a71a02
BS		 2470
2471 fdctrl->version = 0x90; /* Intel 82078 controller */
2472 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
d7a6c270 2473 fdctrl->num_floppies = MAX_FD;
12a71a02 2474
a3ef7a61 2475 if (fdctrl->dma_chann != -1) {
c8a35f1c
HP		 2476 IsaDmaClass *k;
2477 assert(fdctrl->dma);
2478 k = ISADMA_GET_CLASS(fdctrl->dma);
2479 k->register_channel(fdctrl->dma, fdctrl->dma_chann,
2480 &fdctrl_transfer_handler, fdctrl);
a3ef7a61
AF		 2481 }
2482 fdctrl_connect_drives(fdctrl, errp);
f64ab228
BS		 2483}
2484
212ec7ba 2485static const MemoryRegionPortio fdc_portio_list[] = {
2f290a8c 2486 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
212ec7ba
RH		 2487 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
2488 PORTIO_END_OF_LIST(),
2f290a8c
RH		 2489};
2490
db895a1e 2491static void isabus_fdc_realize(DeviceState *dev, Error **errp)
8baf73ad 2492{
db895a1e 2493 ISADevice *isadev = ISA_DEVICE(dev);
020c8e76 2494 FDCtrlISABus *isa = ISA_FDC(dev);
5c02c033 2495 FDCtrl *fdctrl = &isa->state;
a3ef7a61 2496 Error *err = NULL;
8baf73ad 2497
db895a1e
AF		 2498 isa_register_portio_list(isadev, isa->iobase, fdc_portio_list, fdctrl,
2499 "fdc");
dee41d58 2500
db895a1e 2501 isa_init_irq(isadev, &fdctrl->irq, isa->irq);
c9ae703d 2502 fdctrl->dma_chann = isa->dma;
c8a35f1c
HP		 2503 if (fdctrl->dma_chann != -1) {
2504 fdctrl->dma = isa_get_dma(isa_bus_from_device(isadev), isa->dma);
2505 assert(fdctrl->dma);
2506 }
8baf73ad 2507
db895a1e 2508 qdev_set_legacy_instance_id(dev, isa->iobase, 2);
a3ef7a61
AF		 2509 fdctrl_realize_common(fdctrl, &err);
2510 if (err != NULL) {
2511 error_propagate(errp, err);
db895a1e
AF		 2512 return;
2513 }
8baf73ad
GH		 2514}
2515
940194c2 2516static void sysbus_fdc_initfn(Object *obj)
12a71a02 2517{
19d46d71 2518 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
940194c2 2519 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
5c02c033 2520 FDCtrl *fdctrl = &sys->state;
12a71a02 2521
19d46d71
AF		 2522 fdctrl->dma_chann = -1;
2523
940194c2 2524 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl,
2d256e6f 2525 "fdc", 0x08);
19d46d71 2526 sysbus_init_mmio(sbd, &fdctrl->iomem);
940194c2
HT		 2527}
2528
19d46d71 2529static void sun4m_fdc_initfn(Object *obj)
940194c2 2530{
19d46d71
AF		 2531 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2532 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
940194c2 2533 FDCtrl *fdctrl = &sys->state;
940194c2 2534
dd446051
HP		 2535 fdctrl->dma_chann = -1;
2536
19d46d71
AF		 2537 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops,
2538 fdctrl, "fdctrl", 0x08);
2539 sysbus_init_mmio(sbd, &fdctrl->iomem);
940194c2 2540}
2be37833 2541
19d46d71 2542static void sysbus_fdc_common_initfn(Object *obj)
940194c2 2543{
19d46d71
AF		 2544 DeviceState *dev = DEVICE(obj);
2545 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
940194c2
HT		 2546 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2547 FDCtrl *fdctrl = &sys->state;
2548
19d46d71
AF		 2549 qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */
2550
2551 sysbus_init_irq(sbd, &fdctrl->irq);
2552 qdev_init_gpio_in(dev, fdctrl_handle_tc, 1);
12a71a02
BS		 2553}
2554
19d46d71 2555static void sysbus_fdc_common_realize(DeviceState *dev, Error **errp)
12a71a02 2556{
dd3be742
HT		 2557 FDCtrlSysBus *sys = SYSBUS_FDC(dev);
2558 FDCtrl *fdctrl = &sys->state;
12a71a02 2559
19d46d71 2560 fdctrl_realize_common(fdctrl, errp);
12a71a02 2561}
f64ab228 2562
2da44dd0 2563FloppyDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i)
34d4260e 2564{
020c8e76 2565 FDCtrlISABus *isa = ISA_FDC(fdc);
34d4260e 2566
61a8d649 2567 return isa->state.drives[i].drive;
34d4260e
KW		 2568}
2569
e08fde0c
RK		 2570void isa_fdc_get_drive_max_chs(FloppyDriveType type,
2571 uint8_t *maxc, uint8_t *maxh, uint8_t *maxs)
2572{
2573 const FDFormat *fdf;
2574
2575 *maxc = *maxh = *maxs = 0;
2576 for (fdf = fd_formats; fdf->drive != FLOPPY_DRIVE_TYPE_NONE; fdf++) {
2577 if (fdf->drive != type) {
2578 continue;
2579 }
2580 if (*maxc < fdf->max_track) {
2581 *maxc = fdf->max_track;
2582 }
2583 if (*maxh < fdf->max_head) {
2584 *maxh = fdf->max_head;
2585 }
2586 if (*maxs < fdf->last_sect) {
2587 *maxs = fdf->last_sect;
2588 }
2589 }
2590 (*maxc)--;
2591}
2592
a64405d1
JK		 2593static const VMStateDescription vmstate_isa_fdc ={
2594 .name = "fdc",
2595 .version_id = 2,
2596 .minimum_version_id = 2,
d49805ae 2597 .fields = (VMStateField[]) {
a64405d1
JK		 2598 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2599 VMSTATE_END_OF_LIST()
2600 }
2601};
2602
39bffca2 2603static Property isa_fdc_properties[] = {
c7bcc85d 2604 DEFINE_PROP_UINT32("iobase", FDCtrlISABus, iobase, 0x3f0),
c9ae703d
HP		 2605 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
2606 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
4be74634
MA		 2607 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].blk),
2608 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].blk),
09c6d585
HP		 2609 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2610 0, true),
fff4687b
JS		 2611 DEFINE_PROP_DEFAULT("fdtypeA", FDCtrlISABus, state.drives[0].drive,
2612 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2613 FloppyDriveType),
2614 DEFINE_PROP_DEFAULT("fdtypeB", FDCtrlISABus, state.drives[1].drive,
2615 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2616 FloppyDriveType),
a73275dd 2617 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback,
4812fa27 2618 FLOPPY_DRIVE_TYPE_288, qdev_prop_fdc_drive_type,
a73275dd 2619 FloppyDriveType),
39bffca2
AL		 2620 DEFINE_PROP_END_OF_LIST(),
2621};
2622
020c8e76 2623static void isabus_fdc_class_init(ObjectClass *klass, void *data)
8f04ee08 2624{
39bffca2 2625 DeviceClass *dc = DEVICE_CLASS(klass);
db895a1e
AF		 2626
2627 dc->realize = isabus_fdc_realize;
39bffca2 2628 dc->fw_name = "fdc";
39bffca2
AL		 2629 dc->reset = fdctrl_external_reset_isa;
2630 dc->vmsd = &vmstate_isa_fdc;
2631 dc->props = isa_fdc_properties;
125ee0ed 2632 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
39bffca2
AL		 2633}
2634
81782b6a
GA		 2635static void isabus_fdc_instance_init(Object *obj)
2636{
2637 FDCtrlISABus *isa = ISA_FDC(obj);
2638
2639 device_add_bootindex_property(obj, &isa->bootindexA,
2640 "bootindexA", "/floppy@0",
2641 DEVICE(obj), NULL);
2642 device_add_bootindex_property(obj, &isa->bootindexB,
2643 "bootindexB", "/floppy@1",
2644 DEVICE(obj), NULL);
2645}
2646
8c43a6f0 2647static const TypeInfo isa_fdc_info = {
020c8e76 2648 .name = TYPE_ISA_FDC,
39bffca2
AL		 2649 .parent = TYPE_ISA_DEVICE,
2650 .instance_size = sizeof(FDCtrlISABus),
020c8e76 2651 .class_init = isabus_fdc_class_init,
81782b6a 2652 .instance_init = isabus_fdc_instance_init,
8baf73ad
GH		 2653};
2654
a64405d1
JK		 2655static const VMStateDescription vmstate_sysbus_fdc ={
2656 .name = "fdc",
2657 .version_id = 2,
2658 .minimum_version_id = 2,
d49805ae 2659 .fields = (VMStateField[]) {
a64405d1
JK		 2660 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2661 VMSTATE_END_OF_LIST()
2662 }
2663};
2664
999e12bb 2665static Property sysbus_fdc_properties[] = {
4be74634
MA		 2666 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].blk),
2667 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].blk),
fff4687b
JS		 2668 DEFINE_PROP_DEFAULT("fdtypeA", FDCtrlSysBus, state.drives[0].drive,
2669 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2670 FloppyDriveType),
2671 DEFINE_PROP_DEFAULT("fdtypeB", FDCtrlSysBus, state.drives[1].drive,
2672 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2673 FloppyDriveType),
a73275dd
JS		 2674 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback,
2675 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2676 FloppyDriveType),
999e12bb 2677 DEFINE_PROP_END_OF_LIST(),
12a71a02
BS		 2678};
2679
999e12bb
AL		 2680static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2681{
39bffca2 2682 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb 2683
39bffca2 2684 dc->props = sysbus_fdc_properties;
125ee0ed 2685 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
999e12bb
AL		 2686}
2687
8c43a6f0 2688static const TypeInfo sysbus_fdc_info = {
19d46d71
AF		 2689 .name = "sysbus-fdc",
2690 .parent = TYPE_SYSBUS_FDC,
940194c2 2691 .instance_init = sysbus_fdc_initfn,
39bffca2 2692 .class_init = sysbus_fdc_class_init,
999e12bb
AL		 2693};
2694
2695static Property sun4m_fdc_properties[] = {
4be74634 2696 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].blk),
fff4687b
JS		 2697 DEFINE_PROP_DEFAULT("fdtype", FDCtrlSysBus, state.drives[0].drive,
2698 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2699 FloppyDriveType),
a73275dd
JS		 2700 DEFINE_PROP_DEFAULT("fallback", FDCtrlISABus, state.fallback,
2701 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2702 FloppyDriveType),
999e12bb
AL		 2703 DEFINE_PROP_END_OF_LIST(),
2704};
2705
2706static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2707{
39bffca2 2708 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb 2709
39bffca2 2710 dc->props = sun4m_fdc_properties;
125ee0ed 2711 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
999e12bb
AL		 2712}
2713
8c43a6f0 2714static const TypeInfo sun4m_fdc_info = {
39bffca2 2715 .name = "SUNW,fdtwo",
19d46d71 2716 .parent = TYPE_SYSBUS_FDC,
940194c2 2717 .instance_init = sun4m_fdc_initfn,
39bffca2 2718 .class_init = sun4m_fdc_class_init,
f64ab228
BS		 2719};
2720
19d46d71
AF		 2721static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data)
2722{
2723 DeviceClass *dc = DEVICE_CLASS(klass);
2724
2725 dc->realize = sysbus_fdc_common_realize;
2726 dc->reset = fdctrl_external_reset_sysbus;
2727 dc->vmsd = &vmstate_sysbus_fdc;
2728}
2729
2730static const TypeInfo sysbus_fdc_type_info = {
2731 .name = TYPE_SYSBUS_FDC,
2732 .parent = TYPE_SYS_BUS_DEVICE,
2733 .instance_size = sizeof(FDCtrlSysBus),
2734 .instance_init = sysbus_fdc_common_initfn,
2735 .abstract = true,
2736 .class_init = sysbus_fdc_common_class_init,
2737};
2738
83f7d43a 2739static void fdc_register_types(void)
f64ab228 2740{
39bffca2 2741 type_register_static(&isa_fdc_info);
19d46d71 2742 type_register_static(&sysbus_fdc_type_info);
39bffca2
AL		 2743 type_register_static(&sysbus_fdc_info);
2744 type_register_static(&sun4m_fdc_info);
f64ab228
BS		 2745}
2746
83f7d43a 2747type_init(fdc_register_types)
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