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Merge remote-tracking branch 'remotes/sstabellini/tags/xen-20160126-2' into staging
[mirror_qemu.git] / hw / block / m25p80.c
CommitLineData
82a24990
PC		 1/*
2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
3 * set. Known devices table current as of Jun/2012 and taken from linux.
4 * See drivers/mtd/devices/m25p80.c.
5 *
6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Copyright (C) 2012 PetaLogix
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 or
13 * (at your option) a later version of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 */
23
80c71a24 24#include "qemu/osdep.h"
83c9f4ca 25#include "hw/hw.h"
fa1d36df 26#include "sysemu/block-backend.h"
9c17d615 27#include "sysemu/blockdev.h"
8fd06719 28#include "hw/ssi/ssi.h"
82a24990 29
28097d02
PC		 30#ifndef M25P80_ERR_DEBUG
31#define M25P80_ERR_DEBUG 0
82a24990
PC		 32#endif
33
28097d02
PC		 34#define DB_PRINT_L(level, ...) do { \
35 if (M25P80_ERR_DEBUG > (level)) { \
36 fprintf(stderr, ": %s: ", __func__); \
37 fprintf(stderr, ## __VA_ARGS__); \
38 } \
39} while (0);
40
82a24990
PC		 41/* Fields for FlashPartInfo->flags */
42
43/* erase capabilities */
44#define ER_4K 1
45#define ER_32K 2
46/* set to allow the page program command to write 0s back to 1. Useful for
47 * modelling EEPROM with SPI flash command set
48 */
49#define WR_1 0x100
50
51typedef struct FlashPartInfo {
52 const char *part_name;
53 /* jedec code. (jedec >> 16) & 0xff is the 1st byte, >> 8 the 2nd etc */
54 uint32_t jedec;
55 /* extended jedec code */
56 uint16_t ext_jedec;
57 /* there is confusion between manufacturers as to what a sector is. In this
58 * device model, a "sector" is the size that is erased by the ERASE_SECTOR
59 * command (opcode 0xd8).
60 */
61 uint32_t sector_size;
62 uint32_t n_sectors;
63 uint32_t page_size;
64 uint8_t flags;
65} FlashPartInfo;
66
67/* adapted from linux */
68
69#define INFO(_part_name, _jedec, _ext_jedec, _sector_size, _n_sectors, _flags)\
70 .part_name = (_part_name),\
71 .jedec = (_jedec),\
72 .ext_jedec = (_ext_jedec),\
73 .sector_size = (_sector_size),\
74 .n_sectors = (_n_sectors),\
75 .page_size = 256,\
76 .flags = (_flags),\
77
419336a9
PC		 78#define JEDEC_NUMONYX 0x20
79#define JEDEC_WINBOND 0xEF
80#define JEDEC_SPANSION 0x01
81
82a24990
PC		 82static const FlashPartInfo known_devices[] = {
83 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
84 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) },
85 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) },
86
87 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) },
88 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) },
89 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) },
90
91 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) },
92 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) },
93 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) },
94 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) },
95
3e758c1d
EM		 96 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) },
97
82a24990
PC		 98 /* EON -- en25xxx */
99 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) },
100 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) },
101 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) },
102 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) },
3e758c1d
EM		 103 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) },
104
105 /* GigaDevice */
106 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) },
107 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) },
82a24990
PC		 108
109 /* Intel/Numonyx -- xxxs33b */
110 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) },
111 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) },
112 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) },
3e758c1d 113 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) },
82a24990
PC		 114
115 /* Macronix */
3e758c1d 116 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
82a24990
PC		 117 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) },
118 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) },
119 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) },
120 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) },
121 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) },
122 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) },
123 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },
124 { INFO("mx25l25635e", 0xc22019, 0, 64 << 10, 512, 0) },
125 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },
126
3e758c1d 127 /* Micron */
f5aac8e0
EM		 128 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) },
129 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) },
130 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) },
131 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) },
132 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) },
133 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) },
134 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) },
135 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
3e758c1d 136
82a24990
PC		 137 /* Spansion -- single (large) sector size only, at least
138 * for the chips listed here (without boot sectors).
139 */
82a24990 140 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) },
3e758c1d 141 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) },
82a24990
PC		 142 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) },
143 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) },
144 { INFO("s25fl512s", 0x010220, 0x4d00, 256 << 10, 256, 0) },
145 { INFO("s70fl01gs", 0x010221, 0x4d00, 256 << 10, 256, 0) },
146 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) },
147 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) },
148 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) },
149 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) },
3e758c1d
EM		 150 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) },
151 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) },
152 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) },
153 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) },
154 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) },
82a24990
PC		 155 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) },
156 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) },
157
158 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
159 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) },
160 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) },
161 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) },
162 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) },
163 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) },
164 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) },
165 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) },
166 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) },
d857c4c0 167 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) },
82a24990
PC		 168
169 /* ST Microelectronics -- newer production may have feature updates */
170 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) },
171 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) },
172 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) },
173 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) },
174 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) },
175 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) },
176 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) },
177 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) },
178 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) },
3e758c1d 179 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) },
82a24990
PC		 180
181 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) },
182 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) },
183 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) },
184
3e758c1d 185 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) },
82a24990
PC		 186 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) },
187 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) },
188
189 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) },
190 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) },
191 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) },
192 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) },
193
194 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
195 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) },
196 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) },
197 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) },
198 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) },
199 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) },
200 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) },
201 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) },
3e758c1d 202 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) },
82a24990
PC		 203 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) },
204 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) },
3e758c1d
EM		 205 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) },
206 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) },
207 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) },
82a24990
PC		 208
209 /* Numonyx -- n25q128 */
210 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) },
82a24990
PC		 211};
212
213typedef enum {
214 NOP = 0,
03ec2f83 215 WRSR = 0x1,
82a24990
PC		 216 WRDI = 0x4,
217 RDSR = 0x5,
218 WREN = 0x6,
419336a9
PC		 219 JEDEC_READ = 0x9f,
220 BULK_ERASE = 0xc7,
221
222 READ = 0x3,
82a24990 223 FAST_READ = 0xb,
419336a9
PC		 224 DOR = 0x3b,
225 QOR = 0x6b,
226 DIOR = 0xbb,
227 QIOR = 0xeb,
228
229 PP = 0x2,
230 DPP = 0xa2,
231 QPP = 0x32,
232
82a24990
PC		 233 ERASE_4K = 0x20,
234 ERASE_32K = 0x52,
235 ERASE_SECTOR = 0xd8,
82a24990
PC		 236} FlashCMD;
237
238typedef enum {
239 STATE_IDLE,
240 STATE_PAGE_PROGRAM,
241 STATE_READ,
242 STATE_COLLECTING_DATA,
243 STATE_READING_DATA,
244} CMDState;
245
246typedef struct Flash {
cdccf7d7
PC		 247 SSISlave parent_obj;
248
82a24990
PC		 249 uint32_t r;
250
4be74634 251 BlockBackend *blk;
82a24990
PC		 252
253 uint8_t *storage;
254 uint32_t size;
255 int page_size;
256
257 uint8_t state;
258 uint8_t data[16];
259 uint32_t len;
260 uint32_t pos;
261 uint8_t needed_bytes;
262 uint8_t cmd_in_progress;
263 uint64_t cur_addr;
264 bool write_enable;
265
266 int64_t dirty_page;
267
82a24990
PC		 268 const FlashPartInfo *pi;
269
270} Flash;
271
a7fd6915
PC		 272typedef struct M25P80Class {
273 SSISlaveClass parent_class;
274 FlashPartInfo *pi;
275} M25P80Class;
276
277#define TYPE_M25P80 "m25p80-generic"
278#define M25P80(obj) \
279 OBJECT_CHECK(Flash, (obj), TYPE_M25P80)
280#define M25P80_CLASS(klass) \
281 OBJECT_CLASS_CHECK(M25P80Class, (klass), TYPE_M25P80)
282#define M25P80_GET_CLASS(obj) \
283 OBJECT_GET_CLASS(M25P80Class, (obj), TYPE_M25P80)
284
4be74634 285static void blk_sync_complete(void *opaque, int ret)
82a24990
PC		 286{
287 /* do nothing. Masters do not directly interact with the backing store,
288 * only the working copy so no mutexing required.
289 */
290}
291
292static void flash_sync_page(Flash *s, int page)
293{
4be74634 294 int blk_sector, nb_sectors;
fc1084aa
PC		 295 QEMUIOVector iov;
296
4be74634 297 if (!s->blk || blk_is_read_only(s->blk)) {
fc1084aa 298 return;
82a24990 299 }
fc1084aa 300
4be74634 301 blk_sector = (page * s->pi->page_size) / BDRV_SECTOR_SIZE;
fc1084aa
PC		 302 nb_sectors = DIV_ROUND_UP(s->pi->page_size, BDRV_SECTOR_SIZE);
303 qemu_iovec_init(&iov, 1);
4be74634 304 qemu_iovec_add(&iov, s->storage + blk_sector * BDRV_SECTOR_SIZE,
fc1084aa 305 nb_sectors * BDRV_SECTOR_SIZE);
4be74634
MA		 306 blk_aio_writev(s->blk, blk_sector, &iov, nb_sectors, blk_sync_complete,
307 NULL);
82a24990
PC		 308}
309
310static inline void flash_sync_area(Flash *s, int64_t off, int64_t len)
311{
312 int64_t start, end, nb_sectors;
313 QEMUIOVector iov;
314
4be74634 315 if (!s->blk || blk_is_read_only(s->blk)) {
82a24990
PC		 316 return;
317 }
318
319 assert(!(len % BDRV_SECTOR_SIZE));
320 start = off / BDRV_SECTOR_SIZE;
321 end = (off + len) / BDRV_SECTOR_SIZE;
322 nb_sectors = end - start;
323 qemu_iovec_init(&iov, 1);
324 qemu_iovec_add(&iov, s->storage + (start * BDRV_SECTOR_SIZE),
325 nb_sectors * BDRV_SECTOR_SIZE);
4be74634 326 blk_aio_writev(s->blk, start, &iov, nb_sectors, blk_sync_complete, NULL);
82a24990
PC		 327}
328
329static void flash_erase(Flash *s, int offset, FlashCMD cmd)
330{
331 uint32_t len;
332 uint8_t capa_to_assert = 0;
333
334 switch (cmd) {
335 case ERASE_4K:
336 len = 4 << 10;
337 capa_to_assert = ER_4K;
338 break;
339 case ERASE_32K:
340 len = 32 << 10;
341 capa_to_assert = ER_32K;
342 break;
343 case ERASE_SECTOR:
344 len = s->pi->sector_size;
345 break;
346 case BULK_ERASE:
347 len = s->size;
348 break;
349 default:
350 abort();
351 }
352
28097d02 353 DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len);
82a24990 354 if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
e9711b4d
PC		 355 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
356 " device\n", len);
82a24990
PC		 357 }
358
359 if (!s->write_enable) {
e9711b4d 360 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n");
82a24990
PC		 361 return;
362 }
363 memset(s->storage + offset, 0xff, len);
364 flash_sync_area(s, offset, len);
365}
366
367static inline void flash_sync_dirty(Flash *s, int64_t newpage)
368{
369 if (s->dirty_page >= 0 && s->dirty_page != newpage) {
370 flash_sync_page(s, s->dirty_page);
371 s->dirty_page = newpage;
372 }
373}
374
375static inline
376void flash_write8(Flash *s, uint64_t addr, uint8_t data)
377{
378 int64_t page = addr / s->pi->page_size;
379 uint8_t prev = s->storage[s->cur_addr];
380
381 if (!s->write_enable) {
e9711b4d 382 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
82a24990
PC		 383 }
384
385 if ((prev ^ data) & data) {
28097d02
PC		 386 DB_PRINT_L(1, "programming zero to one! addr=%" PRIx64 " %" PRIx8
387 " -> %" PRIx8 "\n", addr, prev, data);
82a24990
PC		 388 }
389
390 if (s->pi->flags & WR_1) {
391 s->storage[s->cur_addr] = data;
392 } else {
393 s->storage[s->cur_addr] &= data;
394 }
395
396 flash_sync_dirty(s, page);
397 s->dirty_page = page;
398}
399
400static void complete_collecting_data(Flash *s)
401{
402 s->cur_addr = s->data[0] << 16;
403 s->cur_addr |= s->data[1] << 8;
404 s->cur_addr |= s->data[2];
405
a56d305a
PC		 406 s->state = STATE_IDLE;
407
82a24990 408 switch (s->cmd_in_progress) {
419336a9
PC		 409 case DPP:
410 case QPP:
82a24990
PC		 411 case PP:
412 s->state = STATE_PAGE_PROGRAM;
413 break;
414 case READ:
415 case FAST_READ:
419336a9
PC		 416 case DOR:
417 case QOR:
418 case DIOR:
419 case QIOR:
82a24990
PC		 420 s->state = STATE_READ;
421 break;
422 case ERASE_4K:
423 case ERASE_32K:
424 case ERASE_SECTOR:
425 flash_erase(s, s->cur_addr, s->cmd_in_progress);
426 break;
03ec2f83
KJS		 427 case WRSR:
428 if (s->write_enable) {
429 s->write_enable = false;
430 }
431 break;
82a24990
PC		 432 default:
433 break;
434 }
435}
436
437static void decode_new_cmd(Flash *s, uint32_t value)
438{
439 s->cmd_in_progress = value;
28097d02 440 DB_PRINT_L(0, "decoded new command:%x\n", value);
82a24990
PC		 441
442 switch (value) {
443
444 case ERASE_4K:
445 case ERASE_32K:
446 case ERASE_SECTOR:
447 case READ:
419336a9
PC		 448 case DPP:
449 case QPP:
82a24990
PC		 450 case PP:
451 s->needed_bytes = 3;
452 s->pos = 0;
453 s->len = 0;
454 s->state = STATE_COLLECTING_DATA;
455 break;
456
457 case FAST_READ:
419336a9
PC		 458 case DOR:
459 case QOR:
82a24990
PC		 460 s->needed_bytes = 4;
461 s->pos = 0;
462 s->len = 0;
463 s->state = STATE_COLLECTING_DATA;
464 break;
465
419336a9
PC		 466 case DIOR:
467 switch ((s->pi->jedec >> 16) & 0xFF) {
468 case JEDEC_WINBOND:
469 case JEDEC_SPANSION:
470 s->needed_bytes = 4;
471 break;
472 case JEDEC_NUMONYX:
473 default:
474 s->needed_bytes = 5;
475 }
476 s->pos = 0;
477 s->len = 0;
478 s->state = STATE_COLLECTING_DATA;
479 break;
480
481 case QIOR:
482 switch ((s->pi->jedec >> 16) & 0xFF) {
483 case JEDEC_WINBOND:
484 case JEDEC_SPANSION:
485 s->needed_bytes = 6;
486 break;
487 case JEDEC_NUMONYX:
488 default:
489 s->needed_bytes = 8;
490 }
491 s->pos = 0;
492 s->len = 0;
493 s->state = STATE_COLLECTING_DATA;
494 break;
495
03ec2f83
KJS		 496 case WRSR:
497 if (s->write_enable) {
498 s->needed_bytes = 1;
499 s->pos = 0;
500 s->len = 0;
501 s->state = STATE_COLLECTING_DATA;
502 }
503 break;
504
82a24990
PC		 505 case WRDI:
506 s->write_enable = false;
507 break;
508 case WREN:
509 s->write_enable = true;
510 break;
511
512 case RDSR:
513 s->data[0] = (!!s->write_enable) << 1;
514 s->pos = 0;
515 s->len = 1;
516 s->state = STATE_READING_DATA;
517 break;
518
519 case JEDEC_READ:
28097d02 520 DB_PRINT_L(0, "populated jedec code\n");
82a24990
PC		 521 s->data[0] = (s->pi->jedec >> 16) & 0xff;
522 s->data[1] = (s->pi->jedec >> 8) & 0xff;
523 s->data[2] = s->pi->jedec & 0xff;
524 if (s->pi->ext_jedec) {
525 s->data[3] = (s->pi->ext_jedec >> 8) & 0xff;
526 s->data[4] = s->pi->ext_jedec & 0xff;
527 s->len = 5;
528 } else {
529 s->len = 3;
530 }
531 s->pos = 0;
532 s->state = STATE_READING_DATA;
533 break;
534
535 case BULK_ERASE:
536 if (s->write_enable) {
28097d02 537 DB_PRINT_L(0, "chip erase\n");
82a24990
PC		 538 flash_erase(s, 0, BULK_ERASE);
539 } else {
e9711b4d
PC		 540 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
541 "protect!\n");
82a24990
PC		 542 }
543 break;
544 case NOP:
545 break;
546 default:
e9711b4d 547 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
82a24990
PC		 548 break;
549 }
550}
551
552static int m25p80_cs(SSISlave *ss, bool select)
553{
cdccf7d7 554 Flash *s = M25P80(ss);
82a24990
PC		 555
556 if (select) {
557 s->len = 0;
558 s->pos = 0;
559 s->state = STATE_IDLE;
560 flash_sync_dirty(s, -1);
561 }
562
28097d02 563 DB_PRINT_L(0, "%sselect\n", select ? "de" : "");
82a24990
PC		 564
565 return 0;
566}
567
568static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
569{
cdccf7d7 570 Flash *s = M25P80(ss);
82a24990
PC		 571 uint32_t r = 0;
572
573 switch (s->state) {
574
575 case STATE_PAGE_PROGRAM:
28097d02
PC		 576 DB_PRINT_L(1, "page program cur_addr=%#" PRIx64 " data=%" PRIx8 "\n",
577 s->cur_addr, (uint8_t)tx);
82a24990
PC		 578 flash_write8(s, s->cur_addr, (uint8_t)tx);
579 s->cur_addr++;
580 break;
581
582 case STATE_READ:
583 r = s->storage[s->cur_addr];
28097d02
PC		 584 DB_PRINT_L(1, "READ 0x%" PRIx64 "=%" PRIx8 "\n", s->cur_addr,
585 (uint8_t)r);
82a24990
PC		 586 s->cur_addr = (s->cur_addr + 1) % s->size;
587 break;
588
589 case STATE_COLLECTING_DATA:
590 s->data[s->len] = (uint8_t)tx;
591 s->len++;
592
593 if (s->len == s->needed_bytes) {
594 complete_collecting_data(s);
595 }
596 break;
597
598 case STATE_READING_DATA:
599 r = s->data[s->pos];
600 s->pos++;
601 if (s->pos == s->len) {
602 s->pos = 0;
603 s->state = STATE_IDLE;
604 }
605 break;
606
607 default:
608 case STATE_IDLE:
609 decode_new_cmd(s, (uint8_t)tx);
610 break;
611 }
612
613 return r;
614}
615
616static int m25p80_init(SSISlave *ss)
617{
618 DriveInfo *dinfo;
cdccf7d7 619 Flash *s = M25P80(ss);
a7fd6915 620 M25P80Class *mc = M25P80_GET_CLASS(s);
82a24990 621
a7fd6915 622 s->pi = mc->pi;
82a24990
PC		 623
624 s->size = s->pi->sector_size * s->pi->n_sectors;
625 s->dirty_page = -1;
82a24990 626
af9e40aa 627 /* FIXME use a qdev drive property instead of drive_get_next() */
82a24990
PC		 628 dinfo = drive_get_next(IF_MTD);
629
fa1d36df 630 if (dinfo) {
28097d02 631 DB_PRINT_L(0, "Binding to IF_MTD drive\n");
4be74634 632 s->blk = blk_by_legacy_dinfo(dinfo);
d07063e4 633 blk_attach_dev_nofail(s->blk, s);
4f8a066b 634
c485cf9c
SH		 635 s->storage = blk_blockalign(s->blk, s->size);
636
82a24990 637 /* FIXME: Move to late init */
4be74634
MA		 638 if (blk_read(s->blk, 0, s->storage,
639 DIV_ROUND_UP(s->size, BDRV_SECTOR_SIZE))) {
82a24990
PC		 640 fprintf(stderr, "Failed to initialize SPI flash!\n");
641 return 1;
642 }
643 } else {
095b9c48 644 DB_PRINT_L(0, "No BDRV - binding to RAM\n");
c485cf9c 645 s->storage = blk_blockalign(NULL, s->size);
82a24990
PC		 646 memset(s->storage, 0xFF, s->size);
647 }
648
649 return 0;
650}
651
652static void m25p80_pre_save(void *opaque)
653{
654 flash_sync_dirty((Flash *)opaque, -1);
655}
656
657static const VMStateDescription vmstate_m25p80 = {
658 .name = "xilinx_spi",
659 .version_id = 1,
660 .minimum_version_id = 1,
82a24990
PC		 661 .pre_save = m25p80_pre_save,
662 .fields = (VMStateField[]) {
663 VMSTATE_UINT8(state, Flash),
664 VMSTATE_UINT8_ARRAY(data, Flash, 16),
665 VMSTATE_UINT32(len, Flash),
666 VMSTATE_UINT32(pos, Flash),
667 VMSTATE_UINT8(needed_bytes, Flash),
668 VMSTATE_UINT8(cmd_in_progress, Flash),
669 VMSTATE_UINT64(cur_addr, Flash),
670 VMSTATE_BOOL(write_enable, Flash),
671 VMSTATE_END_OF_LIST()
672 }
673};
674
82a24990
PC		 675static void m25p80_class_init(ObjectClass *klass, void *data)
676{
677 DeviceClass *dc = DEVICE_CLASS(klass);
678 SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
a7fd6915 679 M25P80Class *mc = M25P80_CLASS(klass);
82a24990
PC		 680
681 k->init = m25p80_init;
682 k->transfer = m25p80_transfer8;
683 k->set_cs = m25p80_cs;
684 k->cs_polarity = SSI_CS_LOW;
82a24990 685 dc->vmsd = &vmstate_m25p80;
a7fd6915 686 mc->pi = data;
82a24990
PC		 687}
688
689static const TypeInfo m25p80_info = {
a7fd6915 690 .name = TYPE_M25P80,
82a24990
PC		 691 .parent = TYPE_SSI_SLAVE,
692 .instance_size = sizeof(Flash),
a7fd6915
PC		 693 .class_size = sizeof(M25P80Class),
694 .abstract = true,
82a24990
PC		 695};
696
697static void m25p80_register_types(void)
698{
a7fd6915
PC		 699 int i;
700
82a24990 701 type_register_static(&m25p80_info);
a7fd6915
PC		 702 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) {
703 TypeInfo ti = {
704 .name = known_devices[i].part_name,
705 .parent = TYPE_M25P80,
706 .class_init = m25p80_class_init,
707 .class_data = (void *)&known_devices[i],
708 };
709 type_register(&ti);
710 }
82a24990
PC		 711}
712
713type_init(m25p80_register_types)
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