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82a24990 PC |
1 | /* |
2 | * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command | |
3 | * set. Known devices table current as of Jun/2012 and taken from linux. | |
4 | * See drivers/mtd/devices/m25p80.c. | |
5 | * | |
6 | * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com> | |
7 | * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> | |
8 | * Copyright (C) 2012 PetaLogix | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 or | |
13 | * (at your option) a later version of the License. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License along | |
21 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
22 | */ | |
23 | ||
80c71a24 | 24 | #include "qemu/osdep.h" |
e8400cf3 | 25 | #include "qemu/units.h" |
83c9f4ca | 26 | #include "hw/hw.h" |
fa1d36df | 27 | #include "sysemu/block-backend.h" |
8fd06719 | 28 | #include "hw/ssi/ssi.h" |
cb475951 | 29 | #include "qemu/bitops.h" |
03dd024f | 30 | #include "qemu/log.h" |
24cb2e0d | 31 | #include "qemu/error-report.h" |
7673bb4c | 32 | #include "qapi/error.h" |
82a24990 | 33 | |
28097d02 PC |
34 | #ifndef M25P80_ERR_DEBUG |
35 | #define M25P80_ERR_DEBUG 0 | |
82a24990 PC |
36 | #endif |
37 | ||
28097d02 PC |
38 | #define DB_PRINT_L(level, ...) do { \ |
39 | if (M25P80_ERR_DEBUG > (level)) { \ | |
40 | fprintf(stderr, ": %s: ", __func__); \ | |
41 | fprintf(stderr, ## __VA_ARGS__); \ | |
42 | } \ | |
2562755e | 43 | } while (0) |
28097d02 | 44 | |
82a24990 PC |
45 | /* Fields for FlashPartInfo->flags */ |
46 | ||
47 | /* erase capabilities */ | |
48 | #define ER_4K 1 | |
49 | #define ER_32K 2 | |
50 | /* set to allow the page program command to write 0s back to 1. Useful for | |
51 | * modelling EEPROM with SPI flash command set | |
52 | */ | |
1435bcd6 | 53 | #define EEPROM 0x100 |
82a24990 | 54 | |
d8a29a7a MK |
55 | /* 16 MiB max in 3 byte address mode */ |
56 | #define MAX_3BYTES_SIZE 0x1000000 | |
57 | ||
e3ba6cd6 MK |
58 | #define SPI_NOR_MAX_ID_LEN 6 |
59 | ||
82a24990 PC |
60 | typedef struct FlashPartInfo { |
61 | const char *part_name; | |
e3ba6cd6 MK |
62 | /* |
63 | * This array stores the ID bytes. | |
64 | * The first three bytes are the JEDIC ID. | |
65 | * JEDEC ID zero means "no ID" (mostly older chips). | |
66 | */ | |
67 | uint8_t id[SPI_NOR_MAX_ID_LEN]; | |
68 | uint8_t id_len; | |
82a24990 PC |
69 | /* there is confusion between manufacturers as to what a sector is. In this |
70 | * device model, a "sector" is the size that is erased by the ERASE_SECTOR | |
71 | * command (opcode 0xd8). | |
72 | */ | |
73 | uint32_t sector_size; | |
74 | uint32_t n_sectors; | |
75 | uint32_t page_size; | |
76e87269 | 76 | uint16_t flags; |
f509dfee MK |
77 | /* |
78 | * Big sized spi nor are often stacked devices, thus sometime | |
79 | * replace chip erase with die erase. | |
80 | * This field inform how many die is in the chip. | |
81 | */ | |
82 | uint8_t die_cnt; | |
82a24990 PC |
83 | } FlashPartInfo; |
84 | ||
85 | /* adapted from linux */ | |
e3ba6cd6 MK |
86 | /* Used when the "_ext_id" is two bytes at most */ |
87 | #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ | |
88 | .part_name = _part_name,\ | |
89 | .id = {\ | |
90 | ((_jedec_id) >> 16) & 0xff,\ | |
91 | ((_jedec_id) >> 8) & 0xff,\ | |
92 | (_jedec_id) & 0xff,\ | |
93 | ((_ext_id) >> 8) & 0xff,\ | |
94 | (_ext_id) & 0xff,\ | |
95 | },\ | |
96 | .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ | |
97 | .sector_size = (_sector_size),\ | |
98 | .n_sectors = (_n_sectors),\ | |
99 | .page_size = 256,\ | |
f509dfee MK |
100 | .flags = (_flags),\ |
101 | .die_cnt = 0 | |
e3ba6cd6 MK |
102 | |
103 | #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\ | |
104 | .part_name = _part_name,\ | |
105 | .id = {\ | |
106 | ((_jedec_id) >> 16) & 0xff,\ | |
107 | ((_jedec_id) >> 8) & 0xff,\ | |
108 | (_jedec_id) & 0xff,\ | |
109 | ((_ext_id) >> 16) & 0xff,\ | |
110 | ((_ext_id) >> 8) & 0xff,\ | |
111 | (_ext_id) & 0xff,\ | |
112 | },\ | |
113 | .id_len = 6,\ | |
82a24990 PC |
114 | .sector_size = (_sector_size),\ |
115 | .n_sectors = (_n_sectors),\ | |
116 | .page_size = 256,\ | |
117 | .flags = (_flags),\ | |
f509dfee MK |
118 | .die_cnt = 0 |
119 | ||
120 | #define INFO_STACKED(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors,\ | |
121 | _flags, _die_cnt)\ | |
122 | .part_name = _part_name,\ | |
123 | .id = {\ | |
124 | ((_jedec_id) >> 16) & 0xff,\ | |
125 | ((_jedec_id) >> 8) & 0xff,\ | |
126 | (_jedec_id) & 0xff,\ | |
127 | ((_ext_id) >> 8) & 0xff,\ | |
128 | (_ext_id) & 0xff,\ | |
129 | },\ | |
130 | .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\ | |
131 | .sector_size = (_sector_size),\ | |
132 | .n_sectors = (_n_sectors),\ | |
133 | .page_size = 256,\ | |
134 | .flags = (_flags),\ | |
135 | .die_cnt = _die_cnt | |
82a24990 | 136 | |
419336a9 PC |
137 | #define JEDEC_NUMONYX 0x20 |
138 | #define JEDEC_WINBOND 0xEF | |
139 | #define JEDEC_SPANSION 0x01 | |
140 | ||
cb475951 MK |
141 | /* Numonyx (Micron) Configuration register macros */ |
142 | #define VCFG_DUMMY 0x1 | |
143 | #define VCFG_WRAP_SEQUENTIAL 0x2 | |
144 | #define NVCFG_XIP_MODE_DISABLED (7 << 9) | |
145 | #define NVCFG_XIP_MODE_MASK (7 << 9) | |
146 | #define VCFG_XIP_MODE_ENABLED (1 << 3) | |
147 | #define CFG_DUMMY_CLK_LEN 4 | |
148 | #define NVCFG_DUMMY_CLK_POS 12 | |
149 | #define VCFG_DUMMY_CLK_POS 4 | |
5c765e7a | 150 | #define EVCFG_OUT_DRIVER_STRENGTH_DEF 7 |
cb475951 MK |
151 | #define EVCFG_VPP_ACCELERATOR (1 << 3) |
152 | #define EVCFG_RESET_HOLD_ENABLED (1 << 4) | |
153 | #define NVCFG_DUAL_IO_MASK (1 << 2) | |
154 | #define EVCFG_DUAL_IO_ENABLED (1 << 6) | |
155 | #define NVCFG_QUAD_IO_MASK (1 << 3) | |
156 | #define EVCFG_QUAD_IO_ENABLED (1 << 7) | |
157 | #define NVCFG_4BYTE_ADDR_MASK (1 << 0) | |
158 | #define NVCFG_LOWER_SEGMENT_MASK (1 << 1) | |
cb475951 | 159 | |
9fbaa364 MK |
160 | /* Numonyx (Micron) Flag Status Register macros */ |
161 | #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1 | |
162 | #define FSR_FLASH_READY (1 << 7) | |
163 | ||
d9cc8701 MK |
164 | /* Spansion configuration registers macros. */ |
165 | #define SPANSION_QUAD_CFG_POS 0 | |
166 | #define SPANSION_QUAD_CFG_LEN 1 | |
167 | #define SPANSION_DUMMY_CLK_POS 0 | |
168 | #define SPANSION_DUMMY_CLK_LEN 4 | |
169 | #define SPANSION_ADDR_LEN_POS 7 | |
170 | #define SPANSION_ADDR_LEN_LEN 1 | |
171 | ||
cf6f1efe MK |
172 | /* |
173 | * Spansion read mode command length in bytes, | |
174 | * the mode is currently not supported. | |
175 | */ | |
176 | ||
177 | #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1 | |
fe847705 | 178 | #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1 |
cf6f1efe | 179 | |
82a24990 PC |
180 | static const FlashPartInfo known_devices[] = { |
181 | /* Atmel -- some are (confusingly) marketed as "DataFlash" */ | |
182 | { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) }, | |
183 | { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) }, | |
184 | ||
185 | { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) }, | |
186 | { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) }, | |
187 | { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) }, | |
188 | ||
189 | { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) }, | |
190 | { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) }, | |
191 | { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) }, | |
192 | { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) }, | |
193 | ||
3e758c1d EM |
194 | { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) }, |
195 | ||
1435bcd6 MK |
196 | /* Atmel EEPROMS - it is assumed, that don't care bit in command |
197 | * is set to 0. Block protection is not supported. | |
198 | */ | |
199 | { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) }, | |
200 | { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) }, | |
201 | ||
82a24990 PC |
202 | /* EON -- en25xxx */ |
203 | { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) }, | |
204 | { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) }, | |
205 | { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) }, | |
206 | { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) }, | |
3e758c1d EM |
207 | { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) }, |
208 | ||
209 | /* GigaDevice */ | |
210 | { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) }, | |
211 | { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) }, | |
82a24990 PC |
212 | |
213 | /* Intel/Numonyx -- xxxs33b */ | |
214 | { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) }, | |
215 | { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) }, | |
216 | { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) }, | |
3e758c1d | 217 | { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) }, |
82a24990 PC |
218 | |
219 | /* Macronix */ | |
3e758c1d | 220 | { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) }, |
82a24990 PC |
221 | { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) }, |
222 | { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) }, | |
223 | { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) }, | |
224 | { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) }, | |
225 | { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) }, | |
226 | { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) }, | |
227 | { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) }, | |
228 | { INFO("mx25l25635e", 0xc22019, 0, 64 << 10, 512, 0) }, | |
229 | { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) }, | |
dadb2f90 MK |
230 | { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) }, |
231 | { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) }, | |
e03192fd | 232 | { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K) }, |
82a24990 | 233 | |
3e758c1d | 234 | /* Micron */ |
f5aac8e0 EM |
235 | { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) }, |
236 | { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) }, | |
237 | { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) }, | |
238 | { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) }, | |
239 | { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) }, | |
240 | { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) }, | |
241 | { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) }, | |
242 | { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, | |
53dc9c79 FI |
243 | { INFO("n25q512a11", 0x20bb20, 0, 64 << 10, 1024, ER_4K) }, |
244 | { INFO("n25q512a13", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, | |
dadb2f90 MK |
245 | { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) }, |
246 | { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) }, | |
247 | { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, | |
eca27213 MK |
248 | { INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, |
249 | { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, | |
250 | { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, | |
251 | { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, | |
3e758c1d | 252 | |
82a24990 PC |
253 | /* Spansion -- single (large) sector size only, at least |
254 | * for the chips listed here (without boot sectors). | |
255 | */ | |
82a24990 | 256 | { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) }, |
3e758c1d | 257 | { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) }, |
82a24990 PC |
258 | { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) }, |
259 | { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) }, | |
dadb2f90 MK |
260 | { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) }, |
261 | { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) }, | |
82a24990 PC |
262 | { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) }, |
263 | { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) }, | |
264 | { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) }, | |
265 | { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) }, | |
3e758c1d EM |
266 | { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) }, |
267 | { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) }, | |
268 | { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) }, | |
269 | { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) }, | |
270 | { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) }, | |
82a24990 PC |
271 | { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) }, |
272 | { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) }, | |
273 | ||
dadb2f90 MK |
274 | /* Spansion -- boot sectors support */ |
275 | { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) }, | |
276 | { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) }, | |
277 | ||
82a24990 PC |
278 | /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */ |
279 | { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) }, | |
280 | { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) }, | |
281 | { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) }, | |
282 | { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) }, | |
283 | { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) }, | |
284 | { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) }, | |
285 | { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) }, | |
286 | { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) }, | |
d857c4c0 | 287 | { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) }, |
82a24990 PC |
288 | |
289 | /* ST Microelectronics -- newer production may have feature updates */ | |
290 | { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) }, | |
291 | { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) }, | |
292 | { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) }, | |
293 | { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) }, | |
294 | { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) }, | |
295 | { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) }, | |
296 | { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) }, | |
297 | { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) }, | |
298 | { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) }, | |
3e758c1d | 299 | { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) }, |
82a24990 PC |
300 | |
301 | { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) }, | |
302 | { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) }, | |
303 | { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) }, | |
304 | ||
3e758c1d | 305 | { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) }, |
82a24990 PC |
306 | { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) }, |
307 | { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) }, | |
308 | ||
309 | { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) }, | |
310 | { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) }, | |
311 | { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) }, | |
312 | { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) }, | |
313 | ||
314 | /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */ | |
315 | { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) }, | |
316 | { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) }, | |
317 | { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) }, | |
318 | { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) }, | |
319 | { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) }, | |
320 | { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) }, | |
321 | { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) }, | |
3e758c1d | 322 | { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) }, |
82a24990 PC |
323 | { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) }, |
324 | { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) }, | |
3e758c1d EM |
325 | { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) }, |
326 | { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) }, | |
327 | { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) }, | |
82a24990 PC |
328 | }; |
329 | ||
330 | typedef enum { | |
331 | NOP = 0, | |
03ec2f83 | 332 | WRSR = 0x1, |
82a24990 PC |
333 | WRDI = 0x4, |
334 | RDSR = 0x5, | |
335 | WREN = 0x6, | |
0f589782 FI |
336 | BRRD = 0x16, |
337 | BRWR = 0x17, | |
419336a9 | 338 | JEDEC_READ = 0x9f, |
0f589782 | 339 | BULK_ERASE_60 = 0x60, |
419336a9 | 340 | BULK_ERASE = 0xc7, |
9fbaa364 | 341 | READ_FSR = 0x70, |
7a69c100 | 342 | RDCR = 0x15, |
419336a9 | 343 | |
63e47f6f MK |
344 | READ = 0x03, |
345 | READ4 = 0x13, | |
346 | FAST_READ = 0x0b, | |
347 | FAST_READ4 = 0x0c, | |
419336a9 | 348 | DOR = 0x3b, |
63e47f6f | 349 | DOR4 = 0x3c, |
419336a9 | 350 | QOR = 0x6b, |
63e47f6f | 351 | QOR4 = 0x6c, |
419336a9 | 352 | DIOR = 0xbb, |
63e47f6f | 353 | DIOR4 = 0xbc, |
419336a9 | 354 | QIOR = 0xeb, |
63e47f6f | 355 | QIOR4 = 0xec, |
419336a9 | 356 | |
63e47f6f MK |
357 | PP = 0x02, |
358 | PP4 = 0x12, | |
30467afe | 359 | PP4_4 = 0x3e, |
419336a9 PC |
360 | DPP = 0xa2, |
361 | QPP = 0x32, | |
597c15f0 | 362 | QPP_4 = 0x34, |
a87fc364 FI |
363 | RDID_90 = 0x90, |
364 | RDID_AB = 0xab, | |
419336a9 | 365 | |
82a24990 | 366 | ERASE_4K = 0x20, |
63e47f6f | 367 | ERASE4_4K = 0x21, |
82a24990 | 368 | ERASE_32K = 0x52, |
30467afe | 369 | ERASE4_32K = 0x5c, |
82a24990 | 370 | ERASE_SECTOR = 0xd8, |
63e47f6f | 371 | ERASE4_SECTOR = 0xdc, |
187c2636 | 372 | |
c0f3f675 MK |
373 | EN_4BYTE_ADDR = 0xB7, |
374 | EX_4BYTE_ADDR = 0xE9, | |
375 | ||
d8a29a7a MK |
376 | EXTEND_ADDR_READ = 0xC8, |
377 | EXTEND_ADDR_WRITE = 0xC5, | |
378 | ||
187c2636 MK |
379 | RESET_ENABLE = 0x66, |
380 | RESET_MEMORY = 0x99, | |
cb475951 | 381 | |
7a69c100 MK |
382 | /* |
383 | * Micron: 0x35 - enable QPI | |
384 | * Spansion: 0x35 - read control register | |
385 | */ | |
386 | RDCR_EQIO = 0x35, | |
387 | RSTQIO = 0xf5, | |
388 | ||
cb475951 MK |
389 | RNVCR = 0xB5, |
390 | WNVCR = 0xB1, | |
391 | ||
392 | RVCR = 0x85, | |
393 | WVCR = 0x81, | |
394 | ||
395 | REVCR = 0x65, | |
396 | WEVCR = 0x61, | |
f509dfee MK |
397 | |
398 | DIE_ERASE = 0xC4, | |
82a24990 PC |
399 | } FlashCMD; |
400 | ||
401 | typedef enum { | |
402 | STATE_IDLE, | |
403 | STATE_PAGE_PROGRAM, | |
404 | STATE_READ, | |
405 | STATE_COLLECTING_DATA, | |
9964674e | 406 | STATE_COLLECTING_VAR_LEN_DATA, |
82a24990 PC |
407 | STATE_READING_DATA, |
408 | } CMDState; | |
409 | ||
c7cd0a6c MK |
410 | typedef enum { |
411 | MAN_SPANSION, | |
412 | MAN_MACRONIX, | |
413 | MAN_NUMONYX, | |
414 | MAN_WINBOND, | |
a87fc364 | 415 | MAN_SST, |
c7cd0a6c MK |
416 | MAN_GENERIC, |
417 | } Manufacturer; | |
418 | ||
24cb2e0d JCD |
419 | #define M25P80_INTERNAL_DATA_BUFFER_SZ 16 |
420 | ||
82a24990 | 421 | typedef struct Flash { |
cdccf7d7 PC |
422 | SSISlave parent_obj; |
423 | ||
4be74634 | 424 | BlockBackend *blk; |
82a24990 PC |
425 | |
426 | uint8_t *storage; | |
427 | uint32_t size; | |
428 | int page_size; | |
429 | ||
430 | uint8_t state; | |
24cb2e0d | 431 | uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ]; |
82a24990 PC |
432 | uint32_t len; |
433 | uint32_t pos; | |
0add925f | 434 | bool data_read_loop; |
82a24990 PC |
435 | uint8_t needed_bytes; |
436 | uint8_t cmd_in_progress; | |
b7f480c3 | 437 | uint32_t cur_addr; |
cb475951 | 438 | uint32_t nonvolatile_cfg; |
d9cc8701 | 439 | /* Configuration register for Macronix */ |
cb475951 MK |
440 | uint32_t volatile_cfg; |
441 | uint32_t enh_volatile_cfg; | |
d9cc8701 MK |
442 | /* Spansion cfg registers. */ |
443 | uint8_t spansion_cr1nv; | |
444 | uint8_t spansion_cr2nv; | |
445 | uint8_t spansion_cr3nv; | |
446 | uint8_t spansion_cr4nv; | |
447 | uint8_t spansion_cr1v; | |
448 | uint8_t spansion_cr2v; | |
449 | uint8_t spansion_cr3v; | |
450 | uint8_t spansion_cr4v; | |
82a24990 | 451 | bool write_enable; |
c0f3f675 | 452 | bool four_bytes_address_mode; |
187c2636 | 453 | bool reset_enable; |
7a69c100 | 454 | bool quad_enable; |
d8a29a7a | 455 | uint8_t ear; |
82a24990 PC |
456 | |
457 | int64_t dirty_page; | |
458 | ||
82a24990 PC |
459 | const FlashPartInfo *pi; |
460 | ||
461 | } Flash; | |
462 | ||
a7fd6915 PC |
463 | typedef struct M25P80Class { |
464 | SSISlaveClass parent_class; | |
465 | FlashPartInfo *pi; | |
466 | } M25P80Class; | |
467 | ||
468 | #define TYPE_M25P80 "m25p80-generic" | |
469 | #define M25P80(obj) \ | |
470 | OBJECT_CHECK(Flash, (obj), TYPE_M25P80) | |
471 | #define M25P80_CLASS(klass) \ | |
472 | OBJECT_CLASS_CHECK(M25P80Class, (klass), TYPE_M25P80) | |
473 | #define M25P80_GET_CLASS(obj) \ | |
474 | OBJECT_GET_CLASS(M25P80Class, (obj), TYPE_M25P80) | |
475 | ||
c7cd0a6c MK |
476 | static inline Manufacturer get_man(Flash *s) |
477 | { | |
e3ba6cd6 | 478 | switch (s->pi->id[0]) { |
c7cd0a6c MK |
479 | case 0x20: |
480 | return MAN_NUMONYX; | |
481 | case 0xEF: | |
482 | return MAN_WINBOND; | |
483 | case 0x01: | |
484 | return MAN_SPANSION; | |
485 | case 0xC2: | |
486 | return MAN_MACRONIX; | |
a87fc364 FI |
487 | case 0xBF: |
488 | return MAN_SST; | |
c7cd0a6c MK |
489 | default: |
490 | return MAN_GENERIC; | |
491 | } | |
492 | } | |
493 | ||
4be74634 | 494 | static void blk_sync_complete(void *opaque, int ret) |
82a24990 | 495 | { |
cace7b80 PB |
496 | QEMUIOVector *iov = opaque; |
497 | ||
498 | qemu_iovec_destroy(iov); | |
499 | g_free(iov); | |
500 | ||
82a24990 PC |
501 | /* do nothing. Masters do not directly interact with the backing store, |
502 | * only the working copy so no mutexing required. | |
503 | */ | |
504 | } | |
505 | ||
506 | static void flash_sync_page(Flash *s, int page) | |
507 | { | |
eef9f19e | 508 | QEMUIOVector *iov; |
fc1084aa | 509 | |
4be74634 | 510 | if (!s->blk || blk_is_read_only(s->blk)) { |
fc1084aa | 511 | return; |
82a24990 | 512 | } |
fc1084aa | 513 | |
eef9f19e | 514 | iov = g_new(QEMUIOVector, 1); |
cace7b80 PB |
515 | qemu_iovec_init(iov, 1); |
516 | qemu_iovec_add(iov, s->storage + page * s->pi->page_size, | |
243e6f69 | 517 | s->pi->page_size); |
cace7b80 PB |
518 | blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0, |
519 | blk_sync_complete, iov); | |
82a24990 PC |
520 | } |
521 | ||
522 | static inline void flash_sync_area(Flash *s, int64_t off, int64_t len) | |
523 | { | |
eef9f19e | 524 | QEMUIOVector *iov; |
82a24990 | 525 | |
4be74634 | 526 | if (!s->blk || blk_is_read_only(s->blk)) { |
82a24990 PC |
527 | return; |
528 | } | |
529 | ||
530 | assert(!(len % BDRV_SECTOR_SIZE)); | |
eef9f19e | 531 | iov = g_new(QEMUIOVector, 1); |
cace7b80 PB |
532 | qemu_iovec_init(iov, 1); |
533 | qemu_iovec_add(iov, s->storage + off, len); | |
534 | blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov); | |
82a24990 PC |
535 | } |
536 | ||
537 | static void flash_erase(Flash *s, int offset, FlashCMD cmd) | |
538 | { | |
539 | uint32_t len; | |
540 | uint8_t capa_to_assert = 0; | |
541 | ||
542 | switch (cmd) { | |
543 | case ERASE_4K: | |
63e47f6f | 544 | case ERASE4_4K: |
e8400cf3 | 545 | len = 4 * KiB; |
82a24990 PC |
546 | capa_to_assert = ER_4K; |
547 | break; | |
548 | case ERASE_32K: | |
30467afe | 549 | case ERASE4_32K: |
e8400cf3 | 550 | len = 32 * KiB; |
82a24990 PC |
551 | capa_to_assert = ER_32K; |
552 | break; | |
553 | case ERASE_SECTOR: | |
63e47f6f | 554 | case ERASE4_SECTOR: |
82a24990 PC |
555 | len = s->pi->sector_size; |
556 | break; | |
557 | case BULK_ERASE: | |
558 | len = s->size; | |
559 | break; | |
f509dfee MK |
560 | case DIE_ERASE: |
561 | if (s->pi->die_cnt) { | |
562 | len = s->size / s->pi->die_cnt; | |
563 | offset = offset & (~(len - 1)); | |
564 | } else { | |
565 | qemu_log_mask(LOG_GUEST_ERROR, "M25P80: die erase is not supported" | |
566 | " by device\n"); | |
567 | return; | |
568 | } | |
569 | break; | |
82a24990 PC |
570 | default: |
571 | abort(); | |
572 | } | |
573 | ||
28097d02 | 574 | DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len); |
82a24990 | 575 | if ((s->pi->flags & capa_to_assert) != capa_to_assert) { |
e9711b4d PC |
576 | qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by" |
577 | " device\n", len); | |
82a24990 PC |
578 | } |
579 | ||
580 | if (!s->write_enable) { | |
e9711b4d | 581 | qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n"); |
82a24990 PC |
582 | return; |
583 | } | |
584 | memset(s->storage + offset, 0xff, len); | |
585 | flash_sync_area(s, offset, len); | |
586 | } | |
587 | ||
588 | static inline void flash_sync_dirty(Flash *s, int64_t newpage) | |
589 | { | |
590 | if (s->dirty_page >= 0 && s->dirty_page != newpage) { | |
591 | flash_sync_page(s, s->dirty_page); | |
592 | s->dirty_page = newpage; | |
593 | } | |
594 | } | |
595 | ||
596 | static inline | |
b7f480c3 | 597 | void flash_write8(Flash *s, uint32_t addr, uint8_t data) |
82a24990 | 598 | { |
b7f480c3 | 599 | uint32_t page = addr / s->pi->page_size; |
82a24990 PC |
600 | uint8_t prev = s->storage[s->cur_addr]; |
601 | ||
602 | if (!s->write_enable) { | |
e9711b4d | 603 | qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n"); |
82a24990 PC |
604 | } |
605 | ||
606 | if ((prev ^ data) & data) { | |
b7f480c3 | 607 | DB_PRINT_L(1, "programming zero to one! addr=%" PRIx32 " %" PRIx8 |
28097d02 | 608 | " -> %" PRIx8 "\n", addr, prev, data); |
82a24990 PC |
609 | } |
610 | ||
1435bcd6 | 611 | if (s->pi->flags & EEPROM) { |
82a24990 PC |
612 | s->storage[s->cur_addr] = data; |
613 | } else { | |
614 | s->storage[s->cur_addr] &= data; | |
615 | } | |
616 | ||
617 | flash_sync_dirty(s, page); | |
618 | s->dirty_page = page; | |
619 | } | |
620 | ||
c0f3f675 MK |
621 | static inline int get_addr_length(Flash *s) |
622 | { | |
1435bcd6 MK |
623 | /* check if eeprom is in use */ |
624 | if (s->pi->flags == EEPROM) { | |
625 | return 2; | |
626 | } | |
627 | ||
63e47f6f MK |
628 | switch (s->cmd_in_progress) { |
629 | case PP4: | |
30467afe | 630 | case PP4_4: |
597c15f0 | 631 | case QPP_4: |
63e47f6f MK |
632 | case READ4: |
633 | case QIOR4: | |
634 | case ERASE4_4K: | |
30467afe | 635 | case ERASE4_32K: |
63e47f6f MK |
636 | case ERASE4_SECTOR: |
637 | case FAST_READ4: | |
638 | case DOR4: | |
639 | case QOR4: | |
640 | case DIOR4: | |
641 | return 4; | |
642 | default: | |
643 | return s->four_bytes_address_mode ? 4 : 3; | |
644 | } | |
c0f3f675 MK |
645 | } |
646 | ||
82a24990 PC |
647 | static void complete_collecting_data(Flash *s) |
648 | { | |
b68cb060 | 649 | int i, n; |
c0f3f675 | 650 | |
b68cb060 PB |
651 | n = get_addr_length(s); |
652 | s->cur_addr = (n == 3 ? s->ear : 0); | |
653 | for (i = 0; i < n; ++i) { | |
c0f3f675 MK |
654 | s->cur_addr <<= 8; |
655 | s->cur_addr |= s->data[i]; | |
656 | } | |
657 | ||
b68cb060 | 658 | s->cur_addr &= s->size - 1; |
82a24990 | 659 | |
a56d305a PC |
660 | s->state = STATE_IDLE; |
661 | ||
82a24990 | 662 | switch (s->cmd_in_progress) { |
419336a9 PC |
663 | case DPP: |
664 | case QPP: | |
597c15f0 | 665 | case QPP_4: |
82a24990 | 666 | case PP: |
63e47f6f | 667 | case PP4: |
30467afe | 668 | case PP4_4: |
82a24990 PC |
669 | s->state = STATE_PAGE_PROGRAM; |
670 | break; | |
671 | case READ: | |
63e47f6f | 672 | case READ4: |
82a24990 | 673 | case FAST_READ: |
63e47f6f | 674 | case FAST_READ4: |
419336a9 | 675 | case DOR: |
63e47f6f | 676 | case DOR4: |
419336a9 | 677 | case QOR: |
63e47f6f | 678 | case QOR4: |
419336a9 | 679 | case DIOR: |
63e47f6f | 680 | case DIOR4: |
419336a9 | 681 | case QIOR: |
63e47f6f | 682 | case QIOR4: |
82a24990 PC |
683 | s->state = STATE_READ; |
684 | break; | |
685 | case ERASE_4K: | |
63e47f6f | 686 | case ERASE4_4K: |
82a24990 | 687 | case ERASE_32K: |
30467afe | 688 | case ERASE4_32K: |
82a24990 | 689 | case ERASE_SECTOR: |
63e47f6f | 690 | case ERASE4_SECTOR: |
f509dfee | 691 | case DIE_ERASE: |
82a24990 PC |
692 | flash_erase(s, s->cur_addr, s->cmd_in_progress); |
693 | break; | |
03ec2f83 | 694 | case WRSR: |
7a69c100 MK |
695 | switch (get_man(s)) { |
696 | case MAN_SPANSION: | |
697 | s->quad_enable = !!(s->data[1] & 0x02); | |
698 | break; | |
699 | case MAN_MACRONIX: | |
700 | s->quad_enable = extract32(s->data[0], 6, 1); | |
d9cc8701 | 701 | if (s->len > 1) { |
2151b044 | 702 | s->volatile_cfg = s->data[1]; |
d9cc8701 MK |
703 | s->four_bytes_address_mode = extract32(s->data[1], 5, 1); |
704 | } | |
7a69c100 MK |
705 | break; |
706 | default: | |
707 | break; | |
708 | } | |
03ec2f83 KJS |
709 | if (s->write_enable) { |
710 | s->write_enable = false; | |
711 | } | |
712 | break; | |
0f589782 | 713 | case BRWR: |
d8a29a7a MK |
714 | case EXTEND_ADDR_WRITE: |
715 | s->ear = s->data[0]; | |
716 | break; | |
cb475951 MK |
717 | case WNVCR: |
718 | s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8); | |
719 | break; | |
720 | case WVCR: | |
721 | s->volatile_cfg = s->data[0]; | |
722 | break; | |
723 | case WEVCR: | |
724 | s->enh_volatile_cfg = s->data[0]; | |
725 | break; | |
a87fc364 FI |
726 | case RDID_90: |
727 | case RDID_AB: | |
728 | if (get_man(s) == MAN_SST) { | |
729 | if (s->cur_addr <= 1) { | |
730 | if (s->cur_addr) { | |
731 | s->data[0] = s->pi->id[2]; | |
732 | s->data[1] = s->pi->id[0]; | |
733 | } else { | |
734 | s->data[0] = s->pi->id[0]; | |
735 | s->data[1] = s->pi->id[2]; | |
736 | } | |
737 | s->pos = 0; | |
738 | s->len = 2; | |
739 | s->data_read_loop = true; | |
740 | s->state = STATE_READING_DATA; | |
741 | } else { | |
742 | qemu_log_mask(LOG_GUEST_ERROR, | |
743 | "M25P80: Invalid read id address\n"); | |
744 | } | |
745 | } else { | |
746 | qemu_log_mask(LOG_GUEST_ERROR, | |
747 | "M25P80: Read id (command 0x90/0xAB) is not supported" | |
748 | " by device\n"); | |
749 | } | |
750 | break; | |
82a24990 PC |
751 | default: |
752 | break; | |
753 | } | |
754 | } | |
755 | ||
187c2636 MK |
756 | static void reset_memory(Flash *s) |
757 | { | |
758 | s->cmd_in_progress = NOP; | |
759 | s->cur_addr = 0; | |
d8a29a7a | 760 | s->ear = 0; |
c0f3f675 | 761 | s->four_bytes_address_mode = false; |
187c2636 MK |
762 | s->len = 0; |
763 | s->needed_bytes = 0; | |
764 | s->pos = 0; | |
765 | s->state = STATE_IDLE; | |
766 | s->write_enable = false; | |
767 | s->reset_enable = false; | |
7a69c100 | 768 | s->quad_enable = false; |
187c2636 | 769 | |
c7cd0a6c MK |
770 | switch (get_man(s)) { |
771 | case MAN_NUMONYX: | |
cb475951 MK |
772 | s->volatile_cfg = 0; |
773 | s->volatile_cfg |= VCFG_DUMMY; | |
774 | s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL; | |
775 | if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK) | |
776 | != NVCFG_XIP_MODE_DISABLED) { | |
777 | s->volatile_cfg |= VCFG_XIP_MODE_ENABLED; | |
778 | } | |
779 | s->volatile_cfg |= deposit32(s->volatile_cfg, | |
780 | VCFG_DUMMY_CLK_POS, | |
781 | CFG_DUMMY_CLK_LEN, | |
782 | extract32(s->nonvolatile_cfg, | |
783 | NVCFG_DUMMY_CLK_POS, | |
784 | CFG_DUMMY_CLK_LEN) | |
785 | ); | |
786 | ||
787 | s->enh_volatile_cfg = 0; | |
5c765e7a | 788 | s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGTH_DEF; |
cb475951 MK |
789 | s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR; |
790 | s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED; | |
791 | if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) { | |
792 | s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED; | |
793 | } | |
794 | if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) { | |
795 | s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED; | |
796 | } | |
797 | if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) { | |
798 | s->four_bytes_address_mode = true; | |
799 | } | |
800 | if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) { | |
e02b3bf2 | 801 | s->ear = s->size / MAX_3BYTES_SIZE - 1; |
cb475951 | 802 | } |
c7cd0a6c | 803 | break; |
d9cc8701 MK |
804 | case MAN_MACRONIX: |
805 | s->volatile_cfg = 0x7; | |
806 | break; | |
807 | case MAN_SPANSION: | |
808 | s->spansion_cr1v = s->spansion_cr1nv; | |
809 | s->spansion_cr2v = s->spansion_cr2nv; | |
810 | s->spansion_cr3v = s->spansion_cr3nv; | |
811 | s->spansion_cr4v = s->spansion_cr4nv; | |
812 | s->quad_enable = extract32(s->spansion_cr1v, | |
813 | SPANSION_QUAD_CFG_POS, | |
814 | SPANSION_QUAD_CFG_LEN | |
815 | ); | |
816 | s->four_bytes_address_mode = extract32(s->spansion_cr2v, | |
817 | SPANSION_ADDR_LEN_POS, | |
818 | SPANSION_ADDR_LEN_LEN | |
819 | ); | |
820 | break; | |
c7cd0a6c MK |
821 | default: |
822 | break; | |
cb475951 MK |
823 | } |
824 | ||
187c2636 MK |
825 | DB_PRINT_L(0, "Reset done.\n"); |
826 | } | |
827 | ||
cf6f1efe MK |
828 | static void decode_fast_read_cmd(Flash *s) |
829 | { | |
830 | s->needed_bytes = get_addr_length(s); | |
831 | switch (get_man(s)) { | |
832 | /* Dummy cycles - modeled with bytes writes instead of bits */ | |
3830c7a4 MK |
833 | case MAN_WINBOND: |
834 | s->needed_bytes += 8; | |
835 | break; | |
cf6f1efe MK |
836 | case MAN_NUMONYX: |
837 | s->needed_bytes += extract32(s->volatile_cfg, 4, 4); | |
838 | break; | |
839 | case MAN_MACRONIX: | |
840 | if (extract32(s->volatile_cfg, 6, 2) == 1) { | |
841 | s->needed_bytes += 6; | |
842 | } else { | |
843 | s->needed_bytes += 8; | |
844 | } | |
845 | break; | |
846 | case MAN_SPANSION: | |
847 | s->needed_bytes += extract32(s->spansion_cr2v, | |
848 | SPANSION_DUMMY_CLK_POS, | |
849 | SPANSION_DUMMY_CLK_LEN | |
850 | ); | |
851 | break; | |
852 | default: | |
853 | break; | |
854 | } | |
855 | s->pos = 0; | |
856 | s->len = 0; | |
857 | s->state = STATE_COLLECTING_DATA; | |
858 | } | |
859 | ||
860 | static void decode_dio_read_cmd(Flash *s) | |
861 | { | |
862 | s->needed_bytes = get_addr_length(s); | |
863 | /* Dummy cycles modeled with bytes writes instead of bits */ | |
864 | switch (get_man(s)) { | |
865 | case MAN_WINBOND: | |
fe847705 | 866 | s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; |
cf6f1efe MK |
867 | break; |
868 | case MAN_SPANSION: | |
869 | s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; | |
870 | s->needed_bytes += extract32(s->spansion_cr2v, | |
871 | SPANSION_DUMMY_CLK_POS, | |
872 | SPANSION_DUMMY_CLK_LEN | |
873 | ); | |
874 | break; | |
875 | case MAN_NUMONYX: | |
876 | s->needed_bytes += extract32(s->volatile_cfg, 4, 4); | |
877 | break; | |
878 | case MAN_MACRONIX: | |
879 | switch (extract32(s->volatile_cfg, 6, 2)) { | |
880 | case 1: | |
881 | s->needed_bytes += 6; | |
882 | break; | |
883 | case 2: | |
884 | s->needed_bytes += 8; | |
885 | break; | |
886 | default: | |
887 | s->needed_bytes += 4; | |
888 | break; | |
889 | } | |
890 | break; | |
891 | default: | |
892 | break; | |
893 | } | |
894 | s->pos = 0; | |
895 | s->len = 0; | |
896 | s->state = STATE_COLLECTING_DATA; | |
897 | } | |
898 | ||
899 | static void decode_qio_read_cmd(Flash *s) | |
900 | { | |
901 | s->needed_bytes = get_addr_length(s); | |
902 | /* Dummy cycles modeled with bytes writes instead of bits */ | |
903 | switch (get_man(s)) { | |
904 | case MAN_WINBOND: | |
fe847705 MK |
905 | s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN; |
906 | s->needed_bytes += 4; | |
cf6f1efe MK |
907 | break; |
908 | case MAN_SPANSION: | |
909 | s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN; | |
910 | s->needed_bytes += extract32(s->spansion_cr2v, | |
911 | SPANSION_DUMMY_CLK_POS, | |
912 | SPANSION_DUMMY_CLK_LEN | |
913 | ); | |
914 | break; | |
915 | case MAN_NUMONYX: | |
916 | s->needed_bytes += extract32(s->volatile_cfg, 4, 4); | |
917 | break; | |
918 | case MAN_MACRONIX: | |
919 | switch (extract32(s->volatile_cfg, 6, 2)) { | |
920 | case 1: | |
921 | s->needed_bytes += 4; | |
922 | break; | |
923 | case 2: | |
924 | s->needed_bytes += 8; | |
925 | break; | |
926 | default: | |
927 | s->needed_bytes += 6; | |
928 | break; | |
929 | } | |
930 | break; | |
931 | default: | |
932 | break; | |
933 | } | |
934 | s->pos = 0; | |
935 | s->len = 0; | |
936 | s->state = STATE_COLLECTING_DATA; | |
937 | } | |
938 | ||
82a24990 PC |
939 | static void decode_new_cmd(Flash *s, uint32_t value) |
940 | { | |
941 | s->cmd_in_progress = value; | |
e3ba6cd6 | 942 | int i; |
28097d02 | 943 | DB_PRINT_L(0, "decoded new command:%x\n", value); |
82a24990 | 944 | |
187c2636 MK |
945 | if (value != RESET_MEMORY) { |
946 | s->reset_enable = false; | |
947 | } | |
948 | ||
82a24990 PC |
949 | switch (value) { |
950 | ||
951 | case ERASE_4K: | |
63e47f6f | 952 | case ERASE4_4K: |
82a24990 | 953 | case ERASE_32K: |
30467afe | 954 | case ERASE4_32K: |
82a24990 | 955 | case ERASE_SECTOR: |
63e47f6f | 956 | case ERASE4_SECTOR: |
82a24990 | 957 | case READ: |
63e47f6f | 958 | case READ4: |
419336a9 PC |
959 | case DPP: |
960 | case QPP: | |
597c15f0 | 961 | case QPP_4: |
82a24990 | 962 | case PP: |
63e47f6f | 963 | case PP4: |
30467afe | 964 | case PP4_4: |
f509dfee | 965 | case DIE_ERASE: |
a87fc364 FI |
966 | case RDID_90: |
967 | case RDID_AB: | |
c0f3f675 | 968 | s->needed_bytes = get_addr_length(s); |
82a24990 PC |
969 | s->pos = 0; |
970 | s->len = 0; | |
971 | s->state = STATE_COLLECTING_DATA; | |
972 | break; | |
973 | ||
974 | case FAST_READ: | |
63e47f6f | 975 | case FAST_READ4: |
419336a9 | 976 | case DOR: |
63e47f6f | 977 | case DOR4: |
419336a9 | 978 | case QOR: |
63e47f6f | 979 | case QOR4: |
cf6f1efe | 980 | decode_fast_read_cmd(s); |
82a24990 PC |
981 | break; |
982 | ||
419336a9 | 983 | case DIOR: |
63e47f6f | 984 | case DIOR4: |
cf6f1efe | 985 | decode_dio_read_cmd(s); |
419336a9 PC |
986 | break; |
987 | ||
988 | case QIOR: | |
63e47f6f | 989 | case QIOR4: |
cf6f1efe | 990 | decode_qio_read_cmd(s); |
419336a9 PC |
991 | break; |
992 | ||
03ec2f83 KJS |
993 | case WRSR: |
994 | if (s->write_enable) { | |
7a69c100 MK |
995 | switch (get_man(s)) { |
996 | case MAN_SPANSION: | |
997 | s->needed_bytes = 2; | |
998 | s->state = STATE_COLLECTING_DATA; | |
999 | break; | |
1000 | case MAN_MACRONIX: | |
1001 | s->needed_bytes = 2; | |
1002 | s->state = STATE_COLLECTING_VAR_LEN_DATA; | |
1003 | break; | |
1004 | default: | |
1005 | s->needed_bytes = 1; | |
1006 | s->state = STATE_COLLECTING_DATA; | |
1007 | } | |
03ec2f83 | 1008 | s->pos = 0; |
03ec2f83 KJS |
1009 | } |
1010 | break; | |
1011 | ||
82a24990 PC |
1012 | case WRDI: |
1013 | s->write_enable = false; | |
1014 | break; | |
1015 | case WREN: | |
1016 | s->write_enable = true; | |
1017 | break; | |
1018 | ||
1019 | case RDSR: | |
1020 | s->data[0] = (!!s->write_enable) << 1; | |
7a69c100 MK |
1021 | if (get_man(s) == MAN_MACRONIX) { |
1022 | s->data[0] |= (!!s->quad_enable) << 6; | |
1023 | } | |
82a24990 PC |
1024 | s->pos = 0; |
1025 | s->len = 1; | |
0add925f | 1026 | s->data_read_loop = true; |
82a24990 PC |
1027 | s->state = STATE_READING_DATA; |
1028 | break; | |
1029 | ||
9fbaa364 MK |
1030 | case READ_FSR: |
1031 | s->data[0] = FSR_FLASH_READY; | |
1032 | if (s->four_bytes_address_mode) { | |
1033 | s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED; | |
1034 | } | |
1035 | s->pos = 0; | |
1036 | s->len = 1; | |
0add925f | 1037 | s->data_read_loop = true; |
9fbaa364 MK |
1038 | s->state = STATE_READING_DATA; |
1039 | break; | |
1040 | ||
82a24990 | 1041 | case JEDEC_READ: |
28097d02 | 1042 | DB_PRINT_L(0, "populated jedec code\n"); |
e3ba6cd6 MK |
1043 | for (i = 0; i < s->pi->id_len; i++) { |
1044 | s->data[i] = s->pi->id[i]; | |
82a24990 | 1045 | } |
e3ba6cd6 MK |
1046 | |
1047 | s->len = s->pi->id_len; | |
82a24990 PC |
1048 | s->pos = 0; |
1049 | s->state = STATE_READING_DATA; | |
1050 | break; | |
1051 | ||
7a69c100 MK |
1052 | case RDCR: |
1053 | s->data[0] = s->volatile_cfg & 0xFF; | |
1054 | s->data[0] |= (!!s->four_bytes_address_mode) << 5; | |
1055 | s->pos = 0; | |
1056 | s->len = 1; | |
1057 | s->state = STATE_READING_DATA; | |
1058 | break; | |
1059 | ||
0f589782 | 1060 | case BULK_ERASE_60: |
82a24990 PC |
1061 | case BULK_ERASE: |
1062 | if (s->write_enable) { | |
28097d02 | 1063 | DB_PRINT_L(0, "chip erase\n"); |
82a24990 PC |
1064 | flash_erase(s, 0, BULK_ERASE); |
1065 | } else { | |
e9711b4d PC |
1066 | qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write " |
1067 | "protect!\n"); | |
82a24990 PC |
1068 | } |
1069 | break; | |
1070 | case NOP: | |
1071 | break; | |
c0f3f675 MK |
1072 | case EN_4BYTE_ADDR: |
1073 | s->four_bytes_address_mode = true; | |
1074 | break; | |
1075 | case EX_4BYTE_ADDR: | |
1076 | s->four_bytes_address_mode = false; | |
1077 | break; | |
0f589782 | 1078 | case BRRD: |
d8a29a7a MK |
1079 | case EXTEND_ADDR_READ: |
1080 | s->data[0] = s->ear; | |
1081 | s->pos = 0; | |
1082 | s->len = 1; | |
1083 | s->state = STATE_READING_DATA; | |
1084 | break; | |
0f589782 | 1085 | case BRWR: |
d8a29a7a MK |
1086 | case EXTEND_ADDR_WRITE: |
1087 | if (s->write_enable) { | |
1088 | s->needed_bytes = 1; | |
1089 | s->pos = 0; | |
1090 | s->len = 0; | |
1091 | s->state = STATE_COLLECTING_DATA; | |
1092 | } | |
1093 | break; | |
cb475951 MK |
1094 | case RNVCR: |
1095 | s->data[0] = s->nonvolatile_cfg & 0xFF; | |
1096 | s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF; | |
1097 | s->pos = 0; | |
1098 | s->len = 2; | |
1099 | s->state = STATE_READING_DATA; | |
1100 | break; | |
1101 | case WNVCR: | |
7a69c100 | 1102 | if (s->write_enable && get_man(s) == MAN_NUMONYX) { |
cb475951 MK |
1103 | s->needed_bytes = 2; |
1104 | s->pos = 0; | |
1105 | s->len = 0; | |
1106 | s->state = STATE_COLLECTING_DATA; | |
1107 | } | |
1108 | break; | |
1109 | case RVCR: | |
1110 | s->data[0] = s->volatile_cfg & 0xFF; | |
1111 | s->pos = 0; | |
1112 | s->len = 1; | |
1113 | s->state = STATE_READING_DATA; | |
1114 | break; | |
1115 | case WVCR: | |
1116 | if (s->write_enable) { | |
1117 | s->needed_bytes = 1; | |
1118 | s->pos = 0; | |
1119 | s->len = 0; | |
1120 | s->state = STATE_COLLECTING_DATA; | |
1121 | } | |
1122 | break; | |
1123 | case REVCR: | |
1124 | s->data[0] = s->enh_volatile_cfg & 0xFF; | |
1125 | s->pos = 0; | |
1126 | s->len = 1; | |
1127 | s->state = STATE_READING_DATA; | |
1128 | break; | |
1129 | case WEVCR: | |
1130 | if (s->write_enable) { | |
1131 | s->needed_bytes = 1; | |
1132 | s->pos = 0; | |
1133 | s->len = 0; | |
1134 | s->state = STATE_COLLECTING_DATA; | |
1135 | } | |
1136 | break; | |
187c2636 MK |
1137 | case RESET_ENABLE: |
1138 | s->reset_enable = true; | |
1139 | break; | |
1140 | case RESET_MEMORY: | |
1141 | if (s->reset_enable) { | |
1142 | reset_memory(s); | |
1143 | } | |
1144 | break; | |
7a69c100 MK |
1145 | case RDCR_EQIO: |
1146 | switch (get_man(s)) { | |
1147 | case MAN_SPANSION: | |
1148 | s->data[0] = (!!s->quad_enable) << 1; | |
1149 | s->pos = 0; | |
1150 | s->len = 1; | |
1151 | s->state = STATE_READING_DATA; | |
1152 | break; | |
1153 | case MAN_MACRONIX: | |
1154 | s->quad_enable = true; | |
1155 | break; | |
1156 | default: | |
1157 | break; | |
1158 | } | |
1159 | break; | |
1160 | case RSTQIO: | |
1161 | s->quad_enable = false; | |
1162 | break; | |
82a24990 | 1163 | default: |
e9711b4d | 1164 | qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value); |
82a24990 PC |
1165 | break; |
1166 | } | |
1167 | } | |
1168 | ||
1169 | static int m25p80_cs(SSISlave *ss, bool select) | |
1170 | { | |
cdccf7d7 | 1171 | Flash *s = M25P80(ss); |
82a24990 PC |
1172 | |
1173 | if (select) { | |
9964674e MK |
1174 | if (s->state == STATE_COLLECTING_VAR_LEN_DATA) { |
1175 | complete_collecting_data(s); | |
1176 | } | |
82a24990 PC |
1177 | s->len = 0; |
1178 | s->pos = 0; | |
1179 | s->state = STATE_IDLE; | |
1180 | flash_sync_dirty(s, -1); | |
0add925f | 1181 | s->data_read_loop = false; |
82a24990 PC |
1182 | } |
1183 | ||
28097d02 | 1184 | DB_PRINT_L(0, "%sselect\n", select ? "de" : ""); |
82a24990 PC |
1185 | |
1186 | return 0; | |
1187 | } | |
1188 | ||
1189 | static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx) | |
1190 | { | |
cdccf7d7 | 1191 | Flash *s = M25P80(ss); |
82a24990 PC |
1192 | uint32_t r = 0; |
1193 | ||
1194 | switch (s->state) { | |
1195 | ||
1196 | case STATE_PAGE_PROGRAM: | |
b7f480c3 | 1197 | DB_PRINT_L(1, "page program cur_addr=%#" PRIx32 " data=%" PRIx8 "\n", |
28097d02 | 1198 | s->cur_addr, (uint8_t)tx); |
82a24990 | 1199 | flash_write8(s, s->cur_addr, (uint8_t)tx); |
b68cb060 | 1200 | s->cur_addr = (s->cur_addr + 1) & (s->size - 1); |
82a24990 PC |
1201 | break; |
1202 | ||
1203 | case STATE_READ: | |
1204 | r = s->storage[s->cur_addr]; | |
b7f480c3 | 1205 | DB_PRINT_L(1, "READ 0x%" PRIx32 "=%" PRIx8 "\n", s->cur_addr, |
28097d02 | 1206 | (uint8_t)r); |
b68cb060 | 1207 | s->cur_addr = (s->cur_addr + 1) & (s->size - 1); |
82a24990 PC |
1208 | break; |
1209 | ||
1210 | case STATE_COLLECTING_DATA: | |
9964674e | 1211 | case STATE_COLLECTING_VAR_LEN_DATA: |
24cb2e0d JCD |
1212 | |
1213 | if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) { | |
1214 | qemu_log_mask(LOG_GUEST_ERROR, | |
1215 | "M25P80: Write overrun internal data buffer. " | |
1216 | "SPI controller (QEMU emulator or guest driver) " | |
1217 | "is misbehaving\n"); | |
1218 | s->len = s->pos = 0; | |
1219 | s->state = STATE_IDLE; | |
1220 | break; | |
1221 | } | |
1222 | ||
82a24990 PC |
1223 | s->data[s->len] = (uint8_t)tx; |
1224 | s->len++; | |
1225 | ||
1226 | if (s->len == s->needed_bytes) { | |
1227 | complete_collecting_data(s); | |
1228 | } | |
1229 | break; | |
1230 | ||
1231 | case STATE_READING_DATA: | |
24cb2e0d JCD |
1232 | |
1233 | if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) { | |
1234 | qemu_log_mask(LOG_GUEST_ERROR, | |
1235 | "M25P80: Read overrun internal data buffer. " | |
1236 | "SPI controller (QEMU emulator or guest driver) " | |
1237 | "is misbehaving\n"); | |
1238 | s->len = s->pos = 0; | |
1239 | s->state = STATE_IDLE; | |
1240 | break; | |
1241 | } | |
1242 | ||
82a24990 PC |
1243 | r = s->data[s->pos]; |
1244 | s->pos++; | |
1245 | if (s->pos == s->len) { | |
1246 | s->pos = 0; | |
0add925f FI |
1247 | if (!s->data_read_loop) { |
1248 | s->state = STATE_IDLE; | |
1249 | } | |
82a24990 PC |
1250 | } |
1251 | break; | |
1252 | ||
1253 | default: | |
1254 | case STATE_IDLE: | |
1255 | decode_new_cmd(s, (uint8_t)tx); | |
1256 | break; | |
1257 | } | |
1258 | ||
1259 | return r; | |
1260 | } | |
1261 | ||
7673bb4c | 1262 | static void m25p80_realize(SSISlave *ss, Error **errp) |
82a24990 | 1263 | { |
cdccf7d7 | 1264 | Flash *s = M25P80(ss); |
a7fd6915 | 1265 | M25P80Class *mc = M25P80_GET_CLASS(s); |
a17c17a2 | 1266 | int ret; |
82a24990 | 1267 | |
a7fd6915 | 1268 | s->pi = mc->pi; |
82a24990 PC |
1269 | |
1270 | s->size = s->pi->sector_size * s->pi->n_sectors; | |
1271 | s->dirty_page = -1; | |
82a24990 | 1272 | |
73bce518 | 1273 | if (s->blk) { |
a17c17a2 KW |
1274 | uint64_t perm = BLK_PERM_CONSISTENT_READ | |
1275 | (blk_is_read_only(s->blk) ? 0 : BLK_PERM_WRITE); | |
1276 | ret = blk_set_perm(s->blk, perm, BLK_PERM_ALL, errp); | |
1277 | if (ret < 0) { | |
1278 | return; | |
1279 | } | |
1280 | ||
28097d02 | 1281 | DB_PRINT_L(0, "Binding to IF_MTD drive\n"); |
c485cf9c SH |
1282 | s->storage = blk_blockalign(s->blk, s->size); |
1283 | ||
9e19036e | 1284 | if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) { |
7673bb4c CLG |
1285 | error_setg(errp, "failed to read the initial flash content"); |
1286 | return; | |
82a24990 PC |
1287 | } |
1288 | } else { | |
095b9c48 | 1289 | DB_PRINT_L(0, "No BDRV - binding to RAM\n"); |
c485cf9c | 1290 | s->storage = blk_blockalign(NULL, s->size); |
82a24990 PC |
1291 | memset(s->storage, 0xFF, s->size); |
1292 | } | |
82a24990 PC |
1293 | } |
1294 | ||
187c2636 MK |
1295 | static void m25p80_reset(DeviceState *d) |
1296 | { | |
1297 | Flash *s = M25P80(d); | |
1298 | ||
1299 | reset_memory(s); | |
1300 | } | |
1301 | ||
44b1ff31 | 1302 | static int m25p80_pre_save(void *opaque) |
82a24990 PC |
1303 | { |
1304 | flash_sync_dirty((Flash *)opaque, -1); | |
44b1ff31 DDAG |
1305 | |
1306 | return 0; | |
82a24990 PC |
1307 | } |
1308 | ||
cb475951 | 1309 | static Property m25p80_properties[] = { |
d9cc8701 | 1310 | /* This is default value for Micron flash */ |
cb475951 | 1311 | DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF), |
d9cc8701 MK |
1312 | DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0), |
1313 | DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8), | |
1314 | DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2), | |
1315 | DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10), | |
73bce518 | 1316 | DEFINE_PROP_DRIVE("drive", Flash, blk), |
cb475951 MK |
1317 | DEFINE_PROP_END_OF_LIST(), |
1318 | }; | |
1319 | ||
0add925f FI |
1320 | static int m25p80_pre_load(void *opaque) |
1321 | { | |
1322 | Flash *s = (Flash *)opaque; | |
1323 | ||
1324 | s->data_read_loop = false; | |
1325 | return 0; | |
1326 | } | |
1327 | ||
1328 | static bool m25p80_data_read_loop_needed(void *opaque) | |
1329 | { | |
1330 | Flash *s = (Flash *)opaque; | |
1331 | ||
1332 | return s->data_read_loop; | |
1333 | } | |
1334 | ||
1335 | static const VMStateDescription vmstate_m25p80_data_read_loop = { | |
1336 | .name = "m25p80/data_read_loop", | |
1337 | .version_id = 1, | |
1338 | .minimum_version_id = 1, | |
1339 | .needed = m25p80_data_read_loop_needed, | |
1340 | .fields = (VMStateField[]) { | |
1341 | VMSTATE_BOOL(data_read_loop, Flash), | |
1342 | VMSTATE_END_OF_LIST() | |
1343 | } | |
1344 | }; | |
1345 | ||
82a24990 | 1346 | static const VMStateDescription vmstate_m25p80 = { |
c827c06a MK |
1347 | .name = "m25p80", |
1348 | .version_id = 0, | |
1349 | .minimum_version_id = 0, | |
82a24990 | 1350 | .pre_save = m25p80_pre_save, |
0add925f | 1351 | .pre_load = m25p80_pre_load, |
82a24990 PC |
1352 | .fields = (VMStateField[]) { |
1353 | VMSTATE_UINT8(state, Flash), | |
24cb2e0d | 1354 | VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ), |
82a24990 PC |
1355 | VMSTATE_UINT32(len, Flash), |
1356 | VMSTATE_UINT32(pos, Flash), | |
1357 | VMSTATE_UINT8(needed_bytes, Flash), | |
1358 | VMSTATE_UINT8(cmd_in_progress, Flash), | |
b7f480c3 | 1359 | VMSTATE_UINT32(cur_addr, Flash), |
82a24990 | 1360 | VMSTATE_BOOL(write_enable, Flash), |
c827c06a MK |
1361 | VMSTATE_BOOL(reset_enable, Flash), |
1362 | VMSTATE_UINT8(ear, Flash), | |
1363 | VMSTATE_BOOL(four_bytes_address_mode, Flash), | |
1364 | VMSTATE_UINT32(nonvolatile_cfg, Flash), | |
1365 | VMSTATE_UINT32(volatile_cfg, Flash), | |
1366 | VMSTATE_UINT32(enh_volatile_cfg, Flash), | |
1367 | VMSTATE_BOOL(quad_enable, Flash), | |
1368 | VMSTATE_UINT8(spansion_cr1nv, Flash), | |
1369 | VMSTATE_UINT8(spansion_cr2nv, Flash), | |
1370 | VMSTATE_UINT8(spansion_cr3nv, Flash), | |
1371 | VMSTATE_UINT8(spansion_cr4nv, Flash), | |
82a24990 | 1372 | VMSTATE_END_OF_LIST() |
0add925f FI |
1373 | }, |
1374 | .subsections = (const VMStateDescription * []) { | |
1375 | &vmstate_m25p80_data_read_loop, | |
1376 | NULL | |
82a24990 PC |
1377 | } |
1378 | }; | |
1379 | ||
82a24990 PC |
1380 | static void m25p80_class_init(ObjectClass *klass, void *data) |
1381 | { | |
1382 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1383 | SSISlaveClass *k = SSI_SLAVE_CLASS(klass); | |
a7fd6915 | 1384 | M25P80Class *mc = M25P80_CLASS(klass); |
82a24990 | 1385 | |
7673bb4c | 1386 | k->realize = m25p80_realize; |
82a24990 PC |
1387 | k->transfer = m25p80_transfer8; |
1388 | k->set_cs = m25p80_cs; | |
1389 | k->cs_polarity = SSI_CS_LOW; | |
82a24990 | 1390 | dc->vmsd = &vmstate_m25p80; |
cb475951 | 1391 | dc->props = m25p80_properties; |
187c2636 | 1392 | dc->reset = m25p80_reset; |
a7fd6915 | 1393 | mc->pi = data; |
82a24990 PC |
1394 | } |
1395 | ||
1396 | static const TypeInfo m25p80_info = { | |
a7fd6915 | 1397 | .name = TYPE_M25P80, |
82a24990 PC |
1398 | .parent = TYPE_SSI_SLAVE, |
1399 | .instance_size = sizeof(Flash), | |
a7fd6915 PC |
1400 | .class_size = sizeof(M25P80Class), |
1401 | .abstract = true, | |
82a24990 PC |
1402 | }; |
1403 | ||
1404 | static void m25p80_register_types(void) | |
1405 | { | |
a7fd6915 PC |
1406 | int i; |
1407 | ||
82a24990 | 1408 | type_register_static(&m25p80_info); |
a7fd6915 PC |
1409 | for (i = 0; i < ARRAY_SIZE(known_devices); ++i) { |
1410 | TypeInfo ti = { | |
1411 | .name = known_devices[i].part_name, | |
1412 | .parent = TYPE_M25P80, | |
1413 | .class_init = m25p80_class_init, | |
1414 | .class_data = (void *)&known_devices[i], | |
1415 | }; | |
1416 | type_register(&ti); | |
1417 | } | |
82a24990 PC |
1418 | } |
1419 | ||
1420 | type_init(m25p80_register_types) |