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block: m25p80: Implemented FSR register
[mirror_qemu.git] / hw / block / m25p80.c
CommitLineData
82a24990
PC		 1/*
2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
3 * set. Known devices table current as of Jun/2012 and taken from linux.
4 * See drivers/mtd/devices/m25p80.c.
5 *
6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Copyright (C) 2012 PetaLogix
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 or
13 * (at your option) a later version of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 */
23
80c71a24 24#include "qemu/osdep.h"
83c9f4ca 25#include "hw/hw.h"
fa1d36df 26#include "sysemu/block-backend.h"
9c17d615 27#include "sysemu/blockdev.h"
8fd06719 28#include "hw/ssi/ssi.h"
cb475951 29#include "qemu/bitops.h"
82a24990 30
28097d02
PC		 31#ifndef M25P80_ERR_DEBUG
32#define M25P80_ERR_DEBUG 0
82a24990
PC		 33#endif
34
28097d02
PC		 35#define DB_PRINT_L(level, ...) do { \
36 if (M25P80_ERR_DEBUG > (level)) { \
37 fprintf(stderr, ": %s: ", __func__); \
38 fprintf(stderr, ## __VA_ARGS__); \
39 } \
40} while (0);
41
82a24990
PC		 42/* Fields for FlashPartInfo->flags */
43
44/* erase capabilities */
45#define ER_4K 1
46#define ER_32K 2
47/* set to allow the page program command to write 0s back to 1. Useful for
48 * modelling EEPROM with SPI flash command set
49 */
50#define WR_1 0x100
51
d8a29a7a
MK		 52/* 16 MiB max in 3 byte address mode */
53#define MAX_3BYTES_SIZE 0x1000000
54
82a24990
PC		 55typedef struct FlashPartInfo {
56 const char *part_name;
57 /* jedec code. (jedec >> 16) & 0xff is the 1st byte, >> 8 the 2nd etc */
58 uint32_t jedec;
59 /* extended jedec code */
60 uint16_t ext_jedec;
61 /* there is confusion between manufacturers as to what a sector is. In this
62 * device model, a "sector" is the size that is erased by the ERASE_SECTOR
63 * command (opcode 0xd8).
64 */
65 uint32_t sector_size;
66 uint32_t n_sectors;
67 uint32_t page_size;
76e87269 68 uint16_t flags;
82a24990
PC		 69} FlashPartInfo;
70
71/* adapted from linux */
72
73#define INFO(_part_name, _jedec, _ext_jedec, _sector_size, _n_sectors, _flags)\
74 .part_name = (_part_name),\
75 .jedec = (_jedec),\
76 .ext_jedec = (_ext_jedec),\
77 .sector_size = (_sector_size),\
78 .n_sectors = (_n_sectors),\
79 .page_size = 256,\
80 .flags = (_flags),\
81
419336a9
PC		 82#define JEDEC_NUMONYX 0x20
83#define JEDEC_WINBOND 0xEF
84#define JEDEC_SPANSION 0x01
85
cb475951
MK		 86/* Numonyx (Micron) Configuration register macros */
87#define VCFG_DUMMY 0x1
88#define VCFG_WRAP_SEQUENTIAL 0x2
89#define NVCFG_XIP_MODE_DISABLED (7 << 9)
90#define NVCFG_XIP_MODE_MASK (7 << 9)
91#define VCFG_XIP_MODE_ENABLED (1 << 3)
92#define CFG_DUMMY_CLK_LEN 4
93#define NVCFG_DUMMY_CLK_POS 12
94#define VCFG_DUMMY_CLK_POS 4
95#define EVCFG_OUT_DRIVER_STRENGHT_DEF 7
96#define EVCFG_VPP_ACCELERATOR (1 << 3)
97#define EVCFG_RESET_HOLD_ENABLED (1 << 4)
98#define NVCFG_DUAL_IO_MASK (1 << 2)
99#define EVCFG_DUAL_IO_ENABLED (1 << 6)
100#define NVCFG_QUAD_IO_MASK (1 << 3)
101#define EVCFG_QUAD_IO_ENABLED (1 << 7)
102#define NVCFG_4BYTE_ADDR_MASK (1 << 0)
103#define NVCFG_LOWER_SEGMENT_MASK (1 << 1)
104#define CFG_UPPER_128MB_SEG_ENABLED 0x3
105
9fbaa364
MK		 106/* Numonyx (Micron) Flag Status Register macros */
107#define FSR_4BYTE_ADDR_MODE_ENABLED 0x1
108#define FSR_FLASH_READY (1 << 7)
109
82a24990
PC		 110static const FlashPartInfo known_devices[] = {
111 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
112 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) },
113 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) },
114
115 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) },
116 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) },
117 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) },
118
119 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) },
120 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) },
121 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) },
122 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) },
123
3e758c1d
EM		 124 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) },
125
82a24990
PC		 126 /* EON -- en25xxx */
127 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) },
128 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) },
129 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) },
130 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) },
3e758c1d
EM		 131 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) },
132
133 /* GigaDevice */
134 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) },
135 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) },
82a24990
PC		 136
137 /* Intel/Numonyx -- xxxs33b */
138 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) },
139 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) },
140 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) },
3e758c1d 141 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) },
82a24990
PC		 142
143 /* Macronix */
3e758c1d 144 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
82a24990
PC		 145 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) },
146 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) },
147 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) },
148 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) },
149 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) },
150 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) },
151 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },
152 { INFO("mx25l25635e", 0xc22019, 0, 64 << 10, 512, 0) },
153 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },
154
3e758c1d 155 /* Micron */
f5aac8e0
EM		 156 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) },
157 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) },
158 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) },
159 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) },
160 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) },
161 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) },
162 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) },
163 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
3e758c1d 164
82a24990
PC		 165 /* Spansion -- single (large) sector size only, at least
166 * for the chips listed here (without boot sectors).
167 */
82a24990 168 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) },
3e758c1d 169 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) },
82a24990
PC		 170 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) },
171 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) },
172 { INFO("s25fl512s", 0x010220, 0x4d00, 256 << 10, 256, 0) },
173 { INFO("s70fl01gs", 0x010221, 0x4d00, 256 << 10, 256, 0) },
174 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) },
175 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) },
176 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) },
177 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) },
3e758c1d
EM		 178 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) },
179 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) },
180 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) },
181 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) },
182 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) },
82a24990
PC		 183 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) },
184 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) },
185
186 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
187 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) },
188 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) },
189 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) },
190 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) },
191 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) },
192 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) },
193 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) },
194 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) },
d857c4c0 195 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) },
82a24990
PC		 196
197 /* ST Microelectronics -- newer production may have feature updates */
198 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) },
199 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) },
200 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) },
201 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) },
202 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) },
203 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) },
204 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) },
205 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) },
206 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) },
3e758c1d 207 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) },
82a24990
PC		 208
209 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) },
210 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) },
211 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) },
212
3e758c1d 213 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) },
82a24990
PC		 214 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) },
215 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) },
216
217 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) },
218 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) },
219 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) },
220 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) },
221
222 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
223 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) },
224 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) },
225 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) },
226 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) },
227 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) },
228 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) },
229 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) },
3e758c1d 230 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) },
82a24990
PC		 231 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) },
232 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) },
3e758c1d
EM		 233 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) },
234 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) },
235 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) },
82a24990
PC		 236
237 /* Numonyx -- n25q128 */
238 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) },
82a24990
PC		 239};
240
241typedef enum {
242 NOP = 0,
03ec2f83 243 WRSR = 0x1,
82a24990
PC		 244 WRDI = 0x4,
245 RDSR = 0x5,
246 WREN = 0x6,
419336a9
PC		 247 JEDEC_READ = 0x9f,
248 BULK_ERASE = 0xc7,
9fbaa364 249 READ_FSR = 0x70,
419336a9 250
63e47f6f
MK		 251 READ = 0x03,
252 READ4 = 0x13,
253 FAST_READ = 0x0b,
254 FAST_READ4 = 0x0c,
419336a9 255 DOR = 0x3b,
63e47f6f 256 DOR4 = 0x3c,
419336a9 257 QOR = 0x6b,
63e47f6f 258 QOR4 = 0x6c,
419336a9 259 DIOR = 0xbb,
63e47f6f 260 DIOR4 = 0xbc,
419336a9 261 QIOR = 0xeb,
63e47f6f 262 QIOR4 = 0xec,
419336a9 263
63e47f6f
MK		 264 PP = 0x02,
265 PP4 = 0x12,
419336a9
PC		 266 DPP = 0xa2,
267 QPP = 0x32,
268
82a24990 269 ERASE_4K = 0x20,
63e47f6f 270 ERASE4_4K = 0x21,
82a24990
PC		 271 ERASE_32K = 0x52,
272 ERASE_SECTOR = 0xd8,
63e47f6f 273 ERASE4_SECTOR = 0xdc,
187c2636 274
c0f3f675
MK		 275 EN_4BYTE_ADDR = 0xB7,
276 EX_4BYTE_ADDR = 0xE9,
277
d8a29a7a
MK		 278 EXTEND_ADDR_READ = 0xC8,
279 EXTEND_ADDR_WRITE = 0xC5,
280
187c2636
MK		 281 RESET_ENABLE = 0x66,
282 RESET_MEMORY = 0x99,
cb475951
MK		 283
284 RNVCR = 0xB5,
285 WNVCR = 0xB1,
286
287 RVCR = 0x85,
288 WVCR = 0x81,
289
290 REVCR = 0x65,
291 WEVCR = 0x61,
82a24990
PC		 292} FlashCMD;
293
294typedef enum {
295 STATE_IDLE,
296 STATE_PAGE_PROGRAM,
297 STATE_READ,
298 STATE_COLLECTING_DATA,
299 STATE_READING_DATA,
300} CMDState;
301
302typedef struct Flash {
cdccf7d7
PC		 303 SSISlave parent_obj;
304
4be74634 305 BlockBackend *blk;
82a24990
PC		 306
307 uint8_t *storage;
308 uint32_t size;
309 int page_size;
310
311 uint8_t state;
312 uint8_t data[16];
313 uint32_t len;
314 uint32_t pos;
315 uint8_t needed_bytes;
316 uint8_t cmd_in_progress;
317 uint64_t cur_addr;
cb475951
MK		 318 uint32_t nonvolatile_cfg;
319 uint32_t volatile_cfg;
320 uint32_t enh_volatile_cfg;
82a24990 321 bool write_enable;
c0f3f675 322 bool four_bytes_address_mode;
187c2636 323 bool reset_enable;
d8a29a7a 324 uint8_t ear;
82a24990
PC		 325
326 int64_t dirty_page;
327
82a24990
PC		 328 const FlashPartInfo *pi;
329
330} Flash;
331
a7fd6915
PC		 332typedef struct M25P80Class {
333 SSISlaveClass parent_class;
334 FlashPartInfo *pi;
335} M25P80Class;
336
337#define TYPE_M25P80 "m25p80-generic"
338#define M25P80(obj) \
339 OBJECT_CHECK(Flash, (obj), TYPE_M25P80)
340#define M25P80_CLASS(klass) \
341 OBJECT_CLASS_CHECK(M25P80Class, (klass), TYPE_M25P80)
342#define M25P80_GET_CLASS(obj) \
343 OBJECT_GET_CLASS(M25P80Class, (obj), TYPE_M25P80)
344
4be74634 345static void blk_sync_complete(void *opaque, int ret)
82a24990
PC		 346{
347 /* do nothing. Masters do not directly interact with the backing store,
348 * only the working copy so no mutexing required.
349 */
350}
351
352static void flash_sync_page(Flash *s, int page)
353{
4be74634 354 int blk_sector, nb_sectors;
fc1084aa
PC		 355 QEMUIOVector iov;
356
4be74634 357 if (!s->blk || blk_is_read_only(s->blk)) {
fc1084aa 358 return;
82a24990 359 }
fc1084aa 360
4be74634 361 blk_sector = (page * s->pi->page_size) / BDRV_SECTOR_SIZE;
fc1084aa
PC		 362 nb_sectors = DIV_ROUND_UP(s->pi->page_size, BDRV_SECTOR_SIZE);
363 qemu_iovec_init(&iov, 1);
4be74634 364 qemu_iovec_add(&iov, s->storage + blk_sector * BDRV_SECTOR_SIZE,
fc1084aa 365 nb_sectors * BDRV_SECTOR_SIZE);
4be74634
MA		 366 blk_aio_writev(s->blk, blk_sector, &iov, nb_sectors, blk_sync_complete,
367 NULL);
82a24990
PC		 368}
369
370static inline void flash_sync_area(Flash *s, int64_t off, int64_t len)
371{
372 int64_t start, end, nb_sectors;
373 QEMUIOVector iov;
374
4be74634 375 if (!s->blk || blk_is_read_only(s->blk)) {
82a24990
PC		 376 return;
377 }
378
379 assert(!(len % BDRV_SECTOR_SIZE));
380 start = off / BDRV_SECTOR_SIZE;
381 end = (off + len) / BDRV_SECTOR_SIZE;
382 nb_sectors = end - start;
383 qemu_iovec_init(&iov, 1);
384 qemu_iovec_add(&iov, s->storage + (start * BDRV_SECTOR_SIZE),
385 nb_sectors * BDRV_SECTOR_SIZE);
4be74634 386 blk_aio_writev(s->blk, start, &iov, nb_sectors, blk_sync_complete, NULL);
82a24990
PC		 387}
388
389static void flash_erase(Flash *s, int offset, FlashCMD cmd)
390{
391 uint32_t len;
392 uint8_t capa_to_assert = 0;
393
394 switch (cmd) {
395 case ERASE_4K:
63e47f6f 396 case ERASE4_4K:
82a24990
PC		 397 len = 4 << 10;
398 capa_to_assert = ER_4K;
399 break;
400 case ERASE_32K:
401 len = 32 << 10;
402 capa_to_assert = ER_32K;
403 break;
404 case ERASE_SECTOR:
63e47f6f 405 case ERASE4_SECTOR:
82a24990
PC		 406 len = s->pi->sector_size;
407 break;
408 case BULK_ERASE:
409 len = s->size;
410 break;
411 default:
412 abort();
413 }
414
28097d02 415 DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len);
82a24990 416 if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
e9711b4d
PC		 417 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
418 " device\n", len);
82a24990
PC		 419 }
420
421 if (!s->write_enable) {
e9711b4d 422 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n");
82a24990
PC		 423 return;
424 }
425 memset(s->storage + offset, 0xff, len);
426 flash_sync_area(s, offset, len);
427}
428
429static inline void flash_sync_dirty(Flash *s, int64_t newpage)
430{
431 if (s->dirty_page >= 0 && s->dirty_page != newpage) {
432 flash_sync_page(s, s->dirty_page);
433 s->dirty_page = newpage;
434 }
435}
436
437static inline
438void flash_write8(Flash *s, uint64_t addr, uint8_t data)
439{
440 int64_t page = addr / s->pi->page_size;
441 uint8_t prev = s->storage[s->cur_addr];
442
443 if (!s->write_enable) {
e9711b4d 444 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
82a24990
PC		 445 }
446
447 if ((prev ^ data) & data) {
28097d02
PC		 448 DB_PRINT_L(1, "programming zero to one! addr=%" PRIx64 " %" PRIx8
449 " -> %" PRIx8 "\n", addr, prev, data);
82a24990
PC		 450 }
451
452 if (s->pi->flags & WR_1) {
453 s->storage[s->cur_addr] = data;
454 } else {
455 s->storage[s->cur_addr] &= data;
456 }
457
458 flash_sync_dirty(s, page);
459 s->dirty_page = page;
460}
461
c0f3f675
MK		 462static inline int get_addr_length(Flash *s)
463{
63e47f6f
MK		 464 switch (s->cmd_in_progress) {
465 case PP4:
466 case READ4:
467 case QIOR4:
468 case ERASE4_4K:
469 case ERASE4_SECTOR:
470 case FAST_READ4:
471 case DOR4:
472 case QOR4:
473 case DIOR4:
474 return 4;
475 default:
476 return s->four_bytes_address_mode ? 4 : 3;
477 }
c0f3f675
MK		 478}
479
82a24990
PC		 480static void complete_collecting_data(Flash *s)
481{
c0f3f675
MK		 482 int i;
483
484 s->cur_addr = 0;
485
486 for (i = 0; i < get_addr_length(s); ++i) {
487 s->cur_addr <<= 8;
488 s->cur_addr |= s->data[i];
489 }
490
491 if (get_addr_length(s) == 3) {
492 s->cur_addr += (s->ear & 0x3) * MAX_3BYTES_SIZE;
493 }
82a24990 494
a56d305a
PC		 495 s->state = STATE_IDLE;
496
82a24990 497 switch (s->cmd_in_progress) {
419336a9
PC		 498 case DPP:
499 case QPP:
82a24990 500 case PP:
63e47f6f 501 case PP4:
82a24990
PC		 502 s->state = STATE_PAGE_PROGRAM;
503 break;
504 case READ:
63e47f6f 505 case READ4:
82a24990 506 case FAST_READ:
63e47f6f 507 case FAST_READ4:
419336a9 508 case DOR:
63e47f6f 509 case DOR4:
419336a9 510 case QOR:
63e47f6f 511 case QOR4:
419336a9 512 case DIOR:
63e47f6f 513 case DIOR4:
419336a9 514 case QIOR:
63e47f6f 515 case QIOR4:
82a24990
PC		 516 s->state = STATE_READ;
517 break;
518 case ERASE_4K:
63e47f6f 519 case ERASE4_4K:
82a24990
PC		 520 case ERASE_32K:
521 case ERASE_SECTOR:
63e47f6f 522 case ERASE4_SECTOR:
82a24990
PC		 523 flash_erase(s, s->cur_addr, s->cmd_in_progress);
524 break;
03ec2f83
KJS		 525 case WRSR:
526 if (s->write_enable) {
527 s->write_enable = false;
528 }
529 break;
d8a29a7a
MK		 530 case EXTEND_ADDR_WRITE:
531 s->ear = s->data[0];
532 break;
cb475951
MK		 533 case WNVCR:
534 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8);
535 break;
536 case WVCR:
537 s->volatile_cfg = s->data[0];
538 break;
539 case WEVCR:
540 s->enh_volatile_cfg = s->data[0];
541 break;
82a24990
PC		 542 default:
543 break;
544 }
545}
546
187c2636
MK		 547static void reset_memory(Flash *s)
548{
549 s->cmd_in_progress = NOP;
550 s->cur_addr = 0;
d8a29a7a 551 s->ear = 0;
c0f3f675 552 s->four_bytes_address_mode = false;
187c2636
MK		 553 s->len = 0;
554 s->needed_bytes = 0;
555 s->pos = 0;
556 s->state = STATE_IDLE;
557 s->write_enable = false;
558 s->reset_enable = false;
559
cb475951
MK		 560 if (((s->pi->jedec >> 16) & 0xFF) == JEDEC_NUMONYX) {
561 s->volatile_cfg = 0;
562 s->volatile_cfg |= VCFG_DUMMY;
563 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL;
564 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK)
565 != NVCFG_XIP_MODE_DISABLED) {
566 s->volatile_cfg |= VCFG_XIP_MODE_ENABLED;
567 }
568 s->volatile_cfg |= deposit32(s->volatile_cfg,
569 VCFG_DUMMY_CLK_POS,
570 CFG_DUMMY_CLK_LEN,
571 extract32(s->nonvolatile_cfg,
572 NVCFG_DUMMY_CLK_POS,
573 CFG_DUMMY_CLK_LEN)
574 );
575
576 s->enh_volatile_cfg = 0;
577 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGHT_DEF;
578 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR;
579 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED;
580 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) {
581 s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED;
582 }
583 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) {
584 s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED;
585 }
586 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) {
587 s->four_bytes_address_mode = true;
588 }
589 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) {
590 s->ear = CFG_UPPER_128MB_SEG_ENABLED;
591 }
592 }
593
187c2636
MK		 594 DB_PRINT_L(0, "Reset done.\n");
595}
596
82a24990
PC		 597static void decode_new_cmd(Flash *s, uint32_t value)
598{
599 s->cmd_in_progress = value;
28097d02 600 DB_PRINT_L(0, "decoded new command:%x\n", value);
82a24990 601
187c2636
MK		 602 if (value != RESET_MEMORY) {
603 s->reset_enable = false;
604 }
605
82a24990
PC		 606 switch (value) {
607
608 case ERASE_4K:
63e47f6f 609 case ERASE4_4K:
82a24990
PC		 610 case ERASE_32K:
611 case ERASE_SECTOR:
63e47f6f 612 case ERASE4_SECTOR:
82a24990 613 case READ:
63e47f6f 614 case READ4:
419336a9
PC		 615 case DPP:
616 case QPP:
82a24990 617 case PP:
63e47f6f 618 case PP4:
c0f3f675 619 s->needed_bytes = get_addr_length(s);
82a24990
PC		 620 s->pos = 0;
621 s->len = 0;
622 s->state = STATE_COLLECTING_DATA;
623 break;
624
625 case FAST_READ:
63e47f6f 626 case FAST_READ4:
419336a9 627 case DOR:
63e47f6f 628 case DOR4:
419336a9 629 case QOR:
63e47f6f 630 case QOR4:
aeb83edb
MK		 631 s->needed_bytes = get_addr_length(s);
632 if (((s->pi->jedec >> 16) & 0xFF) == JEDEC_NUMONYX) {
633 /* Dummy cycles modeled with bytes writes instead of bits */
634 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
635 }
82a24990
PC		 636 s->pos = 0;
637 s->len = 0;
638 s->state = STATE_COLLECTING_DATA;
639 break;
640
419336a9 641 case DIOR:
63e47f6f 642 case DIOR4:
419336a9
PC		 643 switch ((s->pi->jedec >> 16) & 0xFF) {
644 case JEDEC_WINBOND:
645 case JEDEC_SPANSION:
646 s->needed_bytes = 4;
647 break;
419336a9 648 default:
aeb83edb
MK		 649 s->needed_bytes = get_addr_length(s);
650 /* Dummy cycles modeled with bytes writes instead of bits */
651 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
419336a9
PC		 652 }
653 s->pos = 0;
654 s->len = 0;
655 s->state = STATE_COLLECTING_DATA;
656 break;
657
658 case QIOR:
63e47f6f 659 case QIOR4:
419336a9
PC		 660 switch ((s->pi->jedec >> 16) & 0xFF) {
661 case JEDEC_WINBOND:
662 case JEDEC_SPANSION:
663 s->needed_bytes = 6;
664 break;
419336a9 665 default:
aeb83edb
MK		 666 s->needed_bytes = get_addr_length(s);
667 /* Dummy cycles modeled with bytes writes instead of bits */
668 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
419336a9
PC		 669 }
670 s->pos = 0;
671 s->len = 0;
672 s->state = STATE_COLLECTING_DATA;
673 break;
674
03ec2f83
KJS		 675 case WRSR:
676 if (s->write_enable) {
677 s->needed_bytes = 1;
678 s->pos = 0;
679 s->len = 0;
680 s->state = STATE_COLLECTING_DATA;
681 }
682 break;
683
82a24990
PC		 684 case WRDI:
685 s->write_enable = false;
686 break;
687 case WREN:
688 s->write_enable = true;
689 break;
690
691 case RDSR:
692 s->data[0] = (!!s->write_enable) << 1;
693 s->pos = 0;
694 s->len = 1;
695 s->state = STATE_READING_DATA;
696 break;
697
9fbaa364
MK		 698 case READ_FSR:
699 s->data[0] = FSR_FLASH_READY;
700 if (s->four_bytes_address_mode) {
701 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED;
702 }
703 s->pos = 0;
704 s->len = 1;
705 s->state = STATE_READING_DATA;
706 break;
707
82a24990 708 case JEDEC_READ:
28097d02 709 DB_PRINT_L(0, "populated jedec code\n");
82a24990
PC		 710 s->data[0] = (s->pi->jedec >> 16) & 0xff;
711 s->data[1] = (s->pi->jedec >> 8) & 0xff;
712 s->data[2] = s->pi->jedec & 0xff;
713 if (s->pi->ext_jedec) {
714 s->data[3] = (s->pi->ext_jedec >> 8) & 0xff;
715 s->data[4] = s->pi->ext_jedec & 0xff;
716 s->len = 5;
717 } else {
718 s->len = 3;
719 }
720 s->pos = 0;
721 s->state = STATE_READING_DATA;
722 break;
723
724 case BULK_ERASE:
725 if (s->write_enable) {
28097d02 726 DB_PRINT_L(0, "chip erase\n");
82a24990
PC		 727 flash_erase(s, 0, BULK_ERASE);
728 } else {
e9711b4d
PC		 729 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
730 "protect!\n");
82a24990
PC		 731 }
732 break;
733 case NOP:
734 break;
c0f3f675
MK		 735 case EN_4BYTE_ADDR:
736 s->four_bytes_address_mode = true;
737 break;
738 case EX_4BYTE_ADDR:
739 s->four_bytes_address_mode = false;
740 break;
d8a29a7a
MK		 741 case EXTEND_ADDR_READ:
742 s->data[0] = s->ear;
743 s->pos = 0;
744 s->len = 1;
745 s->state = STATE_READING_DATA;
746 break;
747 case EXTEND_ADDR_WRITE:
748 if (s->write_enable) {
749 s->needed_bytes = 1;
750 s->pos = 0;
751 s->len = 0;
752 s->state = STATE_COLLECTING_DATA;
753 }
754 break;
cb475951
MK		 755 case RNVCR:
756 s->data[0] = s->nonvolatile_cfg & 0xFF;
757 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF;
758 s->pos = 0;
759 s->len = 2;
760 s->state = STATE_READING_DATA;
761 break;
762 case WNVCR:
763 if (s->write_enable) {
764 s->needed_bytes = 2;
765 s->pos = 0;
766 s->len = 0;
767 s->state = STATE_COLLECTING_DATA;
768 }
769 break;
770 case RVCR:
771 s->data[0] = s->volatile_cfg & 0xFF;
772 s->pos = 0;
773 s->len = 1;
774 s->state = STATE_READING_DATA;
775 break;
776 case WVCR:
777 if (s->write_enable) {
778 s->needed_bytes = 1;
779 s->pos = 0;
780 s->len = 0;
781 s->state = STATE_COLLECTING_DATA;
782 }
783 break;
784 case REVCR:
785 s->data[0] = s->enh_volatile_cfg & 0xFF;
786 s->pos = 0;
787 s->len = 1;
788 s->state = STATE_READING_DATA;
789 break;
790 case WEVCR:
791 if (s->write_enable) {
792 s->needed_bytes = 1;
793 s->pos = 0;
794 s->len = 0;
795 s->state = STATE_COLLECTING_DATA;
796 }
797 break;
187c2636
MK		 798 case RESET_ENABLE:
799 s->reset_enable = true;
800 break;
801 case RESET_MEMORY:
802 if (s->reset_enable) {
803 reset_memory(s);
804 }
805 break;
82a24990 806 default:
e9711b4d 807 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
82a24990
PC		 808 break;
809 }
810}
811
812static int m25p80_cs(SSISlave *ss, bool select)
813{
cdccf7d7 814 Flash *s = M25P80(ss);
82a24990
PC		 815
816 if (select) {
817 s->len = 0;
818 s->pos = 0;
819 s->state = STATE_IDLE;
820 flash_sync_dirty(s, -1);
821 }
822
28097d02 823 DB_PRINT_L(0, "%sselect\n", select ? "de" : "");
82a24990
PC		 824
825 return 0;
826}
827
828static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
829{
cdccf7d7 830 Flash *s = M25P80(ss);
82a24990
PC		 831 uint32_t r = 0;
832
833 switch (s->state) {
834
835 case STATE_PAGE_PROGRAM:
28097d02
PC		 836 DB_PRINT_L(1, "page program cur_addr=%#" PRIx64 " data=%" PRIx8 "\n",
837 s->cur_addr, (uint8_t)tx);
82a24990
PC		 838 flash_write8(s, s->cur_addr, (uint8_t)tx);
839 s->cur_addr++;
840 break;
841
842 case STATE_READ:
843 r = s->storage[s->cur_addr];
28097d02
PC		 844 DB_PRINT_L(1, "READ 0x%" PRIx64 "=%" PRIx8 "\n", s->cur_addr,
845 (uint8_t)r);
82a24990
PC		 846 s->cur_addr = (s->cur_addr + 1) % s->size;
847 break;
848
849 case STATE_COLLECTING_DATA:
850 s->data[s->len] = (uint8_t)tx;
851 s->len++;
852
853 if (s->len == s->needed_bytes) {
854 complete_collecting_data(s);
855 }
856 break;
857
858 case STATE_READING_DATA:
859 r = s->data[s->pos];
860 s->pos++;
861 if (s->pos == s->len) {
862 s->pos = 0;
863 s->state = STATE_IDLE;
864 }
865 break;
866
867 default:
868 case STATE_IDLE:
869 decode_new_cmd(s, (uint8_t)tx);
870 break;
871 }
872
873 return r;
874}
875
876static int m25p80_init(SSISlave *ss)
877{
878 DriveInfo *dinfo;
cdccf7d7 879 Flash *s = M25P80(ss);
a7fd6915 880 M25P80Class *mc = M25P80_GET_CLASS(s);
82a24990 881
a7fd6915 882 s->pi = mc->pi;
82a24990
PC		 883
884 s->size = s->pi->sector_size * s->pi->n_sectors;
885 s->dirty_page = -1;
82a24990 886
af9e40aa 887 /* FIXME use a qdev drive property instead of drive_get_next() */
82a24990
PC		 888 dinfo = drive_get_next(IF_MTD);
889
fa1d36df 890 if (dinfo) {
28097d02 891 DB_PRINT_L(0, "Binding to IF_MTD drive\n");
4be74634 892 s->blk = blk_by_legacy_dinfo(dinfo);
d07063e4 893 blk_attach_dev_nofail(s->blk, s);
4f8a066b 894
c485cf9c
SH		 895 s->storage = blk_blockalign(s->blk, s->size);
896
82a24990 897 /* FIXME: Move to late init */
4be74634
MA		 898 if (blk_read(s->blk, 0, s->storage,
899 DIV_ROUND_UP(s->size, BDRV_SECTOR_SIZE))) {
82a24990
PC		 900 fprintf(stderr, "Failed to initialize SPI flash!\n");
901 return 1;
902 }
903 } else {
095b9c48 904 DB_PRINT_L(0, "No BDRV - binding to RAM\n");
c485cf9c 905 s->storage = blk_blockalign(NULL, s->size);
82a24990
PC		 906 memset(s->storage, 0xFF, s->size);
907 }
908
909 return 0;
910}
911
187c2636
MK		 912static void m25p80_reset(DeviceState *d)
913{
914 Flash *s = M25P80(d);
915
916 reset_memory(s);
917}
918
82a24990
PC		 919static void m25p80_pre_save(void *opaque)
920{
921 flash_sync_dirty((Flash *)opaque, -1);
922}
923
cb475951
MK		 924static Property m25p80_properties[] = {
925 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF),
926 DEFINE_PROP_END_OF_LIST(),
927};
928
82a24990
PC		 929static const VMStateDescription vmstate_m25p80 = {
930 .name = "xilinx_spi",
187c2636 931 .version_id = 2,
82a24990 932 .minimum_version_id = 1,
82a24990
PC		 933 .pre_save = m25p80_pre_save,
934 .fields = (VMStateField[]) {
935 VMSTATE_UINT8(state, Flash),
936 VMSTATE_UINT8_ARRAY(data, Flash, 16),
937 VMSTATE_UINT32(len, Flash),
938 VMSTATE_UINT32(pos, Flash),
939 VMSTATE_UINT8(needed_bytes, Flash),
940 VMSTATE_UINT8(cmd_in_progress, Flash),
941 VMSTATE_UINT64(cur_addr, Flash),
942 VMSTATE_BOOL(write_enable, Flash),
187c2636 943 VMSTATE_BOOL_V(reset_enable, Flash, 2),
d8a29a7a 944 VMSTATE_UINT8_V(ear, Flash, 2),
c0f3f675 945 VMSTATE_BOOL_V(four_bytes_address_mode, Flash, 2),
cb475951
MK		 946 VMSTATE_UINT32_V(nonvolatile_cfg, Flash, 2),
947 VMSTATE_UINT32_V(volatile_cfg, Flash, 2),
948 VMSTATE_UINT32_V(enh_volatile_cfg, Flash, 2),
82a24990
PC		 949 VMSTATE_END_OF_LIST()
950 }
951};
952
82a24990
PC		 953static void m25p80_class_init(ObjectClass *klass, void *data)
954{
955 DeviceClass *dc = DEVICE_CLASS(klass);
956 SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
a7fd6915 957 M25P80Class *mc = M25P80_CLASS(klass);
82a24990
PC		 958
959 k->init = m25p80_init;
960 k->transfer = m25p80_transfer8;
961 k->set_cs = m25p80_cs;
962 k->cs_polarity = SSI_CS_LOW;
82a24990 963 dc->vmsd = &vmstate_m25p80;
cb475951 964 dc->props = m25p80_properties;
187c2636 965 dc->reset = m25p80_reset;
a7fd6915 966 mc->pi = data;
82a24990
PC		 967}
968
969static const TypeInfo m25p80_info = {
a7fd6915 970 .name = TYPE_M25P80,
82a24990
PC		 971 .parent = TYPE_SSI_SLAVE,
972 .instance_size = sizeof(Flash),
a7fd6915
PC		 973 .class_size = sizeof(M25P80Class),
974 .abstract = true,
82a24990
PC		 975};
976
977static void m25p80_register_types(void)
978{
a7fd6915
PC		 979 int i;
980
82a24990 981 type_register_static(&m25p80_info);
a7fd6915
PC		 982 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) {
983 TypeInfo ti = {
984 .name = known_devices[i].part_name,
985 .parent = TYPE_M25P80,
986 .class_init = m25p80_class_init,
987 .class_data = (void *)&known_devices[i],
988 };
989 type_register(&ti);
990 }
82a24990
PC		 991}
992
993type_init(m25p80_register_types)
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