]> git.proxmox.com Git - mirror_qemu.git/blame - hw/block/m25p80.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
block: m25p80: n25q256a/n25q512a models
[mirror_qemu.git] / hw / block / m25p80.c
CommitLineData
82a24990
PC		 1/*
2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
3 * set. Known devices table current as of Jun/2012 and taken from linux.
4 * See drivers/mtd/devices/m25p80.c.
5 *
6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Copyright (C) 2012 PetaLogix
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 or
13 * (at your option) a later version of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 */
23
80c71a24 24#include "qemu/osdep.h"
83c9f4ca 25#include "hw/hw.h"
fa1d36df 26#include "sysemu/block-backend.h"
9c17d615 27#include "sysemu/blockdev.h"
8fd06719 28#include "hw/ssi/ssi.h"
cb475951 29#include "qemu/bitops.h"
82a24990 30
28097d02
PC		 31#ifndef M25P80_ERR_DEBUG
32#define M25P80_ERR_DEBUG 0
82a24990
PC		 33#endif
34
28097d02
PC		 35#define DB_PRINT_L(level, ...) do { \
36 if (M25P80_ERR_DEBUG > (level)) { \
37 fprintf(stderr, ": %s: ", __func__); \
38 fprintf(stderr, ## __VA_ARGS__); \
39 } \
40} while (0);
41
82a24990
PC		 42/* Fields for FlashPartInfo->flags */
43
44/* erase capabilities */
45#define ER_4K 1
46#define ER_32K 2
47/* set to allow the page program command to write 0s back to 1. Useful for
48 * modelling EEPROM with SPI flash command set
49 */
50#define WR_1 0x100
51
d8a29a7a
MK		 52/* 16 MiB max in 3 byte address mode */
53#define MAX_3BYTES_SIZE 0x1000000
54
82a24990
PC		 55typedef struct FlashPartInfo {
56 const char *part_name;
57 /* jedec code. (jedec >> 16) & 0xff is the 1st byte, >> 8 the 2nd etc */
58 uint32_t jedec;
59 /* extended jedec code */
60 uint16_t ext_jedec;
61 /* there is confusion between manufacturers as to what a sector is. In this
62 * device model, a "sector" is the size that is erased by the ERASE_SECTOR
63 * command (opcode 0xd8).
64 */
65 uint32_t sector_size;
66 uint32_t n_sectors;
67 uint32_t page_size;
76e87269 68 uint16_t flags;
82a24990
PC		 69} FlashPartInfo;
70
71/* adapted from linux */
72
73#define INFO(_part_name, _jedec, _ext_jedec, _sector_size, _n_sectors, _flags)\
74 .part_name = (_part_name),\
75 .jedec = (_jedec),\
76 .ext_jedec = (_ext_jedec),\
77 .sector_size = (_sector_size),\
78 .n_sectors = (_n_sectors),\
79 .page_size = 256,\
80 .flags = (_flags),\
81
419336a9
PC		 82#define JEDEC_NUMONYX 0x20
83#define JEDEC_WINBOND 0xEF
84#define JEDEC_SPANSION 0x01
85
cb475951
MK		 86/* Numonyx (Micron) Configuration register macros */
87#define VCFG_DUMMY 0x1
88#define VCFG_WRAP_SEQUENTIAL 0x2
89#define NVCFG_XIP_MODE_DISABLED (7 << 9)
90#define NVCFG_XIP_MODE_MASK (7 << 9)
91#define VCFG_XIP_MODE_ENABLED (1 << 3)
92#define CFG_DUMMY_CLK_LEN 4
93#define NVCFG_DUMMY_CLK_POS 12
94#define VCFG_DUMMY_CLK_POS 4
95#define EVCFG_OUT_DRIVER_STRENGHT_DEF 7
96#define EVCFG_VPP_ACCELERATOR (1 << 3)
97#define EVCFG_RESET_HOLD_ENABLED (1 << 4)
98#define NVCFG_DUAL_IO_MASK (1 << 2)
99#define EVCFG_DUAL_IO_ENABLED (1 << 6)
100#define NVCFG_QUAD_IO_MASK (1 << 3)
101#define EVCFG_QUAD_IO_ENABLED (1 << 7)
102#define NVCFG_4BYTE_ADDR_MASK (1 << 0)
103#define NVCFG_LOWER_SEGMENT_MASK (1 << 1)
104#define CFG_UPPER_128MB_SEG_ENABLED 0x3
105
9fbaa364
MK		 106/* Numonyx (Micron) Flag Status Register macros */
107#define FSR_4BYTE_ADDR_MODE_ENABLED 0x1
108#define FSR_FLASH_READY (1 << 7)
109
82a24990
PC		 110static const FlashPartInfo known_devices[] = {
111 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
112 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) },
113 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) },
114
115 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) },
116 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) },
117 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) },
118
119 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) },
120 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) },
121 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) },
122 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) },
123
3e758c1d
EM		 124 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) },
125
82a24990
PC		 126 /* EON -- en25xxx */
127 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) },
128 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) },
129 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) },
130 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) },
3e758c1d
EM		 131 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) },
132
133 /* GigaDevice */
134 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) },
135 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) },
82a24990
PC		 136
137 /* Intel/Numonyx -- xxxs33b */
138 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) },
139 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) },
140 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) },
3e758c1d 141 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) },
82a24990
PC		 142
143 /* Macronix */
3e758c1d 144 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
82a24990
PC		 145 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) },
146 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) },
147 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) },
148 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) },
149 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) },
150 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) },
151 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },
152 { INFO("mx25l25635e", 0xc22019, 0, 64 << 10, 512, 0) },
153 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },
154
3e758c1d 155 /* Micron */
f5aac8e0
EM		 156 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) },
157 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) },
158 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) },
159 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) },
160 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) },
161 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) },
162 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) },
163 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
3e758c1d 164
82a24990
PC		 165 /* Spansion -- single (large) sector size only, at least
166 * for the chips listed here (without boot sectors).
167 */
82a24990 168 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) },
3e758c1d 169 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) },
82a24990
PC		 170 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) },
171 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) },
172 { INFO("s25fl512s", 0x010220, 0x4d00, 256 << 10, 256, 0) },
173 { INFO("s70fl01gs", 0x010221, 0x4d00, 256 << 10, 256, 0) },
174 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) },
175 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) },
176 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) },
177 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) },
3e758c1d
EM		 178 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) },
179 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) },
180 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) },
181 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) },
182 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) },
82a24990
PC		 183 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) },
184 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) },
185
186 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
187 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) },
188 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) },
189 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) },
190 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) },
191 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) },
192 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) },
193 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) },
194 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) },
d857c4c0 195 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) },
82a24990
PC		 196
197 /* ST Microelectronics -- newer production may have feature updates */
198 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) },
199 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) },
200 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) },
201 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) },
202 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) },
203 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) },
204 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) },
205 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) },
206 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) },
3e758c1d 207 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) },
82a24990
PC		 208
209 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) },
210 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) },
211 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) },
212
3e758c1d 213 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) },
82a24990
PC		 214 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) },
215 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) },
216
217 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) },
218 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) },
219 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) },
220 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) },
221
222 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
223 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) },
224 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) },
225 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) },
226 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) },
227 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) },
228 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) },
229 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) },
3e758c1d 230 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) },
82a24990
PC		 231 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) },
232 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) },
3e758c1d
EM		 233 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) },
234 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) },
235 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) },
82a24990 236
82a24990 237 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) },
d31912bd
MK		 238 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
239 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
82a24990
PC		 240};
241
242typedef enum {
243 NOP = 0,
03ec2f83 244 WRSR = 0x1,
82a24990
PC		 245 WRDI = 0x4,
246 RDSR = 0x5,
247 WREN = 0x6,
419336a9
PC		 248 JEDEC_READ = 0x9f,
249 BULK_ERASE = 0xc7,
9fbaa364 250 READ_FSR = 0x70,
419336a9 251
63e47f6f
MK		 252 READ = 0x03,
253 READ4 = 0x13,
254 FAST_READ = 0x0b,
255 FAST_READ4 = 0x0c,
419336a9 256 DOR = 0x3b,
63e47f6f 257 DOR4 = 0x3c,
419336a9 258 QOR = 0x6b,
63e47f6f 259 QOR4 = 0x6c,
419336a9 260 DIOR = 0xbb,
63e47f6f 261 DIOR4 = 0xbc,
419336a9 262 QIOR = 0xeb,
63e47f6f 263 QIOR4 = 0xec,
419336a9 264
63e47f6f
MK		 265 PP = 0x02,
266 PP4 = 0x12,
419336a9
PC		 267 DPP = 0xa2,
268 QPP = 0x32,
269
82a24990 270 ERASE_4K = 0x20,
63e47f6f 271 ERASE4_4K = 0x21,
82a24990
PC		 272 ERASE_32K = 0x52,
273 ERASE_SECTOR = 0xd8,
63e47f6f 274 ERASE4_SECTOR = 0xdc,
187c2636 275
c0f3f675
MK		 276 EN_4BYTE_ADDR = 0xB7,
277 EX_4BYTE_ADDR = 0xE9,
278
d8a29a7a
MK		 279 EXTEND_ADDR_READ = 0xC8,
280 EXTEND_ADDR_WRITE = 0xC5,
281
187c2636
MK		 282 RESET_ENABLE = 0x66,
283 RESET_MEMORY = 0x99,
cb475951
MK		 284
285 RNVCR = 0xB5,
286 WNVCR = 0xB1,
287
288 RVCR = 0x85,
289 WVCR = 0x81,
290
291 REVCR = 0x65,
292 WEVCR = 0x61,
82a24990
PC		 293} FlashCMD;
294
295typedef enum {
296 STATE_IDLE,
297 STATE_PAGE_PROGRAM,
298 STATE_READ,
299 STATE_COLLECTING_DATA,
300 STATE_READING_DATA,
301} CMDState;
302
303typedef struct Flash {
cdccf7d7
PC		 304 SSISlave parent_obj;
305
4be74634 306 BlockBackend *blk;
82a24990
PC		 307
308 uint8_t *storage;
309 uint32_t size;
310 int page_size;
311
312 uint8_t state;
313 uint8_t data[16];
314 uint32_t len;
315 uint32_t pos;
316 uint8_t needed_bytes;
317 uint8_t cmd_in_progress;
318 uint64_t cur_addr;
cb475951
MK		 319 uint32_t nonvolatile_cfg;
320 uint32_t volatile_cfg;
321 uint32_t enh_volatile_cfg;
82a24990 322 bool write_enable;
c0f3f675 323 bool four_bytes_address_mode;
187c2636 324 bool reset_enable;
d8a29a7a 325 uint8_t ear;
82a24990
PC		 326
327 int64_t dirty_page;
328
82a24990
PC		 329 const FlashPartInfo *pi;
330
331} Flash;
332
a7fd6915
PC		 333typedef struct M25P80Class {
334 SSISlaveClass parent_class;
335 FlashPartInfo *pi;
336} M25P80Class;
337
338#define TYPE_M25P80 "m25p80-generic"
339#define M25P80(obj) \
340 OBJECT_CHECK(Flash, (obj), TYPE_M25P80)
341#define M25P80_CLASS(klass) \
342 OBJECT_CLASS_CHECK(M25P80Class, (klass), TYPE_M25P80)
343#define M25P80_GET_CLASS(obj) \
344 OBJECT_GET_CLASS(M25P80Class, (obj), TYPE_M25P80)
345
4be74634 346static void blk_sync_complete(void *opaque, int ret)
82a24990
PC		 347{
348 /* do nothing. Masters do not directly interact with the backing store,
349 * only the working copy so no mutexing required.
350 */
351}
352
353static void flash_sync_page(Flash *s, int page)
354{
4be74634 355 int blk_sector, nb_sectors;
fc1084aa
PC		 356 QEMUIOVector iov;
357
4be74634 358 if (!s->blk || blk_is_read_only(s->blk)) {
fc1084aa 359 return;
82a24990 360 }
fc1084aa 361
4be74634 362 blk_sector = (page * s->pi->page_size) / BDRV_SECTOR_SIZE;
fc1084aa
PC		 363 nb_sectors = DIV_ROUND_UP(s->pi->page_size, BDRV_SECTOR_SIZE);
364 qemu_iovec_init(&iov, 1);
4be74634 365 qemu_iovec_add(&iov, s->storage + blk_sector * BDRV_SECTOR_SIZE,
fc1084aa 366 nb_sectors * BDRV_SECTOR_SIZE);
4be74634
MA		 367 blk_aio_writev(s->blk, blk_sector, &iov, nb_sectors, blk_sync_complete,
368 NULL);
82a24990
PC		 369}
370
371static inline void flash_sync_area(Flash *s, int64_t off, int64_t len)
372{
373 int64_t start, end, nb_sectors;
374 QEMUIOVector iov;
375
4be74634 376 if (!s->blk || blk_is_read_only(s->blk)) {
82a24990
PC		 377 return;
378 }
379
380 assert(!(len % BDRV_SECTOR_SIZE));
381 start = off / BDRV_SECTOR_SIZE;
382 end = (off + len) / BDRV_SECTOR_SIZE;
383 nb_sectors = end - start;
384 qemu_iovec_init(&iov, 1);
385 qemu_iovec_add(&iov, s->storage + (start * BDRV_SECTOR_SIZE),
386 nb_sectors * BDRV_SECTOR_SIZE);
4be74634 387 blk_aio_writev(s->blk, start, &iov, nb_sectors, blk_sync_complete, NULL);
82a24990
PC		 388}
389
390static void flash_erase(Flash *s, int offset, FlashCMD cmd)
391{
392 uint32_t len;
393 uint8_t capa_to_assert = 0;
394
395 switch (cmd) {
396 case ERASE_4K:
63e47f6f 397 case ERASE4_4K:
82a24990
PC		 398 len = 4 << 10;
399 capa_to_assert = ER_4K;
400 break;
401 case ERASE_32K:
402 len = 32 << 10;
403 capa_to_assert = ER_32K;
404 break;
405 case ERASE_SECTOR:
63e47f6f 406 case ERASE4_SECTOR:
82a24990
PC		 407 len = s->pi->sector_size;
408 break;
409 case BULK_ERASE:
410 len = s->size;
411 break;
412 default:
413 abort();
414 }
415
28097d02 416 DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len);
82a24990 417 if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
e9711b4d
PC		 418 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
419 " device\n", len);
82a24990
PC		 420 }
421
422 if (!s->write_enable) {
e9711b4d 423 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n");
82a24990
PC		 424 return;
425 }
426 memset(s->storage + offset, 0xff, len);
427 flash_sync_area(s, offset, len);
428}
429
430static inline void flash_sync_dirty(Flash *s, int64_t newpage)
431{
432 if (s->dirty_page >= 0 && s->dirty_page != newpage) {
433 flash_sync_page(s, s->dirty_page);
434 s->dirty_page = newpage;
435 }
436}
437
438static inline
439void flash_write8(Flash *s, uint64_t addr, uint8_t data)
440{
441 int64_t page = addr / s->pi->page_size;
442 uint8_t prev = s->storage[s->cur_addr];
443
444 if (!s->write_enable) {
e9711b4d 445 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
82a24990
PC		 446 }
447
448 if ((prev ^ data) & data) {
28097d02
PC		 449 DB_PRINT_L(1, "programming zero to one! addr=%" PRIx64 " %" PRIx8
450 " -> %" PRIx8 "\n", addr, prev, data);
82a24990
PC		 451 }
452
453 if (s->pi->flags & WR_1) {
454 s->storage[s->cur_addr] = data;
455 } else {
456 s->storage[s->cur_addr] &= data;
457 }
458
459 flash_sync_dirty(s, page);
460 s->dirty_page = page;
461}
462
c0f3f675
MK		 463static inline int get_addr_length(Flash *s)
464{
63e47f6f
MK		 465 switch (s->cmd_in_progress) {
466 case PP4:
467 case READ4:
468 case QIOR4:
469 case ERASE4_4K:
470 case ERASE4_SECTOR:
471 case FAST_READ4:
472 case DOR4:
473 case QOR4:
474 case DIOR4:
475 return 4;
476 default:
477 return s->four_bytes_address_mode ? 4 : 3;
478 }
c0f3f675
MK		 479}
480
82a24990
PC		 481static void complete_collecting_data(Flash *s)
482{
c0f3f675
MK		 483 int i;
484
485 s->cur_addr = 0;
486
487 for (i = 0; i < get_addr_length(s); ++i) {
488 s->cur_addr <<= 8;
489 s->cur_addr |= s->data[i];
490 }
491
492 if (get_addr_length(s) == 3) {
493 s->cur_addr += (s->ear & 0x3) * MAX_3BYTES_SIZE;
494 }
82a24990 495
a56d305a
PC		 496 s->state = STATE_IDLE;
497
82a24990 498 switch (s->cmd_in_progress) {
419336a9
PC		 499 case DPP:
500 case QPP:
82a24990 501 case PP:
63e47f6f 502 case PP4:
82a24990
PC		 503 s->state = STATE_PAGE_PROGRAM;
504 break;
505 case READ:
63e47f6f 506 case READ4:
82a24990 507 case FAST_READ:
63e47f6f 508 case FAST_READ4:
419336a9 509 case DOR:
63e47f6f 510 case DOR4:
419336a9 511 case QOR:
63e47f6f 512 case QOR4:
419336a9 513 case DIOR:
63e47f6f 514 case DIOR4:
419336a9 515 case QIOR:
63e47f6f 516 case QIOR4:
82a24990
PC		 517 s->state = STATE_READ;
518 break;
519 case ERASE_4K:
63e47f6f 520 case ERASE4_4K:
82a24990
PC		 521 case ERASE_32K:
522 case ERASE_SECTOR:
63e47f6f 523 case ERASE4_SECTOR:
82a24990
PC		 524 flash_erase(s, s->cur_addr, s->cmd_in_progress);
525 break;
03ec2f83
KJS		 526 case WRSR:
527 if (s->write_enable) {
528 s->write_enable = false;
529 }
530 break;
d8a29a7a
MK		 531 case EXTEND_ADDR_WRITE:
532 s->ear = s->data[0];
533 break;
cb475951
MK		 534 case WNVCR:
535 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8);
536 break;
537 case WVCR:
538 s->volatile_cfg = s->data[0];
539 break;
540 case WEVCR:
541 s->enh_volatile_cfg = s->data[0];
542 break;
82a24990
PC		 543 default:
544 break;
545 }
546}
547
187c2636
MK		 548static void reset_memory(Flash *s)
549{
550 s->cmd_in_progress = NOP;
551 s->cur_addr = 0;
d8a29a7a 552 s->ear = 0;
c0f3f675 553 s->four_bytes_address_mode = false;
187c2636
MK		 554 s->len = 0;
555 s->needed_bytes = 0;
556 s->pos = 0;
557 s->state = STATE_IDLE;
558 s->write_enable = false;
559 s->reset_enable = false;
560
cb475951
MK		 561 if (((s->pi->jedec >> 16) & 0xFF) == JEDEC_NUMONYX) {
562 s->volatile_cfg = 0;
563 s->volatile_cfg |= VCFG_DUMMY;
564 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL;
565 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK)
566 != NVCFG_XIP_MODE_DISABLED) {
567 s->volatile_cfg |= VCFG_XIP_MODE_ENABLED;
568 }
569 s->volatile_cfg |= deposit32(s->volatile_cfg,
570 VCFG_DUMMY_CLK_POS,
571 CFG_DUMMY_CLK_LEN,
572 extract32(s->nonvolatile_cfg,
573 NVCFG_DUMMY_CLK_POS,
574 CFG_DUMMY_CLK_LEN)
575 );
576
577 s->enh_volatile_cfg = 0;
578 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGHT_DEF;
579 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR;
580 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED;
581 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) {
582 s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED;
583 }
584 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) {
585 s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED;
586 }
587 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) {
588 s->four_bytes_address_mode = true;
589 }
590 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) {
591 s->ear = CFG_UPPER_128MB_SEG_ENABLED;
592 }
593 }
594
187c2636
MK		 595 DB_PRINT_L(0, "Reset done.\n");
596}
597
82a24990
PC		 598static void decode_new_cmd(Flash *s, uint32_t value)
599{
600 s->cmd_in_progress = value;
28097d02 601 DB_PRINT_L(0, "decoded new command:%x\n", value);
82a24990 602
187c2636
MK		 603 if (value != RESET_MEMORY) {
604 s->reset_enable = false;
605 }
606
82a24990
PC		 607 switch (value) {
608
609 case ERASE_4K:
63e47f6f 610 case ERASE4_4K:
82a24990
PC		 611 case ERASE_32K:
612 case ERASE_SECTOR:
63e47f6f 613 case ERASE4_SECTOR:
82a24990 614 case READ:
63e47f6f 615 case READ4:
419336a9
PC		 616 case DPP:
617 case QPP:
82a24990 618 case PP:
63e47f6f 619 case PP4:
c0f3f675 620 s->needed_bytes = get_addr_length(s);
82a24990
PC		 621 s->pos = 0;
622 s->len = 0;
623 s->state = STATE_COLLECTING_DATA;
624 break;
625
626 case FAST_READ:
63e47f6f 627 case FAST_READ4:
419336a9 628 case DOR:
63e47f6f 629 case DOR4:
419336a9 630 case QOR:
63e47f6f 631 case QOR4:
aeb83edb
MK		 632 s->needed_bytes = get_addr_length(s);
633 if (((s->pi->jedec >> 16) & 0xFF) == JEDEC_NUMONYX) {
634 /* Dummy cycles modeled with bytes writes instead of bits */
635 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
636 }
82a24990
PC		 637 s->pos = 0;
638 s->len = 0;
639 s->state = STATE_COLLECTING_DATA;
640 break;
641
419336a9 642 case DIOR:
63e47f6f 643 case DIOR4:
419336a9
PC		 644 switch ((s->pi->jedec >> 16) & 0xFF) {
645 case JEDEC_WINBOND:
646 case JEDEC_SPANSION:
647 s->needed_bytes = 4;
648 break;
419336a9 649 default:
aeb83edb
MK		 650 s->needed_bytes = get_addr_length(s);
651 /* Dummy cycles modeled with bytes writes instead of bits */
652 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
419336a9
PC		 653 }
654 s->pos = 0;
655 s->len = 0;
656 s->state = STATE_COLLECTING_DATA;
657 break;
658
659 case QIOR:
63e47f6f 660 case QIOR4:
419336a9
PC		 661 switch ((s->pi->jedec >> 16) & 0xFF) {
662 case JEDEC_WINBOND:
663 case JEDEC_SPANSION:
664 s->needed_bytes = 6;
665 break;
419336a9 666 default:
aeb83edb
MK		 667 s->needed_bytes = get_addr_length(s);
668 /* Dummy cycles modeled with bytes writes instead of bits */
669 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
419336a9
PC		 670 }
671 s->pos = 0;
672 s->len = 0;
673 s->state = STATE_COLLECTING_DATA;
674 break;
675
03ec2f83
KJS		 676 case WRSR:
677 if (s->write_enable) {
678 s->needed_bytes = 1;
679 s->pos = 0;
680 s->len = 0;
681 s->state = STATE_COLLECTING_DATA;
682 }
683 break;
684
82a24990
PC		 685 case WRDI:
686 s->write_enable = false;
687 break;
688 case WREN:
689 s->write_enable = true;
690 break;
691
692 case RDSR:
693 s->data[0] = (!!s->write_enable) << 1;
694 s->pos = 0;
695 s->len = 1;
696 s->state = STATE_READING_DATA;
697 break;
698
9fbaa364
MK		 699 case READ_FSR:
700 s->data[0] = FSR_FLASH_READY;
701 if (s->four_bytes_address_mode) {
702 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED;
703 }
704 s->pos = 0;
705 s->len = 1;
706 s->state = STATE_READING_DATA;
707 break;
708
82a24990 709 case JEDEC_READ:
28097d02 710 DB_PRINT_L(0, "populated jedec code\n");
82a24990
PC		 711 s->data[0] = (s->pi->jedec >> 16) & 0xff;
712 s->data[1] = (s->pi->jedec >> 8) & 0xff;
713 s->data[2] = s->pi->jedec & 0xff;
714 if (s->pi->ext_jedec) {
715 s->data[3] = (s->pi->ext_jedec >> 8) & 0xff;
716 s->data[4] = s->pi->ext_jedec & 0xff;
717 s->len = 5;
718 } else {
719 s->len = 3;
720 }
721 s->pos = 0;
722 s->state = STATE_READING_DATA;
723 break;
724
725 case BULK_ERASE:
726 if (s->write_enable) {
28097d02 727 DB_PRINT_L(0, "chip erase\n");
82a24990
PC		 728 flash_erase(s, 0, BULK_ERASE);
729 } else {
e9711b4d
PC		 730 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
731 "protect!\n");
82a24990
PC		 732 }
733 break;
734 case NOP:
735 break;
c0f3f675
MK		 736 case EN_4BYTE_ADDR:
737 s->four_bytes_address_mode = true;
738 break;
739 case EX_4BYTE_ADDR:
740 s->four_bytes_address_mode = false;
741 break;
d8a29a7a
MK		 742 case EXTEND_ADDR_READ:
743 s->data[0] = s->ear;
744 s->pos = 0;
745 s->len = 1;
746 s->state = STATE_READING_DATA;
747 break;
748 case EXTEND_ADDR_WRITE:
749 if (s->write_enable) {
750 s->needed_bytes = 1;
751 s->pos = 0;
752 s->len = 0;
753 s->state = STATE_COLLECTING_DATA;
754 }
755 break;
cb475951
MK		 756 case RNVCR:
757 s->data[0] = s->nonvolatile_cfg & 0xFF;
758 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF;
759 s->pos = 0;
760 s->len = 2;
761 s->state = STATE_READING_DATA;
762 break;
763 case WNVCR:
764 if (s->write_enable) {
765 s->needed_bytes = 2;
766 s->pos = 0;
767 s->len = 0;
768 s->state = STATE_COLLECTING_DATA;
769 }
770 break;
771 case RVCR:
772 s->data[0] = s->volatile_cfg & 0xFF;
773 s->pos = 0;
774 s->len = 1;
775 s->state = STATE_READING_DATA;
776 break;
777 case WVCR:
778 if (s->write_enable) {
779 s->needed_bytes = 1;
780 s->pos = 0;
781 s->len = 0;
782 s->state = STATE_COLLECTING_DATA;
783 }
784 break;
785 case REVCR:
786 s->data[0] = s->enh_volatile_cfg & 0xFF;
787 s->pos = 0;
788 s->len = 1;
789 s->state = STATE_READING_DATA;
790 break;
791 case WEVCR:
792 if (s->write_enable) {
793 s->needed_bytes = 1;
794 s->pos = 0;
795 s->len = 0;
796 s->state = STATE_COLLECTING_DATA;
797 }
798 break;
187c2636
MK		 799 case RESET_ENABLE:
800 s->reset_enable = true;
801 break;
802 case RESET_MEMORY:
803 if (s->reset_enable) {
804 reset_memory(s);
805 }
806 break;
82a24990 807 default:
e9711b4d 808 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
82a24990
PC		 809 break;
810 }
811}
812
813static int m25p80_cs(SSISlave *ss, bool select)
814{
cdccf7d7 815 Flash *s = M25P80(ss);
82a24990
PC		 816
817 if (select) {
818 s->len = 0;
819 s->pos = 0;
820 s->state = STATE_IDLE;
821 flash_sync_dirty(s, -1);
822 }
823
28097d02 824 DB_PRINT_L(0, "%sselect\n", select ? "de" : "");
82a24990
PC		 825
826 return 0;
827}
828
829static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
830{
cdccf7d7 831 Flash *s = M25P80(ss);
82a24990
PC		 832 uint32_t r = 0;
833
834 switch (s->state) {
835
836 case STATE_PAGE_PROGRAM:
28097d02
PC		 837 DB_PRINT_L(1, "page program cur_addr=%#" PRIx64 " data=%" PRIx8 "\n",
838 s->cur_addr, (uint8_t)tx);
82a24990
PC		 839 flash_write8(s, s->cur_addr, (uint8_t)tx);
840 s->cur_addr++;
841 break;
842
843 case STATE_READ:
844 r = s->storage[s->cur_addr];
28097d02
PC		 845 DB_PRINT_L(1, "READ 0x%" PRIx64 "=%" PRIx8 "\n", s->cur_addr,
846 (uint8_t)r);
82a24990
PC		 847 s->cur_addr = (s->cur_addr + 1) % s->size;
848 break;
849
850 case STATE_COLLECTING_DATA:
851 s->data[s->len] = (uint8_t)tx;
852 s->len++;
853
854 if (s->len == s->needed_bytes) {
855 complete_collecting_data(s);
856 }
857 break;
858
859 case STATE_READING_DATA:
860 r = s->data[s->pos];
861 s->pos++;
862 if (s->pos == s->len) {
863 s->pos = 0;
864 s->state = STATE_IDLE;
865 }
866 break;
867
868 default:
869 case STATE_IDLE:
870 decode_new_cmd(s, (uint8_t)tx);
871 break;
872 }
873
874 return r;
875}
876
877static int m25p80_init(SSISlave *ss)
878{
879 DriveInfo *dinfo;
cdccf7d7 880 Flash *s = M25P80(ss);
a7fd6915 881 M25P80Class *mc = M25P80_GET_CLASS(s);
82a24990 882
a7fd6915 883 s->pi = mc->pi;
82a24990
PC		 884
885 s->size = s->pi->sector_size * s->pi->n_sectors;
886 s->dirty_page = -1;
82a24990 887
af9e40aa 888 /* FIXME use a qdev drive property instead of drive_get_next() */
82a24990
PC		 889 dinfo = drive_get_next(IF_MTD);
890
fa1d36df 891 if (dinfo) {
28097d02 892 DB_PRINT_L(0, "Binding to IF_MTD drive\n");
4be74634 893 s->blk = blk_by_legacy_dinfo(dinfo);
d07063e4 894 blk_attach_dev_nofail(s->blk, s);
4f8a066b 895
c485cf9c
SH		 896 s->storage = blk_blockalign(s->blk, s->size);
897
82a24990 898 /* FIXME: Move to late init */
4be74634
MA		 899 if (blk_read(s->blk, 0, s->storage,
900 DIV_ROUND_UP(s->size, BDRV_SECTOR_SIZE))) {
82a24990
PC		 901 fprintf(stderr, "Failed to initialize SPI flash!\n");
902 return 1;
903 }
904 } else {
095b9c48 905 DB_PRINT_L(0, "No BDRV - binding to RAM\n");
c485cf9c 906 s->storage = blk_blockalign(NULL, s->size);
82a24990
PC		 907 memset(s->storage, 0xFF, s->size);
908 }
909
910 return 0;
911}
912
187c2636
MK		 913static void m25p80_reset(DeviceState *d)
914{
915 Flash *s = M25P80(d);
916
917 reset_memory(s);
918}
919
82a24990
PC		 920static void m25p80_pre_save(void *opaque)
921{
922 flash_sync_dirty((Flash *)opaque, -1);
923}
924
cb475951
MK		 925static Property m25p80_properties[] = {
926 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF),
927 DEFINE_PROP_END_OF_LIST(),
928};
929
82a24990
PC		 930static const VMStateDescription vmstate_m25p80 = {
931 .name = "xilinx_spi",
187c2636 932 .version_id = 2,
82a24990 933 .minimum_version_id = 1,
82a24990
PC		 934 .pre_save = m25p80_pre_save,
935 .fields = (VMStateField[]) {
936 VMSTATE_UINT8(state, Flash),
937 VMSTATE_UINT8_ARRAY(data, Flash, 16),
938 VMSTATE_UINT32(len, Flash),
939 VMSTATE_UINT32(pos, Flash),
940 VMSTATE_UINT8(needed_bytes, Flash),
941 VMSTATE_UINT8(cmd_in_progress, Flash),
942 VMSTATE_UINT64(cur_addr, Flash),
943 VMSTATE_BOOL(write_enable, Flash),
187c2636 944 VMSTATE_BOOL_V(reset_enable, Flash, 2),
d8a29a7a 945 VMSTATE_UINT8_V(ear, Flash, 2),
c0f3f675 946 VMSTATE_BOOL_V(four_bytes_address_mode, Flash, 2),
cb475951
MK		 947 VMSTATE_UINT32_V(nonvolatile_cfg, Flash, 2),
948 VMSTATE_UINT32_V(volatile_cfg, Flash, 2),
949 VMSTATE_UINT32_V(enh_volatile_cfg, Flash, 2),
82a24990
PC		 950 VMSTATE_END_OF_LIST()
951 }
952};
953
82a24990
PC		 954static void m25p80_class_init(ObjectClass *klass, void *data)
955{
956 DeviceClass *dc = DEVICE_CLASS(klass);
957 SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
a7fd6915 958 M25P80Class *mc = M25P80_CLASS(klass);
82a24990
PC		 959
960 k->init = m25p80_init;
961 k->transfer = m25p80_transfer8;
962 k->set_cs = m25p80_cs;
963 k->cs_polarity = SSI_CS_LOW;
82a24990 964 dc->vmsd = &vmstate_m25p80;
cb475951 965 dc->props = m25p80_properties;
187c2636 966 dc->reset = m25p80_reset;
a7fd6915 967 mc->pi = data;
82a24990
PC		 968}
969
970static const TypeInfo m25p80_info = {
a7fd6915 971 .name = TYPE_M25P80,
82a24990
PC		 972 .parent = TYPE_SSI_SLAVE,
973 .instance_size = sizeof(Flash),
a7fd6915
PC		 974 .class_size = sizeof(M25P80Class),
975 .abstract = true,
82a24990
PC		 976};
977
978static void m25p80_register_types(void)
979{
a7fd6915
PC		 980 int i;
981
82a24990 982 type_register_static(&m25p80_info);
a7fd6915
PC		 983 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) {
984 TypeInfo ti = {
985 .name = known_devices[i].part_name,
986 .parent = TYPE_M25P80,
987 .class_init = m25p80_class_init,
988 .class_data = (void *)&known_devices[i],
989 };
990 type_register(&ti);
991 }
82a24990
PC		 992}
993
994type_init(m25p80_register_types)
QEMU mirror