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7e7c5e4c AZ |
1 | /* |
2 | * OneNAND flash memories emulation. | |
3 | * | |
4 | * Copyright (C) 2008 Nokia Corporation | |
5 | * Written by Andrzej Zaborowski <andrew@openedhand.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 or | |
10 | * (at your option) version 3 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
fad6cb1a | 17 | * You should have received a copy of the GNU General Public License along |
8167ee88 | 18 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
7e7c5e4c AZ |
19 | */ |
20 | ||
80c71a24 | 21 | #include "qemu/osdep.h" |
da34e65c | 22 | #include "qapi/error.h" |
83c9f4ca | 23 | #include "hw/hw.h" |
0d09e41a | 24 | #include "hw/block/flash.h" |
83c9f4ca | 25 | #include "hw/irq.h" |
a27bd6c7 | 26 | #include "hw/qdev-properties.h" |
ce35e229 | 27 | #include "hw/qdev-properties-system.h" |
4be74634 | 28 | #include "sysemu/block-backend.h" |
022c62cb | 29 | #include "exec/memory.h" |
83c9f4ca | 30 | #include "hw/sysbus.h" |
d6454270 | 31 | #include "migration/vmstate.h" |
1de7afc9 | 32 | #include "qemu/error-report.h" |
9e6e9247 | 33 | #include "qemu/log.h" |
0b8fa32f | 34 | #include "qemu/module.h" |
db1015e9 | 35 | #include "qom/object.h" |
7e7c5e4c AZ |
36 | |
37 | /* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */ | |
d091b5b4 | 38 | #define PAGE_SHIFT 11 |
7e7c5e4c AZ |
39 | |
40 | /* Fixed */ | |
d091b5b4 | 41 | #define BLOCK_SHIFT (PAGE_SHIFT + 6) |
7e7c5e4c | 42 | |
af073cd9 | 43 | #define TYPE_ONE_NAND "onenand" |
8063396b | 44 | OBJECT_DECLARE_SIMPLE_TYPE(OneNANDState, ONE_NAND) |
af073cd9 | 45 | |
db1015e9 | 46 | struct OneNANDState { |
af073cd9 AF |
47 | SysBusDevice parent_obj; |
48 | ||
5923ba42 JR |
49 | struct { |
50 | uint16_t man; | |
51 | uint16_t dev; | |
52 | uint16_t ver; | |
53 | } id; | |
7e7c5e4c | 54 | int shift; |
a8170e5e | 55 | hwaddr base; |
7e7c5e4c AZ |
56 | qemu_irq intr; |
57 | qemu_irq rdy; | |
4be74634 MA |
58 | BlockBackend *blk; |
59 | BlockBackend *blk_cur; | |
7e7c5e4c AZ |
60 | uint8_t *image; |
61 | uint8_t *otp; | |
62 | uint8_t *current; | |
689a1921 AK |
63 | MemoryRegion ram; |
64 | MemoryRegion mapped_ram; | |
500954e3 | 65 | uint8_t current_direction; |
7e7c5e4c AZ |
66 | uint8_t *boot[2]; |
67 | uint8_t *data[2][2]; | |
689a1921 AK |
68 | MemoryRegion iomem; |
69 | MemoryRegion container; | |
7e7c5e4c AZ |
70 | int cycle; |
71 | int otpmode; | |
72 | ||
73 | uint16_t addr[8]; | |
74 | uint16_t unladdr[8]; | |
75 | int bufaddr; | |
76 | int count; | |
77 | uint16_t command; | |
78 | uint16_t config[2]; | |
79 | uint16_t status; | |
80 | uint16_t intstatus; | |
81 | uint16_t wpstatus; | |
82 | ||
bc24a225 | 83 | ECCState ecc; |
7e7c5e4c AZ |
84 | |
85 | int density_mask; | |
86 | int secs; | |
87 | int secs_cur; | |
88 | int blocks; | |
89 | uint8_t *blockwp; | |
db1015e9 | 90 | }; |
7e7c5e4c AZ |
91 | |
92 | enum { | |
93 | ONEN_BUF_BLOCK = 0, | |
94 | ONEN_BUF_BLOCK2 = 1, | |
95 | ONEN_BUF_DEST_BLOCK = 2, | |
96 | ONEN_BUF_DEST_PAGE = 3, | |
97 | ONEN_BUF_PAGE = 7, | |
98 | }; | |
99 | ||
100 | enum { | |
101 | ONEN_ERR_CMD = 1 << 10, | |
102 | ONEN_ERR_ERASE = 1 << 11, | |
103 | ONEN_ERR_PROG = 1 << 12, | |
104 | ONEN_ERR_LOAD = 1 << 13, | |
105 | }; | |
106 | ||
107 | enum { | |
108 | ONEN_INT_RESET = 1 << 4, | |
109 | ONEN_INT_ERASE = 1 << 5, | |
110 | ONEN_INT_PROG = 1 << 6, | |
111 | ONEN_INT_LOAD = 1 << 7, | |
112 | ONEN_INT = 1 << 15, | |
113 | }; | |
114 | ||
115 | enum { | |
116 | ONEN_LOCK_LOCKTIGHTEN = 1 << 0, | |
117 | ONEN_LOCK_LOCKED = 1 << 1, | |
118 | ONEN_LOCK_UNLOCKED = 1 << 2, | |
119 | }; | |
120 | ||
689a1921 AK |
121 | static void onenand_mem_setup(OneNANDState *s) |
122 | { | |
123 | /* XXX: We should use IO_MEM_ROMD but we broke it earlier... | |
124 | * Both 0x0000 ... 0x01ff and 0x8000 ... 0x800f can be used to | |
125 | * write boot commands. Also take note of the BWPS bit. */ | |
2d256e6f PB |
126 | memory_region_init(&s->container, OBJECT(s), "onenand", |
127 | 0x10000 << s->shift); | |
689a1921 | 128 | memory_region_add_subregion(&s->container, 0, &s->iomem); |
2d256e6f | 129 | memory_region_init_alias(&s->mapped_ram, OBJECT(s), "onenand-mapped-ram", |
689a1921 AK |
130 | &s->ram, 0x0200 << s->shift, |
131 | 0xbe00 << s->shift); | |
132 | memory_region_add_subregion_overlap(&s->container, | |
133 | 0x0200 << s->shift, | |
134 | &s->mapped_ram, | |
135 | 1); | |
136 | } | |
137 | ||
500954e3 | 138 | static void onenand_intr_update(OneNANDState *s) |
7e7c5e4c | 139 | { |
500954e3 | 140 | qemu_set_irq(s->intr, ((s->intstatus >> 15) ^ (~s->config[0] >> 6)) & 1); |
7e7c5e4c AZ |
141 | } |
142 | ||
44b1ff31 | 143 | static int onenand_pre_save(void *opaque) |
7e7c5e4c | 144 | { |
500954e3 JR |
145 | OneNANDState *s = opaque; |
146 | if (s->current == s->otp) { | |
147 | s->current_direction = 1; | |
148 | } else if (s->current == s->image) { | |
149 | s->current_direction = 2; | |
150 | } else { | |
151 | s->current_direction = 0; | |
152 | } | |
44b1ff31 DDAG |
153 | |
154 | return 0; | |
7e7c5e4c AZ |
155 | } |
156 | ||
500954e3 | 157 | static int onenand_post_load(void *opaque, int version_id) |
7e7c5e4c | 158 | { |
500954e3 JR |
159 | OneNANDState *s = opaque; |
160 | switch (s->current_direction) { | |
161 | case 0: | |
162 | break; | |
163 | case 1: | |
164 | s->current = s->otp; | |
165 | break; | |
166 | case 2: | |
167 | s->current = s->image; | |
168 | break; | |
169 | default: | |
170 | return -1; | |
171 | } | |
172 | onenand_intr_update(s); | |
173 | return 0; | |
7e7c5e4c AZ |
174 | } |
175 | ||
500954e3 JR |
176 | static const VMStateDescription vmstate_onenand = { |
177 | .name = "onenand", | |
178 | .version_id = 1, | |
179 | .minimum_version_id = 1, | |
500954e3 JR |
180 | .pre_save = onenand_pre_save, |
181 | .post_load = onenand_post_load, | |
7d5dc0a3 | 182 | .fields = (const VMStateField[]) { |
500954e3 JR |
183 | VMSTATE_UINT8(current_direction, OneNANDState), |
184 | VMSTATE_INT32(cycle, OneNANDState), | |
185 | VMSTATE_INT32(otpmode, OneNANDState), | |
186 | VMSTATE_UINT16_ARRAY(addr, OneNANDState, 8), | |
187 | VMSTATE_UINT16_ARRAY(unladdr, OneNANDState, 8), | |
188 | VMSTATE_INT32(bufaddr, OneNANDState), | |
189 | VMSTATE_INT32(count, OneNANDState), | |
190 | VMSTATE_UINT16(command, OneNANDState), | |
191 | VMSTATE_UINT16_ARRAY(config, OneNANDState, 2), | |
192 | VMSTATE_UINT16(status, OneNANDState), | |
193 | VMSTATE_UINT16(intstatus, OneNANDState), | |
194 | VMSTATE_UINT16(wpstatus, OneNANDState), | |
195 | VMSTATE_INT32(secs_cur, OneNANDState), | |
196 | VMSTATE_PARTIAL_VBUFFER(blockwp, OneNANDState, blocks), | |
197 | VMSTATE_UINT8(ecc.cp, OneNANDState), | |
198 | VMSTATE_UINT16_ARRAY(ecc.lp, OneNANDState, 2), | |
199 | VMSTATE_UINT16(ecc.count, OneNANDState), | |
b79269b7 IM |
200 | VMSTATE_BUFFER_POINTER_UNSAFE(otp, OneNANDState, 0, |
201 | ((64 + 2) << PAGE_SHIFT)), | |
500954e3 JR |
202 | VMSTATE_END_OF_LIST() |
203 | } | |
204 | }; | |
205 | ||
7e7c5e4c | 206 | /* Hot reset (Reset OneNAND command) or warm reset (RP pin low) */ |
bc24a225 | 207 | static void onenand_reset(OneNANDState *s, int cold) |
7e7c5e4c AZ |
208 | { |
209 | memset(&s->addr, 0, sizeof(s->addr)); | |
210 | s->command = 0; | |
211 | s->count = 1; | |
212 | s->bufaddr = 0; | |
213 | s->config[0] = 0x40c0; | |
214 | s->config[1] = 0x0000; | |
215 | onenand_intr_update(s); | |
216 | qemu_irq_raise(s->rdy); | |
217 | s->status = 0x0000; | |
218 | s->intstatus = cold ? 0x8080 : 0x8010; | |
219 | s->unladdr[0] = 0; | |
220 | s->unladdr[1] = 0; | |
221 | s->wpstatus = 0x0002; | |
222 | s->cycle = 0; | |
223 | s->otpmode = 0; | |
4be74634 | 224 | s->blk_cur = s->blk; |
7e7c5e4c AZ |
225 | s->current = s->image; |
226 | s->secs_cur = s->secs; | |
227 | ||
228 | if (cold) { | |
229 | /* Lock the whole flash */ | |
230 | memset(s->blockwp, ONEN_LOCK_LOCKED, s->blocks); | |
231 | ||
a9262f55 AF |
232 | if (s->blk_cur && blk_pread(s->blk_cur, 0, 8 << BDRV_SECTOR_BITS, |
233 | s->boot[0], 0) < 0) { | |
500954e3 JR |
234 | hw_error("%s: Loading the BootRAM failed.\n", __func__); |
235 | } | |
7e7c5e4c AZ |
236 | } |
237 | } | |
238 | ||
500954e3 JR |
239 | static void onenand_system_reset(DeviceState *dev) |
240 | { | |
af073cd9 AF |
241 | OneNANDState *s = ONE_NAND(dev); |
242 | ||
243 | onenand_reset(s, 1); | |
500954e3 JR |
244 | } |
245 | ||
bc24a225 | 246 | static inline int onenand_load_main(OneNANDState *s, int sec, int secn, |
7e7c5e4c AZ |
247 | void *dest) |
248 | { | |
441692dd EB |
249 | assert(UINT32_MAX >> BDRV_SECTOR_BITS > sec); |
250 | assert(UINT32_MAX >> BDRV_SECTOR_BITS > secn); | |
4be74634 | 251 | if (s->blk_cur) { |
a9262f55 AF |
252 | return blk_pread(s->blk_cur, sec << BDRV_SECTOR_BITS, |
253 | secn << BDRV_SECTOR_BITS, dest, 0) < 0; | |
4be74634 | 254 | } else if (sec + secn > s->secs_cur) { |
7e7c5e4c | 255 | return 1; |
4be74634 | 256 | } |
7e7c5e4c AZ |
257 | |
258 | memcpy(dest, s->current + (sec << 9), secn << 9); | |
259 | ||
260 | return 0; | |
261 | } | |
262 | ||
bc24a225 | 263 | static inline int onenand_prog_main(OneNANDState *s, int sec, int secn, |
7e7c5e4c AZ |
264 | void *src) |
265 | { | |
f1588dd2 JR |
266 | int result = 0; |
267 | ||
268 | if (secn > 0) { | |
441692dd EB |
269 | uint32_t size = secn << BDRV_SECTOR_BITS; |
270 | uint32_t offset = sec << BDRV_SECTOR_BITS; | |
271 | assert(UINT32_MAX >> BDRV_SECTOR_BITS > sec); | |
272 | assert(UINT32_MAX >> BDRV_SECTOR_BITS > secn); | |
7c00b9de | 273 | const uint8_t *sp = (const uint8_t *)src; |
f1588dd2 | 274 | uint8_t *dp = 0; |
4be74634 | 275 | if (s->blk_cur) { |
7267c094 | 276 | dp = g_malloc(size); |
a9262f55 | 277 | if (!dp || blk_pread(s->blk_cur, offset, size, dp, 0) < 0) { |
f1588dd2 JR |
278 | result = 1; |
279 | } | |
280 | } else { | |
281 | if (sec + secn > s->secs_cur) { | |
282 | result = 1; | |
283 | } else { | |
441692dd | 284 | dp = (uint8_t *)s->current + offset; |
f1588dd2 JR |
285 | } |
286 | } | |
287 | if (!result) { | |
288 | uint32_t i; | |
289 | for (i = 0; i < size; i++) { | |
290 | dp[i] &= sp[i]; | |
291 | } | |
4be74634 | 292 | if (s->blk_cur) { |
a9262f55 | 293 | result = blk_pwrite(s->blk_cur, offset, size, dp, 0) < 0; |
f1588dd2 JR |
294 | } |
295 | } | |
4be74634 | 296 | if (dp && s->blk_cur) { |
7267c094 | 297 | g_free(dp); |
f1588dd2 JR |
298 | } |
299 | } | |
7e7c5e4c | 300 | |
f1588dd2 | 301 | return result; |
7e7c5e4c AZ |
302 | } |
303 | ||
bc24a225 | 304 | static inline int onenand_load_spare(OneNANDState *s, int sec, int secn, |
7e7c5e4c AZ |
305 | void *dest) |
306 | { | |
307 | uint8_t buf[512]; | |
308 | ||
4be74634 | 309 | if (s->blk_cur) { |
441692dd | 310 | uint32_t offset = (s->secs_cur + (sec >> 5)) << BDRV_SECTOR_BITS; |
a9262f55 | 311 | if (blk_pread(s->blk_cur, offset, BDRV_SECTOR_SIZE, buf, 0) < 0) { |
7e7c5e4c | 312 | return 1; |
4be74634 | 313 | } |
7e7c5e4c | 314 | memcpy(dest, buf + ((sec & 31) << 4), secn << 4); |
4be74634 | 315 | } else if (sec + secn > s->secs_cur) { |
7e7c5e4c | 316 | return 1; |
4be74634 | 317 | } else { |
7e7c5e4c | 318 | memcpy(dest, s->current + (s->secs_cur << 9) + (sec << 4), secn << 4); |
4be74634 | 319 | } |
441692dd | 320 | |
7e7c5e4c AZ |
321 | return 0; |
322 | } | |
323 | ||
bc24a225 | 324 | static inline int onenand_prog_spare(OneNANDState *s, int sec, int secn, |
7e7c5e4c AZ |
325 | void *src) |
326 | { | |
f1588dd2 JR |
327 | int result = 0; |
328 | if (secn > 0) { | |
7c00b9de | 329 | const uint8_t *sp = (const uint8_t *)src; |
f1588dd2 | 330 | uint8_t *dp = 0, *dpp = 0; |
441692dd EB |
331 | uint32_t offset = (s->secs_cur + (sec >> 5)) << BDRV_SECTOR_BITS; |
332 | assert(UINT32_MAX >> BDRV_SECTOR_BITS > s->secs_cur + (sec >> 5)); | |
4be74634 | 333 | if (s->blk_cur) { |
7267c094 | 334 | dp = g_malloc(512); |
4be74634 | 335 | if (!dp |
a9262f55 | 336 | || blk_pread(s->blk_cur, offset, BDRV_SECTOR_SIZE, dp, 0) < 0) { |
f1588dd2 JR |
337 | result = 1; |
338 | } else { | |
339 | dpp = dp + ((sec & 31) << 4); | |
340 | } | |
341 | } else { | |
342 | if (sec + secn > s->secs_cur) { | |
343 | result = 1; | |
344 | } else { | |
345 | dpp = s->current + (s->secs_cur << 9) + (sec << 4); | |
346 | } | |
347 | } | |
348 | if (!result) { | |
349 | uint32_t i; | |
350 | for (i = 0; i < (secn << 4); i++) { | |
351 | dpp[i] &= sp[i]; | |
352 | } | |
4be74634 | 353 | if (s->blk_cur) { |
a9262f55 AF |
354 | result = blk_pwrite(s->blk_cur, offset, BDRV_SECTOR_SIZE, dp, |
355 | 0) < 0; | |
f1588dd2 JR |
356 | } |
357 | } | |
f7047c2d | 358 | g_free(dp); |
f1588dd2 JR |
359 | } |
360 | return result; | |
7e7c5e4c AZ |
361 | } |
362 | ||
bc24a225 | 363 | static inline int onenand_erase(OneNANDState *s, int sec, int num) |
7e7c5e4c | 364 | { |
f1588dd2 | 365 | uint8_t *blankbuf, *tmpbuf; |
6b0126f9 | 366 | |
7267c094 | 367 | blankbuf = g_malloc(512); |
7267c094 | 368 | tmpbuf = g_malloc(512); |
f1588dd2 JR |
369 | memset(blankbuf, 0xff, 512); |
370 | for (; num > 0; num--, sec++) { | |
4be74634 | 371 | if (s->blk_cur) { |
f1588dd2 | 372 | int erasesec = s->secs_cur + (sec >> 5); |
a9262f55 AF |
373 | if (blk_pwrite(s->blk_cur, sec << BDRV_SECTOR_BITS, |
374 | BDRV_SECTOR_SIZE, blankbuf, 0) < 0) { | |
f1588dd2 JR |
375 | goto fail; |
376 | } | |
a9262f55 AF |
377 | if (blk_pread(s->blk_cur, erasesec << BDRV_SECTOR_BITS, |
378 | BDRV_SECTOR_SIZE, tmpbuf, 0) < 0) { | |
f1588dd2 JR |
379 | goto fail; |
380 | } | |
381 | memcpy(tmpbuf + ((sec & 31) << 4), blankbuf, 1 << 4); | |
a9262f55 AF |
382 | if (blk_pwrite(s->blk_cur, erasesec << BDRV_SECTOR_BITS, |
383 | BDRV_SECTOR_SIZE, tmpbuf, 0) < 0) { | |
f1588dd2 JR |
384 | goto fail; |
385 | } | |
386 | } else { | |
387 | if (sec + 1 > s->secs_cur) { | |
388 | goto fail; | |
389 | } | |
390 | memcpy(s->current + (sec << 9), blankbuf, 512); | |
391 | memcpy(s->current + (s->secs_cur << 9) + (sec << 4), | |
392 | blankbuf, 1 << 4); | |
393 | } | |
7e7c5e4c AZ |
394 | } |
395 | ||
7267c094 AL |
396 | g_free(tmpbuf); |
397 | g_free(blankbuf); | |
7e7c5e4c | 398 | return 0; |
f1588dd2 JR |
399 | |
400 | fail: | |
7267c094 AL |
401 | g_free(tmpbuf); |
402 | g_free(blankbuf); | |
f1588dd2 | 403 | return 1; |
7e7c5e4c AZ |
404 | } |
405 | ||
82866965 | 406 | static void onenand_command(OneNANDState *s) |
7e7c5e4c AZ |
407 | { |
408 | int b; | |
409 | int sec; | |
410 | void *buf; | |
d091b5b4 YF |
411 | #define SETADDR(block, page) \ |
412 | sec = (s->addr[page] & 3) + \ | |
413 | ((((s->addr[page] >> 2) & 0x3f) + \ | |
414 | (((s->addr[block] & 0xfff) | \ | |
415 | (s->addr[block] >> 15 ? s->density_mask : 0)) \ | |
416 | << 6)) \ | |
417 | << (PAGE_SHIFT - 9)); | |
418 | #define SETBUF_M() \ | |
419 | buf = (s->bufaddr & 8) ? s->data[(s->bufaddr >> 2) & 1][0] : s->boot[0]; \ | |
7e7c5e4c | 420 | buf += (s->bufaddr & 3) << 9; |
d091b5b4 YF |
421 | #define SETBUF_S() \ |
422 | buf = (s->bufaddr & 8) ? \ | |
423 | s->data[(s->bufaddr >> 2) & 1][1] : s->boot[1]; \ | |
7e7c5e4c AZ |
424 | buf += (s->bufaddr & 3) << 4; |
425 | ||
82866965 | 426 | switch (s->command) { |
d091b5b4 | 427 | case 0x00: /* Load single/multiple sector data unit into buffer */ |
7e7c5e4c AZ |
428 | SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
429 | ||
430 | SETBUF_M() | |
431 | if (onenand_load_main(s, sec, s->count, buf)) | |
432 | s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD; | |
433 | ||
434 | #if 0 | |
435 | SETBUF_S() | |
436 | if (onenand_load_spare(s, sec, s->count, buf)) | |
437 | s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD; | |
438 | #endif | |
439 | ||
440 | /* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages) | |
441 | * or if (s->bufaddr & 1) + s->count was > 2 (1k-pages) | |
442 | * then we need two split the read/write into two chunks. | |
443 | */ | |
444 | s->intstatus |= ONEN_INT | ONEN_INT_LOAD; | |
445 | break; | |
d091b5b4 | 446 | case 0x13: /* Load single/multiple spare sector into buffer */ |
7e7c5e4c AZ |
447 | SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
448 | ||
449 | SETBUF_S() | |
450 | if (onenand_load_spare(s, sec, s->count, buf)) | |
451 | s->status |= ONEN_ERR_CMD | ONEN_ERR_LOAD; | |
452 | ||
453 | /* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages) | |
454 | * or if (s->bufaddr & 1) + s->count was > 2 (1k-pages) | |
455 | * then we need two split the read/write into two chunks. | |
456 | */ | |
457 | s->intstatus |= ONEN_INT | ONEN_INT_LOAD; | |
458 | break; | |
d091b5b4 | 459 | case 0x80: /* Program single/multiple sector data unit from buffer */ |
7e7c5e4c AZ |
460 | SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
461 | ||
462 | SETBUF_M() | |
463 | if (onenand_prog_main(s, sec, s->count, buf)) | |
464 | s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; | |
465 | ||
466 | #if 0 | |
467 | SETBUF_S() | |
468 | if (onenand_prog_spare(s, sec, s->count, buf)) | |
469 | s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; | |
470 | #endif | |
471 | ||
472 | /* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages) | |
473 | * or if (s->bufaddr & 1) + s->count was > 2 (1k-pages) | |
474 | * then we need two split the read/write into two chunks. | |
475 | */ | |
476 | s->intstatus |= ONEN_INT | ONEN_INT_PROG; | |
477 | break; | |
d091b5b4 | 478 | case 0x1a: /* Program single/multiple spare area sector from buffer */ |
7e7c5e4c AZ |
479 | SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) |
480 | ||
481 | SETBUF_S() | |
482 | if (onenand_prog_spare(s, sec, s->count, buf)) | |
483 | s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; | |
484 | ||
485 | /* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages) | |
486 | * or if (s->bufaddr & 1) + s->count was > 2 (1k-pages) | |
487 | * then we need two split the read/write into two chunks. | |
488 | */ | |
489 | s->intstatus |= ONEN_INT | ONEN_INT_PROG; | |
490 | break; | |
d091b5b4 | 491 | case 0x1b: /* Copy-back program */ |
7e7c5e4c AZ |
492 | SETBUF_S() |
493 | ||
494 | SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) | |
495 | if (onenand_load_main(s, sec, s->count, buf)) | |
496 | s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; | |
497 | ||
498 | SETADDR(ONEN_BUF_DEST_BLOCK, ONEN_BUF_DEST_PAGE) | |
499 | if (onenand_prog_main(s, sec, s->count, buf)) | |
500 | s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG; | |
501 | ||
502 | /* TODO: spare areas */ | |
503 | ||
504 | s->intstatus |= ONEN_INT | ONEN_INT_PROG; | |
505 | break; | |
506 | ||
d091b5b4 | 507 | case 0x23: /* Unlock NAND array block(s) */ |
7e7c5e4c AZ |
508 | s->intstatus |= ONEN_INT; |
509 | ||
510 | /* XXX the previous (?) area should be locked automatically */ | |
511 | for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) { | |
512 | if (b >= s->blocks) { | |
513 | s->status |= ONEN_ERR_CMD; | |
514 | break; | |
515 | } | |
516 | if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN) | |
517 | break; | |
518 | ||
519 | s->wpstatus = s->blockwp[b] = ONEN_LOCK_UNLOCKED; | |
520 | } | |
521 | break; | |
d091b5b4 | 522 | case 0x27: /* Unlock All NAND array blocks */ |
89588a4b AZ |
523 | s->intstatus |= ONEN_INT; |
524 | ||
525 | for (b = 0; b < s->blocks; b ++) { | |
89588a4b AZ |
526 | if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN) |
527 | break; | |
528 | ||
529 | s->wpstatus = s->blockwp[b] = ONEN_LOCK_UNLOCKED; | |
530 | } | |
531 | break; | |
532 | ||
d091b5b4 | 533 | case 0x2a: /* Lock NAND array block(s) */ |
7e7c5e4c AZ |
534 | s->intstatus |= ONEN_INT; |
535 | ||
536 | for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) { | |
537 | if (b >= s->blocks) { | |
538 | s->status |= ONEN_ERR_CMD; | |
539 | break; | |
540 | } | |
541 | if (s->blockwp[b] == ONEN_LOCK_LOCKTIGHTEN) | |
542 | break; | |
543 | ||
544 | s->wpstatus = s->blockwp[b] = ONEN_LOCK_LOCKED; | |
545 | } | |
546 | break; | |
d091b5b4 | 547 | case 0x2c: /* Lock-tight NAND array block(s) */ |
7e7c5e4c AZ |
548 | s->intstatus |= ONEN_INT; |
549 | ||
550 | for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) { | |
551 | if (b >= s->blocks) { | |
552 | s->status |= ONEN_ERR_CMD; | |
553 | break; | |
554 | } | |
555 | if (s->blockwp[b] == ONEN_LOCK_UNLOCKED) | |
556 | continue; | |
557 | ||
558 | s->wpstatus = s->blockwp[b] = ONEN_LOCK_LOCKTIGHTEN; | |
559 | } | |
560 | break; | |
561 | ||
d091b5b4 | 562 | case 0x71: /* Erase-Verify-Read */ |
7e7c5e4c AZ |
563 | s->intstatus |= ONEN_INT; |
564 | break; | |
d091b5b4 | 565 | case 0x95: /* Multi-block erase */ |
7e7c5e4c AZ |
566 | qemu_irq_pulse(s->intr); |
567 | /* Fall through. */ | |
d091b5b4 | 568 | case 0x94: /* Block erase */ |
7e7c5e4c AZ |
569 | sec = ((s->addr[ONEN_BUF_BLOCK] & 0xfff) | |
570 | (s->addr[ONEN_BUF_BLOCK] >> 15 ? s->density_mask : 0)) | |
571 | << (BLOCK_SHIFT - 9); | |
572 | if (onenand_erase(s, sec, 1 << (BLOCK_SHIFT - 9))) | |
573 | s->status |= ONEN_ERR_CMD | ONEN_ERR_ERASE; | |
574 | ||
575 | s->intstatus |= ONEN_INT | ONEN_INT_ERASE; | |
576 | break; | |
d091b5b4 | 577 | case 0xb0: /* Erase suspend */ |
7e7c5e4c | 578 | break; |
d091b5b4 | 579 | case 0x30: /* Erase resume */ |
7e7c5e4c AZ |
580 | s->intstatus |= ONEN_INT | ONEN_INT_ERASE; |
581 | break; | |
582 | ||
d091b5b4 | 583 | case 0xf0: /* Reset NAND Flash core */ |
7e7c5e4c AZ |
584 | onenand_reset(s, 0); |
585 | break; | |
d091b5b4 | 586 | case 0xf3: /* Reset OneNAND */ |
7e7c5e4c AZ |
587 | onenand_reset(s, 0); |
588 | break; | |
589 | ||
d091b5b4 | 590 | case 0x65: /* OTP Access */ |
7e7c5e4c | 591 | s->intstatus |= ONEN_INT; |
4be74634 | 592 | s->blk_cur = NULL; |
7e7c5e4c AZ |
593 | s->current = s->otp; |
594 | s->secs_cur = 1 << (BLOCK_SHIFT - 9); | |
595 | s->addr[ONEN_BUF_BLOCK] = 0; | |
596 | s->otpmode = 1; | |
597 | break; | |
598 | ||
599 | default: | |
600 | s->status |= ONEN_ERR_CMD; | |
601 | s->intstatus |= ONEN_INT; | |
9e6e9247 PM |
602 | qemu_log_mask(LOG_GUEST_ERROR, "unknown OneNAND command %x\n", |
603 | s->command); | |
7e7c5e4c AZ |
604 | } |
605 | ||
606 | onenand_intr_update(s); | |
607 | } | |
608 | ||
a8170e5e | 609 | static uint64_t onenand_read(void *opaque, hwaddr addr, |
689a1921 | 610 | unsigned size) |
7e7c5e4c | 611 | { |
bc24a225 | 612 | OneNANDState *s = (OneNANDState *) opaque; |
8da3ff18 | 613 | int offset = addr >> s->shift; |
7e7c5e4c AZ |
614 | |
615 | switch (offset) { | |
fcf5787c | 616 | case 0x0000 ... 0xbffe: |
8da3ff18 | 617 | return lduw_le_p(s->boot[0] + addr); |
7e7c5e4c | 618 | |
d091b5b4 | 619 | case 0xf000: /* Manufacturer ID */ |
5923ba42 | 620 | return s->id.man; |
d091b5b4 | 621 | case 0xf001: /* Device ID */ |
5923ba42 | 622 | return s->id.dev; |
d091b5b4 | 623 | case 0xf002: /* Version ID */ |
5923ba42 JR |
624 | return s->id.ver; |
625 | /* TODO: get the following values from a real chip! */ | |
d091b5b4 | 626 | case 0xf003: /* Data Buffer size */ |
7e7c5e4c | 627 | return 1 << PAGE_SHIFT; |
d091b5b4 | 628 | case 0xf004: /* Boot Buffer size */ |
7e7c5e4c | 629 | return 0x200; |
d091b5b4 | 630 | case 0xf005: /* Amount of buffers */ |
7e7c5e4c | 631 | return 1 | (2 << 8); |
d091b5b4 | 632 | case 0xf006: /* Technology */ |
7e7c5e4c AZ |
633 | return 0; |
634 | ||
d091b5b4 | 635 | case 0xf100 ... 0xf107: /* Start addresses */ |
7e7c5e4c AZ |
636 | return s->addr[offset - 0xf100]; |
637 | ||
d091b5b4 | 638 | case 0xf200: /* Start buffer */ |
7e7c5e4c AZ |
639 | return (s->bufaddr << 8) | ((s->count - 1) & (1 << (PAGE_SHIFT - 10))); |
640 | ||
d091b5b4 | 641 | case 0xf220: /* Command */ |
7e7c5e4c | 642 | return s->command; |
d091b5b4 | 643 | case 0xf221: /* System Configuration 1 */ |
7e7c5e4c | 644 | return s->config[0] & 0xffe0; |
d091b5b4 | 645 | case 0xf222: /* System Configuration 2 */ |
7e7c5e4c AZ |
646 | return s->config[1]; |
647 | ||
d091b5b4 | 648 | case 0xf240: /* Controller Status */ |
7e7c5e4c | 649 | return s->status; |
d091b5b4 | 650 | case 0xf241: /* Interrupt */ |
7e7c5e4c | 651 | return s->intstatus; |
d091b5b4 | 652 | case 0xf24c: /* Unlock Start Block Address */ |
7e7c5e4c | 653 | return s->unladdr[0]; |
d091b5b4 | 654 | case 0xf24d: /* Unlock End Block Address */ |
7e7c5e4c | 655 | return s->unladdr[1]; |
d091b5b4 | 656 | case 0xf24e: /* Write Protection Status */ |
7e7c5e4c AZ |
657 | return s->wpstatus; |
658 | ||
d091b5b4 | 659 | case 0xff00: /* ECC Status */ |
7e7c5e4c | 660 | return 0x00; |
d091b5b4 YF |
661 | case 0xff01: /* ECC Result of main area data */ |
662 | case 0xff02: /* ECC Result of spare area data */ | |
663 | case 0xff03: /* ECC Result of main area data */ | |
664 | case 0xff04: /* ECC Result of spare area data */ | |
9e6e9247 PM |
665 | qemu_log_mask(LOG_UNIMP, |
666 | "onenand: ECC result registers unimplemented\n"); | |
7e7c5e4c AZ |
667 | return 0x0000; |
668 | } | |
669 | ||
9e6e9247 PM |
670 | qemu_log_mask(LOG_GUEST_ERROR, "read of unknown OneNAND register 0x%x\n", |
671 | offset); | |
7e7c5e4c AZ |
672 | return 0; |
673 | } | |
674 | ||
a8170e5e | 675 | static void onenand_write(void *opaque, hwaddr addr, |
689a1921 | 676 | uint64_t value, unsigned size) |
7e7c5e4c | 677 | { |
bc24a225 | 678 | OneNANDState *s = (OneNANDState *) opaque; |
8da3ff18 | 679 | int offset = addr >> s->shift; |
7e7c5e4c AZ |
680 | int sec; |
681 | ||
682 | switch (offset) { | |
683 | case 0x0000 ... 0x01ff: | |
684 | case 0x8000 ... 0x800f: | |
685 | if (s->cycle) { | |
686 | s->cycle = 0; | |
687 | ||
688 | if (value == 0x0000) { | |
689 | SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE) | |
690 | onenand_load_main(s, sec, | |
691 | 1 << (PAGE_SHIFT - 9), s->data[0][0]); | |
692 | s->addr[ONEN_BUF_PAGE] += 4; | |
693 | s->addr[ONEN_BUF_PAGE] &= 0xff; | |
694 | } | |
695 | break; | |
696 | } | |
697 | ||
698 | switch (value) { | |
d091b5b4 | 699 | case 0x00f0: /* Reset OneNAND */ |
7e7c5e4c AZ |
700 | onenand_reset(s, 0); |
701 | break; | |
702 | ||
d091b5b4 | 703 | case 0x00e0: /* Load Data into Buffer */ |
7e7c5e4c AZ |
704 | s->cycle = 1; |
705 | break; | |
706 | ||
d091b5b4 | 707 | case 0x0090: /* Read Identification Data */ |
7e7c5e4c | 708 | memset(s->boot[0], 0, 3 << s->shift); |
5923ba42 JR |
709 | s->boot[0][0 << s->shift] = s->id.man & 0xff; |
710 | s->boot[0][1 << s->shift] = s->id.dev & 0xff; | |
7e7c5e4c AZ |
711 | s->boot[0][2 << s->shift] = s->wpstatus & 0xff; |
712 | break; | |
713 | ||
714 | default: | |
9e6e9247 PM |
715 | qemu_log_mask(LOG_GUEST_ERROR, |
716 | "unknown OneNAND boot command %" PRIx64 "\n", | |
717 | value); | |
7e7c5e4c AZ |
718 | } |
719 | break; | |
720 | ||
d091b5b4 | 721 | case 0xf100 ... 0xf107: /* Start addresses */ |
7e7c5e4c AZ |
722 | s->addr[offset - 0xf100] = value; |
723 | break; | |
724 | ||
d091b5b4 | 725 | case 0xf200: /* Start buffer */ |
7e7c5e4c AZ |
726 | s->bufaddr = (value >> 8) & 0xf; |
727 | if (PAGE_SHIFT == 11) | |
728 | s->count = (value & 3) ?: 4; | |
729 | else if (PAGE_SHIFT == 10) | |
730 | s->count = (value & 1) ?: 2; | |
731 | break; | |
732 | ||
d091b5b4 | 733 | case 0xf220: /* Command */ |
7e7c5e4c AZ |
734 | if (s->intstatus & (1 << 15)) |
735 | break; | |
736 | s->command = value; | |
82866965 | 737 | onenand_command(s); |
7e7c5e4c | 738 | break; |
d091b5b4 | 739 | case 0xf221: /* System Configuration 1 */ |
7e7c5e4c AZ |
740 | s->config[0] = value; |
741 | onenand_intr_update(s); | |
742 | qemu_set_irq(s->rdy, (s->config[0] >> 7) & 1); | |
743 | break; | |
d091b5b4 | 744 | case 0xf222: /* System Configuration 2 */ |
7e7c5e4c AZ |
745 | s->config[1] = value; |
746 | break; | |
747 | ||
d091b5b4 | 748 | case 0xf241: /* Interrupt */ |
7e7c5e4c AZ |
749 | s->intstatus &= value; |
750 | if ((1 << 15) & ~s->intstatus) | |
751 | s->status &= ~(ONEN_ERR_CMD | ONEN_ERR_ERASE | | |
752 | ONEN_ERR_PROG | ONEN_ERR_LOAD); | |
753 | onenand_intr_update(s); | |
754 | break; | |
d091b5b4 | 755 | case 0xf24c: /* Unlock Start Block Address */ |
7e7c5e4c AZ |
756 | s->unladdr[0] = value & (s->blocks - 1); |
757 | /* For some reason we have to set the end address to by default | |
758 | * be same as start because the software forgets to write anything | |
759 | * in there. */ | |
760 | s->unladdr[1] = value & (s->blocks - 1); | |
761 | break; | |
d091b5b4 | 762 | case 0xf24d: /* Unlock End Block Address */ |
7e7c5e4c AZ |
763 | s->unladdr[1] = value & (s->blocks - 1); |
764 | break; | |
765 | ||
766 | default: | |
9e6e9247 PM |
767 | qemu_log_mask(LOG_GUEST_ERROR, |
768 | "write to unknown OneNAND register 0x%x\n", | |
769 | offset); | |
7e7c5e4c AZ |
770 | } |
771 | } | |
772 | ||
689a1921 AK |
773 | static const MemoryRegionOps onenand_ops = { |
774 | .read = onenand_read, | |
775 | .write = onenand_write, | |
776 | .endianness = DEVICE_NATIVE_ENDIAN, | |
7e7c5e4c AZ |
777 | }; |
778 | ||
887c74ca | 779 | static void onenand_realize(DeviceState *dev, Error **errp) |
7e7c5e4c | 780 | { |
887c74ca | 781 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
af073cd9 | 782 | OneNANDState *s = ONE_NAND(dev); |
500954e3 | 783 | uint32_t size = 1 << (24 + ((s->id.dev >> 4) & 7)); |
7e7c5e4c | 784 | void *ram; |
a17c17a2 | 785 | Error *local_err = NULL; |
af073cd9 | 786 | |
a8170e5e | 787 | s->base = (hwaddr)-1; |
b9d38e95 | 788 | s->rdy = NULL; |
7e7c5e4c AZ |
789 | s->blocks = size >> BLOCK_SHIFT; |
790 | s->secs = size >> 9; | |
7267c094 | 791 | s->blockwp = g_malloc(s->blocks); |
500954e3 JR |
792 | s->density_mask = (s->id.dev & 0x08) |
793 | ? (1 << (6 + ((s->id.dev >> 4) & 7))) : 0; | |
2d256e6f | 794 | memory_region_init_io(&s->iomem, OBJECT(s), &onenand_ops, s, "onenand", |
689a1921 | 795 | 0x10000 << s->shift); |
4be74634 | 796 | if (!s->blk) { |
7267c094 | 797 | s->image = memset(g_malloc(size + (size >> 5)), |
500954e3 JR |
798 | 0xff, size + (size >> 5)); |
799 | } else { | |
86b1cf32 | 800 | if (!blk_supports_write_perm(s->blk)) { |
887c74ca MZ |
801 | error_setg(errp, "Can't use a read-only drive"); |
802 | return; | |
a3efecb8 | 803 | } |
a17c17a2 KW |
804 | blk_set_perm(s->blk, BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE, |
805 | BLK_PERM_ALL, &local_err); | |
806 | if (local_err) { | |
887c74ca MZ |
807 | error_propagate(errp, local_err); |
808 | return; | |
a17c17a2 | 809 | } |
4be74634 | 810 | s->blk_cur = s->blk; |
63efb1d9 | 811 | } |
7267c094 | 812 | s->otp = memset(g_malloc((64 + 2) << PAGE_SHIFT), |
7e7c5e4c | 813 | 0xff, (64 + 2) << PAGE_SHIFT); |
1cfe48c1 | 814 | memory_region_init_ram_nomigrate(&s->ram, OBJECT(s), "onenand.ram", |
f8ed85ac | 815 | 0xc000 << s->shift, &error_fatal); |
c5705a77 | 816 | vmstate_register_ram_global(&s->ram); |
689a1921 | 817 | ram = memory_region_get_ram_ptr(&s->ram); |
7e7c5e4c AZ |
818 | s->boot[0] = ram + (0x0000 << s->shift); |
819 | s->boot[1] = ram + (0x8000 << s->shift); | |
820 | s->data[0][0] = ram + ((0x0200 + (0 << (PAGE_SHIFT - 1))) << s->shift); | |
821 | s->data[0][1] = ram + ((0x8010 + (0 << (PAGE_SHIFT - 6))) << s->shift); | |
822 | s->data[1][0] = ram + ((0x0200 + (1 << (PAGE_SHIFT - 1))) << s->shift); | |
823 | s->data[1][1] = ram + ((0x8010 + (1 << (PAGE_SHIFT - 6))) << s->shift); | |
689a1921 | 824 | onenand_mem_setup(s); |
af073cd9 AF |
825 | sysbus_init_irq(sbd, &s->intr); |
826 | sysbus_init_mmio(sbd, &s->container); | |
3cad405b | 827 | vmstate_register(VMSTATE_IF(dev), |
500954e3 JR |
828 | ((s->shift & 0x7f) << 24) |
829 | | ((s->id.man & 0xff) << 16) | |
830 | | ((s->id.dev & 0xff) << 8) | |
831 | | (s->id.ver & 0xff), | |
832 | &vmstate_onenand, s); | |
500954e3 | 833 | } |
7e7c5e4c | 834 | |
999e12bb AL |
835 | static Property onenand_properties[] = { |
836 | DEFINE_PROP_UINT16("manufacturer_id", OneNANDState, id.man, 0), | |
837 | DEFINE_PROP_UINT16("device_id", OneNANDState, id.dev, 0), | |
838 | DEFINE_PROP_UINT16("version_id", OneNANDState, id.ver, 0), | |
839 | DEFINE_PROP_INT32("shift", OneNANDState, shift, 0), | |
4be74634 | 840 | DEFINE_PROP_DRIVE("drive", OneNANDState, blk), |
999e12bb AL |
841 | DEFINE_PROP_END_OF_LIST(), |
842 | }; | |
843 | ||
844 | static void onenand_class_init(ObjectClass *klass, void *data) | |
845 | { | |
39bffca2 | 846 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 847 | |
887c74ca | 848 | dc->realize = onenand_realize; |
39bffca2 | 849 | dc->reset = onenand_system_reset; |
4f67d30b | 850 | device_class_set_props(dc, onenand_properties); |
999e12bb AL |
851 | } |
852 | ||
8c43a6f0 | 853 | static const TypeInfo onenand_info = { |
af073cd9 | 854 | .name = TYPE_ONE_NAND, |
39bffca2 AL |
855 | .parent = TYPE_SYS_BUS_DEVICE, |
856 | .instance_size = sizeof(OneNANDState), | |
857 | .class_init = onenand_class_init, | |
500954e3 | 858 | }; |
7e7c5e4c | 859 | |
83f7d43a | 860 | static void onenand_register_types(void) |
500954e3 | 861 | { |
39bffca2 | 862 | type_register_static(&onenand_info); |
7e7c5e4c | 863 | } |
c580d92b | 864 | |
500954e3 | 865 | void *onenand_raw_otp(DeviceState *onenand_device) |
c580d92b | 866 | { |
af073cd9 AF |
867 | OneNANDState *s = ONE_NAND(onenand_device); |
868 | ||
869 | return s->otp; | |
c580d92b | 870 | } |
500954e3 | 871 | |
83f7d43a | 872 | type_init(onenand_register_types) |