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Commit | Line | Data |
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05ee37eb AZ |
1 | /* |
2 | * CFI parallel flash with Intel command set emulation | |
3 | * | |
4 | * Copyright (c) 2006 Thorsten Zitterell | |
5 | * Copyright (c) 2005 Jocelyn Mayer | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
05ee37eb AZ |
19 | */ |
20 | ||
21 | /* | |
22 | * For now, this code can emulate flashes of 1, 2 or 4 bytes width. | |
23 | * Supported commands/modes are: | |
24 | * - flash read | |
25 | * - flash write | |
26 | * - flash ID read | |
27 | * - sector erase | |
28 | * - CFI queries | |
29 | * | |
30 | * It does not support timings | |
31 | * It does not support flash interleaving | |
32 | * It does not implement software data protection as found in many real chips | |
33 | * It does not implement erase suspend/resume commands | |
34 | * It does not implement multiple sectors erase | |
35 | * | |
36 | * It does not implement much more ... | |
37 | */ | |
38 | ||
80c71a24 | 39 | #include "qemu/osdep.h" |
83c9f4ca | 40 | #include "hw/hw.h" |
06f15217 | 41 | #include "hw/block/block.h" |
0d09e41a | 42 | #include "hw/block/flash.h" |
4be74634 | 43 | #include "sysemu/block-backend.h" |
da34e65c | 44 | #include "qapi/error.h" |
1de7afc9 | 45 | #include "qemu/timer.h" |
1997b485 | 46 | #include "qemu/bitops.h" |
2d731dbd | 47 | #include "qemu/error-report.h" |
1de7afc9 | 48 | #include "qemu/host-utils.h" |
03dd024f | 49 | #include "qemu/log.h" |
0b8fa32f | 50 | #include "qemu/module.h" |
2d731dbd | 51 | #include "qemu/option.h" |
83c9f4ca | 52 | #include "hw/sysbus.h" |
2d731dbd | 53 | #include "sysemu/blockdev.h" |
90c647db | 54 | #include "sysemu/sysemu.h" |
13019f1f | 55 | #include "trace.h" |
05ee37eb | 56 | |
05ee37eb AZ |
57 | /* #define PFLASH_DEBUG */ |
58 | #ifdef PFLASH_DEBUG | |
ec9ea489 PC |
59 | #define DPRINTF(fmt, ...) \ |
60 | do { \ | |
61 | fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__); \ | |
05ee37eb AZ |
62 | } while (0) |
63 | #else | |
001faf32 | 64 | #define DPRINTF(fmt, ...) do { } while (0) |
05ee37eb AZ |
65 | #endif |
66 | ||
e9809422 | 67 | #define PFLASH_BE 0 |
f71e42a5 | 68 | #define PFLASH_SECURE 1 |
e9809422 | 69 | |
16434065 | 70 | struct PFlashCFI01 { |
f1b44f0e HT |
71 | /*< private >*/ |
72 | SysBusDevice parent_obj; | |
73 | /*< public >*/ | |
74 | ||
4be74634 | 75 | BlockBackend *blk; |
368a354f PC |
76 | uint32_t nb_blocs; |
77 | uint64_t sector_len; | |
4b6fedca | 78 | uint8_t bank_width; |
1997b485 | 79 | uint8_t device_width; /* If 0, device width not specified. */ |
fa21a7b1 | 80 | uint8_t max_device_width; /* max device width in bytes */ |
e9809422 | 81 | uint32_t features; |
d8d24fb7 | 82 | uint8_t wcycle; /* if 0, the flash is read normally */ |
05ee37eb AZ |
83 | int ro; |
84 | uint8_t cmd; | |
85 | uint8_t status; | |
368a354f PC |
86 | uint16_t ident0; |
87 | uint16_t ident1; | |
88 | uint16_t ident2; | |
89 | uint16_t ident3; | |
05ee37eb | 90 | uint8_t cfi_table[0x52]; |
d8d24fb7 | 91 | uint64_t counter; |
b4bf0a9a | 92 | unsigned int writeblock_size; |
05ee37eb | 93 | QEMUTimer *timer; |
cfe5f011 | 94 | MemoryRegion mem; |
368a354f | 95 | char *name; |
05ee37eb | 96 | void *storage; |
90c647db | 97 | VMChangeStateEntry *vmstate; |
feb0b1aa | 98 | bool old_multiple_chip_handling; |
05ee37eb AZ |
99 | }; |
100 | ||
4c0cfc72 LE |
101 | static int pflash_post_load(void *opaque, int version_id); |
102 | ||
d8d24fb7 PM |
103 | static const VMStateDescription vmstate_pflash = { |
104 | .name = "pflash_cfi01", | |
105 | .version_id = 1, | |
106 | .minimum_version_id = 1, | |
4c0cfc72 | 107 | .post_load = pflash_post_load, |
d8d24fb7 | 108 | .fields = (VMStateField[]) { |
16434065 MA |
109 | VMSTATE_UINT8(wcycle, PFlashCFI01), |
110 | VMSTATE_UINT8(cmd, PFlashCFI01), | |
111 | VMSTATE_UINT8(status, PFlashCFI01), | |
112 | VMSTATE_UINT64(counter, PFlashCFI01), | |
d8d24fb7 PM |
113 | VMSTATE_END_OF_LIST() |
114 | } | |
115 | }; | |
116 | ||
05ee37eb AZ |
117 | static void pflash_timer (void *opaque) |
118 | { | |
16434065 | 119 | PFlashCFI01 *pfl = opaque; |
05ee37eb | 120 | |
13019f1f | 121 | trace_pflash_timer_expired(pfl->cmd); |
05ee37eb AZ |
122 | /* Reset flash */ |
123 | pfl->status ^= 0x80; | |
5f9a5ea1 | 124 | memory_region_rom_device_set_romd(&pfl->mem, true); |
5d79b80b | 125 | pfl->wcycle = 0; |
05ee37eb AZ |
126 | pfl->cmd = 0; |
127 | } | |
128 | ||
4433e660 RF |
129 | /* Perform a CFI query based on the bank width of the flash. |
130 | * If this code is called we know we have a device_width set for | |
131 | * this flash. | |
132 | */ | |
16434065 | 133 | static uint32_t pflash_cfi_query(PFlashCFI01 *pfl, hwaddr offset) |
4433e660 RF |
134 | { |
135 | int i; | |
136 | uint32_t resp = 0; | |
137 | hwaddr boff; | |
138 | ||
139 | /* Adjust incoming offset to match expected device-width | |
140 | * addressing. CFI query addresses are always specified in terms of | |
141 | * the maximum supported width of the device. This means that x8 | |
142 | * devices and x8/x16 devices in x8 mode behave differently. For | |
143 | * devices that are not used at their max width, we will be | |
144 | * provided with addresses that use higher address bits than | |
145 | * expected (based on the max width), so we will shift them lower | |
146 | * so that they will match the addresses used when | |
147 | * device_width==max_device_width. | |
148 | */ | |
149 | boff = offset >> (ctz32(pfl->bank_width) + | |
150 | ctz32(pfl->max_device_width) - ctz32(pfl->device_width)); | |
151 | ||
07c13a71 | 152 | if (boff >= sizeof(pfl->cfi_table)) { |
4433e660 RF |
153 | return 0; |
154 | } | |
155 | /* Now we will construct the CFI response generated by a single | |
156 | * device, then replicate that for all devices that make up the | |
157 | * bus. For wide parts used in x8 mode, CFI query responses | |
158 | * are different than native byte-wide parts. | |
159 | */ | |
160 | resp = pfl->cfi_table[boff]; | |
161 | if (pfl->device_width != pfl->max_device_width) { | |
162 | /* The only case currently supported is x8 mode for a | |
163 | * wider part. | |
164 | */ | |
165 | if (pfl->device_width != 1 || pfl->bank_width > 4) { | |
166 | DPRINTF("%s: Unsupported device configuration: " | |
167 | "device_width=%d, max_device_width=%d\n", | |
168 | __func__, pfl->device_width, | |
169 | pfl->max_device_width); | |
170 | return 0; | |
171 | } | |
172 | /* CFI query data is repeated, rather than zero padded for | |
173 | * wide devices used in x8 mode. | |
174 | */ | |
175 | for (i = 1; i < pfl->max_device_width; i++) { | |
176 | resp = deposit32(resp, 8 * i, 8, pfl->cfi_table[boff]); | |
177 | } | |
178 | } | |
179 | /* Replicate responses for each device in bank. */ | |
180 | if (pfl->device_width < pfl->bank_width) { | |
181 | for (i = pfl->device_width; | |
182 | i < pfl->bank_width; i += pfl->device_width) { | |
183 | resp = deposit32(resp, 8 * i, 8 * pfl->device_width, resp); | |
184 | } | |
185 | } | |
186 | ||
187 | return resp; | |
188 | } | |
189 | ||
0163a2dc RF |
190 | |
191 | ||
192 | /* Perform a device id query based on the bank width of the flash. */ | |
16434065 | 193 | static uint32_t pflash_devid_query(PFlashCFI01 *pfl, hwaddr offset) |
0163a2dc RF |
194 | { |
195 | int i; | |
196 | uint32_t resp; | |
197 | hwaddr boff; | |
198 | ||
199 | /* Adjust incoming offset to match expected device-width | |
200 | * addressing. Device ID read addresses are always specified in | |
201 | * terms of the maximum supported width of the device. This means | |
202 | * that x8 devices and x8/x16 devices in x8 mode behave | |
203 | * differently. For devices that are not used at their max width, | |
204 | * we will be provided with addresses that use higher address bits | |
205 | * than expected (based on the max width), so we will shift them | |
206 | * lower so that they will match the addresses used when | |
207 | * device_width==max_device_width. | |
208 | */ | |
209 | boff = offset >> (ctz32(pfl->bank_width) + | |
210 | ctz32(pfl->max_device_width) - ctz32(pfl->device_width)); | |
211 | ||
212 | /* Mask off upper bits which may be used in to query block | |
213 | * or sector lock status at other addresses. | |
214 | * Offsets 2/3 are block lock status, is not emulated. | |
215 | */ | |
216 | switch (boff & 0xFF) { | |
217 | case 0: | |
218 | resp = pfl->ident0; | |
13019f1f | 219 | trace_pflash_manufacturer_id(resp); |
0163a2dc RF |
220 | break; |
221 | case 1: | |
222 | resp = pfl->ident1; | |
13019f1f | 223 | trace_pflash_device_id(resp); |
0163a2dc RF |
224 | break; |
225 | default: | |
13019f1f | 226 | trace_pflash_device_info(offset); |
0163a2dc RF |
227 | return 0; |
228 | break; | |
229 | } | |
230 | /* Replicate responses for each device in bank. */ | |
231 | if (pfl->device_width < pfl->bank_width) { | |
232 | for (i = pfl->device_width; | |
233 | i < pfl->bank_width; i += pfl->device_width) { | |
234 | resp = deposit32(resp, 8 * i, 8 * pfl->device_width, resp); | |
235 | } | |
236 | } | |
237 | ||
238 | return resp; | |
239 | } | |
240 | ||
16434065 | 241 | static uint32_t pflash_data_read(PFlashCFI01 *pfl, hwaddr offset, |
f71e42a5 PB |
242 | int width, int be) |
243 | { | |
244 | uint8_t *p; | |
245 | uint32_t ret; | |
246 | ||
247 | p = pfl->storage; | |
248 | switch (width) { | |
249 | case 1: | |
250 | ret = p[offset]; | |
f71e42a5 PB |
251 | break; |
252 | case 2: | |
253 | if (be) { | |
254 | ret = p[offset] << 8; | |
255 | ret |= p[offset + 1]; | |
256 | } else { | |
257 | ret = p[offset]; | |
258 | ret |= p[offset + 1] << 8; | |
259 | } | |
f71e42a5 PB |
260 | break; |
261 | case 4: | |
262 | if (be) { | |
263 | ret = p[offset] << 24; | |
264 | ret |= p[offset + 1] << 16; | |
265 | ret |= p[offset + 2] << 8; | |
266 | ret |= p[offset + 3]; | |
267 | } else { | |
268 | ret = p[offset]; | |
269 | ret |= p[offset + 1] << 8; | |
270 | ret |= p[offset + 2] << 16; | |
271 | ret |= p[offset + 3] << 24; | |
272 | } | |
f71e42a5 PB |
273 | break; |
274 | default: | |
275 | DPRINTF("BUG in %s\n", __func__); | |
276 | abort(); | |
277 | } | |
c1474acd | 278 | trace_pflash_data_read(offset, width << 1, ret); |
f71e42a5 PB |
279 | return ret; |
280 | } | |
281 | ||
16434065 MA |
282 | static uint32_t pflash_read(PFlashCFI01 *pfl, hwaddr offset, |
283 | int width, int be) | |
05ee37eb | 284 | { |
a8170e5e | 285 | hwaddr boff; |
05ee37eb | 286 | uint32_t ret; |
05ee37eb AZ |
287 | |
288 | ret = -1; | |
05ee37eb | 289 | switch (pfl->cmd) { |
1be97bf2 PM |
290 | default: |
291 | /* This should never happen : reset state & treat it as a read */ | |
292 | DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd); | |
293 | pfl->wcycle = 0; | |
294 | pfl->cmd = 0; | |
295 | /* fall through to read code */ | |
05ee37eb AZ |
296 | case 0x00: |
297 | /* Flash area read */ | |
f71e42a5 | 298 | ret = pflash_data_read(pfl, offset, width, be); |
05ee37eb | 299 | break; |
6e392787 | 300 | case 0x10: /* Single byte program */ |
05ee37eb | 301 | case 0x20: /* Block erase */ |
6e392787 PM |
302 | case 0x28: /* Block erase */ |
303 | case 0x40: /* single byte program */ | |
05ee37eb AZ |
304 | case 0x50: /* Clear status register */ |
305 | case 0x60: /* Block /un)lock */ | |
306 | case 0x70: /* Status Register */ | |
307 | case 0xe8: /* Write block */ | |
2003889f RF |
308 | /* Status register read. Return status from each device in |
309 | * bank. | |
310 | */ | |
05ee37eb | 311 | ret = pfl->status; |
2003889f RF |
312 | if (pfl->device_width && width > pfl->device_width) { |
313 | int shift = pfl->device_width * 8; | |
314 | while (shift + pfl->device_width * 8 <= width * 8) { | |
315 | ret |= pfl->status << shift; | |
316 | shift += pfl->device_width * 8; | |
317 | } | |
318 | } else if (!pfl->device_width && width > 2) { | |
319 | /* Handle 32 bit flash cases where device width is not | |
320 | * set. (Existing behavior before device width added.) | |
321 | */ | |
ea0a4f34 PB |
322 | ret |= pfl->status << 16; |
323 | } | |
05ee37eb AZ |
324 | DPRINTF("%s: status %x\n", __func__, ret); |
325 | break; | |
0b2ec6fc | 326 | case 0x90: |
0163a2dc RF |
327 | if (!pfl->device_width) { |
328 | /* Preserve old behavior if device width not specified */ | |
329 | boff = offset & 0xFF; | |
330 | if (pfl->bank_width == 2) { | |
331 | boff = boff >> 1; | |
332 | } else if (pfl->bank_width == 4) { | |
333 | boff = boff >> 2; | |
334 | } | |
4433e660 | 335 | |
0163a2dc RF |
336 | switch (boff) { |
337 | case 0: | |
338 | ret = pfl->ident0 << 8 | pfl->ident1; | |
13019f1f | 339 | trace_pflash_manufacturer_id(ret); |
0163a2dc RF |
340 | break; |
341 | case 1: | |
342 | ret = pfl->ident2 << 8 | pfl->ident3; | |
13019f1f | 343 | trace_pflash_device_id(ret); |
0163a2dc RF |
344 | break; |
345 | default: | |
13019f1f | 346 | trace_pflash_device_info(boff); |
0163a2dc RF |
347 | ret = 0; |
348 | break; | |
349 | } | |
350 | } else { | |
351 | /* If we have a read larger than the bank_width, combine multiple | |
352 | * manufacturer/device ID queries into a single response. | |
353 | */ | |
354 | int i; | |
355 | for (i = 0; i < width; i += pfl->bank_width) { | |
356 | ret = deposit32(ret, i * 8, pfl->bank_width * 8, | |
357 | pflash_devid_query(pfl, | |
358 | offset + i * pfl->bank_width)); | |
359 | } | |
0b2ec6fc MW |
360 | } |
361 | break; | |
05ee37eb | 362 | case 0x98: /* Query mode */ |
4433e660 RF |
363 | if (!pfl->device_width) { |
364 | /* Preserve old behavior if device width not specified */ | |
365 | boff = offset & 0xFF; | |
366 | if (pfl->bank_width == 2) { | |
367 | boff = boff >> 1; | |
368 | } else if (pfl->bank_width == 4) { | |
369 | boff = boff >> 2; | |
370 | } | |
371 | ||
07c13a71 | 372 | if (boff < sizeof(pfl->cfi_table)) { |
4433e660 | 373 | ret = pfl->cfi_table[boff]; |
07c13a71 PMD |
374 | } else { |
375 | ret = 0; | |
4433e660 RF |
376 | } |
377 | } else { | |
378 | /* If we have a read larger than the bank_width, combine multiple | |
379 | * CFI queries into a single response. | |
380 | */ | |
381 | int i; | |
382 | for (i = 0; i < width; i += pfl->bank_width) { | |
383 | ret = deposit32(ret, i * 8, pfl->bank_width * 8, | |
384 | pflash_cfi_query(pfl, | |
385 | offset + i * pfl->bank_width)); | |
386 | } | |
387 | } | |
388 | ||
05ee37eb | 389 | break; |
05ee37eb | 390 | } |
e8aa2d95 PMD |
391 | trace_pflash_io_read(offset, width, width << 1, ret, pfl->cmd, pfl->wcycle); |
392 | ||
05ee37eb AZ |
393 | return ret; |
394 | } | |
395 | ||
396 | /* update flash content on disk */ | |
16434065 | 397 | static void pflash_update(PFlashCFI01 *pfl, int offset, |
05ee37eb AZ |
398 | int size) |
399 | { | |
400 | int offset_end; | |
4be74634 | 401 | if (pfl->blk) { |
05ee37eb | 402 | offset_end = offset + size; |
098e732d EB |
403 | /* widen to sector boundaries */ |
404 | offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE); | |
405 | offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE); | |
406 | blk_pwrite(pfl->blk, offset, pfl->storage + offset, | |
407 | offset_end - offset, 0); | |
05ee37eb AZ |
408 | } |
409 | } | |
410 | ||
16434065 | 411 | static inline void pflash_data_write(PFlashCFI01 *pfl, hwaddr offset, |
3d08ff69 | 412 | uint32_t value, int width, int be) |
d361be25 AZ |
413 | { |
414 | uint8_t *p = pfl->storage; | |
415 | ||
c1474acd | 416 | trace_pflash_data_write(offset, width << 1, value, pfl->counter); |
d361be25 AZ |
417 | switch (width) { |
418 | case 1: | |
419 | p[offset] = value; | |
d361be25 AZ |
420 | break; |
421 | case 2: | |
3d08ff69 BS |
422 | if (be) { |
423 | p[offset] = value >> 8; | |
424 | p[offset + 1] = value; | |
425 | } else { | |
426 | p[offset] = value; | |
427 | p[offset + 1] = value >> 8; | |
428 | } | |
d361be25 AZ |
429 | break; |
430 | case 4: | |
3d08ff69 BS |
431 | if (be) { |
432 | p[offset] = value >> 24; | |
433 | p[offset + 1] = value >> 16; | |
434 | p[offset + 2] = value >> 8; | |
435 | p[offset + 3] = value; | |
436 | } else { | |
437 | p[offset] = value; | |
438 | p[offset + 1] = value >> 8; | |
439 | p[offset + 2] = value >> 16; | |
440 | p[offset + 3] = value >> 24; | |
441 | } | |
d361be25 AZ |
442 | break; |
443 | } | |
444 | ||
445 | } | |
446 | ||
16434065 | 447 | static void pflash_write(PFlashCFI01 *pfl, hwaddr offset, |
3d08ff69 | 448 | uint32_t value, int width, int be) |
05ee37eb | 449 | { |
05ee37eb AZ |
450 | uint8_t *p; |
451 | uint8_t cmd; | |
452 | ||
05ee37eb | 453 | cmd = value; |
05ee37eb | 454 | |
e8aa2d95 | 455 | trace_pflash_io_write(offset, width, width << 1, value, pfl->wcycle); |
e9cbbcac EI |
456 | if (!pfl->wcycle) { |
457 | /* Set the device in I/O access mode */ | |
5f9a5ea1 | 458 | memory_region_rom_device_set_romd(&pfl->mem, false); |
e9cbbcac | 459 | } |
05ee37eb AZ |
460 | |
461 | switch (pfl->wcycle) { | |
462 | case 0: | |
463 | /* read mode */ | |
464 | switch (cmd) { | |
465 | case 0x00: /* ??? */ | |
466 | goto reset_flash; | |
d361be25 AZ |
467 | case 0x10: /* Single Byte Program */ |
468 | case 0x40: /* Single Byte Program */ | |
fad8c772 | 469 | DPRINTF("%s: Single Byte Program\n", __func__); |
d361be25 | 470 | break; |
05ee37eb AZ |
471 | case 0x20: /* Block erase */ |
472 | p = pfl->storage; | |
473 | offset &= ~(pfl->sector_len - 1); | |
474 | ||
368a354f PC |
475 | DPRINTF("%s: block erase at " TARGET_FMT_plx " bytes %x\n", |
476 | __func__, offset, (unsigned)pfl->sector_len); | |
05ee37eb | 477 | |
de8efe8f JJ |
478 | if (!pfl->ro) { |
479 | memset(p + offset, 0xff, pfl->sector_len); | |
480 | pflash_update(pfl, offset, pfl->sector_len); | |
481 | } else { | |
482 | pfl->status |= 0x20; /* Block erase error */ | |
483 | } | |
05ee37eb AZ |
484 | pfl->status |= 0x80; /* Ready! */ |
485 | break; | |
486 | case 0x50: /* Clear status bits */ | |
487 | DPRINTF("%s: Clear status bits\n", __func__); | |
488 | pfl->status = 0x0; | |
489 | goto reset_flash; | |
490 | case 0x60: /* Block (un)lock */ | |
491 | DPRINTF("%s: Block unlock\n", __func__); | |
492 | break; | |
493 | case 0x70: /* Status Register */ | |
494 | DPRINTF("%s: Read status register\n", __func__); | |
495 | pfl->cmd = cmd; | |
496 | return; | |
0b2ec6fc MW |
497 | case 0x90: /* Read Device ID */ |
498 | DPRINTF("%s: Read Device information\n", __func__); | |
499 | pfl->cmd = cmd; | |
500 | return; | |
05ee37eb AZ |
501 | case 0x98: /* CFI query */ |
502 | DPRINTF("%s: CFI query\n", __func__); | |
503 | break; | |
504 | case 0xe8: /* Write to buffer */ | |
505 | DPRINTF("%s: Write to buffer\n", __func__); | |
4dbda935 MA |
506 | /* FIXME should save @offset, @width for case 1+ */ |
507 | qemu_log_mask(LOG_UNIMP, | |
508 | "%s: Write to buffer emulation is flawed\n", | |
509 | __func__); | |
05ee37eb AZ |
510 | pfl->status |= 0x80; /* Ready! */ |
511 | break; | |
5928023c SW |
512 | case 0xf0: /* Probe for AMD flash */ |
513 | DPRINTF("%s: Probe for AMD flash\n", __func__); | |
514 | goto reset_flash; | |
05ee37eb AZ |
515 | case 0xff: /* Read array mode */ |
516 | DPRINTF("%s: Read array mode\n", __func__); | |
517 | goto reset_flash; | |
518 | default: | |
519 | goto error_flash; | |
520 | } | |
521 | pfl->wcycle++; | |
522 | pfl->cmd = cmd; | |
12dabc79 | 523 | break; |
05ee37eb AZ |
524 | case 1: |
525 | switch (pfl->cmd) { | |
d361be25 AZ |
526 | case 0x10: /* Single Byte Program */ |
527 | case 0x40: /* Single Byte Program */ | |
528 | DPRINTF("%s: Single Byte Program\n", __func__); | |
de8efe8f JJ |
529 | if (!pfl->ro) { |
530 | pflash_data_write(pfl, offset, value, width, be); | |
531 | pflash_update(pfl, offset, width); | |
532 | } else { | |
533 | pfl->status |= 0x10; /* Programming error */ | |
534 | } | |
d361be25 AZ |
535 | pfl->status |= 0x80; /* Ready! */ |
536 | pfl->wcycle = 0; | |
537 | break; | |
05ee37eb AZ |
538 | case 0x20: /* Block erase */ |
539 | case 0x28: | |
540 | if (cmd == 0xd0) { /* confirm */ | |
3656744c | 541 | pfl->wcycle = 0; |
05ee37eb | 542 | pfl->status |= 0x80; |
9248f413 | 543 | } else if (cmd == 0xff) { /* read array mode */ |
05ee37eb AZ |
544 | goto reset_flash; |
545 | } else | |
546 | goto error_flash; | |
547 | ||
548 | break; | |
549 | case 0xe8: | |
1997b485 RF |
550 | /* Mask writeblock size based on device width, or bank width if |
551 | * device width not specified. | |
552 | */ | |
4dbda935 | 553 | /* FIXME check @offset, @width */ |
1997b485 RF |
554 | if (pfl->device_width) { |
555 | value = extract32(value, 0, pfl->device_width * 8); | |
556 | } else { | |
557 | value = extract32(value, 0, pfl->bank_width * 8); | |
558 | } | |
71fb2348 AZ |
559 | DPRINTF("%s: block write of %x bytes\n", __func__, value); |
560 | pfl->counter = value; | |
05ee37eb AZ |
561 | pfl->wcycle++; |
562 | break; | |
563 | case 0x60: | |
564 | if (cmd == 0xd0) { | |
565 | pfl->wcycle = 0; | |
566 | pfl->status |= 0x80; | |
567 | } else if (cmd == 0x01) { | |
568 | pfl->wcycle = 0; | |
569 | pfl->status |= 0x80; | |
570 | } else if (cmd == 0xff) { | |
571 | goto reset_flash; | |
572 | } else { | |
573 | DPRINTF("%s: Unknown (un)locking command\n", __func__); | |
574 | goto reset_flash; | |
575 | } | |
576 | break; | |
577 | case 0x98: | |
578 | if (cmd == 0xff) { | |
579 | goto reset_flash; | |
580 | } else { | |
581 | DPRINTF("%s: leaving query mode\n", __func__); | |
582 | } | |
583 | break; | |
584 | default: | |
585 | goto error_flash; | |
586 | } | |
12dabc79 | 587 | break; |
05ee37eb AZ |
588 | case 2: |
589 | switch (pfl->cmd) { | |
590 | case 0xe8: /* Block write */ | |
4dbda935 | 591 | /* FIXME check @offset, @width */ |
de8efe8f | 592 | if (!pfl->ro) { |
4dbda935 MA |
593 | /* |
594 | * FIXME writing straight to memory is *wrong*. We | |
595 | * should write to a buffer, and flush it to memory | |
596 | * only on confirm command (see below). | |
597 | */ | |
de8efe8f JJ |
598 | pflash_data_write(pfl, offset, value, width, be); |
599 | } else { | |
600 | pfl->status |= 0x10; /* Programming error */ | |
601 | } | |
05ee37eb AZ |
602 | |
603 | pfl->status |= 0x80; | |
604 | ||
605 | if (!pfl->counter) { | |
a8170e5e | 606 | hwaddr mask = pfl->writeblock_size - 1; |
b4bf0a9a EI |
607 | mask = ~mask; |
608 | ||
05ee37eb AZ |
609 | DPRINTF("%s: block write finished\n", __func__); |
610 | pfl->wcycle++; | |
de8efe8f JJ |
611 | if (!pfl->ro) { |
612 | /* Flush the entire write buffer onto backing storage. */ | |
4dbda935 | 613 | /* FIXME premature! */ |
de8efe8f JJ |
614 | pflash_update(pfl, offset & mask, pfl->writeblock_size); |
615 | } else { | |
616 | pfl->status |= 0x10; /* Programming error */ | |
617 | } | |
05ee37eb AZ |
618 | } |
619 | ||
620 | pfl->counter--; | |
621 | break; | |
7317b8ca AZ |
622 | default: |
623 | goto error_flash; | |
05ee37eb | 624 | } |
12dabc79 | 625 | break; |
05ee37eb AZ |
626 | case 3: /* Confirm mode */ |
627 | switch (pfl->cmd) { | |
628 | case 0xe8: /* Block write */ | |
629 | if (cmd == 0xd0) { | |
4dbda935 | 630 | /* FIXME this is where we should write out the buffer */ |
05ee37eb AZ |
631 | pfl->wcycle = 0; |
632 | pfl->status |= 0x80; | |
05ee37eb | 633 | } else { |
2d93bebf MA |
634 | qemu_log_mask(LOG_UNIMP, |
635 | "%s: Aborting write to buffer not implemented," | |
636 | " the data is already written to storage!\n" | |
637 | "Flash device reset into READ mode.\n", | |
638 | __func__); | |
7317b8ca | 639 | goto reset_flash; |
05ee37eb | 640 | } |
7317b8ca AZ |
641 | break; |
642 | default: | |
643 | goto error_flash; | |
05ee37eb | 644 | } |
12dabc79 | 645 | break; |
05ee37eb AZ |
646 | default: |
647 | /* Should never happen */ | |
648 | DPRINTF("%s: invalid write state\n", __func__); | |
649 | goto reset_flash; | |
650 | } | |
651 | return; | |
652 | ||
653 | error_flash: | |
d96fc51c PC |
654 | qemu_log_mask(LOG_UNIMP, "%s: Unimplemented flash cmd sequence " |
655 | "(offset " TARGET_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)" | |
656 | "\n", __func__, offset, pfl->wcycle, pfl->cmd, value); | |
05ee37eb AZ |
657 | |
658 | reset_flash: | |
13019f1f | 659 | trace_pflash_reset(); |
5f9a5ea1 | 660 | memory_region_rom_device_set_romd(&pfl->mem, true); |
05ee37eb AZ |
661 | pfl->wcycle = 0; |
662 | pfl->cmd = 0; | |
05ee37eb AZ |
663 | } |
664 | ||
665 | ||
f71e42a5 PB |
666 | static MemTxResult pflash_mem_read_with_attrs(void *opaque, hwaddr addr, uint64_t *value, |
667 | unsigned len, MemTxAttrs attrs) | |
3d08ff69 | 668 | { |
16434065 | 669 | PFlashCFI01 *pfl = opaque; |
5aa113f0 | 670 | bool be = !!(pfl->features & (1 << PFLASH_BE)); |
3d08ff69 | 671 | |
f71e42a5 PB |
672 | if ((pfl->features & (1 << PFLASH_SECURE)) && !attrs.secure) { |
673 | *value = pflash_data_read(opaque, addr, len, be); | |
674 | } else { | |
675 | *value = pflash_read(opaque, addr, len, be); | |
676 | } | |
677 | return MEMTX_OK; | |
3d08ff69 BS |
678 | } |
679 | ||
f71e42a5 PB |
680 | static MemTxResult pflash_mem_write_with_attrs(void *opaque, hwaddr addr, uint64_t value, |
681 | unsigned len, MemTxAttrs attrs) | |
05ee37eb | 682 | { |
16434065 | 683 | PFlashCFI01 *pfl = opaque; |
5aa113f0 | 684 | bool be = !!(pfl->features & (1 << PFLASH_BE)); |
3d08ff69 | 685 | |
f71e42a5 PB |
686 | if ((pfl->features & (1 << PFLASH_SECURE)) && !attrs.secure) { |
687 | return MEMTX_ERROR; | |
688 | } else { | |
689 | pflash_write(opaque, addr, value, len, be); | |
690 | return MEMTX_OK; | |
691 | } | |
05ee37eb AZ |
692 | } |
693 | ||
5aa113f0 | 694 | static const MemoryRegionOps pflash_cfi01_ops = { |
f71e42a5 PB |
695 | .read_with_attrs = pflash_mem_read_with_attrs, |
696 | .write_with_attrs = pflash_mem_write_with_attrs, | |
cfe5f011 | 697 | .endianness = DEVICE_NATIVE_ENDIAN, |
05ee37eb AZ |
698 | }; |
699 | ||
e40b5f3e | 700 | static void pflash_cfi01_realize(DeviceState *dev, Error **errp) |
05ee37eb | 701 | { |
e7b62741 | 702 | PFlashCFI01 *pfl = PFLASH_CFI01(dev); |
368a354f | 703 | uint64_t total_len; |
d0e7605e | 704 | int ret; |
feb0b1aa | 705 | uint64_t blocks_per_device, sector_len_per_device, device_len; |
a0289b8a | 706 | int num_devices; |
33e0eb52 | 707 | Error *local_err = NULL; |
05ee37eb | 708 | |
8929fc3a ZY |
709 | if (pfl->sector_len == 0) { |
710 | error_setg(errp, "attribute \"sector-length\" not specified or zero."); | |
711 | return; | |
712 | } | |
713 | if (pfl->nb_blocs == 0) { | |
714 | error_setg(errp, "attribute \"num-blocks\" not specified or zero."); | |
715 | return; | |
716 | } | |
717 | if (pfl->name == NULL) { | |
718 | error_setg(errp, "attribute \"name\" not specified."); | |
719 | return; | |
720 | } | |
721 | ||
368a354f | 722 | total_len = pfl->sector_len * pfl->nb_blocs; |
05ee37eb | 723 | |
a0289b8a PM |
724 | /* These are only used to expose the parameters of each device |
725 | * in the cfi_table[]. | |
726 | */ | |
727 | num_devices = pfl->device_width ? (pfl->bank_width / pfl->device_width) : 1; | |
feb0b1aa PM |
728 | if (pfl->old_multiple_chip_handling) { |
729 | blocks_per_device = pfl->nb_blocs / num_devices; | |
730 | sector_len_per_device = pfl->sector_len; | |
731 | } else { | |
732 | blocks_per_device = pfl->nb_blocs; | |
733 | sector_len_per_device = pfl->sector_len / num_devices; | |
734 | } | |
735 | device_len = sector_len_per_device * blocks_per_device; | |
a0289b8a | 736 | |
bba3ddf7 | 737 | memory_region_init_rom_device( |
2d256e6f | 738 | &pfl->mem, OBJECT(dev), |
5aa113f0 | 739 | &pflash_cfi01_ops, |
e9809422 | 740 | pfl, |
33e0eb52 HT |
741 | pfl->name, total_len, &local_err); |
742 | if (local_err) { | |
743 | error_propagate(errp, local_err); | |
744 | return; | |
745 | } | |
746 | ||
cfe5f011 | 747 | pfl->storage = memory_region_get_ram_ptr(&pfl->mem); |
e40b5f3e | 748 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem); |
05ee37eb | 749 | |
a17c17a2 KW |
750 | if (pfl->blk) { |
751 | uint64_t perm; | |
752 | pfl->ro = blk_is_read_only(pfl->blk); | |
753 | perm = BLK_PERM_CONSISTENT_READ | (pfl->ro ? 0 : BLK_PERM_WRITE); | |
754 | ret = blk_set_perm(pfl->blk, perm, BLK_PERM_ALL, errp); | |
755 | if (ret < 0) { | |
756 | return; | |
757 | } | |
758 | } else { | |
759 | pfl->ro = 0; | |
760 | } | |
761 | ||
4be74634 | 762 | if (pfl->blk) { |
06f15217 MA |
763 | if (!blk_check_size_and_read_all(pfl->blk, pfl->storage, total_len, |
764 | errp)) { | |
368a354f | 765 | vmstate_unregister_ram(&pfl->mem, DEVICE(pfl)); |
e40b5f3e | 766 | return; |
d0e7605e | 767 | } |
05ee37eb | 768 | } |
de8efe8f | 769 | |
fa21a7b1 RF |
770 | /* Default to devices being used at their maximum device width. This was |
771 | * assumed before the device_width support was added. | |
772 | */ | |
773 | if (!pfl->max_device_width) { | |
774 | pfl->max_device_width = pfl->device_width; | |
775 | } | |
776 | ||
bc72ad67 | 777 | pfl->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pflash_timer, pfl); |
05ee37eb AZ |
778 | pfl->wcycle = 0; |
779 | pfl->cmd = 0; | |
780 | pfl->status = 0; | |
05ee37eb | 781 | /* Hardcoded CFI table */ |
05ee37eb AZ |
782 | /* Standard "QRY" string */ |
783 | pfl->cfi_table[0x10] = 'Q'; | |
784 | pfl->cfi_table[0x11] = 'R'; | |
785 | pfl->cfi_table[0x12] = 'Y'; | |
786 | /* Command set (Intel) */ | |
787 | pfl->cfi_table[0x13] = 0x01; | |
788 | pfl->cfi_table[0x14] = 0x00; | |
789 | /* Primary extended table address (none) */ | |
790 | pfl->cfi_table[0x15] = 0x31; | |
791 | pfl->cfi_table[0x16] = 0x00; | |
792 | /* Alternate command set (none) */ | |
793 | pfl->cfi_table[0x17] = 0x00; | |
794 | pfl->cfi_table[0x18] = 0x00; | |
795 | /* Alternate extended table (none) */ | |
796 | pfl->cfi_table[0x19] = 0x00; | |
797 | pfl->cfi_table[0x1A] = 0x00; | |
798 | /* Vcc min */ | |
799 | pfl->cfi_table[0x1B] = 0x45; | |
800 | /* Vcc max */ | |
801 | pfl->cfi_table[0x1C] = 0x55; | |
802 | /* Vpp min (no Vpp pin) */ | |
803 | pfl->cfi_table[0x1D] = 0x00; | |
804 | /* Vpp max (no Vpp pin) */ | |
805 | pfl->cfi_table[0x1E] = 0x00; | |
806 | /* Reserved */ | |
807 | pfl->cfi_table[0x1F] = 0x07; | |
808 | /* Timeout for min size buffer write */ | |
809 | pfl->cfi_table[0x20] = 0x07; | |
810 | /* Typical timeout for block erase */ | |
811 | pfl->cfi_table[0x21] = 0x0a; | |
812 | /* Typical timeout for full chip erase (4096 ms) */ | |
813 | pfl->cfi_table[0x22] = 0x00; | |
814 | /* Reserved */ | |
815 | pfl->cfi_table[0x23] = 0x04; | |
816 | /* Max timeout for buffer write */ | |
817 | pfl->cfi_table[0x24] = 0x04; | |
818 | /* Max timeout for block erase */ | |
819 | pfl->cfi_table[0x25] = 0x04; | |
820 | /* Max timeout for chip erase */ | |
821 | pfl->cfi_table[0x26] = 0x00; | |
822 | /* Device size */ | |
a0289b8a | 823 | pfl->cfi_table[0x27] = ctz32(device_len); /* + 1; */ |
05ee37eb AZ |
824 | /* Flash device interface (8 & 16 bits) */ |
825 | pfl->cfi_table[0x28] = 0x02; | |
826 | pfl->cfi_table[0x29] = 0x00; | |
827 | /* Max number of bytes in multi-bytes write */ | |
4b6fedca | 828 | if (pfl->bank_width == 1) { |
4737fa26 EI |
829 | pfl->cfi_table[0x2A] = 0x08; |
830 | } else { | |
831 | pfl->cfi_table[0x2A] = 0x0B; | |
832 | } | |
b4bf0a9a | 833 | pfl->writeblock_size = 1 << pfl->cfi_table[0x2A]; |
feb0b1aa PM |
834 | if (!pfl->old_multiple_chip_handling && num_devices > 1) { |
835 | pfl->writeblock_size *= num_devices; | |
836 | } | |
b4bf0a9a | 837 | |
05ee37eb AZ |
838 | pfl->cfi_table[0x2B] = 0x00; |
839 | /* Number of erase block regions (uniform) */ | |
840 | pfl->cfi_table[0x2C] = 0x01; | |
841 | /* Erase block region 1 */ | |
a0289b8a PM |
842 | pfl->cfi_table[0x2D] = blocks_per_device - 1; |
843 | pfl->cfi_table[0x2E] = (blocks_per_device - 1) >> 8; | |
feb0b1aa PM |
844 | pfl->cfi_table[0x2F] = sector_len_per_device >> 8; |
845 | pfl->cfi_table[0x30] = sector_len_per_device >> 16; | |
05ee37eb AZ |
846 | |
847 | /* Extended */ | |
848 | pfl->cfi_table[0x31] = 'P'; | |
849 | pfl->cfi_table[0x32] = 'R'; | |
850 | pfl->cfi_table[0x33] = 'I'; | |
851 | ||
852 | pfl->cfi_table[0x34] = '1'; | |
262e1eaa | 853 | pfl->cfi_table[0x35] = '0'; |
05ee37eb AZ |
854 | |
855 | pfl->cfi_table[0x36] = 0x00; | |
856 | pfl->cfi_table[0x37] = 0x00; | |
857 | pfl->cfi_table[0x38] = 0x00; | |
858 | pfl->cfi_table[0x39] = 0x00; | |
859 | ||
860 | pfl->cfi_table[0x3a] = 0x00; | |
861 | ||
862 | pfl->cfi_table[0x3b] = 0x00; | |
863 | pfl->cfi_table[0x3c] = 0x00; | |
864 | ||
262e1eaa | 865 | pfl->cfi_table[0x3f] = 0x01; /* Number of protection fields */ |
368a354f PC |
866 | } |
867 | ||
868 | static Property pflash_cfi01_properties[] = { | |
16434065 | 869 | DEFINE_PROP_DRIVE("drive", PFlashCFI01, blk), |
a0289b8a PM |
870 | /* num-blocks is the number of blocks actually visible to the guest, |
871 | * ie the total size of the device divided by the sector length. | |
872 | * If we're emulating flash devices wired in parallel the actual | |
873 | * number of blocks per indvidual device will differ. | |
874 | */ | |
16434065 MA |
875 | DEFINE_PROP_UINT32("num-blocks", PFlashCFI01, nb_blocs, 0), |
876 | DEFINE_PROP_UINT64("sector-length", PFlashCFI01, sector_len, 0), | |
fa21a7b1 RF |
877 | /* width here is the overall width of this QEMU device in bytes. |
878 | * The QEMU device may be emulating a number of flash devices | |
879 | * wired up in parallel; the width of each individual flash | |
880 | * device should be specified via device-width. If the individual | |
881 | * devices have a maximum width which is greater than the width | |
882 | * they are being used for, this maximum width should be set via | |
883 | * max-device-width (which otherwise defaults to device-width). | |
884 | * So for instance a 32-bit wide QEMU flash device made from four | |
885 | * 16-bit flash devices used in 8-bit wide mode would be configured | |
886 | * with width = 4, device-width = 1, max-device-width = 2. | |
887 | * | |
888 | * If device-width is not specified we default to backwards | |
889 | * compatible behaviour which is a bad emulation of two | |
890 | * 16 bit devices making up a 32 bit wide QEMU device. This | |
891 | * is deprecated for new uses of this device. | |
892 | */ | |
16434065 MA |
893 | DEFINE_PROP_UINT8("width", PFlashCFI01, bank_width, 0), |
894 | DEFINE_PROP_UINT8("device-width", PFlashCFI01, device_width, 0), | |
895 | DEFINE_PROP_UINT8("max-device-width", PFlashCFI01, max_device_width, 0), | |
896 | DEFINE_PROP_BIT("big-endian", PFlashCFI01, features, PFLASH_BE, 0), | |
897 | DEFINE_PROP_BIT("secure", PFlashCFI01, features, PFLASH_SECURE, 0), | |
898 | DEFINE_PROP_UINT16("id0", PFlashCFI01, ident0, 0), | |
899 | DEFINE_PROP_UINT16("id1", PFlashCFI01, ident1, 0), | |
900 | DEFINE_PROP_UINT16("id2", PFlashCFI01, ident2, 0), | |
901 | DEFINE_PROP_UINT16("id3", PFlashCFI01, ident3, 0), | |
902 | DEFINE_PROP_STRING("name", PFlashCFI01, name), | |
903 | DEFINE_PROP_BOOL("old-multiple-chip-handling", PFlashCFI01, | |
feb0b1aa | 904 | old_multiple_chip_handling, false), |
368a354f PC |
905 | DEFINE_PROP_END_OF_LIST(), |
906 | }; | |
907 | ||
908 | static void pflash_cfi01_class_init(ObjectClass *klass, void *data) | |
909 | { | |
910 | DeviceClass *dc = DEVICE_CLASS(klass); | |
368a354f | 911 | |
e40b5f3e | 912 | dc->realize = pflash_cfi01_realize; |
368a354f | 913 | dc->props = pflash_cfi01_properties; |
d8d24fb7 | 914 | dc->vmsd = &vmstate_pflash; |
125ee0ed | 915 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
368a354f PC |
916 | } |
917 | ||
918 | ||
919 | static const TypeInfo pflash_cfi01_info = { | |
e7b62741 | 920 | .name = TYPE_PFLASH_CFI01, |
368a354f | 921 | .parent = TYPE_SYS_BUS_DEVICE, |
16434065 | 922 | .instance_size = sizeof(PFlashCFI01), |
368a354f PC |
923 | .class_init = pflash_cfi01_class_init, |
924 | }; | |
925 | ||
926 | static void pflash_cfi01_register_types(void) | |
927 | { | |
928 | type_register_static(&pflash_cfi01_info); | |
929 | } | |
930 | ||
931 | type_init(pflash_cfi01_register_types) | |
932 | ||
16434065 | 933 | PFlashCFI01 *pflash_cfi01_register(hwaddr base, |
940d5b13 | 934 | const char *name, |
16434065 MA |
935 | hwaddr size, |
936 | BlockBackend *blk, | |
ce14710f | 937 | uint32_t sector_len, |
16434065 MA |
938 | int bank_width, |
939 | uint16_t id0, uint16_t id1, | |
940 | uint16_t id2, uint16_t id3, | |
941 | int be) | |
368a354f | 942 | { |
e7b62741 | 943 | DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01); |
368a354f | 944 | |
9b3d111a MA |
945 | if (blk) { |
946 | qdev_prop_set_drive(dev, "drive", blk, &error_abort); | |
368a354f | 947 | } |
ce14710f MA |
948 | assert(size % sector_len == 0); |
949 | qdev_prop_set_uint32(dev, "num-blocks", size / sector_len); | |
368a354f | 950 | qdev_prop_set_uint64(dev, "sector-length", sector_len); |
4b6fedca | 951 | qdev_prop_set_uint8(dev, "width", bank_width); |
e9809422 | 952 | qdev_prop_set_bit(dev, "big-endian", !!be); |
368a354f PC |
953 | qdev_prop_set_uint16(dev, "id0", id0); |
954 | qdev_prop_set_uint16(dev, "id1", id1); | |
955 | qdev_prop_set_uint16(dev, "id2", id2); | |
956 | qdev_prop_set_uint16(dev, "id3", id3); | |
957 | qdev_prop_set_string(dev, "name", name); | |
958 | qdev_init_nofail(dev); | |
959 | ||
f1b44f0e | 960 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); |
e7b62741 | 961 | return PFLASH_CFI01(dev); |
05ee37eb | 962 | } |
cfe5f011 | 963 | |
e60cf765 PMD |
964 | BlockBackend *pflash_cfi01_get_blk(PFlashCFI01 *fl) |
965 | { | |
966 | return fl->blk; | |
967 | } | |
968 | ||
16434065 | 969 | MemoryRegion *pflash_cfi01_get_memory(PFlashCFI01 *fl) |
cfe5f011 AK |
970 | { |
971 | return &fl->mem; | |
972 | } | |
4c0cfc72 | 973 | |
2d731dbd MA |
974 | /* |
975 | * Handle -drive if=pflash for machines that use properties. | |
976 | * If @dinfo is null, do nothing. | |
977 | * Else if @fl's property "drive" is already set, fatal error. | |
978 | * Else set it to the BlockBackend with @dinfo. | |
979 | */ | |
980 | void pflash_cfi01_legacy_drive(PFlashCFI01 *fl, DriveInfo *dinfo) | |
981 | { | |
982 | Location loc; | |
983 | ||
984 | if (!dinfo) { | |
985 | return; | |
986 | } | |
987 | ||
988 | loc_push_none(&loc); | |
989 | qemu_opts_loc_restore(dinfo->opts); | |
990 | if (fl->blk) { | |
991 | error_report("clashes with -machine"); | |
992 | exit(1); | |
993 | } | |
994 | qdev_prop_set_drive(DEVICE(fl), "drive", | |
995 | blk_by_legacy_dinfo(dinfo), &error_fatal); | |
996 | loc_pop(&loc); | |
997 | } | |
998 | ||
90c647db DDAG |
999 | static void postload_update_cb(void *opaque, int running, RunState state) |
1000 | { | |
16434065 | 1001 | PFlashCFI01 *pfl = opaque; |
90c647db DDAG |
1002 | |
1003 | /* This is called after bdrv_invalidate_cache_all. */ | |
1004 | qemu_del_vm_change_state_handler(pfl->vmstate); | |
1005 | pfl->vmstate = NULL; | |
1006 | ||
1007 | DPRINTF("%s: updating bdrv for %s\n", __func__, pfl->name); | |
1008 | pflash_update(pfl, 0, pfl->sector_len * pfl->nb_blocs); | |
1009 | } | |
1010 | ||
4c0cfc72 LE |
1011 | static int pflash_post_load(void *opaque, int version_id) |
1012 | { | |
16434065 | 1013 | PFlashCFI01 *pfl = opaque; |
4c0cfc72 LE |
1014 | |
1015 | if (!pfl->ro) { | |
90c647db DDAG |
1016 | pfl->vmstate = qemu_add_vm_change_state_handler(postload_update_cb, |
1017 | pfl); | |
4c0cfc72 LE |
1018 | } |
1019 | return 0; | |
1020 | } |