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Commit | Line | Data |
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05ee37eb AZ |
1 | /* |
2 | * CFI parallel flash with Intel command set emulation | |
3 | * | |
4 | * Copyright (c) 2006 Thorsten Zitterell | |
5 | * Copyright (c) 2005 Jocelyn Mayer | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
05ee37eb AZ |
19 | */ |
20 | ||
21 | /* | |
22 | * For now, this code can emulate flashes of 1, 2 or 4 bytes width. | |
23 | * Supported commands/modes are: | |
24 | * - flash read | |
25 | * - flash write | |
26 | * - flash ID read | |
27 | * - sector erase | |
28 | * - CFI queries | |
29 | * | |
30 | * It does not support timings | |
31 | * It does not support flash interleaving | |
32 | * It does not implement software data protection as found in many real chips | |
33 | * It does not implement erase suspend/resume commands | |
34 | * It does not implement multiple sectors erase | |
35 | * | |
36 | * It does not implement much more ... | |
37 | */ | |
38 | ||
83c9f4ca | 39 | #include "hw/hw.h" |
0d09e41a | 40 | #include "hw/block/flash.h" |
737e150e | 41 | #include "block/block.h" |
1de7afc9 | 42 | #include "qemu/timer.h" |
022c62cb | 43 | #include "exec/address-spaces.h" |
1de7afc9 | 44 | #include "qemu/host-utils.h" |
83c9f4ca | 45 | #include "hw/sysbus.h" |
05ee37eb | 46 | |
001faf32 | 47 | #define PFLASH_BUG(fmt, ...) \ |
05ee37eb | 48 | do { \ |
ec9ea489 | 49 | fprintf(stderr, "PFLASH: Possible BUG - " fmt, ## __VA_ARGS__); \ |
05ee37eb AZ |
50 | exit(1); \ |
51 | } while(0) | |
52 | ||
53 | /* #define PFLASH_DEBUG */ | |
54 | #ifdef PFLASH_DEBUG | |
ec9ea489 PC |
55 | #define DPRINTF(fmt, ...) \ |
56 | do { \ | |
57 | fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__); \ | |
05ee37eb AZ |
58 | } while (0) |
59 | #else | |
001faf32 | 60 | #define DPRINTF(fmt, ...) do { } while (0) |
05ee37eb AZ |
61 | #endif |
62 | ||
f1b44f0e HT |
63 | #define TYPE_CFI_PFLASH01 "cfi.pflash01" |
64 | #define CFI_PFLASH01(obj) OBJECT_CHECK(pflash_t, (obj), TYPE_CFI_PFLASH01) | |
65 | ||
c227f099 | 66 | struct pflash_t { |
f1b44f0e HT |
67 | /*< private >*/ |
68 | SysBusDevice parent_obj; | |
69 | /*< public >*/ | |
70 | ||
05ee37eb | 71 | BlockDriverState *bs; |
368a354f PC |
72 | uint32_t nb_blocs; |
73 | uint64_t sector_len; | |
74 | uint8_t width; | |
75 | uint8_t be; | |
d8d24fb7 | 76 | uint8_t wcycle; /* if 0, the flash is read normally */ |
05ee37eb AZ |
77 | int ro; |
78 | uint8_t cmd; | |
79 | uint8_t status; | |
368a354f PC |
80 | uint16_t ident0; |
81 | uint16_t ident1; | |
82 | uint16_t ident2; | |
83 | uint16_t ident3; | |
05ee37eb AZ |
84 | uint8_t cfi_len; |
85 | uint8_t cfi_table[0x52]; | |
d8d24fb7 | 86 | uint64_t counter; |
b4bf0a9a | 87 | unsigned int writeblock_size; |
05ee37eb | 88 | QEMUTimer *timer; |
cfe5f011 | 89 | MemoryRegion mem; |
368a354f | 90 | char *name; |
05ee37eb AZ |
91 | void *storage; |
92 | }; | |
93 | ||
d8d24fb7 PM |
94 | static const VMStateDescription vmstate_pflash = { |
95 | .name = "pflash_cfi01", | |
96 | .version_id = 1, | |
97 | .minimum_version_id = 1, | |
98 | .fields = (VMStateField[]) { | |
99 | VMSTATE_UINT8(wcycle, pflash_t), | |
100 | VMSTATE_UINT8(cmd, pflash_t), | |
101 | VMSTATE_UINT8(status, pflash_t), | |
102 | VMSTATE_UINT64(counter, pflash_t), | |
103 | VMSTATE_END_OF_LIST() | |
104 | } | |
105 | }; | |
106 | ||
05ee37eb AZ |
107 | static void pflash_timer (void *opaque) |
108 | { | |
c227f099 | 109 | pflash_t *pfl = opaque; |
05ee37eb AZ |
110 | |
111 | DPRINTF("%s: command %02x done\n", __func__, pfl->cmd); | |
112 | /* Reset flash */ | |
113 | pfl->status ^= 0x80; | |
5f9a5ea1 | 114 | memory_region_rom_device_set_romd(&pfl->mem, true); |
5d79b80b | 115 | pfl->wcycle = 0; |
05ee37eb AZ |
116 | pfl->cmd = 0; |
117 | } | |
118 | ||
a8170e5e | 119 | static uint32_t pflash_read (pflash_t *pfl, hwaddr offset, |
3d08ff69 | 120 | int width, int be) |
05ee37eb | 121 | { |
a8170e5e | 122 | hwaddr boff; |
05ee37eb AZ |
123 | uint32_t ret; |
124 | uint8_t *p; | |
125 | ||
126 | ret = -1; | |
05ee37eb AZ |
127 | boff = offset & 0xFF; /* why this here ?? */ |
128 | ||
129 | if (pfl->width == 2) | |
130 | boff = boff >> 1; | |
131 | else if (pfl->width == 4) | |
132 | boff = boff >> 2; | |
133 | ||
fad8c772 EI |
134 | #if 0 |
135 | DPRINTF("%s: reading offset " TARGET_FMT_plx " under cmd %02x width %d\n", | |
06adb549 | 136 | __func__, offset, pfl->cmd, width); |
fad8c772 | 137 | #endif |
05ee37eb | 138 | switch (pfl->cmd) { |
1be97bf2 PM |
139 | default: |
140 | /* This should never happen : reset state & treat it as a read */ | |
141 | DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd); | |
142 | pfl->wcycle = 0; | |
143 | pfl->cmd = 0; | |
144 | /* fall through to read code */ | |
05ee37eb AZ |
145 | case 0x00: |
146 | /* Flash area read */ | |
147 | p = pfl->storage; | |
148 | switch (width) { | |
149 | case 1: | |
150 | ret = p[offset]; | |
fad8c772 | 151 | DPRINTF("%s: data offset " TARGET_FMT_plx " %02x\n", |
c8b153d7 | 152 | __func__, offset, ret); |
05ee37eb AZ |
153 | break; |
154 | case 2: | |
3d08ff69 BS |
155 | if (be) { |
156 | ret = p[offset] << 8; | |
157 | ret |= p[offset + 1]; | |
158 | } else { | |
159 | ret = p[offset]; | |
160 | ret |= p[offset + 1] << 8; | |
161 | } | |
fad8c772 | 162 | DPRINTF("%s: data offset " TARGET_FMT_plx " %04x\n", |
c8b153d7 | 163 | __func__, offset, ret); |
05ee37eb AZ |
164 | break; |
165 | case 4: | |
3d08ff69 BS |
166 | if (be) { |
167 | ret = p[offset] << 24; | |
168 | ret |= p[offset + 1] << 16; | |
169 | ret |= p[offset + 2] << 8; | |
170 | ret |= p[offset + 3]; | |
171 | } else { | |
172 | ret = p[offset]; | |
173 | ret |= p[offset + 1] << 8; | |
3d08ff69 BS |
174 | ret |= p[offset + 2] << 16; |
175 | ret |= p[offset + 3] << 24; | |
176 | } | |
fad8c772 | 177 | DPRINTF("%s: data offset " TARGET_FMT_plx " %08x\n", |
c8b153d7 | 178 | __func__, offset, ret); |
05ee37eb AZ |
179 | break; |
180 | default: | |
181 | DPRINTF("BUG in %s\n", __func__); | |
182 | } | |
183 | ||
184 | break; | |
6e392787 | 185 | case 0x10: /* Single byte program */ |
05ee37eb | 186 | case 0x20: /* Block erase */ |
6e392787 PM |
187 | case 0x28: /* Block erase */ |
188 | case 0x40: /* single byte program */ | |
05ee37eb AZ |
189 | case 0x50: /* Clear status register */ |
190 | case 0x60: /* Block /un)lock */ | |
191 | case 0x70: /* Status Register */ | |
192 | case 0xe8: /* Write block */ | |
193 | /* Status register read */ | |
194 | ret = pfl->status; | |
195 | DPRINTF("%s: status %x\n", __func__, ret); | |
196 | break; | |
0b2ec6fc MW |
197 | case 0x90: |
198 | switch (boff) { | |
199 | case 0: | |
368a354f | 200 | ret = pfl->ident0 << 8 | pfl->ident1; |
0b2ec6fc MW |
201 | DPRINTF("%s: Manufacturer Code %04x\n", __func__, ret); |
202 | break; | |
203 | case 1: | |
368a354f | 204 | ret = pfl->ident2 << 8 | pfl->ident3; |
0b2ec6fc MW |
205 | DPRINTF("%s: Device ID Code %04x\n", __func__, ret); |
206 | break; | |
207 | default: | |
fc5b64d0 PC |
208 | DPRINTF("%s: Read Device Information boff=%x\n", __func__, |
209 | (unsigned)boff); | |
0b2ec6fc MW |
210 | ret = 0; |
211 | break; | |
212 | } | |
213 | break; | |
05ee37eb AZ |
214 | case 0x98: /* Query mode */ |
215 | if (boff > pfl->cfi_len) | |
216 | ret = 0; | |
217 | else | |
218 | ret = pfl->cfi_table[boff]; | |
219 | break; | |
05ee37eb AZ |
220 | } |
221 | return ret; | |
222 | } | |
223 | ||
224 | /* update flash content on disk */ | |
c227f099 | 225 | static void pflash_update(pflash_t *pfl, int offset, |
05ee37eb AZ |
226 | int size) |
227 | { | |
228 | int offset_end; | |
229 | if (pfl->bs) { | |
230 | offset_end = offset + size; | |
231 | /* round to sectors */ | |
232 | offset = offset >> 9; | |
233 | offset_end = (offset_end + 511) >> 9; | |
234 | bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9), | |
235 | offset_end - offset); | |
236 | } | |
237 | } | |
238 | ||
a8170e5e | 239 | static inline void pflash_data_write(pflash_t *pfl, hwaddr offset, |
3d08ff69 | 240 | uint32_t value, int width, int be) |
d361be25 AZ |
241 | { |
242 | uint8_t *p = pfl->storage; | |
243 | ||
fad8c772 | 244 | DPRINTF("%s: block write offset " TARGET_FMT_plx |
d8d24fb7 | 245 | " value %x counter %016" PRIx64 "\n", |
d361be25 AZ |
246 | __func__, offset, value, pfl->counter); |
247 | switch (width) { | |
248 | case 1: | |
249 | p[offset] = value; | |
d361be25 AZ |
250 | break; |
251 | case 2: | |
3d08ff69 BS |
252 | if (be) { |
253 | p[offset] = value >> 8; | |
254 | p[offset + 1] = value; | |
255 | } else { | |
256 | p[offset] = value; | |
257 | p[offset + 1] = value >> 8; | |
258 | } | |
d361be25 AZ |
259 | break; |
260 | case 4: | |
3d08ff69 BS |
261 | if (be) { |
262 | p[offset] = value >> 24; | |
263 | p[offset + 1] = value >> 16; | |
264 | p[offset + 2] = value >> 8; | |
265 | p[offset + 3] = value; | |
266 | } else { | |
267 | p[offset] = value; | |
268 | p[offset + 1] = value >> 8; | |
269 | p[offset + 2] = value >> 16; | |
270 | p[offset + 3] = value >> 24; | |
271 | } | |
d361be25 AZ |
272 | break; |
273 | } | |
274 | ||
275 | } | |
276 | ||
a8170e5e | 277 | static void pflash_write(pflash_t *pfl, hwaddr offset, |
3d08ff69 | 278 | uint32_t value, int width, int be) |
05ee37eb | 279 | { |
05ee37eb AZ |
280 | uint8_t *p; |
281 | uint8_t cmd; | |
282 | ||
05ee37eb | 283 | cmd = value; |
05ee37eb | 284 | |
fad8c772 | 285 | DPRINTF("%s: writing offset " TARGET_FMT_plx " value %08x width %d wcycle 0x%x\n", |
c8b153d7 | 286 | __func__, offset, value, width, pfl->wcycle); |
05ee37eb | 287 | |
e9cbbcac EI |
288 | if (!pfl->wcycle) { |
289 | /* Set the device in I/O access mode */ | |
5f9a5ea1 | 290 | memory_region_rom_device_set_romd(&pfl->mem, false); |
e9cbbcac | 291 | } |
05ee37eb AZ |
292 | |
293 | switch (pfl->wcycle) { | |
294 | case 0: | |
295 | /* read mode */ | |
296 | switch (cmd) { | |
297 | case 0x00: /* ??? */ | |
298 | goto reset_flash; | |
d361be25 AZ |
299 | case 0x10: /* Single Byte Program */ |
300 | case 0x40: /* Single Byte Program */ | |
fad8c772 | 301 | DPRINTF("%s: Single Byte Program\n", __func__); |
d361be25 | 302 | break; |
05ee37eb AZ |
303 | case 0x20: /* Block erase */ |
304 | p = pfl->storage; | |
305 | offset &= ~(pfl->sector_len - 1); | |
306 | ||
368a354f PC |
307 | DPRINTF("%s: block erase at " TARGET_FMT_plx " bytes %x\n", |
308 | __func__, offset, (unsigned)pfl->sector_len); | |
05ee37eb | 309 | |
de8efe8f JJ |
310 | if (!pfl->ro) { |
311 | memset(p + offset, 0xff, pfl->sector_len); | |
312 | pflash_update(pfl, offset, pfl->sector_len); | |
313 | } else { | |
314 | pfl->status |= 0x20; /* Block erase error */ | |
315 | } | |
05ee37eb AZ |
316 | pfl->status |= 0x80; /* Ready! */ |
317 | break; | |
318 | case 0x50: /* Clear status bits */ | |
319 | DPRINTF("%s: Clear status bits\n", __func__); | |
320 | pfl->status = 0x0; | |
321 | goto reset_flash; | |
322 | case 0x60: /* Block (un)lock */ | |
323 | DPRINTF("%s: Block unlock\n", __func__); | |
324 | break; | |
325 | case 0x70: /* Status Register */ | |
326 | DPRINTF("%s: Read status register\n", __func__); | |
327 | pfl->cmd = cmd; | |
328 | return; | |
0b2ec6fc MW |
329 | case 0x90: /* Read Device ID */ |
330 | DPRINTF("%s: Read Device information\n", __func__); | |
331 | pfl->cmd = cmd; | |
332 | return; | |
05ee37eb AZ |
333 | case 0x98: /* CFI query */ |
334 | DPRINTF("%s: CFI query\n", __func__); | |
335 | break; | |
336 | case 0xe8: /* Write to buffer */ | |
337 | DPRINTF("%s: Write to buffer\n", __func__); | |
338 | pfl->status |= 0x80; /* Ready! */ | |
339 | break; | |
5928023c SW |
340 | case 0xf0: /* Probe for AMD flash */ |
341 | DPRINTF("%s: Probe for AMD flash\n", __func__); | |
342 | goto reset_flash; | |
05ee37eb AZ |
343 | case 0xff: /* Read array mode */ |
344 | DPRINTF("%s: Read array mode\n", __func__); | |
345 | goto reset_flash; | |
346 | default: | |
347 | goto error_flash; | |
348 | } | |
349 | pfl->wcycle++; | |
350 | pfl->cmd = cmd; | |
12dabc79 | 351 | break; |
05ee37eb AZ |
352 | case 1: |
353 | switch (pfl->cmd) { | |
d361be25 AZ |
354 | case 0x10: /* Single Byte Program */ |
355 | case 0x40: /* Single Byte Program */ | |
356 | DPRINTF("%s: Single Byte Program\n", __func__); | |
de8efe8f JJ |
357 | if (!pfl->ro) { |
358 | pflash_data_write(pfl, offset, value, width, be); | |
359 | pflash_update(pfl, offset, width); | |
360 | } else { | |
361 | pfl->status |= 0x10; /* Programming error */ | |
362 | } | |
d361be25 AZ |
363 | pfl->status |= 0x80; /* Ready! */ |
364 | pfl->wcycle = 0; | |
365 | break; | |
05ee37eb AZ |
366 | case 0x20: /* Block erase */ |
367 | case 0x28: | |
368 | if (cmd == 0xd0) { /* confirm */ | |
3656744c | 369 | pfl->wcycle = 0; |
05ee37eb | 370 | pfl->status |= 0x80; |
9248f413 | 371 | } else if (cmd == 0xff) { /* read array mode */ |
05ee37eb AZ |
372 | goto reset_flash; |
373 | } else | |
374 | goto error_flash; | |
375 | ||
376 | break; | |
377 | case 0xe8: | |
71fb2348 AZ |
378 | DPRINTF("%s: block write of %x bytes\n", __func__, value); |
379 | pfl->counter = value; | |
05ee37eb AZ |
380 | pfl->wcycle++; |
381 | break; | |
382 | case 0x60: | |
383 | if (cmd == 0xd0) { | |
384 | pfl->wcycle = 0; | |
385 | pfl->status |= 0x80; | |
386 | } else if (cmd == 0x01) { | |
387 | pfl->wcycle = 0; | |
388 | pfl->status |= 0x80; | |
389 | } else if (cmd == 0xff) { | |
390 | goto reset_flash; | |
391 | } else { | |
392 | DPRINTF("%s: Unknown (un)locking command\n", __func__); | |
393 | goto reset_flash; | |
394 | } | |
395 | break; | |
396 | case 0x98: | |
397 | if (cmd == 0xff) { | |
398 | goto reset_flash; | |
399 | } else { | |
400 | DPRINTF("%s: leaving query mode\n", __func__); | |
401 | } | |
402 | break; | |
403 | default: | |
404 | goto error_flash; | |
405 | } | |
12dabc79 | 406 | break; |
05ee37eb AZ |
407 | case 2: |
408 | switch (pfl->cmd) { | |
409 | case 0xe8: /* Block write */ | |
de8efe8f JJ |
410 | if (!pfl->ro) { |
411 | pflash_data_write(pfl, offset, value, width, be); | |
412 | } else { | |
413 | pfl->status |= 0x10; /* Programming error */ | |
414 | } | |
05ee37eb AZ |
415 | |
416 | pfl->status |= 0x80; | |
417 | ||
418 | if (!pfl->counter) { | |
a8170e5e | 419 | hwaddr mask = pfl->writeblock_size - 1; |
b4bf0a9a EI |
420 | mask = ~mask; |
421 | ||
05ee37eb AZ |
422 | DPRINTF("%s: block write finished\n", __func__); |
423 | pfl->wcycle++; | |
de8efe8f JJ |
424 | if (!pfl->ro) { |
425 | /* Flush the entire write buffer onto backing storage. */ | |
426 | pflash_update(pfl, offset & mask, pfl->writeblock_size); | |
427 | } else { | |
428 | pfl->status |= 0x10; /* Programming error */ | |
429 | } | |
05ee37eb AZ |
430 | } |
431 | ||
432 | pfl->counter--; | |
433 | break; | |
7317b8ca AZ |
434 | default: |
435 | goto error_flash; | |
05ee37eb | 436 | } |
12dabc79 | 437 | break; |
05ee37eb AZ |
438 | case 3: /* Confirm mode */ |
439 | switch (pfl->cmd) { | |
440 | case 0xe8: /* Block write */ | |
441 | if (cmd == 0xd0) { | |
442 | pfl->wcycle = 0; | |
443 | pfl->status |= 0x80; | |
05ee37eb AZ |
444 | } else { |
445 | DPRINTF("%s: unknown command for \"write block\"\n", __func__); | |
446 | PFLASH_BUG("Write block confirm"); | |
7317b8ca | 447 | goto reset_flash; |
05ee37eb | 448 | } |
7317b8ca AZ |
449 | break; |
450 | default: | |
451 | goto error_flash; | |
05ee37eb | 452 | } |
12dabc79 | 453 | break; |
05ee37eb AZ |
454 | default: |
455 | /* Should never happen */ | |
456 | DPRINTF("%s: invalid write state\n", __func__); | |
457 | goto reset_flash; | |
458 | } | |
459 | return; | |
460 | ||
461 | error_flash: | |
d96fc51c PC |
462 | qemu_log_mask(LOG_UNIMP, "%s: Unimplemented flash cmd sequence " |
463 | "(offset " TARGET_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)" | |
464 | "\n", __func__, offset, pfl->wcycle, pfl->cmd, value); | |
05ee37eb AZ |
465 | |
466 | reset_flash: | |
5f9a5ea1 | 467 | memory_region_rom_device_set_romd(&pfl->mem, true); |
05ee37eb | 468 | |
05ee37eb AZ |
469 | pfl->wcycle = 0; |
470 | pfl->cmd = 0; | |
05ee37eb AZ |
471 | } |
472 | ||
473 | ||
a8170e5e | 474 | static uint32_t pflash_readb_be(void *opaque, hwaddr addr) |
3d08ff69 BS |
475 | { |
476 | return pflash_read(opaque, addr, 1, 1); | |
477 | } | |
478 | ||
a8170e5e | 479 | static uint32_t pflash_readb_le(void *opaque, hwaddr addr) |
3d08ff69 BS |
480 | { |
481 | return pflash_read(opaque, addr, 1, 0); | |
482 | } | |
483 | ||
a8170e5e | 484 | static uint32_t pflash_readw_be(void *opaque, hwaddr addr) |
3d08ff69 BS |
485 | { |
486 | pflash_t *pfl = opaque; | |
487 | ||
488 | return pflash_read(pfl, addr, 2, 1); | |
489 | } | |
490 | ||
a8170e5e | 491 | static uint32_t pflash_readw_le(void *opaque, hwaddr addr) |
05ee37eb | 492 | { |
3d08ff69 BS |
493 | pflash_t *pfl = opaque; |
494 | ||
495 | return pflash_read(pfl, addr, 2, 0); | |
05ee37eb AZ |
496 | } |
497 | ||
a8170e5e | 498 | static uint32_t pflash_readl_be(void *opaque, hwaddr addr) |
05ee37eb | 499 | { |
c227f099 | 500 | pflash_t *pfl = opaque; |
05ee37eb | 501 | |
3d08ff69 | 502 | return pflash_read(pfl, addr, 4, 1); |
05ee37eb AZ |
503 | } |
504 | ||
a8170e5e | 505 | static uint32_t pflash_readl_le(void *opaque, hwaddr addr) |
05ee37eb | 506 | { |
c227f099 | 507 | pflash_t *pfl = opaque; |
05ee37eb | 508 | |
3d08ff69 | 509 | return pflash_read(pfl, addr, 4, 0); |
05ee37eb AZ |
510 | } |
511 | ||
a8170e5e | 512 | static void pflash_writeb_be(void *opaque, hwaddr addr, |
3d08ff69 | 513 | uint32_t value) |
05ee37eb | 514 | { |
3d08ff69 | 515 | pflash_write(opaque, addr, value, 1, 1); |
05ee37eb AZ |
516 | } |
517 | ||
a8170e5e | 518 | static void pflash_writeb_le(void *opaque, hwaddr addr, |
3d08ff69 BS |
519 | uint32_t value) |
520 | { | |
521 | pflash_write(opaque, addr, value, 1, 0); | |
522 | } | |
523 | ||
a8170e5e | 524 | static void pflash_writew_be(void *opaque, hwaddr addr, |
3d08ff69 | 525 | uint32_t value) |
05ee37eb | 526 | { |
c227f099 | 527 | pflash_t *pfl = opaque; |
05ee37eb | 528 | |
3d08ff69 | 529 | pflash_write(pfl, addr, value, 2, 1); |
05ee37eb AZ |
530 | } |
531 | ||
a8170e5e | 532 | static void pflash_writew_le(void *opaque, hwaddr addr, |
3d08ff69 | 533 | uint32_t value) |
05ee37eb | 534 | { |
c227f099 | 535 | pflash_t *pfl = opaque; |
05ee37eb | 536 | |
3d08ff69 | 537 | pflash_write(pfl, addr, value, 2, 0); |
05ee37eb AZ |
538 | } |
539 | ||
a8170e5e | 540 | static void pflash_writel_be(void *opaque, hwaddr addr, |
3d08ff69 BS |
541 | uint32_t value) |
542 | { | |
543 | pflash_t *pfl = opaque; | |
544 | ||
545 | pflash_write(pfl, addr, value, 4, 1); | |
546 | } | |
547 | ||
a8170e5e | 548 | static void pflash_writel_le(void *opaque, hwaddr addr, |
3d08ff69 BS |
549 | uint32_t value) |
550 | { | |
551 | pflash_t *pfl = opaque; | |
552 | ||
553 | pflash_write(pfl, addr, value, 4, 0); | |
554 | } | |
555 | ||
cfe5f011 AK |
556 | static const MemoryRegionOps pflash_cfi01_ops_be = { |
557 | .old_mmio = { | |
558 | .read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, }, | |
559 | .write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, }, | |
560 | }, | |
561 | .endianness = DEVICE_NATIVE_ENDIAN, | |
05ee37eb AZ |
562 | }; |
563 | ||
cfe5f011 AK |
564 | static const MemoryRegionOps pflash_cfi01_ops_le = { |
565 | .old_mmio = { | |
566 | .read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, }, | |
567 | .write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, }, | |
568 | }, | |
569 | .endianness = DEVICE_NATIVE_ENDIAN, | |
05ee37eb AZ |
570 | }; |
571 | ||
368a354f | 572 | static int pflash_cfi01_init(SysBusDevice *dev) |
05ee37eb | 573 | { |
f1b44f0e | 574 | pflash_t *pfl = CFI_PFLASH01(dev); |
368a354f | 575 | uint64_t total_len; |
d0e7605e | 576 | int ret; |
05ee37eb | 577 | |
368a354f | 578 | total_len = pfl->sector_len * pfl->nb_blocs; |
05ee37eb AZ |
579 | |
580 | /* XXX: to be fixed */ | |
c8b153d7 | 581 | #if 0 |
05ee37eb AZ |
582 | if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) && |
583 | total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024)) | |
584 | return NULL; | |
c8b153d7 | 585 | #endif |
05ee37eb | 586 | |
cfe5f011 | 587 | memory_region_init_rom_device( |
2d256e6f | 588 | &pfl->mem, OBJECT(dev), |
2c9b15ca | 589 | pfl->be ? &pflash_cfi01_ops_be : &pflash_cfi01_ops_le, pfl, |
368a354f PC |
590 | pfl->name, total_len); |
591 | vmstate_register_ram(&pfl->mem, DEVICE(pfl)); | |
cfe5f011 | 592 | pfl->storage = memory_region_get_ram_ptr(&pfl->mem); |
368a354f | 593 | sysbus_init_mmio(dev, &pfl->mem); |
05ee37eb | 594 | |
05ee37eb AZ |
595 | if (pfl->bs) { |
596 | /* read the initial flash content */ | |
d0e7605e | 597 | ret = bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9); |
368a354f | 598 | |
d0e7605e | 599 | if (ret < 0) { |
368a354f | 600 | vmstate_unregister_ram(&pfl->mem, DEVICE(pfl)); |
cfe5f011 | 601 | memory_region_destroy(&pfl->mem); |
368a354f | 602 | return 1; |
d0e7605e | 603 | } |
05ee37eb | 604 | } |
de8efe8f JJ |
605 | |
606 | if (pfl->bs) { | |
607 | pfl->ro = bdrv_is_read_only(pfl->bs); | |
608 | } else { | |
609 | pfl->ro = 0; | |
610 | } | |
611 | ||
74475455 | 612 | pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl); |
05ee37eb AZ |
613 | pfl->wcycle = 0; |
614 | pfl->cmd = 0; | |
615 | pfl->status = 0; | |
05ee37eb AZ |
616 | /* Hardcoded CFI table */ |
617 | pfl->cfi_len = 0x52; | |
618 | /* Standard "QRY" string */ | |
619 | pfl->cfi_table[0x10] = 'Q'; | |
620 | pfl->cfi_table[0x11] = 'R'; | |
621 | pfl->cfi_table[0x12] = 'Y'; | |
622 | /* Command set (Intel) */ | |
623 | pfl->cfi_table[0x13] = 0x01; | |
624 | pfl->cfi_table[0x14] = 0x00; | |
625 | /* Primary extended table address (none) */ | |
626 | pfl->cfi_table[0x15] = 0x31; | |
627 | pfl->cfi_table[0x16] = 0x00; | |
628 | /* Alternate command set (none) */ | |
629 | pfl->cfi_table[0x17] = 0x00; | |
630 | pfl->cfi_table[0x18] = 0x00; | |
631 | /* Alternate extended table (none) */ | |
632 | pfl->cfi_table[0x19] = 0x00; | |
633 | pfl->cfi_table[0x1A] = 0x00; | |
634 | /* Vcc min */ | |
635 | pfl->cfi_table[0x1B] = 0x45; | |
636 | /* Vcc max */ | |
637 | pfl->cfi_table[0x1C] = 0x55; | |
638 | /* Vpp min (no Vpp pin) */ | |
639 | pfl->cfi_table[0x1D] = 0x00; | |
640 | /* Vpp max (no Vpp pin) */ | |
641 | pfl->cfi_table[0x1E] = 0x00; | |
642 | /* Reserved */ | |
643 | pfl->cfi_table[0x1F] = 0x07; | |
644 | /* Timeout for min size buffer write */ | |
645 | pfl->cfi_table[0x20] = 0x07; | |
646 | /* Typical timeout for block erase */ | |
647 | pfl->cfi_table[0x21] = 0x0a; | |
648 | /* Typical timeout for full chip erase (4096 ms) */ | |
649 | pfl->cfi_table[0x22] = 0x00; | |
650 | /* Reserved */ | |
651 | pfl->cfi_table[0x23] = 0x04; | |
652 | /* Max timeout for buffer write */ | |
653 | pfl->cfi_table[0x24] = 0x04; | |
654 | /* Max timeout for block erase */ | |
655 | pfl->cfi_table[0x25] = 0x04; | |
656 | /* Max timeout for chip erase */ | |
657 | pfl->cfi_table[0x26] = 0x00; | |
658 | /* Device size */ | |
659 | pfl->cfi_table[0x27] = ctz32(total_len); // + 1; | |
660 | /* Flash device interface (8 & 16 bits) */ | |
661 | pfl->cfi_table[0x28] = 0x02; | |
662 | pfl->cfi_table[0x29] = 0x00; | |
663 | /* Max number of bytes in multi-bytes write */ | |
368a354f | 664 | if (pfl->width == 1) { |
4737fa26 EI |
665 | pfl->cfi_table[0x2A] = 0x08; |
666 | } else { | |
667 | pfl->cfi_table[0x2A] = 0x0B; | |
668 | } | |
b4bf0a9a EI |
669 | pfl->writeblock_size = 1 << pfl->cfi_table[0x2A]; |
670 | ||
05ee37eb AZ |
671 | pfl->cfi_table[0x2B] = 0x00; |
672 | /* Number of erase block regions (uniform) */ | |
673 | pfl->cfi_table[0x2C] = 0x01; | |
674 | /* Erase block region 1 */ | |
368a354f PC |
675 | pfl->cfi_table[0x2D] = pfl->nb_blocs - 1; |
676 | pfl->cfi_table[0x2E] = (pfl->nb_blocs - 1) >> 8; | |
677 | pfl->cfi_table[0x2F] = pfl->sector_len >> 8; | |
678 | pfl->cfi_table[0x30] = pfl->sector_len >> 16; | |
05ee37eb AZ |
679 | |
680 | /* Extended */ | |
681 | pfl->cfi_table[0x31] = 'P'; | |
682 | pfl->cfi_table[0x32] = 'R'; | |
683 | pfl->cfi_table[0x33] = 'I'; | |
684 | ||
685 | pfl->cfi_table[0x34] = '1'; | |
262e1eaa | 686 | pfl->cfi_table[0x35] = '0'; |
05ee37eb AZ |
687 | |
688 | pfl->cfi_table[0x36] = 0x00; | |
689 | pfl->cfi_table[0x37] = 0x00; | |
690 | pfl->cfi_table[0x38] = 0x00; | |
691 | pfl->cfi_table[0x39] = 0x00; | |
692 | ||
693 | pfl->cfi_table[0x3a] = 0x00; | |
694 | ||
695 | pfl->cfi_table[0x3b] = 0x00; | |
696 | pfl->cfi_table[0x3c] = 0x00; | |
697 | ||
262e1eaa AJ |
698 | pfl->cfi_table[0x3f] = 0x01; /* Number of protection fields */ |
699 | ||
368a354f PC |
700 | return 0; |
701 | } | |
702 | ||
703 | static Property pflash_cfi01_properties[] = { | |
704 | DEFINE_PROP_DRIVE("drive", struct pflash_t, bs), | |
705 | DEFINE_PROP_UINT32("num-blocks", struct pflash_t, nb_blocs, 0), | |
706 | DEFINE_PROP_UINT64("sector-length", struct pflash_t, sector_len, 0), | |
707 | DEFINE_PROP_UINT8("width", struct pflash_t, width, 0), | |
708 | DEFINE_PROP_UINT8("big-endian", struct pflash_t, be, 0), | |
709 | DEFINE_PROP_UINT16("id0", struct pflash_t, ident0, 0), | |
710 | DEFINE_PROP_UINT16("id1", struct pflash_t, ident1, 0), | |
711 | DEFINE_PROP_UINT16("id2", struct pflash_t, ident2, 0), | |
712 | DEFINE_PROP_UINT16("id3", struct pflash_t, ident3, 0), | |
713 | DEFINE_PROP_STRING("name", struct pflash_t, name), | |
714 | DEFINE_PROP_END_OF_LIST(), | |
715 | }; | |
716 | ||
717 | static void pflash_cfi01_class_init(ObjectClass *klass, void *data) | |
718 | { | |
719 | DeviceClass *dc = DEVICE_CLASS(klass); | |
720 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); | |
721 | ||
722 | k->init = pflash_cfi01_init; | |
723 | dc->props = pflash_cfi01_properties; | |
d8d24fb7 | 724 | dc->vmsd = &vmstate_pflash; |
368a354f PC |
725 | } |
726 | ||
727 | ||
728 | static const TypeInfo pflash_cfi01_info = { | |
f1b44f0e | 729 | .name = TYPE_CFI_PFLASH01, |
368a354f PC |
730 | .parent = TYPE_SYS_BUS_DEVICE, |
731 | .instance_size = sizeof(struct pflash_t), | |
732 | .class_init = pflash_cfi01_class_init, | |
733 | }; | |
734 | ||
735 | static void pflash_cfi01_register_types(void) | |
736 | { | |
737 | type_register_static(&pflash_cfi01_info); | |
738 | } | |
739 | ||
740 | type_init(pflash_cfi01_register_types) | |
741 | ||
742 | pflash_t *pflash_cfi01_register(hwaddr base, | |
743 | DeviceState *qdev, const char *name, | |
744 | hwaddr size, | |
745 | BlockDriverState *bs, | |
746 | uint32_t sector_len, int nb_blocs, int width, | |
747 | uint16_t id0, uint16_t id1, | |
748 | uint16_t id2, uint16_t id3, int be) | |
749 | { | |
f1b44f0e | 750 | DeviceState *dev = qdev_create(NULL, TYPE_CFI_PFLASH01); |
368a354f PC |
751 | |
752 | if (bs && qdev_prop_set_drive(dev, "drive", bs)) { | |
753 | abort(); | |
754 | } | |
755 | qdev_prop_set_uint32(dev, "num-blocks", nb_blocs); | |
756 | qdev_prop_set_uint64(dev, "sector-length", sector_len); | |
757 | qdev_prop_set_uint8(dev, "width", width); | |
758 | qdev_prop_set_uint8(dev, "big-endian", !!be); | |
759 | qdev_prop_set_uint16(dev, "id0", id0); | |
760 | qdev_prop_set_uint16(dev, "id1", id1); | |
761 | qdev_prop_set_uint16(dev, "id2", id2); | |
762 | qdev_prop_set_uint16(dev, "id3", id3); | |
763 | qdev_prop_set_string(dev, "name", name); | |
764 | qdev_init_nofail(dev); | |
765 | ||
f1b44f0e HT |
766 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); |
767 | return CFI_PFLASH01(dev); | |
05ee37eb | 768 | } |
cfe5f011 AK |
769 | |
770 | MemoryRegion *pflash_cfi01_get_memory(pflash_t *fl) | |
771 | { | |
772 | return &fl->mem; | |
773 | } |