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Commit | Line | Data |
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05ee37eb AZ |
1 | /* |
2 | * CFI parallel flash with Intel command set emulation | |
3 | * | |
4 | * Copyright (c) 2006 Thorsten Zitterell | |
5 | * Copyright (c) 2005 Jocelyn Mayer | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
05ee37eb AZ |
19 | */ |
20 | ||
21 | /* | |
22 | * For now, this code can emulate flashes of 1, 2 or 4 bytes width. | |
23 | * Supported commands/modes are: | |
24 | * - flash read | |
25 | * - flash write | |
26 | * - flash ID read | |
27 | * - sector erase | |
28 | * - CFI queries | |
29 | * | |
30 | * It does not support timings | |
31 | * It does not support flash interleaving | |
32 | * It does not implement software data protection as found in many real chips | |
33 | * It does not implement erase suspend/resume commands | |
34 | * It does not implement multiple sectors erase | |
35 | * | |
36 | * It does not implement much more ... | |
37 | */ | |
38 | ||
83c9f4ca | 39 | #include "hw/hw.h" |
0d09e41a | 40 | #include "hw/block/flash.h" |
4be74634 | 41 | #include "sysemu/block-backend.h" |
1de7afc9 | 42 | #include "qemu/timer.h" |
1997b485 | 43 | #include "qemu/bitops.h" |
022c62cb | 44 | #include "exec/address-spaces.h" |
1de7afc9 | 45 | #include "qemu/host-utils.h" |
83c9f4ca | 46 | #include "hw/sysbus.h" |
05ee37eb | 47 | |
001faf32 | 48 | #define PFLASH_BUG(fmt, ...) \ |
05ee37eb | 49 | do { \ |
ec9ea489 | 50 | fprintf(stderr, "PFLASH: Possible BUG - " fmt, ## __VA_ARGS__); \ |
05ee37eb AZ |
51 | exit(1); \ |
52 | } while(0) | |
53 | ||
54 | /* #define PFLASH_DEBUG */ | |
55 | #ifdef PFLASH_DEBUG | |
ec9ea489 PC |
56 | #define DPRINTF(fmt, ...) \ |
57 | do { \ | |
58 | fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__); \ | |
05ee37eb AZ |
59 | } while (0) |
60 | #else | |
001faf32 | 61 | #define DPRINTF(fmt, ...) do { } while (0) |
05ee37eb AZ |
62 | #endif |
63 | ||
f1b44f0e HT |
64 | #define TYPE_CFI_PFLASH01 "cfi.pflash01" |
65 | #define CFI_PFLASH01(obj) OBJECT_CHECK(pflash_t, (obj), TYPE_CFI_PFLASH01) | |
66 | ||
e9809422 PB |
67 | #define PFLASH_BE 0 |
68 | ||
c227f099 | 69 | struct pflash_t { |
f1b44f0e HT |
70 | /*< private >*/ |
71 | SysBusDevice parent_obj; | |
72 | /*< public >*/ | |
73 | ||
4be74634 | 74 | BlockBackend *blk; |
368a354f PC |
75 | uint32_t nb_blocs; |
76 | uint64_t sector_len; | |
4b6fedca | 77 | uint8_t bank_width; |
1997b485 | 78 | uint8_t device_width; /* If 0, device width not specified. */ |
fa21a7b1 | 79 | uint8_t max_device_width; /* max device width in bytes */ |
e9809422 | 80 | uint32_t features; |
d8d24fb7 | 81 | uint8_t wcycle; /* if 0, the flash is read normally */ |
05ee37eb AZ |
82 | int ro; |
83 | uint8_t cmd; | |
84 | uint8_t status; | |
368a354f PC |
85 | uint16_t ident0; |
86 | uint16_t ident1; | |
87 | uint16_t ident2; | |
88 | uint16_t ident3; | |
05ee37eb AZ |
89 | uint8_t cfi_len; |
90 | uint8_t cfi_table[0x52]; | |
d8d24fb7 | 91 | uint64_t counter; |
b4bf0a9a | 92 | unsigned int writeblock_size; |
05ee37eb | 93 | QEMUTimer *timer; |
cfe5f011 | 94 | MemoryRegion mem; |
368a354f | 95 | char *name; |
05ee37eb AZ |
96 | void *storage; |
97 | }; | |
98 | ||
4c0cfc72 LE |
99 | static int pflash_post_load(void *opaque, int version_id); |
100 | ||
d8d24fb7 PM |
101 | static const VMStateDescription vmstate_pflash = { |
102 | .name = "pflash_cfi01", | |
103 | .version_id = 1, | |
104 | .minimum_version_id = 1, | |
4c0cfc72 | 105 | .post_load = pflash_post_load, |
d8d24fb7 PM |
106 | .fields = (VMStateField[]) { |
107 | VMSTATE_UINT8(wcycle, pflash_t), | |
108 | VMSTATE_UINT8(cmd, pflash_t), | |
109 | VMSTATE_UINT8(status, pflash_t), | |
110 | VMSTATE_UINT64(counter, pflash_t), | |
111 | VMSTATE_END_OF_LIST() | |
112 | } | |
113 | }; | |
114 | ||
05ee37eb AZ |
115 | static void pflash_timer (void *opaque) |
116 | { | |
c227f099 | 117 | pflash_t *pfl = opaque; |
05ee37eb AZ |
118 | |
119 | DPRINTF("%s: command %02x done\n", __func__, pfl->cmd); | |
120 | /* Reset flash */ | |
121 | pfl->status ^= 0x80; | |
5f9a5ea1 | 122 | memory_region_rom_device_set_romd(&pfl->mem, true); |
5d79b80b | 123 | pfl->wcycle = 0; |
05ee37eb AZ |
124 | pfl->cmd = 0; |
125 | } | |
126 | ||
4433e660 RF |
127 | /* Perform a CFI query based on the bank width of the flash. |
128 | * If this code is called we know we have a device_width set for | |
129 | * this flash. | |
130 | */ | |
131 | static uint32_t pflash_cfi_query(pflash_t *pfl, hwaddr offset) | |
132 | { | |
133 | int i; | |
134 | uint32_t resp = 0; | |
135 | hwaddr boff; | |
136 | ||
137 | /* Adjust incoming offset to match expected device-width | |
138 | * addressing. CFI query addresses are always specified in terms of | |
139 | * the maximum supported width of the device. This means that x8 | |
140 | * devices and x8/x16 devices in x8 mode behave differently. For | |
141 | * devices that are not used at their max width, we will be | |
142 | * provided with addresses that use higher address bits than | |
143 | * expected (based on the max width), so we will shift them lower | |
144 | * so that they will match the addresses used when | |
145 | * device_width==max_device_width. | |
146 | */ | |
147 | boff = offset >> (ctz32(pfl->bank_width) + | |
148 | ctz32(pfl->max_device_width) - ctz32(pfl->device_width)); | |
149 | ||
150 | if (boff > pfl->cfi_len) { | |
151 | return 0; | |
152 | } | |
153 | /* Now we will construct the CFI response generated by a single | |
154 | * device, then replicate that for all devices that make up the | |
155 | * bus. For wide parts used in x8 mode, CFI query responses | |
156 | * are different than native byte-wide parts. | |
157 | */ | |
158 | resp = pfl->cfi_table[boff]; | |
159 | if (pfl->device_width != pfl->max_device_width) { | |
160 | /* The only case currently supported is x8 mode for a | |
161 | * wider part. | |
162 | */ | |
163 | if (pfl->device_width != 1 || pfl->bank_width > 4) { | |
164 | DPRINTF("%s: Unsupported device configuration: " | |
165 | "device_width=%d, max_device_width=%d\n", | |
166 | __func__, pfl->device_width, | |
167 | pfl->max_device_width); | |
168 | return 0; | |
169 | } | |
170 | /* CFI query data is repeated, rather than zero padded for | |
171 | * wide devices used in x8 mode. | |
172 | */ | |
173 | for (i = 1; i < pfl->max_device_width; i++) { | |
174 | resp = deposit32(resp, 8 * i, 8, pfl->cfi_table[boff]); | |
175 | } | |
176 | } | |
177 | /* Replicate responses for each device in bank. */ | |
178 | if (pfl->device_width < pfl->bank_width) { | |
179 | for (i = pfl->device_width; | |
180 | i < pfl->bank_width; i += pfl->device_width) { | |
181 | resp = deposit32(resp, 8 * i, 8 * pfl->device_width, resp); | |
182 | } | |
183 | } | |
184 | ||
185 | return resp; | |
186 | } | |
187 | ||
0163a2dc RF |
188 | |
189 | ||
190 | /* Perform a device id query based on the bank width of the flash. */ | |
191 | static uint32_t pflash_devid_query(pflash_t *pfl, hwaddr offset) | |
192 | { | |
193 | int i; | |
194 | uint32_t resp; | |
195 | hwaddr boff; | |
196 | ||
197 | /* Adjust incoming offset to match expected device-width | |
198 | * addressing. Device ID read addresses are always specified in | |
199 | * terms of the maximum supported width of the device. This means | |
200 | * that x8 devices and x8/x16 devices in x8 mode behave | |
201 | * differently. For devices that are not used at their max width, | |
202 | * we will be provided with addresses that use higher address bits | |
203 | * than expected (based on the max width), so we will shift them | |
204 | * lower so that they will match the addresses used when | |
205 | * device_width==max_device_width. | |
206 | */ | |
207 | boff = offset >> (ctz32(pfl->bank_width) + | |
208 | ctz32(pfl->max_device_width) - ctz32(pfl->device_width)); | |
209 | ||
210 | /* Mask off upper bits which may be used in to query block | |
211 | * or sector lock status at other addresses. | |
212 | * Offsets 2/3 are block lock status, is not emulated. | |
213 | */ | |
214 | switch (boff & 0xFF) { | |
215 | case 0: | |
216 | resp = pfl->ident0; | |
afeb25f9 | 217 | DPRINTF("%s: Manufacturer Code %04x\n", __func__, resp); |
0163a2dc RF |
218 | break; |
219 | case 1: | |
220 | resp = pfl->ident1; | |
afeb25f9 | 221 | DPRINTF("%s: Device ID Code %04x\n", __func__, resp); |
0163a2dc RF |
222 | break; |
223 | default: | |
224 | DPRINTF("%s: Read Device Information offset=%x\n", __func__, | |
225 | (unsigned)offset); | |
226 | return 0; | |
227 | break; | |
228 | } | |
229 | /* Replicate responses for each device in bank. */ | |
230 | if (pfl->device_width < pfl->bank_width) { | |
231 | for (i = pfl->device_width; | |
232 | i < pfl->bank_width; i += pfl->device_width) { | |
233 | resp = deposit32(resp, 8 * i, 8 * pfl->device_width, resp); | |
234 | } | |
235 | } | |
236 | ||
237 | return resp; | |
238 | } | |
239 | ||
a8170e5e | 240 | static uint32_t pflash_read (pflash_t *pfl, hwaddr offset, |
3d08ff69 | 241 | int width, int be) |
05ee37eb | 242 | { |
a8170e5e | 243 | hwaddr boff; |
05ee37eb AZ |
244 | uint32_t ret; |
245 | uint8_t *p; | |
246 | ||
247 | ret = -1; | |
05ee37eb | 248 | |
fad8c772 EI |
249 | #if 0 |
250 | DPRINTF("%s: reading offset " TARGET_FMT_plx " under cmd %02x width %d\n", | |
06adb549 | 251 | __func__, offset, pfl->cmd, width); |
fad8c772 | 252 | #endif |
05ee37eb | 253 | switch (pfl->cmd) { |
1be97bf2 PM |
254 | default: |
255 | /* This should never happen : reset state & treat it as a read */ | |
256 | DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd); | |
257 | pfl->wcycle = 0; | |
258 | pfl->cmd = 0; | |
259 | /* fall through to read code */ | |
05ee37eb AZ |
260 | case 0x00: |
261 | /* Flash area read */ | |
262 | p = pfl->storage; | |
263 | switch (width) { | |
264 | case 1: | |
265 | ret = p[offset]; | |
fad8c772 | 266 | DPRINTF("%s: data offset " TARGET_FMT_plx " %02x\n", |
c8b153d7 | 267 | __func__, offset, ret); |
05ee37eb AZ |
268 | break; |
269 | case 2: | |
3d08ff69 BS |
270 | if (be) { |
271 | ret = p[offset] << 8; | |
272 | ret |= p[offset + 1]; | |
273 | } else { | |
274 | ret = p[offset]; | |
275 | ret |= p[offset + 1] << 8; | |
276 | } | |
fad8c772 | 277 | DPRINTF("%s: data offset " TARGET_FMT_plx " %04x\n", |
c8b153d7 | 278 | __func__, offset, ret); |
05ee37eb AZ |
279 | break; |
280 | case 4: | |
3d08ff69 BS |
281 | if (be) { |
282 | ret = p[offset] << 24; | |
283 | ret |= p[offset + 1] << 16; | |
284 | ret |= p[offset + 2] << 8; | |
285 | ret |= p[offset + 3]; | |
286 | } else { | |
287 | ret = p[offset]; | |
288 | ret |= p[offset + 1] << 8; | |
3d08ff69 BS |
289 | ret |= p[offset + 2] << 16; |
290 | ret |= p[offset + 3] << 24; | |
291 | } | |
fad8c772 | 292 | DPRINTF("%s: data offset " TARGET_FMT_plx " %08x\n", |
c8b153d7 | 293 | __func__, offset, ret); |
05ee37eb AZ |
294 | break; |
295 | default: | |
296 | DPRINTF("BUG in %s\n", __func__); | |
297 | } | |
298 | ||
299 | break; | |
6e392787 | 300 | case 0x10: /* Single byte program */ |
05ee37eb | 301 | case 0x20: /* Block erase */ |
6e392787 PM |
302 | case 0x28: /* Block erase */ |
303 | case 0x40: /* single byte program */ | |
05ee37eb AZ |
304 | case 0x50: /* Clear status register */ |
305 | case 0x60: /* Block /un)lock */ | |
306 | case 0x70: /* Status Register */ | |
307 | case 0xe8: /* Write block */ | |
2003889f RF |
308 | /* Status register read. Return status from each device in |
309 | * bank. | |
310 | */ | |
05ee37eb | 311 | ret = pfl->status; |
2003889f RF |
312 | if (pfl->device_width && width > pfl->device_width) { |
313 | int shift = pfl->device_width * 8; | |
314 | while (shift + pfl->device_width * 8 <= width * 8) { | |
315 | ret |= pfl->status << shift; | |
316 | shift += pfl->device_width * 8; | |
317 | } | |
318 | } else if (!pfl->device_width && width > 2) { | |
319 | /* Handle 32 bit flash cases where device width is not | |
320 | * set. (Existing behavior before device width added.) | |
321 | */ | |
ea0a4f34 PB |
322 | ret |= pfl->status << 16; |
323 | } | |
05ee37eb AZ |
324 | DPRINTF("%s: status %x\n", __func__, ret); |
325 | break; | |
0b2ec6fc | 326 | case 0x90: |
0163a2dc RF |
327 | if (!pfl->device_width) { |
328 | /* Preserve old behavior if device width not specified */ | |
329 | boff = offset & 0xFF; | |
330 | if (pfl->bank_width == 2) { | |
331 | boff = boff >> 1; | |
332 | } else if (pfl->bank_width == 4) { | |
333 | boff = boff >> 2; | |
334 | } | |
4433e660 | 335 | |
0163a2dc RF |
336 | switch (boff) { |
337 | case 0: | |
338 | ret = pfl->ident0 << 8 | pfl->ident1; | |
339 | DPRINTF("%s: Manufacturer Code %04x\n", __func__, ret); | |
340 | break; | |
341 | case 1: | |
342 | ret = pfl->ident2 << 8 | pfl->ident3; | |
343 | DPRINTF("%s: Device ID Code %04x\n", __func__, ret); | |
344 | break; | |
345 | default: | |
346 | DPRINTF("%s: Read Device Information boff=%x\n", __func__, | |
347 | (unsigned)boff); | |
348 | ret = 0; | |
349 | break; | |
350 | } | |
351 | } else { | |
352 | /* If we have a read larger than the bank_width, combine multiple | |
353 | * manufacturer/device ID queries into a single response. | |
354 | */ | |
355 | int i; | |
356 | for (i = 0; i < width; i += pfl->bank_width) { | |
357 | ret = deposit32(ret, i * 8, pfl->bank_width * 8, | |
358 | pflash_devid_query(pfl, | |
359 | offset + i * pfl->bank_width)); | |
360 | } | |
0b2ec6fc MW |
361 | } |
362 | break; | |
05ee37eb | 363 | case 0x98: /* Query mode */ |
4433e660 RF |
364 | if (!pfl->device_width) { |
365 | /* Preserve old behavior if device width not specified */ | |
366 | boff = offset & 0xFF; | |
367 | if (pfl->bank_width == 2) { | |
368 | boff = boff >> 1; | |
369 | } else if (pfl->bank_width == 4) { | |
370 | boff = boff >> 2; | |
371 | } | |
372 | ||
373 | if (boff > pfl->cfi_len) { | |
374 | ret = 0; | |
375 | } else { | |
376 | ret = pfl->cfi_table[boff]; | |
377 | } | |
378 | } else { | |
379 | /* If we have a read larger than the bank_width, combine multiple | |
380 | * CFI queries into a single response. | |
381 | */ | |
382 | int i; | |
383 | for (i = 0; i < width; i += pfl->bank_width) { | |
384 | ret = deposit32(ret, i * 8, pfl->bank_width * 8, | |
385 | pflash_cfi_query(pfl, | |
386 | offset + i * pfl->bank_width)); | |
387 | } | |
388 | } | |
389 | ||
05ee37eb | 390 | break; |
05ee37eb AZ |
391 | } |
392 | return ret; | |
393 | } | |
394 | ||
395 | /* update flash content on disk */ | |
c227f099 | 396 | static void pflash_update(pflash_t *pfl, int offset, |
05ee37eb AZ |
397 | int size) |
398 | { | |
399 | int offset_end; | |
4be74634 | 400 | if (pfl->blk) { |
05ee37eb AZ |
401 | offset_end = offset + size; |
402 | /* round to sectors */ | |
403 | offset = offset >> 9; | |
404 | offset_end = (offset_end + 511) >> 9; | |
4be74634 MA |
405 | blk_write(pfl->blk, offset, pfl->storage + (offset << 9), |
406 | offset_end - offset); | |
05ee37eb AZ |
407 | } |
408 | } | |
409 | ||
a8170e5e | 410 | static inline void pflash_data_write(pflash_t *pfl, hwaddr offset, |
3d08ff69 | 411 | uint32_t value, int width, int be) |
d361be25 AZ |
412 | { |
413 | uint8_t *p = pfl->storage; | |
414 | ||
fad8c772 | 415 | DPRINTF("%s: block write offset " TARGET_FMT_plx |
d8d24fb7 | 416 | " value %x counter %016" PRIx64 "\n", |
d361be25 AZ |
417 | __func__, offset, value, pfl->counter); |
418 | switch (width) { | |
419 | case 1: | |
420 | p[offset] = value; | |
d361be25 AZ |
421 | break; |
422 | case 2: | |
3d08ff69 BS |
423 | if (be) { |
424 | p[offset] = value >> 8; | |
425 | p[offset + 1] = value; | |
426 | } else { | |
427 | p[offset] = value; | |
428 | p[offset + 1] = value >> 8; | |
429 | } | |
d361be25 AZ |
430 | break; |
431 | case 4: | |
3d08ff69 BS |
432 | if (be) { |
433 | p[offset] = value >> 24; | |
434 | p[offset + 1] = value >> 16; | |
435 | p[offset + 2] = value >> 8; | |
436 | p[offset + 3] = value; | |
437 | } else { | |
438 | p[offset] = value; | |
439 | p[offset + 1] = value >> 8; | |
440 | p[offset + 2] = value >> 16; | |
441 | p[offset + 3] = value >> 24; | |
442 | } | |
d361be25 AZ |
443 | break; |
444 | } | |
445 | ||
446 | } | |
447 | ||
a8170e5e | 448 | static void pflash_write(pflash_t *pfl, hwaddr offset, |
3d08ff69 | 449 | uint32_t value, int width, int be) |
05ee37eb | 450 | { |
05ee37eb AZ |
451 | uint8_t *p; |
452 | uint8_t cmd; | |
453 | ||
05ee37eb | 454 | cmd = value; |
05ee37eb | 455 | |
fad8c772 | 456 | DPRINTF("%s: writing offset " TARGET_FMT_plx " value %08x width %d wcycle 0x%x\n", |
c8b153d7 | 457 | __func__, offset, value, width, pfl->wcycle); |
05ee37eb | 458 | |
e9cbbcac EI |
459 | if (!pfl->wcycle) { |
460 | /* Set the device in I/O access mode */ | |
5f9a5ea1 | 461 | memory_region_rom_device_set_romd(&pfl->mem, false); |
e9cbbcac | 462 | } |
05ee37eb AZ |
463 | |
464 | switch (pfl->wcycle) { | |
465 | case 0: | |
466 | /* read mode */ | |
467 | switch (cmd) { | |
468 | case 0x00: /* ??? */ | |
469 | goto reset_flash; | |
d361be25 AZ |
470 | case 0x10: /* Single Byte Program */ |
471 | case 0x40: /* Single Byte Program */ | |
fad8c772 | 472 | DPRINTF("%s: Single Byte Program\n", __func__); |
d361be25 | 473 | break; |
05ee37eb AZ |
474 | case 0x20: /* Block erase */ |
475 | p = pfl->storage; | |
476 | offset &= ~(pfl->sector_len - 1); | |
477 | ||
368a354f PC |
478 | DPRINTF("%s: block erase at " TARGET_FMT_plx " bytes %x\n", |
479 | __func__, offset, (unsigned)pfl->sector_len); | |
05ee37eb | 480 | |
de8efe8f JJ |
481 | if (!pfl->ro) { |
482 | memset(p + offset, 0xff, pfl->sector_len); | |
483 | pflash_update(pfl, offset, pfl->sector_len); | |
484 | } else { | |
485 | pfl->status |= 0x20; /* Block erase error */ | |
486 | } | |
05ee37eb AZ |
487 | pfl->status |= 0x80; /* Ready! */ |
488 | break; | |
489 | case 0x50: /* Clear status bits */ | |
490 | DPRINTF("%s: Clear status bits\n", __func__); | |
491 | pfl->status = 0x0; | |
492 | goto reset_flash; | |
493 | case 0x60: /* Block (un)lock */ | |
494 | DPRINTF("%s: Block unlock\n", __func__); | |
495 | break; | |
496 | case 0x70: /* Status Register */ | |
497 | DPRINTF("%s: Read status register\n", __func__); | |
498 | pfl->cmd = cmd; | |
499 | return; | |
0b2ec6fc MW |
500 | case 0x90: /* Read Device ID */ |
501 | DPRINTF("%s: Read Device information\n", __func__); | |
502 | pfl->cmd = cmd; | |
503 | return; | |
05ee37eb AZ |
504 | case 0x98: /* CFI query */ |
505 | DPRINTF("%s: CFI query\n", __func__); | |
506 | break; | |
507 | case 0xe8: /* Write to buffer */ | |
508 | DPRINTF("%s: Write to buffer\n", __func__); | |
509 | pfl->status |= 0x80; /* Ready! */ | |
510 | break; | |
5928023c SW |
511 | case 0xf0: /* Probe for AMD flash */ |
512 | DPRINTF("%s: Probe for AMD flash\n", __func__); | |
513 | goto reset_flash; | |
05ee37eb AZ |
514 | case 0xff: /* Read array mode */ |
515 | DPRINTF("%s: Read array mode\n", __func__); | |
516 | goto reset_flash; | |
517 | default: | |
518 | goto error_flash; | |
519 | } | |
520 | pfl->wcycle++; | |
521 | pfl->cmd = cmd; | |
12dabc79 | 522 | break; |
05ee37eb AZ |
523 | case 1: |
524 | switch (pfl->cmd) { | |
d361be25 AZ |
525 | case 0x10: /* Single Byte Program */ |
526 | case 0x40: /* Single Byte Program */ | |
527 | DPRINTF("%s: Single Byte Program\n", __func__); | |
de8efe8f JJ |
528 | if (!pfl->ro) { |
529 | pflash_data_write(pfl, offset, value, width, be); | |
530 | pflash_update(pfl, offset, width); | |
531 | } else { | |
532 | pfl->status |= 0x10; /* Programming error */ | |
533 | } | |
d361be25 AZ |
534 | pfl->status |= 0x80; /* Ready! */ |
535 | pfl->wcycle = 0; | |
536 | break; | |
05ee37eb AZ |
537 | case 0x20: /* Block erase */ |
538 | case 0x28: | |
539 | if (cmd == 0xd0) { /* confirm */ | |
3656744c | 540 | pfl->wcycle = 0; |
05ee37eb | 541 | pfl->status |= 0x80; |
9248f413 | 542 | } else if (cmd == 0xff) { /* read array mode */ |
05ee37eb AZ |
543 | goto reset_flash; |
544 | } else | |
545 | goto error_flash; | |
546 | ||
547 | break; | |
548 | case 0xe8: | |
1997b485 RF |
549 | /* Mask writeblock size based on device width, or bank width if |
550 | * device width not specified. | |
551 | */ | |
552 | if (pfl->device_width) { | |
553 | value = extract32(value, 0, pfl->device_width * 8); | |
554 | } else { | |
555 | value = extract32(value, 0, pfl->bank_width * 8); | |
556 | } | |
71fb2348 AZ |
557 | DPRINTF("%s: block write of %x bytes\n", __func__, value); |
558 | pfl->counter = value; | |
05ee37eb AZ |
559 | pfl->wcycle++; |
560 | break; | |
561 | case 0x60: | |
562 | if (cmd == 0xd0) { | |
563 | pfl->wcycle = 0; | |
564 | pfl->status |= 0x80; | |
565 | } else if (cmd == 0x01) { | |
566 | pfl->wcycle = 0; | |
567 | pfl->status |= 0x80; | |
568 | } else if (cmd == 0xff) { | |
569 | goto reset_flash; | |
570 | } else { | |
571 | DPRINTF("%s: Unknown (un)locking command\n", __func__); | |
572 | goto reset_flash; | |
573 | } | |
574 | break; | |
575 | case 0x98: | |
576 | if (cmd == 0xff) { | |
577 | goto reset_flash; | |
578 | } else { | |
579 | DPRINTF("%s: leaving query mode\n", __func__); | |
580 | } | |
581 | break; | |
582 | default: | |
583 | goto error_flash; | |
584 | } | |
12dabc79 | 585 | break; |
05ee37eb AZ |
586 | case 2: |
587 | switch (pfl->cmd) { | |
588 | case 0xe8: /* Block write */ | |
de8efe8f JJ |
589 | if (!pfl->ro) { |
590 | pflash_data_write(pfl, offset, value, width, be); | |
591 | } else { | |
592 | pfl->status |= 0x10; /* Programming error */ | |
593 | } | |
05ee37eb AZ |
594 | |
595 | pfl->status |= 0x80; | |
596 | ||
597 | if (!pfl->counter) { | |
a8170e5e | 598 | hwaddr mask = pfl->writeblock_size - 1; |
b4bf0a9a EI |
599 | mask = ~mask; |
600 | ||
05ee37eb AZ |
601 | DPRINTF("%s: block write finished\n", __func__); |
602 | pfl->wcycle++; | |
de8efe8f JJ |
603 | if (!pfl->ro) { |
604 | /* Flush the entire write buffer onto backing storage. */ | |
605 | pflash_update(pfl, offset & mask, pfl->writeblock_size); | |
606 | } else { | |
607 | pfl->status |= 0x10; /* Programming error */ | |
608 | } | |
05ee37eb AZ |
609 | } |
610 | ||
611 | pfl->counter--; | |
612 | break; | |
7317b8ca AZ |
613 | default: |
614 | goto error_flash; | |
05ee37eb | 615 | } |
12dabc79 | 616 | break; |
05ee37eb AZ |
617 | case 3: /* Confirm mode */ |
618 | switch (pfl->cmd) { | |
619 | case 0xe8: /* Block write */ | |
620 | if (cmd == 0xd0) { | |
621 | pfl->wcycle = 0; | |
622 | pfl->status |= 0x80; | |
05ee37eb AZ |
623 | } else { |
624 | DPRINTF("%s: unknown command for \"write block\"\n", __func__); | |
625 | PFLASH_BUG("Write block confirm"); | |
7317b8ca | 626 | goto reset_flash; |
05ee37eb | 627 | } |
7317b8ca AZ |
628 | break; |
629 | default: | |
630 | goto error_flash; | |
05ee37eb | 631 | } |
12dabc79 | 632 | break; |
05ee37eb AZ |
633 | default: |
634 | /* Should never happen */ | |
635 | DPRINTF("%s: invalid write state\n", __func__); | |
636 | goto reset_flash; | |
637 | } | |
638 | return; | |
639 | ||
640 | error_flash: | |
d96fc51c PC |
641 | qemu_log_mask(LOG_UNIMP, "%s: Unimplemented flash cmd sequence " |
642 | "(offset " TARGET_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)" | |
643 | "\n", __func__, offset, pfl->wcycle, pfl->cmd, value); | |
05ee37eb AZ |
644 | |
645 | reset_flash: | |
5f9a5ea1 | 646 | memory_region_rom_device_set_romd(&pfl->mem, true); |
05ee37eb | 647 | |
05ee37eb AZ |
648 | pfl->wcycle = 0; |
649 | pfl->cmd = 0; | |
05ee37eb AZ |
650 | } |
651 | ||
652 | ||
a8170e5e | 653 | static uint32_t pflash_readb_be(void *opaque, hwaddr addr) |
3d08ff69 BS |
654 | { |
655 | return pflash_read(opaque, addr, 1, 1); | |
656 | } | |
657 | ||
a8170e5e | 658 | static uint32_t pflash_readb_le(void *opaque, hwaddr addr) |
3d08ff69 BS |
659 | { |
660 | return pflash_read(opaque, addr, 1, 0); | |
661 | } | |
662 | ||
a8170e5e | 663 | static uint32_t pflash_readw_be(void *opaque, hwaddr addr) |
3d08ff69 BS |
664 | { |
665 | pflash_t *pfl = opaque; | |
666 | ||
667 | return pflash_read(pfl, addr, 2, 1); | |
668 | } | |
669 | ||
a8170e5e | 670 | static uint32_t pflash_readw_le(void *opaque, hwaddr addr) |
05ee37eb | 671 | { |
3d08ff69 BS |
672 | pflash_t *pfl = opaque; |
673 | ||
674 | return pflash_read(pfl, addr, 2, 0); | |
05ee37eb AZ |
675 | } |
676 | ||
a8170e5e | 677 | static uint32_t pflash_readl_be(void *opaque, hwaddr addr) |
05ee37eb | 678 | { |
c227f099 | 679 | pflash_t *pfl = opaque; |
05ee37eb | 680 | |
3d08ff69 | 681 | return pflash_read(pfl, addr, 4, 1); |
05ee37eb AZ |
682 | } |
683 | ||
a8170e5e | 684 | static uint32_t pflash_readl_le(void *opaque, hwaddr addr) |
05ee37eb | 685 | { |
c227f099 | 686 | pflash_t *pfl = opaque; |
05ee37eb | 687 | |
3d08ff69 | 688 | return pflash_read(pfl, addr, 4, 0); |
05ee37eb AZ |
689 | } |
690 | ||
a8170e5e | 691 | static void pflash_writeb_be(void *opaque, hwaddr addr, |
3d08ff69 | 692 | uint32_t value) |
05ee37eb | 693 | { |
3d08ff69 | 694 | pflash_write(opaque, addr, value, 1, 1); |
05ee37eb AZ |
695 | } |
696 | ||
a8170e5e | 697 | static void pflash_writeb_le(void *opaque, hwaddr addr, |
3d08ff69 BS |
698 | uint32_t value) |
699 | { | |
700 | pflash_write(opaque, addr, value, 1, 0); | |
701 | } | |
702 | ||
a8170e5e | 703 | static void pflash_writew_be(void *opaque, hwaddr addr, |
3d08ff69 | 704 | uint32_t value) |
05ee37eb | 705 | { |
c227f099 | 706 | pflash_t *pfl = opaque; |
05ee37eb | 707 | |
3d08ff69 | 708 | pflash_write(pfl, addr, value, 2, 1); |
05ee37eb AZ |
709 | } |
710 | ||
a8170e5e | 711 | static void pflash_writew_le(void *opaque, hwaddr addr, |
3d08ff69 | 712 | uint32_t value) |
05ee37eb | 713 | { |
c227f099 | 714 | pflash_t *pfl = opaque; |
05ee37eb | 715 | |
3d08ff69 | 716 | pflash_write(pfl, addr, value, 2, 0); |
05ee37eb AZ |
717 | } |
718 | ||
a8170e5e | 719 | static void pflash_writel_be(void *opaque, hwaddr addr, |
3d08ff69 BS |
720 | uint32_t value) |
721 | { | |
722 | pflash_t *pfl = opaque; | |
723 | ||
724 | pflash_write(pfl, addr, value, 4, 1); | |
725 | } | |
726 | ||
a8170e5e | 727 | static void pflash_writel_le(void *opaque, hwaddr addr, |
3d08ff69 BS |
728 | uint32_t value) |
729 | { | |
730 | pflash_t *pfl = opaque; | |
731 | ||
732 | pflash_write(pfl, addr, value, 4, 0); | |
733 | } | |
734 | ||
cfe5f011 AK |
735 | static const MemoryRegionOps pflash_cfi01_ops_be = { |
736 | .old_mmio = { | |
737 | .read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, }, | |
738 | .write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, }, | |
739 | }, | |
740 | .endianness = DEVICE_NATIVE_ENDIAN, | |
05ee37eb AZ |
741 | }; |
742 | ||
cfe5f011 AK |
743 | static const MemoryRegionOps pflash_cfi01_ops_le = { |
744 | .old_mmio = { | |
745 | .read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, }, | |
746 | .write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, }, | |
747 | }, | |
748 | .endianness = DEVICE_NATIVE_ENDIAN, | |
05ee37eb AZ |
749 | }; |
750 | ||
e40b5f3e | 751 | static void pflash_cfi01_realize(DeviceState *dev, Error **errp) |
05ee37eb | 752 | { |
f1b44f0e | 753 | pflash_t *pfl = CFI_PFLASH01(dev); |
368a354f | 754 | uint64_t total_len; |
d0e7605e | 755 | int ret; |
a0289b8a PM |
756 | uint64_t blocks_per_device, device_len; |
757 | int num_devices; | |
33e0eb52 | 758 | Error *local_err = NULL; |
05ee37eb | 759 | |
368a354f | 760 | total_len = pfl->sector_len * pfl->nb_blocs; |
05ee37eb | 761 | |
a0289b8a PM |
762 | /* These are only used to expose the parameters of each device |
763 | * in the cfi_table[]. | |
764 | */ | |
765 | num_devices = pfl->device_width ? (pfl->bank_width / pfl->device_width) : 1; | |
766 | blocks_per_device = pfl->nb_blocs / num_devices; | |
767 | device_len = pfl->sector_len * blocks_per_device; | |
768 | ||
05ee37eb | 769 | /* XXX: to be fixed */ |
c8b153d7 | 770 | #if 0 |
05ee37eb AZ |
771 | if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) && |
772 | total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024)) | |
773 | return NULL; | |
c8b153d7 | 774 | #endif |
05ee37eb | 775 | |
cfe5f011 | 776 | memory_region_init_rom_device( |
2d256e6f | 777 | &pfl->mem, OBJECT(dev), |
e9809422 PB |
778 | pfl->features & (1 << PFLASH_BE) ? &pflash_cfi01_ops_be : &pflash_cfi01_ops_le, |
779 | pfl, | |
33e0eb52 HT |
780 | pfl->name, total_len, &local_err); |
781 | if (local_err) { | |
782 | error_propagate(errp, local_err); | |
783 | return; | |
784 | } | |
785 | ||
368a354f | 786 | vmstate_register_ram(&pfl->mem, DEVICE(pfl)); |
cfe5f011 | 787 | pfl->storage = memory_region_get_ram_ptr(&pfl->mem); |
e40b5f3e | 788 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem); |
05ee37eb | 789 | |
4be74634 | 790 | if (pfl->blk) { |
05ee37eb | 791 | /* read the initial flash content */ |
4be74634 | 792 | ret = blk_read(pfl->blk, 0, pfl->storage, total_len >> 9); |
368a354f | 793 | |
d0e7605e | 794 | if (ret < 0) { |
368a354f | 795 | vmstate_unregister_ram(&pfl->mem, DEVICE(pfl)); |
e40b5f3e HT |
796 | error_setg(errp, "failed to read the initial flash content"); |
797 | return; | |
d0e7605e | 798 | } |
05ee37eb | 799 | } |
de8efe8f | 800 | |
4be74634 MA |
801 | if (pfl->blk) { |
802 | pfl->ro = blk_is_read_only(pfl->blk); | |
de8efe8f JJ |
803 | } else { |
804 | pfl->ro = 0; | |
805 | } | |
806 | ||
fa21a7b1 RF |
807 | /* Default to devices being used at their maximum device width. This was |
808 | * assumed before the device_width support was added. | |
809 | */ | |
810 | if (!pfl->max_device_width) { | |
811 | pfl->max_device_width = pfl->device_width; | |
812 | } | |
813 | ||
bc72ad67 | 814 | pfl->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pflash_timer, pfl); |
05ee37eb AZ |
815 | pfl->wcycle = 0; |
816 | pfl->cmd = 0; | |
817 | pfl->status = 0; | |
05ee37eb AZ |
818 | /* Hardcoded CFI table */ |
819 | pfl->cfi_len = 0x52; | |
820 | /* Standard "QRY" string */ | |
821 | pfl->cfi_table[0x10] = 'Q'; | |
822 | pfl->cfi_table[0x11] = 'R'; | |
823 | pfl->cfi_table[0x12] = 'Y'; | |
824 | /* Command set (Intel) */ | |
825 | pfl->cfi_table[0x13] = 0x01; | |
826 | pfl->cfi_table[0x14] = 0x00; | |
827 | /* Primary extended table address (none) */ | |
828 | pfl->cfi_table[0x15] = 0x31; | |
829 | pfl->cfi_table[0x16] = 0x00; | |
830 | /* Alternate command set (none) */ | |
831 | pfl->cfi_table[0x17] = 0x00; | |
832 | pfl->cfi_table[0x18] = 0x00; | |
833 | /* Alternate extended table (none) */ | |
834 | pfl->cfi_table[0x19] = 0x00; | |
835 | pfl->cfi_table[0x1A] = 0x00; | |
836 | /* Vcc min */ | |
837 | pfl->cfi_table[0x1B] = 0x45; | |
838 | /* Vcc max */ | |
839 | pfl->cfi_table[0x1C] = 0x55; | |
840 | /* Vpp min (no Vpp pin) */ | |
841 | pfl->cfi_table[0x1D] = 0x00; | |
842 | /* Vpp max (no Vpp pin) */ | |
843 | pfl->cfi_table[0x1E] = 0x00; | |
844 | /* Reserved */ | |
845 | pfl->cfi_table[0x1F] = 0x07; | |
846 | /* Timeout for min size buffer write */ | |
847 | pfl->cfi_table[0x20] = 0x07; | |
848 | /* Typical timeout for block erase */ | |
849 | pfl->cfi_table[0x21] = 0x0a; | |
850 | /* Typical timeout for full chip erase (4096 ms) */ | |
851 | pfl->cfi_table[0x22] = 0x00; | |
852 | /* Reserved */ | |
853 | pfl->cfi_table[0x23] = 0x04; | |
854 | /* Max timeout for buffer write */ | |
855 | pfl->cfi_table[0x24] = 0x04; | |
856 | /* Max timeout for block erase */ | |
857 | pfl->cfi_table[0x25] = 0x04; | |
858 | /* Max timeout for chip erase */ | |
859 | pfl->cfi_table[0x26] = 0x00; | |
860 | /* Device size */ | |
a0289b8a | 861 | pfl->cfi_table[0x27] = ctz32(device_len); /* + 1; */ |
05ee37eb AZ |
862 | /* Flash device interface (8 & 16 bits) */ |
863 | pfl->cfi_table[0x28] = 0x02; | |
864 | pfl->cfi_table[0x29] = 0x00; | |
865 | /* Max number of bytes in multi-bytes write */ | |
4b6fedca | 866 | if (pfl->bank_width == 1) { |
4737fa26 EI |
867 | pfl->cfi_table[0x2A] = 0x08; |
868 | } else { | |
869 | pfl->cfi_table[0x2A] = 0x0B; | |
870 | } | |
b4bf0a9a EI |
871 | pfl->writeblock_size = 1 << pfl->cfi_table[0x2A]; |
872 | ||
05ee37eb AZ |
873 | pfl->cfi_table[0x2B] = 0x00; |
874 | /* Number of erase block regions (uniform) */ | |
875 | pfl->cfi_table[0x2C] = 0x01; | |
876 | /* Erase block region 1 */ | |
a0289b8a PM |
877 | pfl->cfi_table[0x2D] = blocks_per_device - 1; |
878 | pfl->cfi_table[0x2E] = (blocks_per_device - 1) >> 8; | |
368a354f PC |
879 | pfl->cfi_table[0x2F] = pfl->sector_len >> 8; |
880 | pfl->cfi_table[0x30] = pfl->sector_len >> 16; | |
05ee37eb AZ |
881 | |
882 | /* Extended */ | |
883 | pfl->cfi_table[0x31] = 'P'; | |
884 | pfl->cfi_table[0x32] = 'R'; | |
885 | pfl->cfi_table[0x33] = 'I'; | |
886 | ||
887 | pfl->cfi_table[0x34] = '1'; | |
262e1eaa | 888 | pfl->cfi_table[0x35] = '0'; |
05ee37eb AZ |
889 | |
890 | pfl->cfi_table[0x36] = 0x00; | |
891 | pfl->cfi_table[0x37] = 0x00; | |
892 | pfl->cfi_table[0x38] = 0x00; | |
893 | pfl->cfi_table[0x39] = 0x00; | |
894 | ||
895 | pfl->cfi_table[0x3a] = 0x00; | |
896 | ||
897 | pfl->cfi_table[0x3b] = 0x00; | |
898 | pfl->cfi_table[0x3c] = 0x00; | |
899 | ||
262e1eaa | 900 | pfl->cfi_table[0x3f] = 0x01; /* Number of protection fields */ |
368a354f PC |
901 | } |
902 | ||
903 | static Property pflash_cfi01_properties[] = { | |
4be74634 | 904 | DEFINE_PROP_DRIVE("drive", struct pflash_t, blk), |
a0289b8a PM |
905 | /* num-blocks is the number of blocks actually visible to the guest, |
906 | * ie the total size of the device divided by the sector length. | |
907 | * If we're emulating flash devices wired in parallel the actual | |
908 | * number of blocks per indvidual device will differ. | |
909 | */ | |
368a354f PC |
910 | DEFINE_PROP_UINT32("num-blocks", struct pflash_t, nb_blocs, 0), |
911 | DEFINE_PROP_UINT64("sector-length", struct pflash_t, sector_len, 0), | |
fa21a7b1 RF |
912 | /* width here is the overall width of this QEMU device in bytes. |
913 | * The QEMU device may be emulating a number of flash devices | |
914 | * wired up in parallel; the width of each individual flash | |
915 | * device should be specified via device-width. If the individual | |
916 | * devices have a maximum width which is greater than the width | |
917 | * they are being used for, this maximum width should be set via | |
918 | * max-device-width (which otherwise defaults to device-width). | |
919 | * So for instance a 32-bit wide QEMU flash device made from four | |
920 | * 16-bit flash devices used in 8-bit wide mode would be configured | |
921 | * with width = 4, device-width = 1, max-device-width = 2. | |
922 | * | |
923 | * If device-width is not specified we default to backwards | |
924 | * compatible behaviour which is a bad emulation of two | |
925 | * 16 bit devices making up a 32 bit wide QEMU device. This | |
926 | * is deprecated for new uses of this device. | |
927 | */ | |
4b6fedca | 928 | DEFINE_PROP_UINT8("width", struct pflash_t, bank_width, 0), |
1997b485 | 929 | DEFINE_PROP_UINT8("device-width", struct pflash_t, device_width, 0), |
fa21a7b1 | 930 | DEFINE_PROP_UINT8("max-device-width", struct pflash_t, max_device_width, 0), |
e9809422 | 931 | DEFINE_PROP_BIT("big-endian", struct pflash_t, features, PFLASH_BE, 0), |
368a354f PC |
932 | DEFINE_PROP_UINT16("id0", struct pflash_t, ident0, 0), |
933 | DEFINE_PROP_UINT16("id1", struct pflash_t, ident1, 0), | |
934 | DEFINE_PROP_UINT16("id2", struct pflash_t, ident2, 0), | |
935 | DEFINE_PROP_UINT16("id3", struct pflash_t, ident3, 0), | |
936 | DEFINE_PROP_STRING("name", struct pflash_t, name), | |
937 | DEFINE_PROP_END_OF_LIST(), | |
938 | }; | |
939 | ||
940 | static void pflash_cfi01_class_init(ObjectClass *klass, void *data) | |
941 | { | |
942 | DeviceClass *dc = DEVICE_CLASS(klass); | |
368a354f | 943 | |
e40b5f3e | 944 | dc->realize = pflash_cfi01_realize; |
368a354f | 945 | dc->props = pflash_cfi01_properties; |
d8d24fb7 | 946 | dc->vmsd = &vmstate_pflash; |
125ee0ed | 947 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
368a354f PC |
948 | } |
949 | ||
950 | ||
951 | static const TypeInfo pflash_cfi01_info = { | |
f1b44f0e | 952 | .name = TYPE_CFI_PFLASH01, |
368a354f PC |
953 | .parent = TYPE_SYS_BUS_DEVICE, |
954 | .instance_size = sizeof(struct pflash_t), | |
955 | .class_init = pflash_cfi01_class_init, | |
956 | }; | |
957 | ||
958 | static void pflash_cfi01_register_types(void) | |
959 | { | |
960 | type_register_static(&pflash_cfi01_info); | |
961 | } | |
962 | ||
963 | type_init(pflash_cfi01_register_types) | |
964 | ||
965 | pflash_t *pflash_cfi01_register(hwaddr base, | |
966 | DeviceState *qdev, const char *name, | |
967 | hwaddr size, | |
4be74634 | 968 | BlockBackend *blk, |
4b6fedca RF |
969 | uint32_t sector_len, int nb_blocs, |
970 | int bank_width, uint16_t id0, uint16_t id1, | |
368a354f PC |
971 | uint16_t id2, uint16_t id3, int be) |
972 | { | |
f1b44f0e | 973 | DeviceState *dev = qdev_create(NULL, TYPE_CFI_PFLASH01); |
368a354f | 974 | |
9b3d111a MA |
975 | if (blk) { |
976 | qdev_prop_set_drive(dev, "drive", blk, &error_abort); | |
368a354f PC |
977 | } |
978 | qdev_prop_set_uint32(dev, "num-blocks", nb_blocs); | |
979 | qdev_prop_set_uint64(dev, "sector-length", sector_len); | |
4b6fedca | 980 | qdev_prop_set_uint8(dev, "width", bank_width); |
e9809422 | 981 | qdev_prop_set_bit(dev, "big-endian", !!be); |
368a354f PC |
982 | qdev_prop_set_uint16(dev, "id0", id0); |
983 | qdev_prop_set_uint16(dev, "id1", id1); | |
984 | qdev_prop_set_uint16(dev, "id2", id2); | |
985 | qdev_prop_set_uint16(dev, "id3", id3); | |
986 | qdev_prop_set_string(dev, "name", name); | |
987 | qdev_init_nofail(dev); | |
988 | ||
f1b44f0e HT |
989 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); |
990 | return CFI_PFLASH01(dev); | |
05ee37eb | 991 | } |
cfe5f011 AK |
992 | |
993 | MemoryRegion *pflash_cfi01_get_memory(pflash_t *fl) | |
994 | { | |
995 | return &fl->mem; | |
996 | } | |
4c0cfc72 LE |
997 | |
998 | static int pflash_post_load(void *opaque, int version_id) | |
999 | { | |
1000 | pflash_t *pfl = opaque; | |
1001 | ||
1002 | if (!pfl->ro) { | |
1003 | DPRINTF("%s: updating bdrv for %s\n", __func__, pfl->name); | |
1004 | pflash_update(pfl, 0, pfl->sector_len * pfl->nb_blocs); | |
1005 | } | |
1006 | return 0; | |
1007 | } |