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Commit | Line | Data |
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29133e9a FB |
1 | /* |
2 | * CFI parallel flash with AMD command set emulation | |
5fafdf24 | 3 | * |
29133e9a FB |
4 | * Copyright (c) 2005 Jocelyn Mayer |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
3564a919 | 9 | * version 2.1 of the License, or (at your option) any later version. |
29133e9a FB |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
29133e9a FB |
18 | */ |
19 | ||
20 | /* | |
21 | * For now, this code can emulate flashes of 1, 2 or 4 bytes width. | |
22 | * Supported commands/modes are: | |
23 | * - flash read | |
24 | * - flash write | |
25 | * - flash ID read | |
26 | * - sector erase | |
27 | * - chip erase | |
28 | * - unlock bypass command | |
29 | * - CFI queries | |
30 | * | |
31 | * It does not support flash interleaving. | |
29133e9a | 32 | * It does not implement software data protection as found in many real chips |
29133e9a FB |
33 | */ |
34 | ||
80c71a24 | 35 | #include "qemu/osdep.h" |
06f15217 | 36 | #include "hw/block/block.h" |
0d09e41a | 37 | #include "hw/block/flash.h" |
a27bd6c7 | 38 | #include "hw/qdev-properties.h" |
ce35e229 | 39 | #include "hw/qdev-properties-system.h" |
da34e65c | 40 | #include "qapi/error.h" |
1857b9db | 41 | #include "qemu/error-report.h" |
ddb6f225 | 42 | #include "qemu/bitmap.h" |
1de7afc9 | 43 | #include "qemu/timer.h" |
4be74634 | 44 | #include "sysemu/block-backend.h" |
1de7afc9 | 45 | #include "qemu/host-utils.h" |
0b8fa32f | 46 | #include "qemu/module.h" |
83c9f4ca | 47 | #include "hw/sysbus.h" |
d6454270 | 48 | #include "migration/vmstate.h" |
13019f1f | 49 | #include "trace.h" |
29133e9a | 50 | |
661bfc80 JK |
51 | #define PFLASH_LAZY_ROMD_THRESHOLD 42 |
52 | ||
64659053 SC |
53 | /* |
54 | * The size of the cfi_table indirectly depends on this and the start of the | |
55 | * PRI table directly depends on it. 4 is the maximum size (and also what | |
56 | * seems common) without changing the PRT table address. | |
57 | */ | |
58 | #define PFLASH_MAX_ERASE_REGIONS 4 | |
59 | ||
aeaf6c20 PMD |
60 | /* Special write cycles for CFI queries. */ |
61 | enum { | |
62 | WCYCLE_CFI = 7, | |
46fb7809 | 63 | WCYCLE_AUTOSELECT_CFI = 8, |
aeaf6c20 PMD |
64 | }; |
65 | ||
16434065 | 66 | struct PFlashCFI02 { |
3509c396 HT |
67 | /*< private >*/ |
68 | SysBusDevice parent_obj; | |
69 | /*< public >*/ | |
70 | ||
4be74634 | 71 | BlockBackend *blk; |
64659053 SC |
72 | uint32_t uniform_nb_blocs; |
73 | uint32_t uniform_sector_len; | |
ddb6f225 | 74 | uint32_t total_sectors; |
64659053 SC |
75 | uint32_t nb_blocs[PFLASH_MAX_ERASE_REGIONS]; |
76 | uint32_t sector_len[PFLASH_MAX_ERASE_REGIONS]; | |
4fbd24ba | 77 | uint32_t chip_len; |
368a354f PC |
78 | uint8_t mappings; |
79 | uint8_t width; | |
80 | uint8_t be; | |
29133e9a FB |
81 | int wcycle; /* if 0, the flash is read normally */ |
82 | int bypass; | |
83 | int ro; | |
84 | uint8_t cmd; | |
85 | uint8_t status; | |
368a354f PC |
86 | /* FIXME: implement array device properties */ |
87 | uint16_t ident0; | |
88 | uint16_t ident1; | |
89 | uint16_t ident2; | |
90 | uint16_t ident3; | |
91 | uint16_t unlock_addr0; | |
92 | uint16_t unlock_addr1; | |
64659053 | 93 | uint8_t cfi_table[0x4d]; |
d80cf1eb | 94 | QEMUTimer timer; |
ccd8014b PMD |
95 | /* |
96 | * The device replicates the flash memory across its memory space. Emulate | |
cfe5f011 AK |
97 | * that by having a container (.mem) filled with an array of aliases |
98 | * (.mem_mappings) pointing to the flash memory (.orig_mem). | |
99 | */ | |
100 | MemoryRegion mem; | |
101 | MemoryRegion *mem_mappings; /* array; one per mapping */ | |
102 | MemoryRegion orig_mem; | |
326d02c3 | 103 | bool rom_mode; |
661bfc80 | 104 | int read_counter; /* used for lazy switch-back to rom mode */ |
a50547ac | 105 | int sectors_to_erase; |
ddb6f225 SC |
106 | uint64_t erase_time_remaining; |
107 | unsigned long *sector_erase_map; | |
368a354f | 108 | char *name; |
29133e9a FB |
109 | void *storage; |
110 | }; | |
111 | ||
1d311e73 PMD |
112 | /* |
113 | * Toggle status bit DQ7. | |
114 | */ | |
115 | static inline void toggle_dq7(PFlashCFI02 *pfl) | |
116 | { | |
117 | pfl->status ^= 0x80; | |
118 | } | |
119 | ||
120 | /* | |
121 | * Set status bit DQ7 to bit 7 of value. | |
122 | */ | |
123 | static inline void set_dq7(PFlashCFI02 *pfl, uint8_t value) | |
124 | { | |
125 | pfl->status &= 0x7F; | |
126 | pfl->status |= value & 0x80; | |
127 | } | |
128 | ||
129 | /* | |
130 | * Toggle status bit DQ6. | |
131 | */ | |
132 | static inline void toggle_dq6(PFlashCFI02 *pfl) | |
133 | { | |
134 | pfl->status ^= 0x40; | |
135 | } | |
136 | ||
a50547ac SC |
137 | /* |
138 | * Turn on DQ3. | |
139 | */ | |
140 | static inline void assert_dq3(PFlashCFI02 *pfl) | |
141 | { | |
142 | pfl->status |= 0x08; | |
143 | } | |
144 | ||
145 | /* | |
146 | * Turn off DQ3. | |
147 | */ | |
148 | static inline void reset_dq3(PFlashCFI02 *pfl) | |
149 | { | |
150 | pfl->status &= ~0x08; | |
151 | } | |
152 | ||
ddb6f225 SC |
153 | /* |
154 | * Toggle status bit DQ2. | |
155 | */ | |
156 | static inline void toggle_dq2(PFlashCFI02 *pfl) | |
157 | { | |
158 | pfl->status ^= 0x04; | |
159 | } | |
160 | ||
cfe5f011 AK |
161 | /* |
162 | * Set up replicated mappings of the same region. | |
163 | */ | |
16434065 | 164 | static void pflash_setup_mappings(PFlashCFI02 *pfl) |
c8a50e59 | 165 | { |
cfe5f011 | 166 | unsigned i; |
a8170e5e | 167 | hwaddr size = memory_region_size(&pfl->orig_mem); |
cfe5f011 | 168 | |
2d256e6f | 169 | memory_region_init(&pfl->mem, OBJECT(pfl), "pflash", pfl->mappings * size); |
cfe5f011 AK |
170 | pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings); |
171 | for (i = 0; i < pfl->mappings; ++i) { | |
2d256e6f PB |
172 | memory_region_init_alias(&pfl->mem_mappings[i], OBJECT(pfl), |
173 | "pflash-alias", &pfl->orig_mem, 0, size); | |
cfe5f011 AK |
174 | memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]); |
175 | } | |
176 | } | |
01e0451a | 177 | |
7d1df53f | 178 | static void pflash_reset_state_machine(PFlashCFI02 *pfl) |
cfe5f011 | 179 | { |
91316cbb | 180 | trace_pflash_reset(pfl->name); |
7cb10960 PMD |
181 | pfl->cmd = 0x00; |
182 | pfl->wcycle = 0; | |
7d1df53f PMD |
183 | } |
184 | ||
185 | static void pflash_mode_read_array(PFlashCFI02 *pfl) | |
186 | { | |
91316cbb | 187 | trace_pflash_mode_read_array(pfl->name); |
7d1df53f | 188 | pflash_reset_state_machine(pfl); |
7cb10960 PMD |
189 | pfl->rom_mode = true; |
190 | memory_region_rom_device_set_romd(&pfl->orig_mem, true); | |
4fbd24ba AZ |
191 | } |
192 | ||
102f0f79 PMD |
193 | static size_t pflash_regions_count(PFlashCFI02 *pfl) |
194 | { | |
195 | return pfl->cfi_table[0x2c]; | |
196 | } | |
197 | ||
ddb6f225 SC |
198 | /* |
199 | * Returns the time it takes to erase the number of sectors scheduled for | |
200 | * erasure based on CFI address 0x21 which is "Typical timeout per individual | |
201 | * block erase 2^N ms." | |
202 | */ | |
203 | static uint64_t pflash_erase_time(PFlashCFI02 *pfl) | |
204 | { | |
205 | /* | |
206 | * If there are no sectors to erase (which can happen if all of the sectors | |
207 | * to be erased are protected), then erase takes 100 us. Protected sectors | |
208 | * aren't supported so this should never happen. | |
209 | */ | |
210 | return ((1ULL << pfl->cfi_table[0x21]) * pfl->sectors_to_erase) * SCALE_US; | |
211 | } | |
212 | ||
213 | /* | |
214 | * Returns true if the device is currently in erase suspend mode. | |
215 | */ | |
216 | static inline bool pflash_erase_suspend_mode(PFlashCFI02 *pfl) | |
217 | { | |
218 | return pfl->erase_time_remaining > 0; | |
219 | } | |
220 | ||
a50547ac | 221 | static void pflash_timer(void *opaque) |
29133e9a | 222 | { |
16434065 | 223 | PFlashCFI02 *pfl = opaque; |
29133e9a | 224 | |
91316cbb | 225 | trace_pflash_timer_expired(pfl->name, pfl->cmd); |
a50547ac SC |
226 | if (pfl->cmd == 0x30) { |
227 | /* | |
228 | * Sector erase. If DQ3 is 0 when the timer expires, then the 50 | |
229 | * us erase timeout has expired so we need to start the timer for the | |
230 | * sector erase algorithm. Otherwise, the erase completed and we should | |
231 | * go back to read array mode. | |
232 | */ | |
233 | if ((pfl->status & 0x08) == 0) { | |
234 | assert_dq3(pfl); | |
ddb6f225 | 235 | uint64_t timeout = pflash_erase_time(pfl); |
a50547ac SC |
236 | timer_mod(&pfl->timer, |
237 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout); | |
91316cbb | 238 | trace_pflash_erase_timeout(pfl->name, pfl->sectors_to_erase); |
a50547ac SC |
239 | return; |
240 | } | |
91316cbb | 241 | trace_pflash_erase_complete(pfl->name); |
ddb6f225 | 242 | bitmap_zero(pfl->sector_erase_map, pfl->total_sectors); |
a50547ac SC |
243 | pfl->sectors_to_erase = 0; |
244 | reset_dq3(pfl); | |
245 | } | |
246 | ||
29133e9a | 247 | /* Reset flash */ |
1d311e73 | 248 | toggle_dq7(pfl); |
29133e9a FB |
249 | if (pfl->bypass) { |
250 | pfl->wcycle = 2; | |
7cb10960 | 251 | pfl->cmd = 0; |
29133e9a | 252 | } else { |
7cb10960 | 253 | pflash_mode_read_array(pfl); |
29133e9a | 254 | } |
29133e9a FB |
255 | } |
256 | ||
06e8b8e3 PMD |
257 | /* |
258 | * Read data from flash. | |
259 | */ | |
260 | static uint64_t pflash_data_read(PFlashCFI02 *pfl, hwaddr offset, | |
261 | unsigned int width) | |
262 | { | |
263 | uint8_t *p = (uint8_t *)pfl->storage + offset; | |
264 | uint64_t ret = pfl->be ? ldn_be_p(p, width) : ldn_le_p(p, width); | |
91316cbb | 265 | trace_pflash_data_read(pfl->name, offset, width, ret); |
06e8b8e3 PMD |
266 | return ret; |
267 | } | |
268 | ||
ddb6f225 SC |
269 | typedef struct { |
270 | uint32_t len; | |
271 | uint32_t num; | |
272 | } SectorInfo; | |
273 | ||
64659053 SC |
274 | /* |
275 | * offset should be a byte offset of the QEMU device and _not_ a device | |
276 | * offset. | |
277 | */ | |
ddb6f225 | 278 | static SectorInfo pflash_sector_info(PFlashCFI02 *pfl, hwaddr offset) |
64659053 SC |
279 | { |
280 | assert(offset < pfl->chip_len); | |
64659053 | 281 | hwaddr addr = 0; |
ddb6f225 | 282 | uint32_t sector_num = 0; |
102f0f79 | 283 | for (int i = 0; i < pflash_regions_count(pfl); ++i) { |
64659053 SC |
284 | uint64_t region_size = (uint64_t)pfl->nb_blocs[i] * pfl->sector_len[i]; |
285 | if (addr <= offset && offset < addr + region_size) { | |
ddb6f225 SC |
286 | return (SectorInfo) { |
287 | .len = pfl->sector_len[i], | |
288 | .num = sector_num + (offset - addr) / pfl->sector_len[i], | |
289 | }; | |
64659053 | 290 | } |
ddb6f225 | 291 | sector_num += pfl->nb_blocs[i]; |
64659053 SC |
292 | addr += region_size; |
293 | } | |
294 | abort(); | |
295 | } | |
296 | ||
ddb6f225 SC |
297 | /* |
298 | * Returns true if the offset refers to a flash sector that is currently being | |
299 | * erased. | |
300 | */ | |
301 | static bool pflash_sector_is_erasing(PFlashCFI02 *pfl, hwaddr offset) | |
302 | { | |
303 | long sector_num = pflash_sector_info(pfl, offset).num; | |
304 | return test_bit(sector_num, pfl->sector_erase_map); | |
305 | } | |
306 | ||
aff498cf | 307 | static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int width) |
29133e9a | 308 | { |
aff498cf | 309 | PFlashCFI02 *pfl = opaque; |
a8170e5e | 310 | hwaddr boff; |
aff498cf | 311 | uint64_t ret; |
29133e9a | 312 | |
661bfc80 JK |
313 | /* Lazy reset to ROMD mode after a certain amount of read accesses */ |
314 | if (!pfl->rom_mode && pfl->wcycle == 0 && | |
315 | ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) { | |
7cb10960 | 316 | pflash_mode_read_array(pfl); |
0f459d16 | 317 | } |
4fbd24ba | 318 | offset &= pfl->chip_len - 1; |
29133e9a | 319 | boff = offset & 0xFF; |
64659053 | 320 | if (pfl->width == 2) { |
29133e9a | 321 | boff = boff >> 1; |
51500d37 PMD |
322 | } else if (pfl->width == 4) { |
323 | boff = boff >> 2; | |
64659053 | 324 | } |
29133e9a FB |
325 | switch (pfl->cmd) { |
326 | default: | |
327 | /* This should never happen : reset state & treat it as a read*/ | |
91316cbb | 328 | trace_pflash_read_unknown_state(pfl->name, pfl->cmd); |
7d1df53f | 329 | pflash_reset_state_machine(pfl); |
30954850 | 330 | /* fall through to the read code */ |
b0349937 | 331 | case 0x80: /* Erase (unlock) */ |
29133e9a FB |
332 | /* We accept reads during second unlock sequence... */ |
333 | case 0x00: | |
ddb6f225 SC |
334 | if (pflash_erase_suspend_mode(pfl) && |
335 | pflash_sector_is_erasing(pfl, offset)) { | |
336 | /* Toggle bit 2, but not 6. */ | |
337 | toggle_dq2(pfl); | |
338 | /* Status register read */ | |
339 | ret = pfl->status; | |
91316cbb | 340 | trace_pflash_read_status(pfl->name, ret); |
ddb6f225 SC |
341 | break; |
342 | } | |
29133e9a | 343 | /* Flash area read */ |
06e8b8e3 | 344 | ret = pflash_data_read(pfl, offset, width); |
29133e9a | 345 | break; |
b0349937 | 346 | case 0x90: /* flash ID read */ |
29133e9a FB |
347 | switch (boff) { |
348 | case 0x00: | |
349 | case 0x01: | |
368a354f | 350 | ret = boff & 0x01 ? pfl->ident1 : pfl->ident0; |
29133e9a FB |
351 | break; |
352 | case 0x02: | |
353 | ret = 0x00; /* Pretend all sectors are unprotected */ | |
354 | break; | |
355 | case 0x0E: | |
356 | case 0x0F: | |
368a354f | 357 | ret = boff & 0x01 ? pfl->ident3 : pfl->ident2; |
7f7bdcaf PMD |
358 | if (ret != (uint8_t)-1) { |
359 | break; | |
368a354f | 360 | } |
7f7bdcaf | 361 | /* Fall through to data read. */ |
29133e9a | 362 | default: |
06e8b8e3 | 363 | ret = pflash_data_read(pfl, offset, width); |
29133e9a | 364 | } |
91316cbb | 365 | trace_pflash_read_done(pfl->name, boff, ret); |
29133e9a | 366 | break; |
b0349937 PMD |
367 | case 0x10: /* Chip Erase */ |
368 | case 0x30: /* Sector Erase */ | |
ddb6f225 SC |
369 | /* Toggle bit 2 during erase, but not program. */ |
370 | toggle_dq2(pfl); | |
2658594f | 371 | /* fall through */ |
b0349937 | 372 | case 0xA0: /* Program */ |
ddb6f225 SC |
373 | /* Toggle bit 6 */ |
374 | toggle_dq6(pfl); | |
29133e9a FB |
375 | /* Status register read */ |
376 | ret = pfl->status; | |
91316cbb | 377 | trace_pflash_read_status(pfl->name, ret); |
29133e9a FB |
378 | break; |
379 | case 0x98: | |
380 | /* CFI query mode */ | |
07c13a71 | 381 | if (boff < sizeof(pfl->cfi_table)) { |
29133e9a | 382 | ret = pfl->cfi_table[boff]; |
07c13a71 PMD |
383 | } else { |
384 | ret = 0; | |
385 | } | |
29133e9a FB |
386 | break; |
387 | } | |
91316cbb | 388 | trace_pflash_io_read(pfl->name, offset, width, ret, pfl->cmd, pfl->wcycle); |
29133e9a FB |
389 | |
390 | return ret; | |
391 | } | |
392 | ||
393 | /* update flash content on disk */ | |
aff498cf | 394 | static void pflash_update(PFlashCFI02 *pfl, int offset, int size) |
29133e9a FB |
395 | { |
396 | int offset_end; | |
1857b9db | 397 | int ret; |
4be74634 | 398 | if (pfl->blk) { |
29133e9a | 399 | offset_end = offset + size; |
098e732d EB |
400 | /* widen to sector boundaries */ |
401 | offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE); | |
402 | offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE); | |
a9262f55 AF |
403 | ret = blk_pwrite(pfl->blk, offset, offset_end - offset, |
404 | pfl->storage + offset, 0); | |
1857b9db MA |
405 | if (ret < 0) { |
406 | /* TODO set error bit in status */ | |
407 | error_report("Could not update PFLASH: %s", strerror(-ret)); | |
408 | } | |
29133e9a FB |
409 | } |
410 | } | |
411 | ||
a50547ac SC |
412 | static void pflash_sector_erase(PFlashCFI02 *pfl, hwaddr offset) |
413 | { | |
ddb6f225 SC |
414 | SectorInfo sector_info = pflash_sector_info(pfl, offset); |
415 | uint64_t sector_len = sector_info.len; | |
a50547ac | 416 | offset &= ~(sector_len - 1); |
91316cbb DE |
417 | trace_pflash_sector_erase_start(pfl->name, pfl->width * 2, offset, |
418 | pfl->width * 2, offset + sector_len - 1); | |
a50547ac SC |
419 | if (!pfl->ro) { |
420 | uint8_t *p = pfl->storage; | |
421 | memset(p + offset, 0xff, sector_len); | |
422 | pflash_update(pfl, offset, sector_len); | |
423 | } | |
424 | set_dq7(pfl, 0x00); | |
425 | ++pfl->sectors_to_erase; | |
ddb6f225 | 426 | set_bit(sector_info.num, pfl->sector_erase_map); |
a50547ac SC |
427 | /* Set (or reset) the 50 us timer for additional erase commands. */ |
428 | timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 50000); | |
429 | } | |
430 | ||
aff498cf PMD |
431 | static void pflash_write(void *opaque, hwaddr offset, uint64_t value, |
432 | unsigned int width) | |
29133e9a | 433 | { |
aff498cf | 434 | PFlashCFI02 *pfl = opaque; |
a8170e5e | 435 | hwaddr boff; |
29133e9a FB |
436 | uint8_t *p; |
437 | uint8_t cmd; | |
438 | ||
91316cbb | 439 | trace_pflash_io_write(pfl->name, offset, width, value, pfl->wcycle); |
95d1f3ed | 440 | cmd = value; |
8a508e70 | 441 | if (pfl->cmd != 0xA0) { |
a9791042 SC |
442 | /* Reset does nothing during chip erase and sector erase. */ |
443 | if (cmd == 0xF0 && pfl->cmd != 0x10 && pfl->cmd != 0x30) { | |
46fb7809 SC |
444 | if (pfl->wcycle == WCYCLE_AUTOSELECT_CFI) { |
445 | /* Return to autoselect mode. */ | |
446 | pfl->wcycle = 3; | |
447 | pfl->cmd = 0x90; | |
448 | return; | |
449 | } | |
8a508e70 PMD |
450 | goto reset_flash; |
451 | } | |
95d1f3ed | 452 | } |
4fbd24ba | 453 | offset &= pfl->chip_len - 1; |
3b46e624 | 454 | |
6682bc1e | 455 | boff = offset; |
64659053 | 456 | if (pfl->width == 2) { |
29133e9a | 457 | boff = boff >> 1; |
51500d37 PMD |
458 | } else if (pfl->width == 4) { |
459 | boff = boff >> 2; | |
64659053 | 460 | } |
6682bc1e SC |
461 | /* Only the least-significant 11 bits are used in most cases. */ |
462 | boff &= 0x7FF; | |
29133e9a FB |
463 | switch (pfl->wcycle) { |
464 | case 0: | |
9c9bb6c8 | 465 | /* Set the device in I/O access mode if required */ |
cadf25cf PMD |
466 | if (pfl->rom_mode) { |
467 | pfl->rom_mode = false; | |
468 | memory_region_rom_device_set_romd(&pfl->orig_mem, false); | |
469 | } | |
661bfc80 | 470 | pfl->read_counter = 0; |
29133e9a FB |
471 | /* We're in read mode */ |
472 | check_unlock0: | |
473 | if (boff == 0x55 && cmd == 0x98) { | |
29133e9a | 474 | /* Enter CFI query mode */ |
aeaf6c20 | 475 | pfl->wcycle = WCYCLE_CFI; |
29133e9a FB |
476 | pfl->cmd = 0x98; |
477 | return; | |
478 | } | |
ddb6f225 | 479 | /* Handle erase resume in erase suspend mode, otherwise reset. */ |
b0349937 | 480 | if (cmd == 0x30) { /* Erase Resume */ |
ddb6f225 SC |
481 | if (pflash_erase_suspend_mode(pfl)) { |
482 | /* Resume the erase. */ | |
483 | timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + | |
484 | pfl->erase_time_remaining); | |
485 | pfl->erase_time_remaining = 0; | |
486 | pfl->wcycle = 6; | |
487 | pfl->cmd = 0x30; | |
488 | set_dq7(pfl, 0x00); | |
489 | assert_dq3(pfl); | |
490 | return; | |
491 | } | |
492 | goto reset_flash; | |
493 | } | |
494 | /* Ignore erase suspend. */ | |
b0349937 | 495 | if (cmd == 0xB0) { /* Erase Suspend */ |
ddb6f225 SC |
496 | return; |
497 | } | |
368a354f | 498 | if (boff != pfl->unlock_addr0 || cmd != 0xAA) { |
91316cbb DE |
499 | trace_pflash_unlock0_failed(pfl->name, boff, |
500 | cmd, pfl->unlock_addr0); | |
29133e9a FB |
501 | goto reset_flash; |
502 | } | |
91316cbb | 503 | trace_pflash_write(pfl->name, "unlock sequence started"); |
29133e9a FB |
504 | break; |
505 | case 1: | |
506 | /* We started an unlock sequence */ | |
507 | check_unlock1: | |
368a354f | 508 | if (boff != pfl->unlock_addr1 || cmd != 0x55) { |
91316cbb | 509 | trace_pflash_unlock1_failed(pfl->name, boff, cmd); |
29133e9a FB |
510 | goto reset_flash; |
511 | } | |
91316cbb | 512 | trace_pflash_write(pfl->name, "unlock sequence done"); |
29133e9a FB |
513 | break; |
514 | case 2: | |
515 | /* We finished an unlock sequence */ | |
368a354f | 516 | if (!pfl->bypass && boff != pfl->unlock_addr0) { |
91316cbb | 517 | trace_pflash_write_failed(pfl->name, boff, cmd); |
29133e9a FB |
518 | goto reset_flash; |
519 | } | |
520 | switch (cmd) { | |
521 | case 0x20: | |
522 | pfl->bypass = 1; | |
523 | goto do_bypass; | |
b0349937 PMD |
524 | case 0x80: /* Erase */ |
525 | case 0x90: /* Autoselect */ | |
526 | case 0xA0: /* Program */ | |
29133e9a | 527 | pfl->cmd = cmd; |
91316cbb | 528 | trace_pflash_write_start(pfl->name, cmd); |
29133e9a FB |
529 | break; |
530 | default: | |
91316cbb | 531 | trace_pflash_write_unknown(pfl->name, cmd); |
29133e9a FB |
532 | goto reset_flash; |
533 | } | |
534 | break; | |
535 | case 3: | |
536 | switch (pfl->cmd) { | |
b0349937 | 537 | case 0x80: /* Erase */ |
29133e9a FB |
538 | /* We need another unlock sequence */ |
539 | goto check_unlock0; | |
b0349937 | 540 | case 0xA0: /* Program */ |
ddb6f225 SC |
541 | if (pflash_erase_suspend_mode(pfl) && |
542 | pflash_sector_is_erasing(pfl, offset)) { | |
543 | /* Ignore writes to erasing sectors. */ | |
544 | if (pfl->bypass) { | |
545 | goto do_bypass; | |
546 | } | |
547 | goto reset_flash; | |
548 | } | |
91316cbb | 549 | trace_pflash_data_write(pfl->name, offset, width, value, 0); |
de8efe8f | 550 | if (!pfl->ro) { |
c3d25271 PMD |
551 | p = (uint8_t *)pfl->storage + offset; |
552 | if (pfl->be) { | |
553 | uint64_t current = ldn_be_p(p, width); | |
554 | stn_be_p(p, width, current & value); | |
555 | } else { | |
556 | uint64_t current = ldn_le_p(p, width); | |
557 | stn_le_p(p, width, current & value); | |
5f9fc5ad | 558 | } |
c3d25271 | 559 | pflash_update(pfl, offset, width); |
29133e9a | 560 | } |
1d311e73 PMD |
561 | /* |
562 | * While programming, status bit DQ7 should hold the opposite | |
563 | * value from how it was programmed. | |
564 | */ | |
565 | set_dq7(pfl, ~value); | |
29133e9a FB |
566 | /* Let's pretend write is immediate */ |
567 | if (pfl->bypass) | |
568 | goto do_bypass; | |
569 | goto reset_flash; | |
b0349937 | 570 | case 0x90: /* Autoselect */ |
29133e9a FB |
571 | if (pfl->bypass && cmd == 0x00) { |
572 | /* Unlock bypass reset */ | |
573 | goto reset_flash; | |
574 | } | |
46fb7809 SC |
575 | /* |
576 | * We can enter CFI query mode from autoselect mode, but we must | |
577 | * return to autoselect mode after a reset. | |
578 | */ | |
579 | if (boff == 0x55 && cmd == 0x98) { | |
580 | /* Enter autoselect CFI query mode */ | |
581 | pfl->wcycle = WCYCLE_AUTOSELECT_CFI; | |
582 | pfl->cmd = 0x98; | |
583 | return; | |
584 | } | |
124e4cfa | 585 | /* fall through */ |
29133e9a | 586 | default: |
91316cbb | 587 | trace_pflash_write_invalid(pfl->name, pfl->cmd); |
29133e9a FB |
588 | goto reset_flash; |
589 | } | |
590 | case 4: | |
591 | switch (pfl->cmd) { | |
b0349937 | 592 | case 0xA0: /* Program */ |
a1c7273b | 593 | /* Ignore writes while flash data write is occurring */ |
29133e9a FB |
594 | /* As we suppose write is immediate, this should never happen */ |
595 | return; | |
b0349937 | 596 | case 0x80: /* Erase */ |
29133e9a FB |
597 | goto check_unlock1; |
598 | default: | |
599 | /* Should never happen */ | |
91316cbb | 600 | trace_pflash_write_invalid_state(pfl->name, pfl->cmd, 5); |
29133e9a FB |
601 | goto reset_flash; |
602 | } | |
603 | break; | |
604 | case 5: | |
ddb6f225 SC |
605 | if (pflash_erase_suspend_mode(pfl)) { |
606 | /* Erasing is not supported in erase suspend mode. */ | |
607 | goto reset_flash; | |
608 | } | |
29133e9a | 609 | switch (cmd) { |
b0349937 | 610 | case 0x10: /* Chip Erase */ |
368a354f | 611 | if (boff != pfl->unlock_addr0) { |
91316cbb | 612 | trace_pflash_chip_erase_invalid(pfl->name, offset); |
29133e9a FB |
613 | goto reset_flash; |
614 | } | |
615 | /* Chip erase */ | |
91316cbb | 616 | trace_pflash_chip_erase_start(pfl->name); |
de8efe8f | 617 | if (!pfl->ro) { |
1eb27d69 | 618 | memset(pfl->storage, 0xff, pfl->chip_len); |
de8efe8f JJ |
619 | pflash_update(pfl, 0, pfl->chip_len); |
620 | } | |
1d311e73 | 621 | set_dq7(pfl, 0x00); |
80f2c625 | 622 | /* Wait the time specified at CFI address 0x22. */ |
d80cf1eb | 623 | timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
80f2c625 | 624 | (1ULL << pfl->cfi_table[0x22]) * SCALE_MS); |
29133e9a | 625 | break; |
b0349937 | 626 | case 0x30: /* Sector erase */ |
a50547ac | 627 | pflash_sector_erase(pfl, offset); |
29133e9a FB |
628 | break; |
629 | default: | |
91316cbb | 630 | trace_pflash_write_invalid_command(pfl->name, cmd); |
29133e9a FB |
631 | goto reset_flash; |
632 | } | |
633 | pfl->cmd = cmd; | |
634 | break; | |
635 | case 6: | |
636 | switch (pfl->cmd) { | |
b0349937 | 637 | case 0x10: /* Chip Erase */ |
29133e9a FB |
638 | /* Ignore writes during chip erase */ |
639 | return; | |
b0349937 | 640 | case 0x30: /* Sector erase */ |
ddb6f225 SC |
641 | if (cmd == 0xB0) { |
642 | /* | |
643 | * If erase suspend happens during the erase timeout (so DQ3 is | |
644 | * 0), then the device suspends erasing immediately. Set the | |
645 | * remaining time to be the total time to erase. Otherwise, | |
646 | * there is a maximum amount of time it can take to enter | |
647 | * suspend mode. Let's ignore that and suspend immediately and | |
648 | * set the remaining time to the actual time remaining on the | |
649 | * timer. | |
650 | */ | |
651 | if ((pfl->status & 0x08) == 0) { | |
652 | pfl->erase_time_remaining = pflash_erase_time(pfl); | |
653 | } else { | |
654 | int64_t delta = timer_expire_time_ns(&pfl->timer) - | |
655 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | |
656 | /* Make sure we have a positive time remaining. */ | |
657 | pfl->erase_time_remaining = delta <= 0 ? 1 : delta; | |
658 | } | |
659 | reset_dq3(pfl); | |
660 | timer_del(&pfl->timer); | |
7d1df53f | 661 | pflash_reset_state_machine(pfl); |
ddb6f225 SC |
662 | return; |
663 | } | |
a50547ac SC |
664 | /* |
665 | * If DQ3 is 0, additional sector erase commands can be | |
666 | * written and anything else (other than an erase suspend) resets | |
667 | * the device. | |
668 | */ | |
669 | if ((pfl->status & 0x08) == 0) { | |
670 | if (cmd == 0x30) { | |
671 | pflash_sector_erase(pfl, offset); | |
672 | } else { | |
673 | goto reset_flash; | |
674 | } | |
675 | } | |
676 | /* Ignore writes during the actual erase. */ | |
29133e9a FB |
677 | return; |
678 | default: | |
679 | /* Should never happen */ | |
91316cbb | 680 | trace_pflash_write_invalid_state(pfl->name, pfl->cmd, 6); |
29133e9a FB |
681 | goto reset_flash; |
682 | } | |
683 | break; | |
aeaf6c20 PMD |
684 | /* Special values for CFI queries */ |
685 | case WCYCLE_CFI: | |
46fb7809 | 686 | case WCYCLE_AUTOSELECT_CFI: |
91316cbb | 687 | trace_pflash_write(pfl->name, "invalid write in CFI query mode"); |
29133e9a FB |
688 | goto reset_flash; |
689 | default: | |
690 | /* Should never happen */ | |
91316cbb | 691 | trace_pflash_write(pfl->name, "invalid write state (wc 7)"); |
29133e9a FB |
692 | goto reset_flash; |
693 | } | |
694 | pfl->wcycle++; | |
695 | ||
696 | return; | |
697 | ||
698 | /* Reset flash */ | |
699 | reset_flash: | |
29133e9a | 700 | pfl->bypass = 0; |
7d1df53f | 701 | pflash_reset_state_machine(pfl); |
29133e9a FB |
702 | return; |
703 | ||
704 | do_bypass: | |
705 | pfl->wcycle = 2; | |
706 | pfl->cmd = 0; | |
29133e9a FB |
707 | } |
708 | ||
aff498cf PMD |
709 | static const MemoryRegionOps pflash_cfi02_ops = { |
710 | .read = pflash_read, | |
711 | .write = pflash_write, | |
a4afb28d PM |
712 | .valid.min_access_size = 1, |
713 | .valid.max_access_size = 4, | |
cfe5f011 | 714 | .endianness = DEVICE_NATIVE_ENDIAN, |
29133e9a FB |
715 | }; |
716 | ||
4586c2e5 PMD |
717 | static void pflash_cfi02_fill_cfi_table(PFlashCFI02 *pfl, int nb_regions) |
718 | { | |
719 | /* Hardcoded CFI table (mostly from SG29 Spansion flash) */ | |
720 | const uint16_t pri_ofs = 0x40; | |
721 | /* Standard "QRY" string */ | |
722 | pfl->cfi_table[0x10] = 'Q'; | |
723 | pfl->cfi_table[0x11] = 'R'; | |
724 | pfl->cfi_table[0x12] = 'Y'; | |
725 | /* Command set (AMD/Fujitsu) */ | |
726 | pfl->cfi_table[0x13] = 0x02; | |
727 | pfl->cfi_table[0x14] = 0x00; | |
728 | /* Primary extended table address */ | |
729 | pfl->cfi_table[0x15] = pri_ofs; | |
730 | pfl->cfi_table[0x16] = pri_ofs >> 8; | |
731 | /* Alternate command set (none) */ | |
732 | pfl->cfi_table[0x17] = 0x00; | |
733 | pfl->cfi_table[0x18] = 0x00; | |
734 | /* Alternate extended table (none) */ | |
735 | pfl->cfi_table[0x19] = 0x00; | |
736 | pfl->cfi_table[0x1A] = 0x00; | |
737 | /* Vcc min */ | |
738 | pfl->cfi_table[0x1B] = 0x27; | |
739 | /* Vcc max */ | |
740 | pfl->cfi_table[0x1C] = 0x36; | |
741 | /* Vpp min (no Vpp pin) */ | |
742 | pfl->cfi_table[0x1D] = 0x00; | |
743 | /* Vpp max (no Vpp pin) */ | |
744 | pfl->cfi_table[0x1E] = 0x00; | |
745 | /* Timeout per single byte/word write (128 ms) */ | |
746 | pfl->cfi_table[0x1F] = 0x07; | |
747 | /* Timeout for min size buffer write (NA) */ | |
748 | pfl->cfi_table[0x20] = 0x00; | |
749 | /* Typical timeout for block erase (512 ms) */ | |
750 | pfl->cfi_table[0x21] = 0x09; | |
751 | /* Typical timeout for full chip erase (4096 ms) */ | |
752 | pfl->cfi_table[0x22] = 0x0C; | |
753 | /* Reserved */ | |
754 | pfl->cfi_table[0x23] = 0x01; | |
755 | /* Max timeout for buffer write (NA) */ | |
756 | pfl->cfi_table[0x24] = 0x00; | |
757 | /* Max timeout for block erase */ | |
758 | pfl->cfi_table[0x25] = 0x0A; | |
759 | /* Max timeout for chip erase */ | |
760 | pfl->cfi_table[0x26] = 0x0D; | |
761 | /* Device size */ | |
762 | pfl->cfi_table[0x27] = ctz32(pfl->chip_len); | |
763 | /* Flash device interface (8 & 16 bits) */ | |
764 | pfl->cfi_table[0x28] = 0x02; | |
765 | pfl->cfi_table[0x29] = 0x00; | |
766 | /* Max number of bytes in multi-bytes write */ | |
767 | /* | |
768 | * XXX: disable buffered write as it's not supported | |
769 | * pfl->cfi_table[0x2A] = 0x05; | |
770 | */ | |
771 | pfl->cfi_table[0x2A] = 0x00; | |
772 | pfl->cfi_table[0x2B] = 0x00; | |
773 | /* Number of erase block regions */ | |
774 | pfl->cfi_table[0x2c] = nb_regions; | |
775 | /* Erase block regions */ | |
776 | for (int i = 0; i < nb_regions; ++i) { | |
777 | uint32_t sector_len_per_device = pfl->sector_len[i]; | |
778 | pfl->cfi_table[0x2d + 4 * i] = pfl->nb_blocs[i] - 1; | |
779 | pfl->cfi_table[0x2e + 4 * i] = (pfl->nb_blocs[i] - 1) >> 8; | |
780 | pfl->cfi_table[0x2f + 4 * i] = sector_len_per_device >> 8; | |
781 | pfl->cfi_table[0x30 + 4 * i] = sector_len_per_device >> 16; | |
782 | } | |
783 | assert(0x2c + 4 * nb_regions < pri_ofs); | |
784 | ||
785 | /* Extended */ | |
786 | pfl->cfi_table[0x00 + pri_ofs] = 'P'; | |
787 | pfl->cfi_table[0x01 + pri_ofs] = 'R'; | |
788 | pfl->cfi_table[0x02 + pri_ofs] = 'I'; | |
789 | ||
790 | /* Extended version 1.0 */ | |
791 | pfl->cfi_table[0x03 + pri_ofs] = '1'; | |
792 | pfl->cfi_table[0x04 + pri_ofs] = '0'; | |
793 | ||
794 | /* Address sensitive unlock required. */ | |
795 | pfl->cfi_table[0x05 + pri_ofs] = 0x00; | |
796 | /* Erase suspend to read/write. */ | |
797 | pfl->cfi_table[0x06 + pri_ofs] = 0x02; | |
798 | /* Sector protect not supported. */ | |
799 | pfl->cfi_table[0x07 + pri_ofs] = 0x00; | |
800 | /* Temporary sector unprotect not supported. */ | |
801 | pfl->cfi_table[0x08 + pri_ofs] = 0x00; | |
802 | ||
803 | /* Sector protect/unprotect scheme. */ | |
804 | pfl->cfi_table[0x09 + pri_ofs] = 0x00; | |
805 | ||
806 | /* Simultaneous operation not supported. */ | |
807 | pfl->cfi_table[0x0a + pri_ofs] = 0x00; | |
808 | /* Burst mode not supported. */ | |
809 | pfl->cfi_table[0x0b + pri_ofs] = 0x00; | |
810 | /* Page mode not supported. */ | |
811 | pfl->cfi_table[0x0c + pri_ofs] = 0x00; | |
812 | assert(0x0c + pri_ofs < ARRAY_SIZE(pfl->cfi_table)); | |
813 | } | |
814 | ||
da3bd642 | 815 | static void pflash_cfi02_realize(DeviceState *dev, Error **errp) |
29133e9a | 816 | { |
76612456 | 817 | ERRP_GUARD(); |
e7b62741 | 818 | PFlashCFI02 *pfl = PFLASH_CFI02(dev); |
d0e7605e | 819 | int ret; |
29133e9a | 820 | |
64659053 | 821 | if (pfl->uniform_sector_len == 0 && pfl->sector_len[0] == 0) { |
8929fc3a ZY |
822 | error_setg(errp, "attribute \"sector-length\" not specified or zero."); |
823 | return; | |
824 | } | |
64659053 | 825 | if (pfl->uniform_nb_blocs == 0 && pfl->nb_blocs[0] == 0) { |
8929fc3a ZY |
826 | error_setg(errp, "attribute \"num-blocks\" not specified or zero."); |
827 | return; | |
828 | } | |
829 | if (pfl->name == NULL) { | |
830 | error_setg(errp, "attribute \"name\" not specified."); | |
831 | return; | |
832 | } | |
833 | ||
64659053 SC |
834 | int nb_regions; |
835 | pfl->chip_len = 0; | |
ddb6f225 | 836 | pfl->total_sectors = 0; |
64659053 SC |
837 | for (nb_regions = 0; nb_regions < PFLASH_MAX_ERASE_REGIONS; ++nb_regions) { |
838 | if (pfl->nb_blocs[nb_regions] == 0) { | |
839 | break; | |
840 | } | |
ddb6f225 | 841 | pfl->total_sectors += pfl->nb_blocs[nb_regions]; |
64659053 SC |
842 | uint64_t sector_len_per_device = pfl->sector_len[nb_regions]; |
843 | ||
844 | /* | |
845 | * The size of each flash sector must be a power of 2 and it must be | |
846 | * aligned at the same power of 2. | |
847 | */ | |
848 | if (sector_len_per_device & 0xff || | |
849 | sector_len_per_device >= (1 << 24) || | |
850 | !is_power_of_2(sector_len_per_device)) | |
851 | { | |
852 | error_setg(errp, "unsupported configuration: " | |
853 | "sector length[%d] per device = %" PRIx64 ".", | |
854 | nb_regions, sector_len_per_device); | |
855 | return; | |
856 | } | |
857 | if (pfl->chip_len & (sector_len_per_device - 1)) { | |
858 | error_setg(errp, "unsupported configuration: " | |
859 | "flash region %d not correctly aligned.", | |
860 | nb_regions); | |
861 | return; | |
862 | } | |
863 | ||
864 | pfl->chip_len += (uint64_t)pfl->sector_len[nb_regions] * | |
865 | pfl->nb_blocs[nb_regions]; | |
866 | } | |
867 | ||
868 | uint64_t uniform_len = (uint64_t)pfl->uniform_nb_blocs * | |
869 | pfl->uniform_sector_len; | |
870 | if (nb_regions == 0) { | |
871 | nb_regions = 1; | |
872 | pfl->nb_blocs[0] = pfl->uniform_nb_blocs; | |
873 | pfl->sector_len[0] = pfl->uniform_sector_len; | |
874 | pfl->chip_len = uniform_len; | |
ddb6f225 | 875 | pfl->total_sectors = pfl->uniform_nb_blocs; |
64659053 SC |
876 | } else if (uniform_len != 0 && uniform_len != pfl->chip_len) { |
877 | error_setg(errp, "\"num-blocks\"*\"sector-length\" " | |
878 | "different from \"num-blocks0\"*\'sector-length0\" + ... + " | |
879 | "\"num-blocks3\"*\"sector-length3\""); | |
880 | return; | |
881 | } | |
368a354f | 882 | |
aff498cf PMD |
883 | memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl), |
884 | &pflash_cfi02_ops, pfl, pfl->name, | |
76612456 VSO |
885 | pfl->chip_len, errp); |
886 | if (*errp) { | |
33e0eb52 HT |
887 | return; |
888 | } | |
889 | ||
cfe5f011 | 890 | pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem); |
a17c17a2 KW |
891 | |
892 | if (pfl->blk) { | |
893 | uint64_t perm; | |
86b1cf32 | 894 | pfl->ro = !blk_supports_write_perm(pfl->blk); |
a17c17a2 KW |
895 | perm = BLK_PERM_CONSISTENT_READ | (pfl->ro ? 0 : BLK_PERM_WRITE); |
896 | ret = blk_set_perm(pfl->blk, perm, BLK_PERM_ALL, errp); | |
897 | if (ret < 0) { | |
898 | return; | |
899 | } | |
900 | } else { | |
901 | pfl->ro = 0; | |
902 | } | |
903 | ||
4be74634 | 904 | if (pfl->blk) { |
1eb27d69 PMD |
905 | if (!blk_check_size_and_read_all(pfl->blk, pfl->storage, |
906 | pfl->chip_len, errp)) { | |
da3bd642 | 907 | vmstate_unregister_ram(&pfl->orig_mem, DEVICE(pfl)); |
da3bd642 | 908 | return; |
d0e7605e | 909 | } |
29133e9a | 910 | } |
de8efe8f | 911 | |
6682bc1e SC |
912 | /* Only 11 bits are used in the comparison. */ |
913 | pfl->unlock_addr0 &= 0x7FF; | |
914 | pfl->unlock_addr1 &= 0x7FF; | |
915 | ||
ddb6f225 SC |
916 | /* Allocate memory for a bitmap for sectors being erased. */ |
917 | pfl->sector_erase_map = bitmap_new(pfl->total_sectors); | |
918 | ||
1d4ae5a3 | 919 | pfl->rom_mode = true; |
27545c9d PMD |
920 | if (pfl->mappings > 1) { |
921 | pflash_setup_mappings(pfl); | |
922 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem); | |
923 | } else { | |
924 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->orig_mem); | |
925 | } | |
de8efe8f | 926 | |
d80cf1eb | 927 | timer_init_ns(&pfl->timer, QEMU_CLOCK_VIRTUAL, pflash_timer, pfl); |
29133e9a | 928 | pfl->status = 0; |
9ac45b88 | 929 | |
4586c2e5 | 930 | pflash_cfi02_fill_cfi_table(pfl, nb_regions); |
368a354f PC |
931 | } |
932 | ||
d9106341 PMD |
933 | static void pflash_cfi02_reset(DeviceState *dev) |
934 | { | |
935 | PFlashCFI02 *pfl = PFLASH_CFI02(dev); | |
936 | ||
937 | pflash_reset_state_machine(pfl); | |
938 | } | |
939 | ||
368a354f | 940 | static Property pflash_cfi02_properties[] = { |
16434065 | 941 | DEFINE_PROP_DRIVE("drive", PFlashCFI02, blk), |
64659053 SC |
942 | DEFINE_PROP_UINT32("num-blocks", PFlashCFI02, uniform_nb_blocs, 0), |
943 | DEFINE_PROP_UINT32("sector-length", PFlashCFI02, uniform_sector_len, 0), | |
944 | DEFINE_PROP_UINT32("num-blocks0", PFlashCFI02, nb_blocs[0], 0), | |
945 | DEFINE_PROP_UINT32("sector-length0", PFlashCFI02, sector_len[0], 0), | |
946 | DEFINE_PROP_UINT32("num-blocks1", PFlashCFI02, nb_blocs[1], 0), | |
947 | DEFINE_PROP_UINT32("sector-length1", PFlashCFI02, sector_len[1], 0), | |
948 | DEFINE_PROP_UINT32("num-blocks2", PFlashCFI02, nb_blocs[2], 0), | |
949 | DEFINE_PROP_UINT32("sector-length2", PFlashCFI02, sector_len[2], 0), | |
950 | DEFINE_PROP_UINT32("num-blocks3", PFlashCFI02, nb_blocs[3], 0), | |
951 | DEFINE_PROP_UINT32("sector-length3", PFlashCFI02, sector_len[3], 0), | |
16434065 MA |
952 | DEFINE_PROP_UINT8("width", PFlashCFI02, width, 0), |
953 | DEFINE_PROP_UINT8("mappings", PFlashCFI02, mappings, 0), | |
954 | DEFINE_PROP_UINT8("big-endian", PFlashCFI02, be, 0), | |
955 | DEFINE_PROP_UINT16("id0", PFlashCFI02, ident0, 0), | |
956 | DEFINE_PROP_UINT16("id1", PFlashCFI02, ident1, 0), | |
957 | DEFINE_PROP_UINT16("id2", PFlashCFI02, ident2, 0), | |
958 | DEFINE_PROP_UINT16("id3", PFlashCFI02, ident3, 0), | |
959 | DEFINE_PROP_UINT16("unlock-addr0", PFlashCFI02, unlock_addr0, 0), | |
960 | DEFINE_PROP_UINT16("unlock-addr1", PFlashCFI02, unlock_addr1, 0), | |
961 | DEFINE_PROP_STRING("name", PFlashCFI02, name), | |
368a354f PC |
962 | DEFINE_PROP_END_OF_LIST(), |
963 | }; | |
964 | ||
b69c3c21 | 965 | static void pflash_cfi02_unrealize(DeviceState *dev) |
d80cf1eb | 966 | { |
e7b62741 | 967 | PFlashCFI02 *pfl = PFLASH_CFI02(dev); |
d80cf1eb | 968 | timer_del(&pfl->timer); |
ddb6f225 | 969 | g_free(pfl->sector_erase_map); |
d80cf1eb SC |
970 | } |
971 | ||
368a354f PC |
972 | static void pflash_cfi02_class_init(ObjectClass *klass, void *data) |
973 | { | |
974 | DeviceClass *dc = DEVICE_CLASS(klass); | |
368a354f | 975 | |
da3bd642 | 976 | dc->realize = pflash_cfi02_realize; |
d9106341 | 977 | dc->reset = pflash_cfi02_reset; |
d80cf1eb | 978 | dc->unrealize = pflash_cfi02_unrealize; |
4f67d30b | 979 | device_class_set_props(dc, pflash_cfi02_properties); |
df6f9318 | 980 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
368a354f PC |
981 | } |
982 | ||
983 | static const TypeInfo pflash_cfi02_info = { | |
e7b62741 | 984 | .name = TYPE_PFLASH_CFI02, |
368a354f | 985 | .parent = TYPE_SYS_BUS_DEVICE, |
16434065 | 986 | .instance_size = sizeof(PFlashCFI02), |
368a354f PC |
987 | .class_init = pflash_cfi02_class_init, |
988 | }; | |
989 | ||
990 | static void pflash_cfi02_register_types(void) | |
991 | { | |
992 | type_register_static(&pflash_cfi02_info); | |
993 | } | |
994 | ||
995 | type_init(pflash_cfi02_register_types) | |
996 | ||
16434065 | 997 | PFlashCFI02 *pflash_cfi02_register(hwaddr base, |
940d5b13 | 998 | const char *name, |
16434065 MA |
999 | hwaddr size, |
1000 | BlockBackend *blk, | |
ce14710f | 1001 | uint32_t sector_len, |
16434065 MA |
1002 | int nb_mappings, int width, |
1003 | uint16_t id0, uint16_t id1, | |
1004 | uint16_t id2, uint16_t id3, | |
1005 | uint16_t unlock_addr0, | |
1006 | uint16_t unlock_addr1, | |
1007 | int be) | |
368a354f | 1008 | { |
3e80f690 | 1009 | DeviceState *dev = qdev_new(TYPE_PFLASH_CFI02); |
368a354f | 1010 | |
9b3d111a | 1011 | if (blk) { |
934df912 | 1012 | qdev_prop_set_drive(dev, "drive", blk); |
368a354f | 1013 | } |
4cdd0a77 | 1014 | assert(QEMU_IS_ALIGNED(size, sector_len)); |
ce14710f | 1015 | qdev_prop_set_uint32(dev, "num-blocks", size / sector_len); |
368a354f PC |
1016 | qdev_prop_set_uint32(dev, "sector-length", sector_len); |
1017 | qdev_prop_set_uint8(dev, "width", width); | |
1018 | qdev_prop_set_uint8(dev, "mappings", nb_mappings); | |
1019 | qdev_prop_set_uint8(dev, "big-endian", !!be); | |
1020 | qdev_prop_set_uint16(dev, "id0", id0); | |
1021 | qdev_prop_set_uint16(dev, "id1", id1); | |
1022 | qdev_prop_set_uint16(dev, "id2", id2); | |
1023 | qdev_prop_set_uint16(dev, "id3", id3); | |
1024 | qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0); | |
1025 | qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1); | |
1026 | qdev_prop_set_string(dev, "name", name); | |
3c6ef471 | 1027 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
368a354f | 1028 | |
3509c396 | 1029 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); |
e7b62741 | 1030 | return PFLASH_CFI02(dev); |
29133e9a | 1031 | } |