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Commit | Line | Data |
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29133e9a FB |
1 | /* |
2 | * CFI parallel flash with AMD command set emulation | |
5fafdf24 | 3 | * |
29133e9a FB |
4 | * Copyright (c) 2005 Jocelyn Mayer |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
29133e9a FB |
18 | */ |
19 | ||
20 | /* | |
21 | * For now, this code can emulate flashes of 1, 2 or 4 bytes width. | |
22 | * Supported commands/modes are: | |
23 | * - flash read | |
24 | * - flash write | |
25 | * - flash ID read | |
26 | * - sector erase | |
27 | * - chip erase | |
28 | * - unlock bypass command | |
29 | * - CFI queries | |
30 | * | |
31 | * It does not support flash interleaving. | |
32 | * It does not implement boot blocs with reduced size | |
33 | * It does not implement software data protection as found in many real chips | |
34 | * It does not implement erase suspend/resume commands | |
35 | * It does not implement multiple sectors erase | |
36 | */ | |
37 | ||
80c71a24 | 38 | #include "qemu/osdep.h" |
83c9f4ca | 39 | #include "hw/hw.h" |
06f15217 | 40 | #include "hw/block/block.h" |
0d09e41a | 41 | #include "hw/block/flash.h" |
da34e65c | 42 | #include "qapi/error.h" |
1de7afc9 | 43 | #include "qemu/timer.h" |
4be74634 | 44 | #include "sysemu/block-backend.h" |
1de7afc9 | 45 | #include "qemu/host-utils.h" |
0b8fa32f | 46 | #include "qemu/module.h" |
83c9f4ca | 47 | #include "hw/sysbus.h" |
13019f1f | 48 | #include "trace.h" |
29133e9a | 49 | |
6536987f | 50 | #define PFLASH_DEBUG false |
ec9ea489 PC |
51 | #define DPRINTF(fmt, ...) \ |
52 | do { \ | |
6536987f PMD |
53 | if (PFLASH_DEBUG) { \ |
54 | fprintf(stderr, "PFLASH: " fmt, ## __VA_ARGS__); \ | |
55 | } \ | |
29133e9a | 56 | } while (0) |
29133e9a | 57 | |
661bfc80 JK |
58 | #define PFLASH_LAZY_ROMD_THRESHOLD 42 |
59 | ||
16434065 | 60 | struct PFlashCFI02 { |
3509c396 HT |
61 | /*< private >*/ |
62 | SysBusDevice parent_obj; | |
63 | /*< public >*/ | |
64 | ||
4be74634 | 65 | BlockBackend *blk; |
71db710f | 66 | uint32_t sector_len; |
368a354f | 67 | uint32_t nb_blocs; |
4fbd24ba | 68 | uint32_t chip_len; |
368a354f PC |
69 | uint8_t mappings; |
70 | uint8_t width; | |
71 | uint8_t be; | |
29133e9a FB |
72 | int wcycle; /* if 0, the flash is read normally */ |
73 | int bypass; | |
74 | int ro; | |
75 | uint8_t cmd; | |
76 | uint8_t status; | |
368a354f PC |
77 | /* FIXME: implement array device properties */ |
78 | uint16_t ident0; | |
79 | uint16_t ident1; | |
80 | uint16_t ident2; | |
81 | uint16_t ident3; | |
82 | uint16_t unlock_addr0; | |
83 | uint16_t unlock_addr1; | |
29133e9a | 84 | uint8_t cfi_table[0x52]; |
d80cf1eb | 85 | QEMUTimer timer; |
cfe5f011 AK |
86 | /* The device replicates the flash memory across its memory space. Emulate |
87 | * that by having a container (.mem) filled with an array of aliases | |
88 | * (.mem_mappings) pointing to the flash memory (.orig_mem). | |
89 | */ | |
90 | MemoryRegion mem; | |
91 | MemoryRegion *mem_mappings; /* array; one per mapping */ | |
92 | MemoryRegion orig_mem; | |
9c9bb6c8 | 93 | int rom_mode; |
661bfc80 | 94 | int read_counter; /* used for lazy switch-back to rom mode */ |
368a354f | 95 | char *name; |
29133e9a FB |
96 | void *storage; |
97 | }; | |
98 | ||
cfe5f011 AK |
99 | /* |
100 | * Set up replicated mappings of the same region. | |
101 | */ | |
16434065 | 102 | static void pflash_setup_mappings(PFlashCFI02 *pfl) |
c8a50e59 | 103 | { |
cfe5f011 | 104 | unsigned i; |
a8170e5e | 105 | hwaddr size = memory_region_size(&pfl->orig_mem); |
cfe5f011 | 106 | |
2d256e6f | 107 | memory_region_init(&pfl->mem, OBJECT(pfl), "pflash", pfl->mappings * size); |
cfe5f011 AK |
108 | pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings); |
109 | for (i = 0; i < pfl->mappings; ++i) { | |
2d256e6f PB |
110 | memory_region_init_alias(&pfl->mem_mappings[i], OBJECT(pfl), |
111 | "pflash-alias", &pfl->orig_mem, 0, size); | |
cfe5f011 AK |
112 | memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]); |
113 | } | |
114 | } | |
01e0451a | 115 | |
16434065 | 116 | static void pflash_register_memory(PFlashCFI02 *pfl, int rom_mode) |
cfe5f011 | 117 | { |
5f9a5ea1 | 118 | memory_region_rom_device_set_romd(&pfl->orig_mem, rom_mode); |
bda254da | 119 | pfl->rom_mode = rom_mode; |
4fbd24ba AZ |
120 | } |
121 | ||
29133e9a FB |
122 | static void pflash_timer (void *opaque) |
123 | { | |
16434065 | 124 | PFlashCFI02 *pfl = opaque; |
29133e9a | 125 | |
13019f1f | 126 | trace_pflash_timer_expired(pfl->cmd); |
29133e9a FB |
127 | /* Reset flash */ |
128 | pfl->status ^= 0x80; | |
129 | if (pfl->bypass) { | |
130 | pfl->wcycle = 2; | |
131 | } else { | |
4fbd24ba | 132 | pflash_register_memory(pfl, 1); |
29133e9a FB |
133 | pfl->wcycle = 0; |
134 | } | |
135 | pfl->cmd = 0; | |
136 | } | |
137 | ||
16434065 MA |
138 | static uint32_t pflash_read(PFlashCFI02 *pfl, hwaddr offset, |
139 | int width, int be) | |
29133e9a | 140 | { |
a8170e5e | 141 | hwaddr boff; |
29133e9a FB |
142 | uint32_t ret; |
143 | uint8_t *p; | |
144 | ||
29133e9a | 145 | ret = -1; |
661bfc80 JK |
146 | /* Lazy reset to ROMD mode after a certain amount of read accesses */ |
147 | if (!pfl->rom_mode && pfl->wcycle == 0 && | |
148 | ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) { | |
149 | pflash_register_memory(pfl, 1); | |
0f459d16 | 150 | } |
4fbd24ba | 151 | offset &= pfl->chip_len - 1; |
29133e9a FB |
152 | boff = offset & 0xFF; |
153 | if (pfl->width == 2) | |
154 | boff = boff >> 1; | |
155 | else if (pfl->width == 4) | |
156 | boff = boff >> 2; | |
157 | switch (pfl->cmd) { | |
158 | default: | |
159 | /* This should never happen : reset state & treat it as a read*/ | |
160 | DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd); | |
161 | pfl->wcycle = 0; | |
162 | pfl->cmd = 0; | |
30954850 | 163 | /* fall through to the read code */ |
29133e9a FB |
164 | case 0x80: |
165 | /* We accept reads during second unlock sequence... */ | |
166 | case 0x00: | |
167 | flash_read: | |
168 | /* Flash area read */ | |
169 | p = pfl->storage; | |
170 | switch (width) { | |
171 | case 1: | |
172 | ret = p[offset]; | |
29133e9a FB |
173 | break; |
174 | case 2: | |
5f9fc5ad BS |
175 | if (be) { |
176 | ret = p[offset] << 8; | |
177 | ret |= p[offset + 1]; | |
178 | } else { | |
179 | ret = p[offset]; | |
180 | ret |= p[offset + 1] << 8; | |
181 | } | |
29133e9a FB |
182 | break; |
183 | case 4: | |
5f9fc5ad BS |
184 | if (be) { |
185 | ret = p[offset] << 24; | |
186 | ret |= p[offset + 1] << 16; | |
187 | ret |= p[offset + 2] << 8; | |
188 | ret |= p[offset + 3]; | |
189 | } else { | |
190 | ret = p[offset]; | |
191 | ret |= p[offset + 1] << 8; | |
192 | ret |= p[offset + 2] << 16; | |
193 | ret |= p[offset + 3] << 24; | |
194 | } | |
29133e9a FB |
195 | break; |
196 | } | |
c1474acd | 197 | trace_pflash_data_read(offset, width << 1, ret); |
29133e9a FB |
198 | break; |
199 | case 0x90: | |
200 | /* flash ID read */ | |
201 | switch (boff) { | |
202 | case 0x00: | |
203 | case 0x01: | |
368a354f | 204 | ret = boff & 0x01 ? pfl->ident1 : pfl->ident0; |
29133e9a FB |
205 | break; |
206 | case 0x02: | |
207 | ret = 0x00; /* Pretend all sectors are unprotected */ | |
208 | break; | |
209 | case 0x0E: | |
210 | case 0x0F: | |
368a354f PC |
211 | ret = boff & 0x01 ? pfl->ident3 : pfl->ident2; |
212 | if (ret == (uint8_t)-1) { | |
29133e9a | 213 | goto flash_read; |
368a354f | 214 | } |
29133e9a FB |
215 | break; |
216 | default: | |
217 | goto flash_read; | |
218 | } | |
6536987f | 219 | DPRINTF("%s: ID " TARGET_FMT_plx " %" PRIx32 "\n", __func__, boff, ret); |
29133e9a FB |
220 | break; |
221 | case 0xA0: | |
222 | case 0x10: | |
223 | case 0x30: | |
224 | /* Status register read */ | |
225 | ret = pfl->status; | |
6536987f | 226 | DPRINTF("%s: status %" PRIx32 "\n", __func__, ret); |
29133e9a FB |
227 | /* Toggle bit 6 */ |
228 | pfl->status ^= 0x40; | |
229 | break; | |
230 | case 0x98: | |
231 | /* CFI query mode */ | |
07c13a71 | 232 | if (boff < sizeof(pfl->cfi_table)) { |
29133e9a | 233 | ret = pfl->cfi_table[boff]; |
07c13a71 PMD |
234 | } else { |
235 | ret = 0; | |
236 | } | |
29133e9a FB |
237 | break; |
238 | } | |
e8aa2d95 | 239 | trace_pflash_io_read(offset, width, width << 1, ret, pfl->cmd, pfl->wcycle); |
29133e9a FB |
240 | |
241 | return ret; | |
242 | } | |
243 | ||
244 | /* update flash content on disk */ | |
16434065 | 245 | static void pflash_update(PFlashCFI02 *pfl, int offset, |
29133e9a FB |
246 | int size) |
247 | { | |
248 | int offset_end; | |
4be74634 | 249 | if (pfl->blk) { |
29133e9a | 250 | offset_end = offset + size; |
098e732d EB |
251 | /* widen to sector boundaries */ |
252 | offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE); | |
253 | offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE); | |
254 | blk_pwrite(pfl->blk, offset, pfl->storage + offset, | |
255 | offset_end - offset, 0); | |
29133e9a FB |
256 | } |
257 | } | |
258 | ||
16434065 MA |
259 | static void pflash_write(PFlashCFI02 *pfl, hwaddr offset, |
260 | uint32_t value, int width, int be) | |
29133e9a | 261 | { |
a8170e5e | 262 | hwaddr boff; |
29133e9a FB |
263 | uint8_t *p; |
264 | uint8_t cmd; | |
265 | ||
e8aa2d95 | 266 | trace_pflash_io_write(offset, width, width << 1, value, pfl->wcycle); |
95d1f3ed JM |
267 | cmd = value; |
268 | if (pfl->cmd != 0xA0 && cmd == 0xF0) { | |
95d1f3ed JM |
269 | goto reset_flash; |
270 | } | |
4fbd24ba | 271 | offset &= pfl->chip_len - 1; |
3b46e624 | 272 | |
29133e9a FB |
273 | boff = offset & (pfl->sector_len - 1); |
274 | if (pfl->width == 2) | |
275 | boff = boff >> 1; | |
276 | else if (pfl->width == 4) | |
277 | boff = boff >> 2; | |
278 | switch (pfl->wcycle) { | |
279 | case 0: | |
9c9bb6c8 AZ |
280 | /* Set the device in I/O access mode if required */ |
281 | if (pfl->rom_mode) | |
282 | pflash_register_memory(pfl, 0); | |
661bfc80 | 283 | pfl->read_counter = 0; |
29133e9a FB |
284 | /* We're in read mode */ |
285 | check_unlock0: | |
286 | if (boff == 0x55 && cmd == 0x98) { | |
287 | enter_CFI_mode: | |
288 | /* Enter CFI query mode */ | |
289 | pfl->wcycle = 7; | |
290 | pfl->cmd = 0x98; | |
291 | return; | |
292 | } | |
368a354f | 293 | if (boff != pfl->unlock_addr0 || cmd != 0xAA) { |
f8be67ee | 294 | DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n", |
368a354f | 295 | __func__, boff, cmd, pfl->unlock_addr0); |
29133e9a FB |
296 | goto reset_flash; |
297 | } | |
298 | DPRINTF("%s: unlock sequence started\n", __func__); | |
299 | break; | |
300 | case 1: | |
301 | /* We started an unlock sequence */ | |
302 | check_unlock1: | |
368a354f | 303 | if (boff != pfl->unlock_addr1 || cmd != 0x55) { |
f8be67ee | 304 | DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__, |
e96efcfc | 305 | boff, cmd); |
29133e9a FB |
306 | goto reset_flash; |
307 | } | |
308 | DPRINTF("%s: unlock sequence done\n", __func__); | |
309 | break; | |
310 | case 2: | |
311 | /* We finished an unlock sequence */ | |
368a354f | 312 | if (!pfl->bypass && boff != pfl->unlock_addr0) { |
f8be67ee | 313 | DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__, |
e96efcfc | 314 | boff, cmd); |
29133e9a FB |
315 | goto reset_flash; |
316 | } | |
317 | switch (cmd) { | |
318 | case 0x20: | |
319 | pfl->bypass = 1; | |
320 | goto do_bypass; | |
321 | case 0x80: | |
322 | case 0x90: | |
323 | case 0xA0: | |
324 | pfl->cmd = cmd; | |
325 | DPRINTF("%s: starting command %02x\n", __func__, cmd); | |
326 | break; | |
327 | default: | |
328 | DPRINTF("%s: unknown command %02x\n", __func__, cmd); | |
329 | goto reset_flash; | |
330 | } | |
331 | break; | |
332 | case 3: | |
333 | switch (pfl->cmd) { | |
334 | case 0x80: | |
335 | /* We need another unlock sequence */ | |
336 | goto check_unlock0; | |
337 | case 0xA0: | |
c1474acd | 338 | trace_pflash_data_write(offset, width << 1, value, 0); |
29133e9a | 339 | p = pfl->storage; |
de8efe8f JJ |
340 | if (!pfl->ro) { |
341 | switch (width) { | |
342 | case 1: | |
5f9fc5ad | 343 | p[offset] &= value; |
de8efe8f JJ |
344 | pflash_update(pfl, offset, 1); |
345 | break; | |
346 | case 2: | |
347 | if (be) { | |
348 | p[offset] &= value >> 8; | |
349 | p[offset + 1] &= value; | |
350 | } else { | |
351 | p[offset] &= value; | |
352 | p[offset + 1] &= value >> 8; | |
353 | } | |
354 | pflash_update(pfl, offset, 2); | |
355 | break; | |
356 | case 4: | |
357 | if (be) { | |
358 | p[offset] &= value >> 24; | |
359 | p[offset + 1] &= value >> 16; | |
360 | p[offset + 2] &= value >> 8; | |
361 | p[offset + 3] &= value; | |
362 | } else { | |
363 | p[offset] &= value; | |
364 | p[offset + 1] &= value >> 8; | |
365 | p[offset + 2] &= value >> 16; | |
366 | p[offset + 3] &= value >> 24; | |
367 | } | |
368 | pflash_update(pfl, offset, 4); | |
369 | break; | |
5f9fc5ad | 370 | } |
29133e9a FB |
371 | } |
372 | pfl->status = 0x00 | ~(value & 0x80); | |
373 | /* Let's pretend write is immediate */ | |
374 | if (pfl->bypass) | |
375 | goto do_bypass; | |
376 | goto reset_flash; | |
377 | case 0x90: | |
378 | if (pfl->bypass && cmd == 0x00) { | |
379 | /* Unlock bypass reset */ | |
380 | goto reset_flash; | |
381 | } | |
382 | /* We can enter CFI query mode from autoselect mode */ | |
383 | if (boff == 0x55 && cmd == 0x98) | |
384 | goto enter_CFI_mode; | |
385 | /* No break here */ | |
386 | default: | |
387 | DPRINTF("%s: invalid write for command %02x\n", | |
388 | __func__, pfl->cmd); | |
389 | goto reset_flash; | |
390 | } | |
391 | case 4: | |
392 | switch (pfl->cmd) { | |
393 | case 0xA0: | |
a1c7273b | 394 | /* Ignore writes while flash data write is occurring */ |
29133e9a FB |
395 | /* As we suppose write is immediate, this should never happen */ |
396 | return; | |
397 | case 0x80: | |
398 | goto check_unlock1; | |
399 | default: | |
400 | /* Should never happen */ | |
401 | DPRINTF("%s: invalid command state %02x (wc 4)\n", | |
402 | __func__, pfl->cmd); | |
403 | goto reset_flash; | |
404 | } | |
405 | break; | |
406 | case 5: | |
407 | switch (cmd) { | |
408 | case 0x10: | |
368a354f | 409 | if (boff != pfl->unlock_addr0) { |
f8be67ee | 410 | DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n", |
29133e9a FB |
411 | __func__, offset); |
412 | goto reset_flash; | |
413 | } | |
414 | /* Chip erase */ | |
415 | DPRINTF("%s: start chip erase\n", __func__); | |
de8efe8f JJ |
416 | if (!pfl->ro) { |
417 | memset(pfl->storage, 0xFF, pfl->chip_len); | |
418 | pflash_update(pfl, 0, pfl->chip_len); | |
419 | } | |
29133e9a | 420 | pfl->status = 0x00; |
29133e9a | 421 | /* Let's wait 5 seconds before chip erase is done */ |
d80cf1eb | 422 | timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
73bcb24d | 423 | (NANOSECONDS_PER_SECOND * 5)); |
29133e9a FB |
424 | break; |
425 | case 0x30: | |
426 | /* Sector erase */ | |
427 | p = pfl->storage; | |
428 | offset &= ~(pfl->sector_len - 1); | |
f8be67ee | 429 | DPRINTF("%s: start sector erase at " TARGET_FMT_plx "\n", __func__, |
e96efcfc | 430 | offset); |
de8efe8f JJ |
431 | if (!pfl->ro) { |
432 | memset(p + offset, 0xFF, pfl->sector_len); | |
433 | pflash_update(pfl, offset, pfl->sector_len); | |
434 | } | |
29133e9a FB |
435 | pfl->status = 0x00; |
436 | /* Let's wait 1/2 second before sector erase is done */ | |
d80cf1eb | 437 | timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
73bcb24d | 438 | (NANOSECONDS_PER_SECOND / 2)); |
29133e9a FB |
439 | break; |
440 | default: | |
441 | DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd); | |
442 | goto reset_flash; | |
443 | } | |
444 | pfl->cmd = cmd; | |
445 | break; | |
446 | case 6: | |
447 | switch (pfl->cmd) { | |
448 | case 0x10: | |
449 | /* Ignore writes during chip erase */ | |
450 | return; | |
451 | case 0x30: | |
452 | /* Ignore writes during sector erase */ | |
453 | return; | |
454 | default: | |
455 | /* Should never happen */ | |
456 | DPRINTF("%s: invalid command state %02x (wc 6)\n", | |
457 | __func__, pfl->cmd); | |
458 | goto reset_flash; | |
459 | } | |
460 | break; | |
461 | case 7: /* Special value for CFI queries */ | |
462 | DPRINTF("%s: invalid write in CFI query mode\n", __func__); | |
463 | goto reset_flash; | |
464 | default: | |
465 | /* Should never happen */ | |
466 | DPRINTF("%s: invalid write state (wc 7)\n", __func__); | |
467 | goto reset_flash; | |
468 | } | |
469 | pfl->wcycle++; | |
470 | ||
471 | return; | |
472 | ||
473 | /* Reset flash */ | |
474 | reset_flash: | |
13019f1f | 475 | trace_pflash_reset(); |
29133e9a FB |
476 | pfl->bypass = 0; |
477 | pfl->wcycle = 0; | |
478 | pfl->cmd = 0; | |
479 | return; | |
480 | ||
481 | do_bypass: | |
482 | pfl->wcycle = 2; | |
483 | pfl->cmd = 0; | |
29133e9a FB |
484 | } |
485 | ||
a4afb28d | 486 | static uint64_t pflash_be_readfn(void *opaque, hwaddr addr, unsigned size) |
5f9fc5ad | 487 | { |
a4afb28d | 488 | return pflash_read(opaque, addr, size, 1); |
5f9fc5ad BS |
489 | } |
490 | ||
a4afb28d PM |
491 | static void pflash_be_writefn(void *opaque, hwaddr addr, |
492 | uint64_t value, unsigned size) | |
5f9fc5ad | 493 | { |
a4afb28d | 494 | pflash_write(opaque, addr, value, size, 1); |
5f9fc5ad BS |
495 | } |
496 | ||
a4afb28d | 497 | static uint64_t pflash_le_readfn(void *opaque, hwaddr addr, unsigned size) |
5f9fc5ad | 498 | { |
a4afb28d | 499 | return pflash_read(opaque, addr, size, 0); |
29133e9a FB |
500 | } |
501 | ||
a4afb28d PM |
502 | static void pflash_le_writefn(void *opaque, hwaddr addr, |
503 | uint64_t value, unsigned size) | |
5f9fc5ad | 504 | { |
a4afb28d | 505 | pflash_write(opaque, addr, value, size, 0); |
29133e9a FB |
506 | } |
507 | ||
cfe5f011 | 508 | static const MemoryRegionOps pflash_cfi02_ops_be = { |
a4afb28d PM |
509 | .read = pflash_be_readfn, |
510 | .write = pflash_be_writefn, | |
511 | .valid.min_access_size = 1, | |
512 | .valid.max_access_size = 4, | |
cfe5f011 | 513 | .endianness = DEVICE_NATIVE_ENDIAN, |
5f9fc5ad BS |
514 | }; |
515 | ||
cfe5f011 | 516 | static const MemoryRegionOps pflash_cfi02_ops_le = { |
a4afb28d PM |
517 | .read = pflash_le_readfn, |
518 | .write = pflash_le_writefn, | |
519 | .valid.min_access_size = 1, | |
520 | .valid.max_access_size = 4, | |
cfe5f011 | 521 | .endianness = DEVICE_NATIVE_ENDIAN, |
29133e9a FB |
522 | }; |
523 | ||
da3bd642 | 524 | static void pflash_cfi02_realize(DeviceState *dev, Error **errp) |
29133e9a | 525 | { |
e7b62741 | 526 | PFlashCFI02 *pfl = PFLASH_CFI02(dev); |
368a354f | 527 | uint32_t chip_len; |
d0e7605e | 528 | int ret; |
33e0eb52 | 529 | Error *local_err = NULL; |
29133e9a | 530 | |
8929fc3a ZY |
531 | if (pfl->sector_len == 0) { |
532 | error_setg(errp, "attribute \"sector-length\" not specified or zero."); | |
533 | return; | |
534 | } | |
535 | if (pfl->nb_blocs == 0) { | |
536 | error_setg(errp, "attribute \"num-blocks\" not specified or zero."); | |
537 | return; | |
538 | } | |
539 | if (pfl->name == NULL) { | |
540 | error_setg(errp, "attribute \"name\" not specified."); | |
541 | return; | |
542 | } | |
543 | ||
368a354f | 544 | chip_len = pfl->sector_len * pfl->nb_blocs; |
368a354f | 545 | |
bba3ddf7 | 546 | memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl), pfl->be ? |
368a354f | 547 | &pflash_cfi02_ops_be : &pflash_cfi02_ops_le, |
33e0eb52 HT |
548 | pfl, pfl->name, chip_len, &local_err); |
549 | if (local_err) { | |
550 | error_propagate(errp, local_err); | |
551 | return; | |
552 | } | |
553 | ||
cfe5f011 | 554 | pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem); |
4fbd24ba | 555 | pfl->chip_len = chip_len; |
a17c17a2 KW |
556 | |
557 | if (pfl->blk) { | |
558 | uint64_t perm; | |
559 | pfl->ro = blk_is_read_only(pfl->blk); | |
560 | perm = BLK_PERM_CONSISTENT_READ | (pfl->ro ? 0 : BLK_PERM_WRITE); | |
561 | ret = blk_set_perm(pfl->blk, perm, BLK_PERM_ALL, errp); | |
562 | if (ret < 0) { | |
563 | return; | |
564 | } | |
565 | } else { | |
566 | pfl->ro = 0; | |
567 | } | |
568 | ||
4be74634 | 569 | if (pfl->blk) { |
06f15217 MA |
570 | if (!blk_check_size_and_read_all(pfl->blk, pfl->storage, chip_len, |
571 | errp)) { | |
da3bd642 | 572 | vmstate_unregister_ram(&pfl->orig_mem, DEVICE(pfl)); |
da3bd642 | 573 | return; |
d0e7605e | 574 | } |
29133e9a | 575 | } |
de8efe8f | 576 | |
cfe5f011 AK |
577 | pflash_setup_mappings(pfl); |
578 | pfl->rom_mode = 1; | |
da3bd642 | 579 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem); |
de8efe8f | 580 | |
d80cf1eb | 581 | timer_init_ns(&pfl->timer, QEMU_CLOCK_VIRTUAL, pflash_timer, pfl); |
29133e9a FB |
582 | pfl->wcycle = 0; |
583 | pfl->cmd = 0; | |
584 | pfl->status = 0; | |
29133e9a | 585 | /* Hardcoded CFI table (mostly from SG29 Spansion flash) */ |
29133e9a FB |
586 | /* Standard "QRY" string */ |
587 | pfl->cfi_table[0x10] = 'Q'; | |
588 | pfl->cfi_table[0x11] = 'R'; | |
589 | pfl->cfi_table[0x12] = 'Y'; | |
590 | /* Command set (AMD/Fujitsu) */ | |
591 | pfl->cfi_table[0x13] = 0x02; | |
592 | pfl->cfi_table[0x14] = 0x00; | |
78556820 EI |
593 | /* Primary extended table address */ |
594 | pfl->cfi_table[0x15] = 0x31; | |
29133e9a FB |
595 | pfl->cfi_table[0x16] = 0x00; |
596 | /* Alternate command set (none) */ | |
597 | pfl->cfi_table[0x17] = 0x00; | |
598 | pfl->cfi_table[0x18] = 0x00; | |
599 | /* Alternate extended table (none) */ | |
600 | pfl->cfi_table[0x19] = 0x00; | |
601 | pfl->cfi_table[0x1A] = 0x00; | |
602 | /* Vcc min */ | |
603 | pfl->cfi_table[0x1B] = 0x27; | |
604 | /* Vcc max */ | |
605 | pfl->cfi_table[0x1C] = 0x36; | |
606 | /* Vpp min (no Vpp pin) */ | |
607 | pfl->cfi_table[0x1D] = 0x00; | |
608 | /* Vpp max (no Vpp pin) */ | |
609 | pfl->cfi_table[0x1E] = 0x00; | |
610 | /* Reserved */ | |
611 | pfl->cfi_table[0x1F] = 0x07; | |
78556820 EI |
612 | /* Timeout for min size buffer write (NA) */ |
613 | pfl->cfi_table[0x20] = 0x00; | |
29133e9a FB |
614 | /* Typical timeout for block erase (512 ms) */ |
615 | pfl->cfi_table[0x21] = 0x09; | |
616 | /* Typical timeout for full chip erase (4096 ms) */ | |
617 | pfl->cfi_table[0x22] = 0x0C; | |
618 | /* Reserved */ | |
619 | pfl->cfi_table[0x23] = 0x01; | |
78556820 EI |
620 | /* Max timeout for buffer write (NA) */ |
621 | pfl->cfi_table[0x24] = 0x00; | |
29133e9a FB |
622 | /* Max timeout for block erase */ |
623 | pfl->cfi_table[0x25] = 0x0A; | |
624 | /* Max timeout for chip erase */ | |
625 | pfl->cfi_table[0x26] = 0x0D; | |
626 | /* Device size */ | |
78556820 | 627 | pfl->cfi_table[0x27] = ctz32(chip_len); |
29133e9a FB |
628 | /* Flash device interface (8 & 16 bits) */ |
629 | pfl->cfi_table[0x28] = 0x02; | |
630 | pfl->cfi_table[0x29] = 0x00; | |
631 | /* Max number of bytes in multi-bytes write */ | |
95d1f3ed JM |
632 | /* XXX: disable buffered write as it's not supported */ |
633 | // pfl->cfi_table[0x2A] = 0x05; | |
634 | pfl->cfi_table[0x2A] = 0x00; | |
29133e9a FB |
635 | pfl->cfi_table[0x2B] = 0x00; |
636 | /* Number of erase block regions (uniform) */ | |
637 | pfl->cfi_table[0x2C] = 0x01; | |
638 | /* Erase block region 1 */ | |
368a354f PC |
639 | pfl->cfi_table[0x2D] = pfl->nb_blocs - 1; |
640 | pfl->cfi_table[0x2E] = (pfl->nb_blocs - 1) >> 8; | |
641 | pfl->cfi_table[0x2F] = pfl->sector_len >> 8; | |
642 | pfl->cfi_table[0x30] = pfl->sector_len >> 16; | |
29133e9a | 643 | |
78556820 EI |
644 | /* Extended */ |
645 | pfl->cfi_table[0x31] = 'P'; | |
646 | pfl->cfi_table[0x32] = 'R'; | |
647 | pfl->cfi_table[0x33] = 'I'; | |
648 | ||
649 | pfl->cfi_table[0x34] = '1'; | |
650 | pfl->cfi_table[0x35] = '0'; | |
651 | ||
652 | pfl->cfi_table[0x36] = 0x00; | |
653 | pfl->cfi_table[0x37] = 0x00; | |
654 | pfl->cfi_table[0x38] = 0x00; | |
655 | pfl->cfi_table[0x39] = 0x00; | |
656 | ||
657 | pfl->cfi_table[0x3a] = 0x00; | |
658 | ||
659 | pfl->cfi_table[0x3b] = 0x00; | |
660 | pfl->cfi_table[0x3c] = 0x00; | |
368a354f PC |
661 | } |
662 | ||
663 | static Property pflash_cfi02_properties[] = { | |
16434065 MA |
664 | DEFINE_PROP_DRIVE("drive", PFlashCFI02, blk), |
665 | DEFINE_PROP_UINT32("num-blocks", PFlashCFI02, nb_blocs, 0), | |
666 | DEFINE_PROP_UINT32("sector-length", PFlashCFI02, sector_len, 0), | |
667 | DEFINE_PROP_UINT8("width", PFlashCFI02, width, 0), | |
668 | DEFINE_PROP_UINT8("mappings", PFlashCFI02, mappings, 0), | |
669 | DEFINE_PROP_UINT8("big-endian", PFlashCFI02, be, 0), | |
670 | DEFINE_PROP_UINT16("id0", PFlashCFI02, ident0, 0), | |
671 | DEFINE_PROP_UINT16("id1", PFlashCFI02, ident1, 0), | |
672 | DEFINE_PROP_UINT16("id2", PFlashCFI02, ident2, 0), | |
673 | DEFINE_PROP_UINT16("id3", PFlashCFI02, ident3, 0), | |
674 | DEFINE_PROP_UINT16("unlock-addr0", PFlashCFI02, unlock_addr0, 0), | |
675 | DEFINE_PROP_UINT16("unlock-addr1", PFlashCFI02, unlock_addr1, 0), | |
676 | DEFINE_PROP_STRING("name", PFlashCFI02, name), | |
368a354f PC |
677 | DEFINE_PROP_END_OF_LIST(), |
678 | }; | |
679 | ||
d80cf1eb SC |
680 | static void pflash_cfi02_unrealize(DeviceState *dev, Error **errp) |
681 | { | |
e7b62741 | 682 | PFlashCFI02 *pfl = PFLASH_CFI02(dev); |
d80cf1eb SC |
683 | timer_del(&pfl->timer); |
684 | } | |
685 | ||
368a354f PC |
686 | static void pflash_cfi02_class_init(ObjectClass *klass, void *data) |
687 | { | |
688 | DeviceClass *dc = DEVICE_CLASS(klass); | |
368a354f | 689 | |
da3bd642 | 690 | dc->realize = pflash_cfi02_realize; |
d80cf1eb | 691 | dc->unrealize = pflash_cfi02_unrealize; |
368a354f | 692 | dc->props = pflash_cfi02_properties; |
df6f9318 | 693 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
368a354f PC |
694 | } |
695 | ||
696 | static const TypeInfo pflash_cfi02_info = { | |
e7b62741 | 697 | .name = TYPE_PFLASH_CFI02, |
368a354f | 698 | .parent = TYPE_SYS_BUS_DEVICE, |
16434065 | 699 | .instance_size = sizeof(PFlashCFI02), |
368a354f PC |
700 | .class_init = pflash_cfi02_class_init, |
701 | }; | |
702 | ||
703 | static void pflash_cfi02_register_types(void) | |
704 | { | |
705 | type_register_static(&pflash_cfi02_info); | |
706 | } | |
707 | ||
708 | type_init(pflash_cfi02_register_types) | |
709 | ||
16434065 | 710 | PFlashCFI02 *pflash_cfi02_register(hwaddr base, |
940d5b13 | 711 | const char *name, |
16434065 MA |
712 | hwaddr size, |
713 | BlockBackend *blk, | |
ce14710f | 714 | uint32_t sector_len, |
16434065 MA |
715 | int nb_mappings, int width, |
716 | uint16_t id0, uint16_t id1, | |
717 | uint16_t id2, uint16_t id3, | |
718 | uint16_t unlock_addr0, | |
719 | uint16_t unlock_addr1, | |
720 | int be) | |
368a354f | 721 | { |
e7b62741 | 722 | DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI02); |
368a354f | 723 | |
9b3d111a MA |
724 | if (blk) { |
725 | qdev_prop_set_drive(dev, "drive", blk, &error_abort); | |
368a354f | 726 | } |
ce14710f MA |
727 | assert(size % sector_len == 0); |
728 | qdev_prop_set_uint32(dev, "num-blocks", size / sector_len); | |
368a354f PC |
729 | qdev_prop_set_uint32(dev, "sector-length", sector_len); |
730 | qdev_prop_set_uint8(dev, "width", width); | |
731 | qdev_prop_set_uint8(dev, "mappings", nb_mappings); | |
732 | qdev_prop_set_uint8(dev, "big-endian", !!be); | |
733 | qdev_prop_set_uint16(dev, "id0", id0); | |
734 | qdev_prop_set_uint16(dev, "id1", id1); | |
735 | qdev_prop_set_uint16(dev, "id2", id2); | |
736 | qdev_prop_set_uint16(dev, "id3", id3); | |
737 | qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0); | |
738 | qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1); | |
739 | qdev_prop_set_string(dev, "name", name); | |
740 | qdev_init_nofail(dev); | |
741 | ||
3509c396 | 742 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); |
e7b62741 | 743 | return PFLASH_CFI02(dev); |
29133e9a | 744 | } |