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Commit | Line | Data |
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29133e9a FB |
1 | /* |
2 | * CFI parallel flash with AMD command set emulation | |
5fafdf24 | 3 | * |
29133e9a FB |
4 | * Copyright (c) 2005 Jocelyn Mayer |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
29133e9a FB |
18 | */ |
19 | ||
20 | /* | |
21 | * For now, this code can emulate flashes of 1, 2 or 4 bytes width. | |
22 | * Supported commands/modes are: | |
23 | * - flash read | |
24 | * - flash write | |
25 | * - flash ID read | |
26 | * - sector erase | |
27 | * - chip erase | |
28 | * - unlock bypass command | |
29 | * - CFI queries | |
30 | * | |
31 | * It does not support flash interleaving. | |
29133e9a FB |
32 | * It does not implement software data protection as found in many real chips |
33 | * It does not implement erase suspend/resume commands | |
34 | * It does not implement multiple sectors erase | |
35 | */ | |
36 | ||
80c71a24 | 37 | #include "qemu/osdep.h" |
83c9f4ca | 38 | #include "hw/hw.h" |
06f15217 | 39 | #include "hw/block/block.h" |
0d09e41a | 40 | #include "hw/block/flash.h" |
da34e65c | 41 | #include "qapi/error.h" |
1de7afc9 | 42 | #include "qemu/timer.h" |
4be74634 | 43 | #include "sysemu/block-backend.h" |
1de7afc9 | 44 | #include "qemu/host-utils.h" |
0b8fa32f | 45 | #include "qemu/module.h" |
83c9f4ca | 46 | #include "hw/sysbus.h" |
13019f1f | 47 | #include "trace.h" |
29133e9a | 48 | |
6536987f | 49 | #define PFLASH_DEBUG false |
ec9ea489 PC |
50 | #define DPRINTF(fmt, ...) \ |
51 | do { \ | |
6536987f PMD |
52 | if (PFLASH_DEBUG) { \ |
53 | fprintf(stderr, "PFLASH: " fmt, ## __VA_ARGS__); \ | |
54 | } \ | |
29133e9a | 55 | } while (0) |
29133e9a | 56 | |
661bfc80 JK |
57 | #define PFLASH_LAZY_ROMD_THRESHOLD 42 |
58 | ||
64659053 SC |
59 | /* |
60 | * The size of the cfi_table indirectly depends on this and the start of the | |
61 | * PRI table directly depends on it. 4 is the maximum size (and also what | |
62 | * seems common) without changing the PRT table address. | |
63 | */ | |
64 | #define PFLASH_MAX_ERASE_REGIONS 4 | |
65 | ||
aeaf6c20 PMD |
66 | /* Special write cycles for CFI queries. */ |
67 | enum { | |
68 | WCYCLE_CFI = 7, | |
46fb7809 | 69 | WCYCLE_AUTOSELECT_CFI = 8, |
aeaf6c20 PMD |
70 | }; |
71 | ||
16434065 | 72 | struct PFlashCFI02 { |
3509c396 HT |
73 | /*< private >*/ |
74 | SysBusDevice parent_obj; | |
75 | /*< public >*/ | |
76 | ||
4be74634 | 77 | BlockBackend *blk; |
64659053 SC |
78 | uint32_t uniform_nb_blocs; |
79 | uint32_t uniform_sector_len; | |
80 | uint32_t nb_blocs[PFLASH_MAX_ERASE_REGIONS]; | |
81 | uint32_t sector_len[PFLASH_MAX_ERASE_REGIONS]; | |
4fbd24ba | 82 | uint32_t chip_len; |
368a354f PC |
83 | uint8_t mappings; |
84 | uint8_t width; | |
85 | uint8_t be; | |
29133e9a FB |
86 | int wcycle; /* if 0, the flash is read normally */ |
87 | int bypass; | |
88 | int ro; | |
89 | uint8_t cmd; | |
90 | uint8_t status; | |
368a354f PC |
91 | /* FIXME: implement array device properties */ |
92 | uint16_t ident0; | |
93 | uint16_t ident1; | |
94 | uint16_t ident2; | |
95 | uint16_t ident3; | |
96 | uint16_t unlock_addr0; | |
97 | uint16_t unlock_addr1; | |
64659053 | 98 | uint8_t cfi_table[0x4d]; |
d80cf1eb | 99 | QEMUTimer timer; |
cfe5f011 AK |
100 | /* The device replicates the flash memory across its memory space. Emulate |
101 | * that by having a container (.mem) filled with an array of aliases | |
102 | * (.mem_mappings) pointing to the flash memory (.orig_mem). | |
103 | */ | |
104 | MemoryRegion mem; | |
105 | MemoryRegion *mem_mappings; /* array; one per mapping */ | |
106 | MemoryRegion orig_mem; | |
9c9bb6c8 | 107 | int rom_mode; |
661bfc80 | 108 | int read_counter; /* used for lazy switch-back to rom mode */ |
368a354f | 109 | char *name; |
29133e9a FB |
110 | void *storage; |
111 | }; | |
112 | ||
1d311e73 PMD |
113 | /* |
114 | * Toggle status bit DQ7. | |
115 | */ | |
116 | static inline void toggle_dq7(PFlashCFI02 *pfl) | |
117 | { | |
118 | pfl->status ^= 0x80; | |
119 | } | |
120 | ||
121 | /* | |
122 | * Set status bit DQ7 to bit 7 of value. | |
123 | */ | |
124 | static inline void set_dq7(PFlashCFI02 *pfl, uint8_t value) | |
125 | { | |
126 | pfl->status &= 0x7F; | |
127 | pfl->status |= value & 0x80; | |
128 | } | |
129 | ||
130 | /* | |
131 | * Toggle status bit DQ6. | |
132 | */ | |
133 | static inline void toggle_dq6(PFlashCFI02 *pfl) | |
134 | { | |
135 | pfl->status ^= 0x40; | |
136 | } | |
137 | ||
cfe5f011 AK |
138 | /* |
139 | * Set up replicated mappings of the same region. | |
140 | */ | |
16434065 | 141 | static void pflash_setup_mappings(PFlashCFI02 *pfl) |
c8a50e59 | 142 | { |
cfe5f011 | 143 | unsigned i; |
a8170e5e | 144 | hwaddr size = memory_region_size(&pfl->orig_mem); |
cfe5f011 | 145 | |
2d256e6f | 146 | memory_region_init(&pfl->mem, OBJECT(pfl), "pflash", pfl->mappings * size); |
cfe5f011 AK |
147 | pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings); |
148 | for (i = 0; i < pfl->mappings; ++i) { | |
2d256e6f PB |
149 | memory_region_init_alias(&pfl->mem_mappings[i], OBJECT(pfl), |
150 | "pflash-alias", &pfl->orig_mem, 0, size); | |
cfe5f011 AK |
151 | memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]); |
152 | } | |
153 | } | |
01e0451a | 154 | |
16434065 | 155 | static void pflash_register_memory(PFlashCFI02 *pfl, int rom_mode) |
cfe5f011 | 156 | { |
5f9a5ea1 | 157 | memory_region_rom_device_set_romd(&pfl->orig_mem, rom_mode); |
bda254da | 158 | pfl->rom_mode = rom_mode; |
4fbd24ba AZ |
159 | } |
160 | ||
102f0f79 PMD |
161 | static size_t pflash_regions_count(PFlashCFI02 *pfl) |
162 | { | |
163 | return pfl->cfi_table[0x2c]; | |
164 | } | |
165 | ||
29133e9a FB |
166 | static void pflash_timer (void *opaque) |
167 | { | |
16434065 | 168 | PFlashCFI02 *pfl = opaque; |
29133e9a | 169 | |
13019f1f | 170 | trace_pflash_timer_expired(pfl->cmd); |
29133e9a | 171 | /* Reset flash */ |
1d311e73 | 172 | toggle_dq7(pfl); |
29133e9a FB |
173 | if (pfl->bypass) { |
174 | pfl->wcycle = 2; | |
175 | } else { | |
4fbd24ba | 176 | pflash_register_memory(pfl, 1); |
29133e9a FB |
177 | pfl->wcycle = 0; |
178 | } | |
179 | pfl->cmd = 0; | |
180 | } | |
181 | ||
06e8b8e3 PMD |
182 | /* |
183 | * Read data from flash. | |
184 | */ | |
185 | static uint64_t pflash_data_read(PFlashCFI02 *pfl, hwaddr offset, | |
186 | unsigned int width) | |
187 | { | |
188 | uint8_t *p = (uint8_t *)pfl->storage + offset; | |
189 | uint64_t ret = pfl->be ? ldn_be_p(p, width) : ldn_le_p(p, width); | |
190 | trace_pflash_data_read(offset, width << 1, ret); | |
191 | return ret; | |
192 | } | |
193 | ||
64659053 SC |
194 | /* |
195 | * offset should be a byte offset of the QEMU device and _not_ a device | |
196 | * offset. | |
197 | */ | |
198 | static uint32_t pflash_sector_len(PFlashCFI02 *pfl, hwaddr offset) | |
199 | { | |
200 | assert(offset < pfl->chip_len); | |
64659053 | 201 | hwaddr addr = 0; |
102f0f79 | 202 | for (int i = 0; i < pflash_regions_count(pfl); ++i) { |
64659053 SC |
203 | uint64_t region_size = (uint64_t)pfl->nb_blocs[i] * pfl->sector_len[i]; |
204 | if (addr <= offset && offset < addr + region_size) { | |
205 | return pfl->sector_len[i]; | |
206 | } | |
207 | addr += region_size; | |
208 | } | |
209 | abort(); | |
210 | } | |
211 | ||
aff498cf | 212 | static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int width) |
29133e9a | 213 | { |
aff498cf | 214 | PFlashCFI02 *pfl = opaque; |
a8170e5e | 215 | hwaddr boff; |
aff498cf | 216 | uint64_t ret; |
29133e9a | 217 | |
29133e9a | 218 | ret = -1; |
661bfc80 JK |
219 | /* Lazy reset to ROMD mode after a certain amount of read accesses */ |
220 | if (!pfl->rom_mode && pfl->wcycle == 0 && | |
221 | ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) { | |
222 | pflash_register_memory(pfl, 1); | |
0f459d16 | 223 | } |
4fbd24ba | 224 | offset &= pfl->chip_len - 1; |
29133e9a | 225 | boff = offset & 0xFF; |
64659053 | 226 | if (pfl->width == 2) { |
29133e9a | 227 | boff = boff >> 1; |
64659053 | 228 | } else if (pfl->width == 4) { |
29133e9a | 229 | boff = boff >> 2; |
64659053 | 230 | } |
29133e9a FB |
231 | switch (pfl->cmd) { |
232 | default: | |
233 | /* This should never happen : reset state & treat it as a read*/ | |
234 | DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd); | |
235 | pfl->wcycle = 0; | |
236 | pfl->cmd = 0; | |
30954850 | 237 | /* fall through to the read code */ |
29133e9a FB |
238 | case 0x80: |
239 | /* We accept reads during second unlock sequence... */ | |
240 | case 0x00: | |
29133e9a | 241 | /* Flash area read */ |
06e8b8e3 | 242 | ret = pflash_data_read(pfl, offset, width); |
29133e9a FB |
243 | break; |
244 | case 0x90: | |
245 | /* flash ID read */ | |
246 | switch (boff) { | |
247 | case 0x00: | |
248 | case 0x01: | |
368a354f | 249 | ret = boff & 0x01 ? pfl->ident1 : pfl->ident0; |
29133e9a FB |
250 | break; |
251 | case 0x02: | |
252 | ret = 0x00; /* Pretend all sectors are unprotected */ | |
253 | break; | |
254 | case 0x0E: | |
255 | case 0x0F: | |
368a354f | 256 | ret = boff & 0x01 ? pfl->ident3 : pfl->ident2; |
7f7bdcaf PMD |
257 | if (ret != (uint8_t)-1) { |
258 | break; | |
368a354f | 259 | } |
7f7bdcaf | 260 | /* Fall through to data read. */ |
29133e9a | 261 | default: |
06e8b8e3 | 262 | ret = pflash_data_read(pfl, offset, width); |
29133e9a | 263 | } |
aff498cf | 264 | DPRINTF("%s: ID " TARGET_FMT_plx " %" PRIx64 "\n", __func__, boff, ret); |
29133e9a FB |
265 | break; |
266 | case 0xA0: | |
267 | case 0x10: | |
268 | case 0x30: | |
269 | /* Status register read */ | |
270 | ret = pfl->status; | |
aff498cf | 271 | DPRINTF("%s: status %" PRIx64 "\n", __func__, ret); |
1d311e73 | 272 | toggle_dq6(pfl); |
29133e9a FB |
273 | break; |
274 | case 0x98: | |
275 | /* CFI query mode */ | |
07c13a71 | 276 | if (boff < sizeof(pfl->cfi_table)) { |
29133e9a | 277 | ret = pfl->cfi_table[boff]; |
07c13a71 PMD |
278 | } else { |
279 | ret = 0; | |
280 | } | |
29133e9a FB |
281 | break; |
282 | } | |
e8aa2d95 | 283 | trace_pflash_io_read(offset, width, width << 1, ret, pfl->cmd, pfl->wcycle); |
29133e9a FB |
284 | |
285 | return ret; | |
286 | } | |
287 | ||
288 | /* update flash content on disk */ | |
aff498cf | 289 | static void pflash_update(PFlashCFI02 *pfl, int offset, int size) |
29133e9a FB |
290 | { |
291 | int offset_end; | |
4be74634 | 292 | if (pfl->blk) { |
29133e9a | 293 | offset_end = offset + size; |
098e732d EB |
294 | /* widen to sector boundaries */ |
295 | offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE); | |
296 | offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE); | |
297 | blk_pwrite(pfl->blk, offset, pfl->storage + offset, | |
298 | offset_end - offset, 0); | |
29133e9a FB |
299 | } |
300 | } | |
301 | ||
aff498cf PMD |
302 | static void pflash_write(void *opaque, hwaddr offset, uint64_t value, |
303 | unsigned int width) | |
29133e9a | 304 | { |
aff498cf | 305 | PFlashCFI02 *pfl = opaque; |
a8170e5e | 306 | hwaddr boff; |
29133e9a FB |
307 | uint8_t *p; |
308 | uint8_t cmd; | |
64659053 | 309 | uint32_t sector_len; |
29133e9a | 310 | |
e8aa2d95 | 311 | trace_pflash_io_write(offset, width, width << 1, value, pfl->wcycle); |
95d1f3ed | 312 | cmd = value; |
8a508e70 | 313 | if (pfl->cmd != 0xA0) { |
a9791042 SC |
314 | /* Reset does nothing during chip erase and sector erase. */ |
315 | if (cmd == 0xF0 && pfl->cmd != 0x10 && pfl->cmd != 0x30) { | |
46fb7809 SC |
316 | if (pfl->wcycle == WCYCLE_AUTOSELECT_CFI) { |
317 | /* Return to autoselect mode. */ | |
318 | pfl->wcycle = 3; | |
319 | pfl->cmd = 0x90; | |
320 | return; | |
321 | } | |
8a508e70 PMD |
322 | goto reset_flash; |
323 | } | |
95d1f3ed | 324 | } |
4fbd24ba | 325 | offset &= pfl->chip_len - 1; |
3b46e624 | 326 | |
6682bc1e | 327 | boff = offset; |
64659053 | 328 | if (pfl->width == 2) { |
29133e9a | 329 | boff = boff >> 1; |
64659053 | 330 | } else if (pfl->width == 4) { |
29133e9a | 331 | boff = boff >> 2; |
64659053 | 332 | } |
6682bc1e SC |
333 | /* Only the least-significant 11 bits are used in most cases. */ |
334 | boff &= 0x7FF; | |
29133e9a FB |
335 | switch (pfl->wcycle) { |
336 | case 0: | |
9c9bb6c8 AZ |
337 | /* Set the device in I/O access mode if required */ |
338 | if (pfl->rom_mode) | |
339 | pflash_register_memory(pfl, 0); | |
661bfc80 | 340 | pfl->read_counter = 0; |
29133e9a FB |
341 | /* We're in read mode */ |
342 | check_unlock0: | |
343 | if (boff == 0x55 && cmd == 0x98) { | |
29133e9a | 344 | /* Enter CFI query mode */ |
aeaf6c20 | 345 | pfl->wcycle = WCYCLE_CFI; |
29133e9a FB |
346 | pfl->cmd = 0x98; |
347 | return; | |
348 | } | |
368a354f | 349 | if (boff != pfl->unlock_addr0 || cmd != 0xAA) { |
f8be67ee | 350 | DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n", |
368a354f | 351 | __func__, boff, cmd, pfl->unlock_addr0); |
29133e9a FB |
352 | goto reset_flash; |
353 | } | |
354 | DPRINTF("%s: unlock sequence started\n", __func__); | |
355 | break; | |
356 | case 1: | |
357 | /* We started an unlock sequence */ | |
358 | check_unlock1: | |
368a354f | 359 | if (boff != pfl->unlock_addr1 || cmd != 0x55) { |
f8be67ee | 360 | DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__, |
e96efcfc | 361 | boff, cmd); |
29133e9a FB |
362 | goto reset_flash; |
363 | } | |
364 | DPRINTF("%s: unlock sequence done\n", __func__); | |
365 | break; | |
366 | case 2: | |
367 | /* We finished an unlock sequence */ | |
368a354f | 368 | if (!pfl->bypass && boff != pfl->unlock_addr0) { |
f8be67ee | 369 | DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__, |
e96efcfc | 370 | boff, cmd); |
29133e9a FB |
371 | goto reset_flash; |
372 | } | |
373 | switch (cmd) { | |
374 | case 0x20: | |
375 | pfl->bypass = 1; | |
376 | goto do_bypass; | |
377 | case 0x80: | |
378 | case 0x90: | |
379 | case 0xA0: | |
380 | pfl->cmd = cmd; | |
381 | DPRINTF("%s: starting command %02x\n", __func__, cmd); | |
382 | break; | |
383 | default: | |
384 | DPRINTF("%s: unknown command %02x\n", __func__, cmd); | |
385 | goto reset_flash; | |
386 | } | |
387 | break; | |
388 | case 3: | |
389 | switch (pfl->cmd) { | |
390 | case 0x80: | |
391 | /* We need another unlock sequence */ | |
392 | goto check_unlock0; | |
393 | case 0xA0: | |
c1474acd | 394 | trace_pflash_data_write(offset, width << 1, value, 0); |
de8efe8f | 395 | if (!pfl->ro) { |
c3d25271 PMD |
396 | p = (uint8_t *)pfl->storage + offset; |
397 | if (pfl->be) { | |
398 | uint64_t current = ldn_be_p(p, width); | |
399 | stn_be_p(p, width, current & value); | |
400 | } else { | |
401 | uint64_t current = ldn_le_p(p, width); | |
402 | stn_le_p(p, width, current & value); | |
5f9fc5ad | 403 | } |
c3d25271 | 404 | pflash_update(pfl, offset, width); |
29133e9a | 405 | } |
1d311e73 PMD |
406 | /* |
407 | * While programming, status bit DQ7 should hold the opposite | |
408 | * value from how it was programmed. | |
409 | */ | |
410 | set_dq7(pfl, ~value); | |
29133e9a FB |
411 | /* Let's pretend write is immediate */ |
412 | if (pfl->bypass) | |
413 | goto do_bypass; | |
414 | goto reset_flash; | |
415 | case 0x90: | |
416 | if (pfl->bypass && cmd == 0x00) { | |
417 | /* Unlock bypass reset */ | |
418 | goto reset_flash; | |
419 | } | |
46fb7809 SC |
420 | /* |
421 | * We can enter CFI query mode from autoselect mode, but we must | |
422 | * return to autoselect mode after a reset. | |
423 | */ | |
424 | if (boff == 0x55 && cmd == 0x98) { | |
425 | /* Enter autoselect CFI query mode */ | |
426 | pfl->wcycle = WCYCLE_AUTOSELECT_CFI; | |
427 | pfl->cmd = 0x98; | |
428 | return; | |
429 | } | |
29133e9a FB |
430 | /* No break here */ |
431 | default: | |
432 | DPRINTF("%s: invalid write for command %02x\n", | |
433 | __func__, pfl->cmd); | |
434 | goto reset_flash; | |
435 | } | |
436 | case 4: | |
437 | switch (pfl->cmd) { | |
438 | case 0xA0: | |
a1c7273b | 439 | /* Ignore writes while flash data write is occurring */ |
29133e9a FB |
440 | /* As we suppose write is immediate, this should never happen */ |
441 | return; | |
442 | case 0x80: | |
443 | goto check_unlock1; | |
444 | default: | |
445 | /* Should never happen */ | |
446 | DPRINTF("%s: invalid command state %02x (wc 4)\n", | |
447 | __func__, pfl->cmd); | |
448 | goto reset_flash; | |
449 | } | |
450 | break; | |
451 | case 5: | |
452 | switch (cmd) { | |
453 | case 0x10: | |
368a354f | 454 | if (boff != pfl->unlock_addr0) { |
f8be67ee | 455 | DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n", |
29133e9a FB |
456 | __func__, offset); |
457 | goto reset_flash; | |
458 | } | |
459 | /* Chip erase */ | |
460 | DPRINTF("%s: start chip erase\n", __func__); | |
de8efe8f | 461 | if (!pfl->ro) { |
1eb27d69 | 462 | memset(pfl->storage, 0xff, pfl->chip_len); |
de8efe8f JJ |
463 | pflash_update(pfl, 0, pfl->chip_len); |
464 | } | |
1d311e73 | 465 | set_dq7(pfl, 0x00); |
29133e9a | 466 | /* Let's wait 5 seconds before chip erase is done */ |
d80cf1eb | 467 | timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
73bcb24d | 468 | (NANOSECONDS_PER_SECOND * 5)); |
29133e9a FB |
469 | break; |
470 | case 0x30: | |
471 | /* Sector erase */ | |
472 | p = pfl->storage; | |
64659053 SC |
473 | sector_len = pflash_sector_len(pfl, offset); |
474 | offset &= ~(sector_len - 1); | |
475 | DPRINTF("%s: start sector erase at %0*" PRIx64 "-%0*" PRIx64 "\n", | |
476 | __func__, pfl->width * 2, offset, | |
477 | pfl->width * 2, offset + sector_len - 1); | |
de8efe8f | 478 | if (!pfl->ro) { |
64659053 SC |
479 | memset(p + offset, 0xff, sector_len); |
480 | pflash_update(pfl, offset, sector_len); | |
de8efe8f | 481 | } |
1d311e73 | 482 | set_dq7(pfl, 0x00); |
29133e9a | 483 | /* Let's wait 1/2 second before sector erase is done */ |
d80cf1eb | 484 | timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
73bcb24d | 485 | (NANOSECONDS_PER_SECOND / 2)); |
29133e9a FB |
486 | break; |
487 | default: | |
488 | DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd); | |
489 | goto reset_flash; | |
490 | } | |
491 | pfl->cmd = cmd; | |
492 | break; | |
493 | case 6: | |
494 | switch (pfl->cmd) { | |
495 | case 0x10: | |
496 | /* Ignore writes during chip erase */ | |
497 | return; | |
498 | case 0x30: | |
499 | /* Ignore writes during sector erase */ | |
500 | return; | |
501 | default: | |
502 | /* Should never happen */ | |
503 | DPRINTF("%s: invalid command state %02x (wc 6)\n", | |
504 | __func__, pfl->cmd); | |
505 | goto reset_flash; | |
506 | } | |
507 | break; | |
aeaf6c20 PMD |
508 | /* Special values for CFI queries */ |
509 | case WCYCLE_CFI: | |
46fb7809 | 510 | case WCYCLE_AUTOSELECT_CFI: |
29133e9a FB |
511 | DPRINTF("%s: invalid write in CFI query mode\n", __func__); |
512 | goto reset_flash; | |
513 | default: | |
514 | /* Should never happen */ | |
515 | DPRINTF("%s: invalid write state (wc 7)\n", __func__); | |
516 | goto reset_flash; | |
517 | } | |
518 | pfl->wcycle++; | |
519 | ||
520 | return; | |
521 | ||
522 | /* Reset flash */ | |
523 | reset_flash: | |
13019f1f | 524 | trace_pflash_reset(); |
29133e9a FB |
525 | pfl->bypass = 0; |
526 | pfl->wcycle = 0; | |
527 | pfl->cmd = 0; | |
528 | return; | |
529 | ||
530 | do_bypass: | |
531 | pfl->wcycle = 2; | |
532 | pfl->cmd = 0; | |
29133e9a FB |
533 | } |
534 | ||
aff498cf PMD |
535 | static const MemoryRegionOps pflash_cfi02_ops = { |
536 | .read = pflash_read, | |
537 | .write = pflash_write, | |
a4afb28d PM |
538 | .valid.min_access_size = 1, |
539 | .valid.max_access_size = 4, | |
cfe5f011 | 540 | .endianness = DEVICE_NATIVE_ENDIAN, |
29133e9a FB |
541 | }; |
542 | ||
da3bd642 | 543 | static void pflash_cfi02_realize(DeviceState *dev, Error **errp) |
29133e9a | 544 | { |
e7b62741 | 545 | PFlashCFI02 *pfl = PFLASH_CFI02(dev); |
d0e7605e | 546 | int ret; |
33e0eb52 | 547 | Error *local_err = NULL; |
29133e9a | 548 | |
64659053 | 549 | if (pfl->uniform_sector_len == 0 && pfl->sector_len[0] == 0) { |
8929fc3a ZY |
550 | error_setg(errp, "attribute \"sector-length\" not specified or zero."); |
551 | return; | |
552 | } | |
64659053 | 553 | if (pfl->uniform_nb_blocs == 0 && pfl->nb_blocs[0] == 0) { |
8929fc3a ZY |
554 | error_setg(errp, "attribute \"num-blocks\" not specified or zero."); |
555 | return; | |
556 | } | |
557 | if (pfl->name == NULL) { | |
558 | error_setg(errp, "attribute \"name\" not specified."); | |
559 | return; | |
560 | } | |
561 | ||
64659053 SC |
562 | int nb_regions; |
563 | pfl->chip_len = 0; | |
564 | for (nb_regions = 0; nb_regions < PFLASH_MAX_ERASE_REGIONS; ++nb_regions) { | |
565 | if (pfl->nb_blocs[nb_regions] == 0) { | |
566 | break; | |
567 | } | |
568 | uint64_t sector_len_per_device = pfl->sector_len[nb_regions]; | |
569 | ||
570 | /* | |
571 | * The size of each flash sector must be a power of 2 and it must be | |
572 | * aligned at the same power of 2. | |
573 | */ | |
574 | if (sector_len_per_device & 0xff || | |
575 | sector_len_per_device >= (1 << 24) || | |
576 | !is_power_of_2(sector_len_per_device)) | |
577 | { | |
578 | error_setg(errp, "unsupported configuration: " | |
579 | "sector length[%d] per device = %" PRIx64 ".", | |
580 | nb_regions, sector_len_per_device); | |
581 | return; | |
582 | } | |
583 | if (pfl->chip_len & (sector_len_per_device - 1)) { | |
584 | error_setg(errp, "unsupported configuration: " | |
585 | "flash region %d not correctly aligned.", | |
586 | nb_regions); | |
587 | return; | |
588 | } | |
589 | ||
590 | pfl->chip_len += (uint64_t)pfl->sector_len[nb_regions] * | |
591 | pfl->nb_blocs[nb_regions]; | |
592 | } | |
593 | ||
594 | uint64_t uniform_len = (uint64_t)pfl->uniform_nb_blocs * | |
595 | pfl->uniform_sector_len; | |
596 | if (nb_regions == 0) { | |
597 | nb_regions = 1; | |
598 | pfl->nb_blocs[0] = pfl->uniform_nb_blocs; | |
599 | pfl->sector_len[0] = pfl->uniform_sector_len; | |
600 | pfl->chip_len = uniform_len; | |
601 | } else if (uniform_len != 0 && uniform_len != pfl->chip_len) { | |
602 | error_setg(errp, "\"num-blocks\"*\"sector-length\" " | |
603 | "different from \"num-blocks0\"*\'sector-length0\" + ... + " | |
604 | "\"num-blocks3\"*\"sector-length3\""); | |
605 | return; | |
606 | } | |
368a354f | 607 | |
aff498cf PMD |
608 | memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl), |
609 | &pflash_cfi02_ops, pfl, pfl->name, | |
1eb27d69 | 610 | pfl->chip_len, &local_err); |
33e0eb52 HT |
611 | if (local_err) { |
612 | error_propagate(errp, local_err); | |
613 | return; | |
614 | } | |
615 | ||
cfe5f011 | 616 | pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem); |
a17c17a2 KW |
617 | |
618 | if (pfl->blk) { | |
619 | uint64_t perm; | |
620 | pfl->ro = blk_is_read_only(pfl->blk); | |
621 | perm = BLK_PERM_CONSISTENT_READ | (pfl->ro ? 0 : BLK_PERM_WRITE); | |
622 | ret = blk_set_perm(pfl->blk, perm, BLK_PERM_ALL, errp); | |
623 | if (ret < 0) { | |
624 | return; | |
625 | } | |
626 | } else { | |
627 | pfl->ro = 0; | |
628 | } | |
629 | ||
4be74634 | 630 | if (pfl->blk) { |
1eb27d69 PMD |
631 | if (!blk_check_size_and_read_all(pfl->blk, pfl->storage, |
632 | pfl->chip_len, errp)) { | |
da3bd642 | 633 | vmstate_unregister_ram(&pfl->orig_mem, DEVICE(pfl)); |
da3bd642 | 634 | return; |
d0e7605e | 635 | } |
29133e9a | 636 | } |
de8efe8f | 637 | |
6682bc1e SC |
638 | /* Only 11 bits are used in the comparison. */ |
639 | pfl->unlock_addr0 &= 0x7FF; | |
640 | pfl->unlock_addr1 &= 0x7FF; | |
641 | ||
cfe5f011 AK |
642 | pflash_setup_mappings(pfl); |
643 | pfl->rom_mode = 1; | |
da3bd642 | 644 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem); |
de8efe8f | 645 | |
d80cf1eb | 646 | timer_init_ns(&pfl->timer, QEMU_CLOCK_VIRTUAL, pflash_timer, pfl); |
29133e9a FB |
647 | pfl->wcycle = 0; |
648 | pfl->cmd = 0; | |
649 | pfl->status = 0; | |
9ac45b88 | 650 | |
29133e9a | 651 | /* Hardcoded CFI table (mostly from SG29 Spansion flash) */ |
64659053 | 652 | const uint16_t pri_ofs = 0x40; |
29133e9a FB |
653 | /* Standard "QRY" string */ |
654 | pfl->cfi_table[0x10] = 'Q'; | |
655 | pfl->cfi_table[0x11] = 'R'; | |
656 | pfl->cfi_table[0x12] = 'Y'; | |
657 | /* Command set (AMD/Fujitsu) */ | |
658 | pfl->cfi_table[0x13] = 0x02; | |
659 | pfl->cfi_table[0x14] = 0x00; | |
78556820 | 660 | /* Primary extended table address */ |
d6874c83 PMD |
661 | pfl->cfi_table[0x15] = pri_ofs; |
662 | pfl->cfi_table[0x16] = pri_ofs >> 8; | |
29133e9a FB |
663 | /* Alternate command set (none) */ |
664 | pfl->cfi_table[0x17] = 0x00; | |
665 | pfl->cfi_table[0x18] = 0x00; | |
666 | /* Alternate extended table (none) */ | |
667 | pfl->cfi_table[0x19] = 0x00; | |
668 | pfl->cfi_table[0x1A] = 0x00; | |
669 | /* Vcc min */ | |
670 | pfl->cfi_table[0x1B] = 0x27; | |
671 | /* Vcc max */ | |
672 | pfl->cfi_table[0x1C] = 0x36; | |
673 | /* Vpp min (no Vpp pin) */ | |
674 | pfl->cfi_table[0x1D] = 0x00; | |
675 | /* Vpp max (no Vpp pin) */ | |
676 | pfl->cfi_table[0x1E] = 0x00; | |
9ac45b88 | 677 | /* Timeout per single byte/word write (128 ms) */ |
29133e9a | 678 | pfl->cfi_table[0x1F] = 0x07; |
78556820 EI |
679 | /* Timeout for min size buffer write (NA) */ |
680 | pfl->cfi_table[0x20] = 0x00; | |
29133e9a FB |
681 | /* Typical timeout for block erase (512 ms) */ |
682 | pfl->cfi_table[0x21] = 0x09; | |
683 | /* Typical timeout for full chip erase (4096 ms) */ | |
684 | pfl->cfi_table[0x22] = 0x0C; | |
685 | /* Reserved */ | |
686 | pfl->cfi_table[0x23] = 0x01; | |
78556820 EI |
687 | /* Max timeout for buffer write (NA) */ |
688 | pfl->cfi_table[0x24] = 0x00; | |
29133e9a FB |
689 | /* Max timeout for block erase */ |
690 | pfl->cfi_table[0x25] = 0x0A; | |
691 | /* Max timeout for chip erase */ | |
692 | pfl->cfi_table[0x26] = 0x0D; | |
693 | /* Device size */ | |
1eb27d69 | 694 | pfl->cfi_table[0x27] = ctz32(pfl->chip_len); |
29133e9a FB |
695 | /* Flash device interface (8 & 16 bits) */ |
696 | pfl->cfi_table[0x28] = 0x02; | |
697 | pfl->cfi_table[0x29] = 0x00; | |
698 | /* Max number of bytes in multi-bytes write */ | |
95d1f3ed JM |
699 | /* XXX: disable buffered write as it's not supported */ |
700 | // pfl->cfi_table[0x2A] = 0x05; | |
701 | pfl->cfi_table[0x2A] = 0x00; | |
29133e9a | 702 | pfl->cfi_table[0x2B] = 0x00; |
64659053 SC |
703 | /* Number of erase block regions */ |
704 | pfl->cfi_table[0x2c] = nb_regions; | |
705 | /* Erase block regions */ | |
706 | for (int i = 0; i < nb_regions; ++i) { | |
707 | uint32_t sector_len_per_device = pfl->sector_len[i]; | |
708 | pfl->cfi_table[0x2d + 4 * i] = pfl->nb_blocs[i] - 1; | |
709 | pfl->cfi_table[0x2e + 4 * i] = (pfl->nb_blocs[i] - 1) >> 8; | |
710 | pfl->cfi_table[0x2f + 4 * i] = sector_len_per_device >> 8; | |
711 | pfl->cfi_table[0x30 + 4 * i] = sector_len_per_device >> 16; | |
712 | } | |
713 | assert(0x2c + 4 * nb_regions < pri_ofs); | |
29133e9a | 714 | |
78556820 | 715 | /* Extended */ |
d6874c83 PMD |
716 | pfl->cfi_table[0x00 + pri_ofs] = 'P'; |
717 | pfl->cfi_table[0x01 + pri_ofs] = 'R'; | |
718 | pfl->cfi_table[0x02 + pri_ofs] = 'I'; | |
78556820 | 719 | |
9ac45b88 | 720 | /* Extended version 1.0 */ |
d6874c83 PMD |
721 | pfl->cfi_table[0x03 + pri_ofs] = '1'; |
722 | pfl->cfi_table[0x04 + pri_ofs] = '0'; | |
78556820 | 723 | |
9ac45b88 | 724 | /* Address sensitive unlock required. */ |
d6874c83 | 725 | pfl->cfi_table[0x05 + pri_ofs] = 0x00; |
9ac45b88 | 726 | /* Erase suspend not supported. */ |
d6874c83 | 727 | pfl->cfi_table[0x06 + pri_ofs] = 0x00; |
9ac45b88 | 728 | /* Sector protect not supported. */ |
d6874c83 | 729 | pfl->cfi_table[0x07 + pri_ofs] = 0x00; |
9ac45b88 | 730 | /* Temporary sector unprotect not supported. */ |
d6874c83 | 731 | pfl->cfi_table[0x08 + pri_ofs] = 0x00; |
78556820 | 732 | |
9ac45b88 | 733 | /* Sector protect/unprotect scheme. */ |
d6874c83 | 734 | pfl->cfi_table[0x09 + pri_ofs] = 0x00; |
78556820 | 735 | |
9ac45b88 | 736 | /* Simultaneous operation not supported. */ |
d6874c83 | 737 | pfl->cfi_table[0x0a + pri_ofs] = 0x00; |
9ac45b88 | 738 | /* Burst mode not supported. */ |
d6874c83 | 739 | pfl->cfi_table[0x0b + pri_ofs] = 0x00; |
c2c1bf44 PMD |
740 | /* Page mode not supported. */ |
741 | pfl->cfi_table[0x0c + pri_ofs] = 0x00; | |
742 | assert(0x0c + pri_ofs < ARRAY_SIZE(pfl->cfi_table)); | |
368a354f PC |
743 | } |
744 | ||
745 | static Property pflash_cfi02_properties[] = { | |
16434065 | 746 | DEFINE_PROP_DRIVE("drive", PFlashCFI02, blk), |
64659053 SC |
747 | DEFINE_PROP_UINT32("num-blocks", PFlashCFI02, uniform_nb_blocs, 0), |
748 | DEFINE_PROP_UINT32("sector-length", PFlashCFI02, uniform_sector_len, 0), | |
749 | DEFINE_PROP_UINT32("num-blocks0", PFlashCFI02, nb_blocs[0], 0), | |
750 | DEFINE_PROP_UINT32("sector-length0", PFlashCFI02, sector_len[0], 0), | |
751 | DEFINE_PROP_UINT32("num-blocks1", PFlashCFI02, nb_blocs[1], 0), | |
752 | DEFINE_PROP_UINT32("sector-length1", PFlashCFI02, sector_len[1], 0), | |
753 | DEFINE_PROP_UINT32("num-blocks2", PFlashCFI02, nb_blocs[2], 0), | |
754 | DEFINE_PROP_UINT32("sector-length2", PFlashCFI02, sector_len[2], 0), | |
755 | DEFINE_PROP_UINT32("num-blocks3", PFlashCFI02, nb_blocs[3], 0), | |
756 | DEFINE_PROP_UINT32("sector-length3", PFlashCFI02, sector_len[3], 0), | |
16434065 MA |
757 | DEFINE_PROP_UINT8("width", PFlashCFI02, width, 0), |
758 | DEFINE_PROP_UINT8("mappings", PFlashCFI02, mappings, 0), | |
759 | DEFINE_PROP_UINT8("big-endian", PFlashCFI02, be, 0), | |
760 | DEFINE_PROP_UINT16("id0", PFlashCFI02, ident0, 0), | |
761 | DEFINE_PROP_UINT16("id1", PFlashCFI02, ident1, 0), | |
762 | DEFINE_PROP_UINT16("id2", PFlashCFI02, ident2, 0), | |
763 | DEFINE_PROP_UINT16("id3", PFlashCFI02, ident3, 0), | |
764 | DEFINE_PROP_UINT16("unlock-addr0", PFlashCFI02, unlock_addr0, 0), | |
765 | DEFINE_PROP_UINT16("unlock-addr1", PFlashCFI02, unlock_addr1, 0), | |
766 | DEFINE_PROP_STRING("name", PFlashCFI02, name), | |
368a354f PC |
767 | DEFINE_PROP_END_OF_LIST(), |
768 | }; | |
769 | ||
d80cf1eb SC |
770 | static void pflash_cfi02_unrealize(DeviceState *dev, Error **errp) |
771 | { | |
e7b62741 | 772 | PFlashCFI02 *pfl = PFLASH_CFI02(dev); |
d80cf1eb SC |
773 | timer_del(&pfl->timer); |
774 | } | |
775 | ||
368a354f PC |
776 | static void pflash_cfi02_class_init(ObjectClass *klass, void *data) |
777 | { | |
778 | DeviceClass *dc = DEVICE_CLASS(klass); | |
368a354f | 779 | |
da3bd642 | 780 | dc->realize = pflash_cfi02_realize; |
d80cf1eb | 781 | dc->unrealize = pflash_cfi02_unrealize; |
368a354f | 782 | dc->props = pflash_cfi02_properties; |
df6f9318 | 783 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
368a354f PC |
784 | } |
785 | ||
786 | static const TypeInfo pflash_cfi02_info = { | |
e7b62741 | 787 | .name = TYPE_PFLASH_CFI02, |
368a354f | 788 | .parent = TYPE_SYS_BUS_DEVICE, |
16434065 | 789 | .instance_size = sizeof(PFlashCFI02), |
368a354f PC |
790 | .class_init = pflash_cfi02_class_init, |
791 | }; | |
792 | ||
793 | static void pflash_cfi02_register_types(void) | |
794 | { | |
795 | type_register_static(&pflash_cfi02_info); | |
796 | } | |
797 | ||
798 | type_init(pflash_cfi02_register_types) | |
799 | ||
16434065 | 800 | PFlashCFI02 *pflash_cfi02_register(hwaddr base, |
940d5b13 | 801 | const char *name, |
16434065 MA |
802 | hwaddr size, |
803 | BlockBackend *blk, | |
ce14710f | 804 | uint32_t sector_len, |
16434065 MA |
805 | int nb_mappings, int width, |
806 | uint16_t id0, uint16_t id1, | |
807 | uint16_t id2, uint16_t id3, | |
808 | uint16_t unlock_addr0, | |
809 | uint16_t unlock_addr1, | |
810 | int be) | |
368a354f | 811 | { |
e7b62741 | 812 | DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI02); |
368a354f | 813 | |
9b3d111a MA |
814 | if (blk) { |
815 | qdev_prop_set_drive(dev, "drive", blk, &error_abort); | |
368a354f | 816 | } |
ce14710f MA |
817 | assert(size % sector_len == 0); |
818 | qdev_prop_set_uint32(dev, "num-blocks", size / sector_len); | |
368a354f PC |
819 | qdev_prop_set_uint32(dev, "sector-length", sector_len); |
820 | qdev_prop_set_uint8(dev, "width", width); | |
821 | qdev_prop_set_uint8(dev, "mappings", nb_mappings); | |
822 | qdev_prop_set_uint8(dev, "big-endian", !!be); | |
823 | qdev_prop_set_uint16(dev, "id0", id0); | |
824 | qdev_prop_set_uint16(dev, "id1", id1); | |
825 | qdev_prop_set_uint16(dev, "id2", id2); | |
826 | qdev_prop_set_uint16(dev, "id3", id3); | |
827 | qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0); | |
828 | qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1); | |
829 | qdev_prop_set_string(dev, "name", name); | |
830 | qdev_init_nofail(dev); | |
831 | ||
3509c396 | 832 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); |
e7b62741 | 833 | return PFLASH_CFI02(dev); |
29133e9a | 834 | } |