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Commit | Line | Data |
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87e0331c | 1 | # See docs/devel/tracing.txt for syntax documentation. |
92d32652 DB |
2 | |
3 | # hw/block/virtio-blk.c | |
a576ceac SH |
4 | virtio_blk_req_complete(void *vdev, void *req, int status) "vdev %p req %p status %d" |
5 | virtio_blk_rw_complete(void *vdev, void *req, int ret) "vdev %p req %p ret %d" | |
6 | virtio_blk_handle_write(void *vdev, void *req, uint64_t sector, size_t nsectors) "vdev %p req %p sector %"PRIu64" nsectors %zu" | |
7 | virtio_blk_handle_read(void *vdev, void *req, uint64_t sector, size_t nsectors) "vdev %p req %p sector %"PRIu64" nsectors %zu" | |
8 | virtio_blk_submit_multireq(void *vdev, void *mrb, int start, int num_reqs, uint64_t offset, size_t size, bool is_write) "vdev %p mrb %p start %d num_reqs %d offset %"PRIu64" size %zu is_write %d" | |
92d32652 | 9 | |
92d32652 DB |
10 | # hw/block/hd-geometry.c |
11 | hd_geometry_lchs_guess(void *blk, int cyls, int heads, int secs) "blk %p LCHS %d %d %d" | |
12 | hd_geometry_guess(void *blk, uint32_t cyls, uint32_t heads, uint32_t secs, int trans) "blk %p CHS %u %u %u trans %d" | |
1491ede7 | 13 | |
1ee24514 DG |
14 | # hw/block/nvme.c |
15 | # nvme traces for successful events | |
16 | nvme_irq_msix(uint32_t vector) "raising MSI-X IRQ vector %u" | |
17 | nvme_irq_pin(void) "pulsing IRQ pin" | |
18 | nvme_irq_masked(void) "IRQ is masked" | |
19 | nvme_dma_read(uint64_t prp1, uint64_t prp2) "DMA read, prp1=0x%"PRIx64" prp2=0x%"PRIx64"" | |
7f1d87ab | 20 | nvme_rw(const char *verb, uint32_t blk_count, uint64_t byte_count, uint64_t lba) "%s %"PRIu32" blocks (%"PRIu64" bytes) from LBA %"PRIu64"" |
1ee24514 DG |
21 | nvme_create_sq(uint64_t addr, uint16_t sqid, uint16_t cqid, uint16_t qsize, uint16_t qflags) "create submission queue, addr=0x%"PRIx64", sqid=%"PRIu16", cqid=%"PRIu16", qsize=%"PRIu16", qflags=%"PRIu16"" |
22 | nvme_create_cq(uint64_t addr, uint16_t cqid, uint16_t vector, uint16_t size, uint16_t qflags, int ien) "create completion queue, addr=0x%"PRIx64", cqid=%"PRIu16", vector=%"PRIu16", qsize=%"PRIu16", qflags=%"PRIu16", ien=%d" | |
23 | nvme_del_sq(uint16_t qid) "deleting submission queue sqid=%"PRIu16"" | |
24 | nvme_del_cq(uint16_t cqid) "deleted completion queue, sqid=%"PRIu16"" | |
25 | nvme_identify_ctrl(void) "identify controller" | |
26 | nvme_identify_ns(uint16_t ns) "identify namespace, nsid=%"PRIu16"" | |
27 | nvme_identify_nslist(uint16_t ns) "identify namespace list, nsid=%"PRIu16"" | |
7f1d87ab | 28 | nvme_getfeat_vwcache(const char* result) "get feature volatile write cache, result=%s" |
1ee24514 DG |
29 | nvme_getfeat_numq(int result) "get feature number of queues, result=%d" |
30 | nvme_setfeat_numq(int reqcq, int reqsq, int gotcq, int gotsq) "requested cq_count=%d sq_count=%d, responding with cq_count=%d sq_count=%d" | |
31 | nvme_mmio_intm_set(uint64_t data, uint64_t new_mask) "wrote MMIO, interrupt mask set, data=0x%"PRIx64", new_mask=0x%"PRIx64"" | |
32 | nvme_mmio_intm_clr(uint64_t data, uint64_t new_mask) "wrote MMIO, interrupt mask clr, data=0x%"PRIx64", new_mask=0x%"PRIx64"" | |
33 | nvme_mmio_cfg(uint64_t data) "wrote MMIO, config controller config=0x%"PRIx64"" | |
34 | nvme_mmio_aqattr(uint64_t data) "wrote MMIO, admin queue attributes=0x%"PRIx64"" | |
35 | nvme_mmio_asqaddr(uint64_t data) "wrote MMIO, admin submission queue address=0x%"PRIx64"" | |
36 | nvme_mmio_acqaddr(uint64_t data) "wrote MMIO, admin completion queue address=0x%"PRIx64"" | |
37 | nvme_mmio_asqaddr_hi(uint64_t data, uint64_t new_addr) "wrote MMIO, admin submission queue high half=0x%"PRIx64", new_address=0x%"PRIx64"" | |
38 | nvme_mmio_acqaddr_hi(uint64_t data, uint64_t new_addr) "wrote MMIO, admin completion queue high half=0x%"PRIx64", new_address=0x%"PRIx64"" | |
39 | nvme_mmio_start_success(void) "setting controller enable bit succeeded" | |
40 | nvme_mmio_stopped(void) "cleared controller enable bit" | |
41 | nvme_mmio_shutdown_set(void) "shutdown bit set" | |
42 | nvme_mmio_shutdown_cleared(void) "shutdown bit cleared" | |
43 | ||
44 | # nvme traces for error conditions | |
45 | nvme_err_invalid_dma(void) "PRP/SGL is too small for transfer size" | |
46 | nvme_err_invalid_prplist_ent(uint64_t prplist) "PRP list entry is null or not page aligned: 0x%"PRIx64"" | |
47 | nvme_err_invalid_prp2_align(uint64_t prp2) "PRP2 is not page aligned: 0x%"PRIx64"" | |
48 | nvme_err_invalid_prp2_missing(void) "PRP2 is null and more data to be transferred" | |
49 | nvme_err_invalid_field(void) "invalid field" | |
50 | nvme_err_invalid_prp(void) "invalid PRP" | |
51 | nvme_err_invalid_sgl(void) "invalid SGL" | |
52 | nvme_err_invalid_ns(uint32_t ns, uint32_t limit) "invalid namespace %u not within 1-%u" | |
53 | nvme_err_invalid_opc(uint8_t opc) "invalid opcode 0x%"PRIx8"" | |
54 | nvme_err_invalid_admin_opc(uint8_t opc) "invalid admin opcode 0x%"PRIx8"" | |
55 | nvme_err_invalid_lba_range(uint64_t start, uint64_t len, uint64_t limit) "Invalid LBA start=%"PRIu64" len=%"PRIu64" limit=%"PRIu64"" | |
56 | nvme_err_invalid_del_sq(uint16_t qid) "invalid submission queue deletion, sid=%"PRIu16"" | |
57 | nvme_err_invalid_create_sq_cqid(uint16_t cqid) "failed creating submission queue, invalid cqid=%"PRIu16"" | |
58 | nvme_err_invalid_create_sq_sqid(uint16_t sqid) "failed creating submission queue, invalid sqid=%"PRIu16"" | |
59 | nvme_err_invalid_create_sq_size(uint16_t qsize) "failed creating submission queue, invalid qsize=%"PRIu16"" | |
60 | nvme_err_invalid_create_sq_addr(uint64_t addr) "failed creating submission queue, addr=0x%"PRIx64"" | |
61 | nvme_err_invalid_create_sq_qflags(uint16_t qflags) "failed creating submission queue, qflags=%"PRIu16"" | |
62 | nvme_err_invalid_del_cq_cqid(uint16_t cqid) "failed deleting completion queue, cqid=%"PRIu16"" | |
63 | nvme_err_invalid_del_cq_notempty(uint16_t cqid) "failed deleting completion queue, it is not empty, cqid=%"PRIu16"" | |
64 | nvme_err_invalid_create_cq_cqid(uint16_t cqid) "failed creating completion queue, cqid=%"PRIu16"" | |
65 | nvme_err_invalid_create_cq_size(uint16_t size) "failed creating completion queue, size=%"PRIu16"" | |
66 | nvme_err_invalid_create_cq_addr(uint64_t addr) "failed creating completion queue, addr=0x%"PRIx64"" | |
67 | nvme_err_invalid_create_cq_vector(uint16_t vector) "failed creating completion queue, vector=%"PRIu16"" | |
68 | nvme_err_invalid_create_cq_qflags(uint16_t qflags) "failed creating completion queue, qflags=%"PRIu16"" | |
69 | nvme_err_invalid_identify_cns(uint16_t cns) "identify, invalid cns=0x%"PRIx16"" | |
70 | nvme_err_invalid_getfeat(int dw10) "invalid get features, dw10=0x%"PRIx32"" | |
71 | nvme_err_invalid_setfeat(uint32_t dw10) "invalid set features, dw10=0x%"PRIx32"" | |
72 | nvme_err_startfail_cq(void) "nvme_start_ctrl failed because there are non-admin completion queues" | |
73 | nvme_err_startfail_sq(void) "nvme_start_ctrl failed because there are non-admin submission queues" | |
74 | nvme_err_startfail_nbarasq(void) "nvme_start_ctrl failed because the admin submission queue address is null" | |
75 | nvme_err_startfail_nbaracq(void) "nvme_start_ctrl failed because the admin completion queue address is null" | |
76 | nvme_err_startfail_asq_misaligned(uint64_t addr) "nvme_start_ctrl failed because the admin submission queue address is misaligned: 0x%"PRIx64"" | |
77 | nvme_err_startfail_acq_misaligned(uint64_t addr) "nvme_start_ctrl failed because the admin completion queue address is misaligned: 0x%"PRIx64"" | |
78 | nvme_err_startfail_page_too_small(uint8_t log2ps, uint8_t maxlog2ps) "nvme_start_ctrl failed because the page size is too small: log2size=%u, min=%u" | |
79 | nvme_err_startfail_page_too_large(uint8_t log2ps, uint8_t maxlog2ps) "nvme_start_ctrl failed because the page size is too large: log2size=%u, max=%u" | |
80 | nvme_err_startfail_cqent_too_small(uint8_t log2ps, uint8_t maxlog2ps) "nvme_start_ctrl failed because the completion queue entry size is too small: log2size=%u, min=%u" | |
81 | nvme_err_startfail_cqent_too_large(uint8_t log2ps, uint8_t maxlog2ps) "nvme_start_ctrl failed because the completion queue entry size is too large: log2size=%u, max=%u" | |
82 | nvme_err_startfail_sqent_too_small(uint8_t log2ps, uint8_t maxlog2ps) "nvme_start_ctrl failed because the submission queue entry size is too small: log2size=%u, min=%u" | |
83 | nvme_err_startfail_sqent_too_large(uint8_t log2ps, uint8_t maxlog2ps) "nvme_start_ctrl failed because the submission queue entry size is too large: log2size=%u, max=%u" | |
84 | nvme_err_startfail_asqent_sz_zero(void) "nvme_start_ctrl failed because the admin submission queue size is zero" | |
85 | nvme_err_startfail_acqent_sz_zero(void) "nvme_start_ctrl failed because the admin completion queue size is zero" | |
86 | nvme_err_startfail(void) "setting controller enable bit failed" | |
87 | ||
88 | # Traces for undefined behavior | |
89 | nvme_ub_mmiowr_misaligned32(uint64_t offset) "MMIO write not 32-bit aligned, offset=0x%"PRIx64"" | |
90 | nvme_ub_mmiowr_toosmall(uint64_t offset, unsigned size) "MMIO write smaller than 32 bits, offset=0x%"PRIx64", size=%u" | |
91 | nvme_ub_mmiowr_intmask_with_msix(void) "undefined access to interrupt mask set when MSI-X is enabled" | |
92 | nvme_ub_mmiowr_ro_csts(void) "attempted to set a read only bit of controller status" | |
93 | nvme_ub_mmiowr_ssreset_w1c_unsupported(void) "attempted to W1C CSTS.NSSRO but CAP.NSSRS is zero (not supported)" | |
94 | nvme_ub_mmiowr_ssreset_unsupported(void) "attempted NVM subsystem reset but CAP.NSSRS is zero (not supported)" | |
95 | nvme_ub_mmiowr_cmbloc_reserved(void) "invalid write to reserved CMBLOC when CMBSZ is zero, ignored" | |
96 | nvme_ub_mmiowr_cmbsz_readonly(void) "invalid write to read only CMBSZ, ignored" | |
97 | nvme_ub_mmiowr_invalid(uint64_t offset, uint64_t data) "invalid MMIO write, offset=0x%"PRIx64", data=0x%"PRIx64"" | |
98 | nvme_ub_mmiord_misaligned32(uint64_t offset) "MMIO read not 32-bit aligned, offset=0x%"PRIx64"" | |
99 | nvme_ub_mmiord_toosmall(uint64_t offset) "MMIO read smaller than 32-bits, offset=0x%"PRIx64"" | |
100 | nvme_ub_mmiord_invalid_ofs(uint64_t offset) "MMIO read beyond last register, offset=0x%"PRIx64", returning 0" | |
101 | nvme_ub_db_wr_misaligned(uint64_t offset) "doorbell write not 32-bit aligned, offset=0x%"PRIx64", ignoring" | |
102 | nvme_ub_db_wr_invalid_cq(uint32_t qid) "completion queue doorbell write for nonexistent queue, cqid=%"PRIu32", ignoring" | |
103 | nvme_ub_db_wr_invalid_cqhead(uint32_t qid, uint16_t new_head) "completion queue doorbell write value beyond queue size, cqid=%"PRIu32", new_head=%"PRIu16", ignoring" | |
104 | nvme_ub_db_wr_invalid_sq(uint32_t qid) "submission queue doorbell write for nonexistent queue, sqid=%"PRIu32", ignoring" | |
105 | nvme_ub_db_wr_invalid_sqtail(uint32_t qid, uint16_t new_tail) "submission queue doorbell write value beyond queue size, sqid=%"PRIu32", new_head=%"PRIu16", ignoring" | |
106 | ||
1491ede7 PD |
107 | # hw/block/xen_disk.c |
108 | xen_disk_alloc(char *name) "%s" | |
109 | xen_disk_init(char *name) "%s" | |
110 | xen_disk_connect(char *name) "%s" | |
111 | xen_disk_disconnect(char *name) "%s" | |
112 | xen_disk_free(char *name) "%s" |