[mirror_qemu.git] / hw / char / bcm2835_aux.c

/*
 * BCM2835 (Raspberry Pi / Pi 2) Aux block (mini UART and SPI).
 * Copyright (c) 2015, Microsoft
 * Written by Andrew Baumann
 * Based on pl011.c, copyright terms below:
 *
 * Arm PrimeCell PL011 UART
 *
 * Copyright (c) 2006 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 *
 * At present only the core UART functions (data path for tx/rx) are
 * implemented. The following features/registers are unimplemented:
 *  - Line/modem control
 *  - Scratch register
 *  - Extra control
 *  - Baudrate
 *  - SPI interfaces
 */

#include "qemu/osdep.h"
#include "hw/char/bcm2835_aux.h"
#include "qemu/log.h"
#include "qemu/module.h"

#define AUX_IRQ         0x0
#define AUX_ENABLES     0x4
#define AUX_MU_IO_REG   0x40
#define AUX_MU_IER_REG  0x44
#define AUX_MU_IIR_REG  0x48
#define AUX_MU_LCR_REG  0x4c
#define AUX_MU_MCR_REG  0x50
#define AUX_MU_LSR_REG  0x54
#define AUX_MU_MSR_REG  0x58
#define AUX_MU_SCRATCH  0x5c
#define AUX_MU_CNTL_REG 0x60
#define AUX_MU_STAT_REG 0x64
#define AUX_MU_BAUD_REG 0x68

/* bits in IER/IIR registers */
#define RX_INT  0x1
#define TX_INT  0x2

static void bcm2835_aux_update(BCM2835AuxState *s)
{
    /* signal an interrupt if either:
     * 1. rx interrupt is enabled and we have a non-empty rx fifo, or
     * 2. the tx interrupt is enabled (since we instantly drain the tx fifo)
     */
    s->iir = 0;
    if ((s->ier & RX_INT) && s->read_count != 0) {
        s->iir |= RX_INT;
    }
    if (s->ier & TX_INT) {
        s->iir |= TX_INT;
    }
    qemu_set_irq(s->irq, s->iir != 0);
}

static uint64_t bcm2835_aux_read(void *opaque, hwaddr offset, unsigned size)
{
    BCM2835AuxState *s = opaque;
    uint32_t c, res;

    switch (offset) {
    case AUX_IRQ:
        return s->iir != 0;

    case AUX_ENABLES:
        return 1; /* mini UART permanently enabled */

    case AUX_MU_IO_REG:
        /* "DLAB bit set means access baudrate register" is NYI */
        c = s->read_fifo[s->read_pos];
        if (s->read_count > 0) {
            s->read_count--;
            if (++s->read_pos == BCM2835_AUX_RX_FIFO_LEN) {
                s->read_pos = 0;
            }
        }
        qemu_chr_fe_accept_input(&s->chr);
        bcm2835_aux_update(s);
        return c;

    case AUX_MU_IER_REG:
        /* "DLAB bit set means access baudrate register" is NYI */
        return 0xc0 | s->ier; /* FIFO enables always read 1 */

    case AUX_MU_IIR_REG:
        res = 0xc0; /* FIFO enables */
        /* The spec is unclear on what happens when both tx and rx
         * interrupts are active, besides that this cannot occur. At
         * present, we choose to prioritise the rx interrupt, since
         * the tx fifo is always empty. */
        if (s->read_count != 0) {
            res |= 0x4;
        } else {
            res |= 0x2;
        }
        if (s->iir == 0) {
            res |= 0x1;
        }
        return res;

    case AUX_MU_LCR_REG:
        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_LCR_REG unsupported\n", __func__);
        return 0;

    case AUX_MU_MCR_REG:
        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MCR_REG unsupported\n", __func__);
        return 0;

    case AUX_MU_LSR_REG:
        res = 0x60; /* tx idle, empty */
        if (s->read_count != 0) {
            res |= 0x1;
        }
        return res;

    case AUX_MU_MSR_REG:
        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MSR_REG unsupported\n", __func__);
        return 0;

    case AUX_MU_SCRATCH:
        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_SCRATCH unsupported\n", __func__);
        return 0;

    case AUX_MU_CNTL_REG:
        return 0x3; /* tx, rx enabled */

    case AUX_MU_STAT_REG:
        res = 0x30e; /* space in the output buffer, empty tx fifo, idle tx/rx */
        if (s->read_count > 0) {
            res |= 0x1; /* data in input buffer */
            assert(s->read_count < BCM2835_AUX_RX_FIFO_LEN);
            res |= ((uint32_t)s->read_count) << 16; /* rx fifo fill level */
        }
        return res;

    case AUX_MU_BAUD_REG:
        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_BAUD_REG unsupported\n", __func__);
        return 0;

    default:
        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
                      __func__, offset);
        return 0;
    }
}

static void bcm2835_aux_write(void *opaque, hwaddr offset, uint64_t value,
                              unsigned size)
{
    BCM2835AuxState *s = opaque;
    unsigned char ch;

    switch (offset) {
    case AUX_ENABLES:
        if (value != 1) {
            qemu_log_mask(LOG_UNIMP, "%s: unsupported attempt to enable SPI "
                          "or disable UART\n", __func__);
        }
        break;

    case AUX_MU_IO_REG:
        /* "DLAB bit set means access baudrate register" is NYI */
        ch = value;
        /* XXX this blocks entire thread. Rewrite to use
         * qemu_chr_fe_write and background I/O callbacks */
        qemu_chr_fe_write_all(&s->chr, &ch, 1);
        break;

    case AUX_MU_IER_REG:
        /* "DLAB bit set means access baudrate register" is NYI */
        s->ier = value & (TX_INT | RX_INT);
        bcm2835_aux_update(s);
        break;

    case AUX_MU_IIR_REG:
        if (value & 0x2) {
            s->read_count = 0;
        }
        break;

    case AUX_MU_LCR_REG:
        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_LCR_REG unsupported\n", __func__);
        break;

    case AUX_MU_MCR_REG:
        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MCR_REG unsupported\n", __func__);
        break;

    case AUX_MU_SCRATCH:
        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_SCRATCH unsupported\n", __func__);
        break;

    case AUX_MU_CNTL_REG:
        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_CNTL_REG unsupported\n", __func__);
        break;

    case AUX_MU_BAUD_REG:
        qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_BAUD_REG unsupported\n", __func__);
        break;

    default:
        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
                      __func__, offset);
    }

    bcm2835_aux_update(s);
}

static int bcm2835_aux_can_receive(void *opaque)
{
    BCM2835AuxState *s = opaque;

    return s->read_count < BCM2835_AUX_RX_FIFO_LEN;
}

static void bcm2835_aux_put_fifo(void *opaque, uint8_t value)
{
    BCM2835AuxState *s = opaque;
    int slot;

    slot = s->read_pos + s->read_count;
    if (slot >= BCM2835_AUX_RX_FIFO_LEN) {
        slot -= BCM2835_AUX_RX_FIFO_LEN;
    }
    s->read_fifo[slot] = value;
    s->read_count++;
    if (s->read_count == BCM2835_AUX_RX_FIFO_LEN) {
        /* buffer full */
    }
    bcm2835_aux_update(s);
}

static void bcm2835_aux_receive(void *opaque, const uint8_t *buf, int size)
{
    bcm2835_aux_put_fifo(opaque, *buf);
}

static const MemoryRegionOps bcm2835_aux_ops = {
    .read = bcm2835_aux_read,
    .write = bcm2835_aux_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid.min_access_size = 4,
    .valid.max_access_size = 4,
};

static const VMStateDescription vmstate_bcm2835_aux = {
    .name = TYPE_BCM2835_AUX,
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT8_ARRAY(read_fifo, BCM2835AuxState,
                            BCM2835_AUX_RX_FIFO_LEN),
        VMSTATE_UINT8(read_pos, BCM2835AuxState),
        VMSTATE_UINT8(read_count, BCM2835AuxState),
        VMSTATE_UINT8(ier, BCM2835AuxState),
        VMSTATE_UINT8(iir, BCM2835AuxState),
        VMSTATE_END_OF_LIST()
    }
};

static void bcm2835_aux_init(Object *obj)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    BCM2835AuxState *s = BCM2835_AUX(obj);

    memory_region_init_io(&s->iomem, OBJECT(s), &bcm2835_aux_ops, s,
                          TYPE_BCM2835_AUX, 0x100);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq);
}

static void bcm2835_aux_realize(DeviceState *dev, Error **errp)
{
    BCM2835AuxState *s = BCM2835_AUX(dev);

    qemu_chr_fe_set_handlers(&s->chr, bcm2835_aux_can_receive,
                             bcm2835_aux_receive, NULL, NULL, s, NULL, true);
}

static Property bcm2835_aux_props[] = {
    DEFINE_PROP_CHR("chardev", BCM2835AuxState, chr),
    DEFINE_PROP_END_OF_LIST(),
};

static void bcm2835_aux_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize = bcm2835_aux_realize;
    dc->vmsd = &vmstate_bcm2835_aux;
    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
    dc->props = bcm2835_aux_props;
}

static const TypeInfo bcm2835_aux_info = {
    .name          = TYPE_BCM2835_AUX,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(BCM2835AuxState),
    .instance_init = bcm2835_aux_init,
    .class_init    = bcm2835_aux_class_init,
};

static void bcm2835_aux_register_types(void)
{
    type_register_static(&bcm2835_aux_info);
}

type_init(bcm2835_aux_register_types)
Commit	Line	Data
97398d90 AB	1	/*
	2	* BCM2835 (Raspberry Pi / Pi 2) Aux block (mini UART and SPI).
	3	* Copyright (c) 2015, Microsoft
	4	* Written by Andrew Baumann
	5	* Based on pl011.c, copyright terms below:
	6	*
	7	* Arm PrimeCell PL011 UART
	8	*
	9	* Copyright (c) 2006 CodeSourcery.
	10	* Written by Paul Brook
	11	*
	12	* This code is licensed under the GPL.
	13	*
	14	* At present only the core UART functions (data path for tx/rx) are
	15	* implemented. The following features/registers are unimplemented:
	16	* - Line/modem control
	17	* - Scratch register
	18	* - Extra control
	19	* - Baudrate
	20	* - SPI interfaces
	21	*/
	22
	23	#include "qemu/osdep.h"
	24	#include "hw/char/bcm2835_aux.h"
03dd024f	25	#include "qemu/log.h"
0b8fa32f	26	#include "qemu/module.h"
97398d90 AB	27
	28	#define AUX_IRQ 0x0
	29	#define AUX_ENABLES 0x4
	30	#define AUX_MU_IO_REG 0x40
	31	#define AUX_MU_IER_REG 0x44
	32	#define AUX_MU_IIR_REG 0x48
	33	#define AUX_MU_LCR_REG 0x4c
	34	#define AUX_MU_MCR_REG 0x50
	35	#define AUX_MU_LSR_REG 0x54
	36	#define AUX_MU_MSR_REG 0x58
	37	#define AUX_MU_SCRATCH 0x5c
	38	#define AUX_MU_CNTL_REG 0x60
	39	#define AUX_MU_STAT_REG 0x64
	40	#define AUX_MU_BAUD_REG 0x68
	41
	42	/* bits in IER/IIR registers */
65e9f27f GR	43	#define RX_INT 0x1
65e9f27f GR	44	#define TX_INT 0x2
97398d90 AB	45
	46	static void bcm2835_aux_update(BCM2835AuxState *s)
	47	{
	48	/* signal an interrupt if either:
	49	* 1. rx interrupt is enabled and we have a non-empty rx fifo, or
	50	* 2. the tx interrupt is enabled (since we instantly drain the tx fifo)
	51	*/
	52	s->iir = 0;
	53	if ((s->ier & RX_INT) && s->read_count != 0) {
	54	s->iir \|= RX_INT;
	55	}
	56	if (s->ier & TX_INT) {
	57	s->iir \|= TX_INT;
	58	}
	59	qemu_set_irq(s->irq, s->iir != 0);
	60	}
	61
	62	static uint64_t bcm2835_aux_read(void *opaque, hwaddr offset, unsigned size)
	63	{
	64	BCM2835AuxState *s = opaque;
	65	uint32_t c, res;
	66
	67	switch (offset) {
	68	case AUX_IRQ:
	69	return s->iir != 0;
	70
	71	case AUX_ENABLES:
	72	return 1; /* mini UART permanently enabled */
	73
	74	case AUX_MU_IO_REG:
	75	/* "DLAB bit set means access baudrate register" is NYI */
	76	c = s->read_fifo[s->read_pos];
	77	if (s->read_count > 0) {
	78	s->read_count--;
	79	if (++s->read_pos == BCM2835_AUX_RX_FIFO_LEN) {
	80	s->read_pos = 0;
	81	}
	82	}
fa394ed6	83	qemu_chr_fe_accept_input(&s->chr);
97398d90 AB	84	bcm2835_aux_update(s);
	85	return c;
	86
	87	case AUX_MU_IER_REG:
	88	/* "DLAB bit set means access baudrate register" is NYI */
	89	return 0xc0 \| s->ier; /* FIFO enables always read 1 */
	90
	91	case AUX_MU_IIR_REG:
	92	res = 0xc0; /* FIFO enables */
	93	/* The spec is unclear on what happens when both tx and rx
	94	* interrupts are active, besides that this cannot occur. At
	95	* present, we choose to prioritise the rx interrupt, since
	96	* the tx fifo is always empty. */
	97	if (s->read_count != 0) {
	98	res \|= 0x4;
	99	} else {
	100	res \|= 0x2;
	101	}
	102	if (s->iir == 0) {
	103	res \|= 0x1;
	104	}
	105	return res;
	106
	107	case AUX_MU_LCR_REG:
	108	qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_LCR_REG unsupported\n", __func__);
	109	return 0;
	110
	111	case AUX_MU_MCR_REG:
	112	qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MCR_REG unsupported\n", __func__);
	113	return 0;
	114
	115	case AUX_MU_LSR_REG:
	116	res = 0x60; /* tx idle, empty */
	117	if (s->read_count != 0) {
	118	res \|= 0x1;
	119	}
	120	return res;
	121
	122	case AUX_MU_MSR_REG:
	123	qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MSR_REG unsupported\n", __func__);
	124	return 0;
	125
	126	case AUX_MU_SCRATCH:
	127	qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_SCRATCH unsupported\n", __func__);
	128	return 0;
	129
	130	case AUX_MU_CNTL_REG:
	131	return 0x3; /* tx, rx enabled */
	132
	133	case AUX_MU_STAT_REG:
	134	res = 0x30e; /* space in the output buffer, empty tx fifo, idle tx/rx */
	135	if (s->read_count > 0) {
	136	res \|= 0x1; /* data in input buffer */
	137	assert(s->read_count < BCM2835_AUX_RX_FIFO_LEN);
	138	res \|= ((uint32_t)s->read_count) << 16; /* rx fifo fill level */
	139	}
	140	return res;
	141
	142	case AUX_MU_BAUD_REG:
	143	qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_BAUD_REG unsupported\n", __func__);
	144	return 0;
	145
	146	default:
	147	qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
148	__func__, offset);
149	return 0;
150	}
151	}
152
153	static void bcm2835_aux_write(void *opaque, hwaddr offset, uint64_t value,
154	unsigned size)
155	{
156	BCM2835AuxState *s = opaque;
157	unsigned char ch;
158
159	switch (offset) {
160	case AUX_ENABLES:
161	if (value != 1) {
162	qemu_log_mask(LOG_UNIMP, "%s: unsupported attempt to enable SPI "
163	"or disable UART\n", __func__);
164	}
165	break;
166
167	case AUX_MU_IO_REG:
168	/* "DLAB bit set means access baudrate register" is NYI */
169	ch = value;
fa394ed6 MAL	170	/* XXX this blocks entire thread. Rewrite to use
	171	* qemu_chr_fe_write and background I/O callbacks */
	172	qemu_chr_fe_write_all(&s->chr, &ch, 1);
97398d90 AB	173	break;
	174
	175	case AUX_MU_IER_REG:
	176	/* "DLAB bit set means access baudrate register" is NYI */
	177	s->ier = value & (TX_INT \| RX_INT);
	178	bcm2835_aux_update(s);
	179	break;
	180
	181	case AUX_MU_IIR_REG:
	182	if (value & 0x2) {
	183	s->read_count = 0;
	184	}
	185	break;
	186
	187	case AUX_MU_LCR_REG:
	188	qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_LCR_REG unsupported\n", __func__);
	189	break;
	190
	191	case AUX_MU_MCR_REG:
	192	qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MCR_REG unsupported\n", __func__);
	193	break;
	194
	195	case AUX_MU_SCRATCH:
	196	qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_SCRATCH unsupported\n", __func__);
	197	break;
	198
	199	case AUX_MU_CNTL_REG:
	200	qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_CNTL_REG unsupported\n", __func__);
	201	break;
	202
	203	case AUX_MU_BAUD_REG:
	204	qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_BAUD_REG unsupported\n", __func__);
	205	break;
	206
	207	default:
	208	qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n",
	209	__func__, offset);
	210	}
	211
	212	bcm2835_aux_update(s);
	213	}
	214
	215	static int bcm2835_aux_can_receive(void *opaque)
	216	{
	217	BCM2835AuxState *s = opaque;
	218
	219	return s->read_count < BCM2835_AUX_RX_FIFO_LEN;
	220	}
	221
	222	static void bcm2835_aux_put_fifo(void *opaque, uint8_t value)
	223	{
	224	BCM2835AuxState *s = opaque;
	225	int slot;
	226
	227	slot = s->read_pos + s->read_count;
	228	if (slot >= BCM2835_AUX_RX_FIFO_LEN) {
	229	slot -= BCM2835_AUX_RX_FIFO_LEN;
	230	}
	231	s->read_fifo[slot] = value;
	232	s->read_count++;
	233	if (s->read_count == BCM2835_AUX_RX_FIFO_LEN) {
	234	/* buffer full */
	235	}
	236	bcm2835_aux_update(s);
237	}
238
239	static void bcm2835_aux_receive(void opaque, const uint8_t buf, int size)
240	{
241	bcm2835_aux_put_fifo(opaque, *buf);
242	}
243
244	static const MemoryRegionOps bcm2835_aux_ops = {
245	.read = bcm2835_aux_read,
246	.write = bcm2835_aux_write,
247	.endianness = DEVICE_NATIVE_ENDIAN,
248	.valid.min_access_size = 4,
249	.valid.max_access_size = 4,
250	};
251
252	static const VMStateDescription vmstate_bcm2835_aux = {
253	.name = TYPE_BCM2835_AUX,
254	.version_id = 1,
255	.minimum_version_id = 1,
256	.fields = (VMStateField[]) {
257	VMSTATE_UINT8_ARRAY(read_fifo, BCM2835AuxState,
258	BCM2835_AUX_RX_FIFO_LEN),
259	VMSTATE_UINT8(read_pos, BCM2835AuxState),
260	VMSTATE_UINT8(read_count, BCM2835AuxState),
261	VMSTATE_UINT8(ier, BCM2835AuxState),
262	VMSTATE_UINT8(iir, BCM2835AuxState),
263	VMSTATE_END_OF_LIST()
264	}
265	};
266
267	static void bcm2835_aux_init(Object *obj)
268	{
269	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
270	BCM2835AuxState *s = BCM2835_AUX(obj);
271
272	memory_region_init_io(&s->iomem, OBJECT(s), &bcm2835_aux_ops, s,
273	TYPE_BCM2835_AUX, 0x100);
274	sysbus_init_mmio(sbd, &s->iomem);
275	sysbus_init_irq(sbd, &s->irq);
276	}
277
278	static void bcm2835_aux_realize(DeviceState dev, Error *errp)
279	{
280	BCM2835AuxState *s = BCM2835_AUX(dev);
281
fa394ed6	282	qemu_chr_fe_set_handlers(&s->chr, bcm2835_aux_can_receive,
81517ba3	283	bcm2835_aux_receive, NULL, NULL, s, NULL, true);
97398d90 AB	284	}
	285
	286	static Property bcm2835_aux_props[] = {
	287	DEFINE_PROP_CHR("chardev", BCM2835AuxState, chr),
	288	DEFINE_PROP_END_OF_LIST(),
	289	};
	290
	291	static void bcm2835_aux_class_init(ObjectClass oc, void data)
	292	{
	293	DeviceClass *dc = DEVICE_CLASS(oc);
	294
	295	dc->realize = bcm2835_aux_realize;
	296	dc->vmsd = &vmstate_bcm2835_aux;
	297	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
	298	dc->props = bcm2835_aux_props;
	299	}
	300
	301	static const TypeInfo bcm2835_aux_info = {
	302	.name = TYPE_BCM2835_AUX,
	303	.parent = TYPE_SYS_BUS_DEVICE,
	304	.instance_size = sizeof(BCM2835AuxState),
	305	.instance_init = bcm2835_aux_init,
	306	.class_init = bcm2835_aux_class_init,
	307	};
	308
	309	static void bcm2835_aux_register_types(void)
	310	{
	311	type_register_static(&bcm2835_aux_info);
	312	}
	313
	314	type_init(bcm2835_aux_register_types)