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hw: replace most use of qemu_chr_fe_write with qemu_chr_fe_write_all
[mirror_qemu.git] / hw / char / debugcon.c
CommitLineData
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1/*
2 * QEMU Bochs-style debug console ("port E9") emulation
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2008 Citrix Systems, Inc.
6 * Copyright (c) Intel Corporation; author: H. Peter Anvin
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
b6a0aa05 27#include "qemu/osdep.h"
da34e65c 28#include "qapi/error.h"
83c9f4ca 29#include "hw/hw.h"
dccfcd0e 30#include "sysemu/char.h"
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31#include "hw/isa/isa.h"
32#include "hw/i386/pc.h"
c9f398e5 33
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34#define TYPE_ISA_DEBUGCON_DEVICE "isa-debugcon"
35#define ISA_DEBUGCON_DEVICE(obj) \
36 OBJECT_CHECK(ISADebugconState, (obj), TYPE_ISA_DEBUGCON_DEVICE)
37
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38//#define DEBUG_DEBUGCON
39
40typedef struct DebugconState {
e8ba1ce9 41 MemoryRegion io;
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42 CharDriverState *chr;
43 uint32_t readback;
44} DebugconState;
45
46typedef struct ISADebugconState {
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47 ISADevice parent_obj;
48
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49 uint32_t iobase;
50 DebugconState state;
51} ISADebugconState;
52
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53static void debugcon_ioport_write(void *opaque, hwaddr addr, uint64_t val,
54 unsigned width)
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55{
56 DebugconState *s = opaque;
57 unsigned char ch = val;
58
59#ifdef DEBUG_DEBUGCON
668fca91 60 printf(" [debugcon: write addr=0x%04" HWADDR_PRIx " val=0x%02" PRIx64 "]\n", addr, val);
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61#endif
62
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63 /* XXX this blocks entire thread. Rewrite to use
64 * qemu_chr_fe_write and background I/O callbacks */
65 qemu_chr_fe_write_all(s->chr, &ch, 1);
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66}
67
68
e8ba1ce9 69static uint64_t debugcon_ioport_read(void *opaque, hwaddr addr, unsigned width)
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70{
71 DebugconState *s = opaque;
72
73#ifdef DEBUG_DEBUGCON
668fca91 74 printf("debugcon: read addr=0x%04" HWADDR_PRIx "\n", addr);
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75#endif
76
77 return s->readback;
78}
79
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80static const MemoryRegionOps debugcon_ops = {
81 .read = debugcon_ioport_read,
82 .write = debugcon_ioport_write,
83 .valid.min_access_size = 1,
84 .valid.max_access_size = 1,
85 .endianness = DEVICE_LITTLE_ENDIAN,
86};
87
db895a1e 88static void debugcon_realize_core(DebugconState *s, Error **errp)
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89{
90 if (!s->chr) {
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91 error_setg(errp, "Can't create debugcon device, empty char device");
92 return;
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93 }
94
95 qemu_chr_add_handlers(s->chr, NULL, NULL, NULL, s);
96}
97
db895a1e 98static void debugcon_isa_realizefn(DeviceState *dev, Error **errp)
c9f398e5 99{
db895a1e 100 ISADevice *d = ISA_DEVICE(dev);
e8ba1ce9 101 ISADebugconState *isa = ISA_DEBUGCON_DEVICE(dev);
c9f398e5 102 DebugconState *s = &isa->state;
db895a1e 103 Error *err = NULL;
c9f398e5 104
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105 debugcon_realize_core(s, &err);
106 if (err != NULL) {
107 error_propagate(errp, err);
108 return;
109 }
300b1fc6 110 memory_region_init_io(&s->io, OBJECT(dev), &debugcon_ops, s,
e8ba1ce9 111 TYPE_ISA_DEBUGCON_DEVICE, 1);
db895a1e 112 memory_region_add_subregion(isa_address_space_io(d),
e8ba1ce9 113 isa->iobase, &s->io);
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114}
115
39bffca2 116static Property debugcon_isa_properties[] = {
c7bcc85d 117 DEFINE_PROP_UINT32("iobase", ISADebugconState, iobase, 0xe9),
39bffca2 118 DEFINE_PROP_CHR("chardev", ISADebugconState, state.chr),
c7bcc85d 119 DEFINE_PROP_UINT32("readback", ISADebugconState, state.readback, 0xe9),
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120 DEFINE_PROP_END_OF_LIST(),
121};
122
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123static void debugcon_isa_class_initfn(ObjectClass *klass, void *data)
124{
39bffca2 125 DeviceClass *dc = DEVICE_CLASS(klass);
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126
127 dc->realize = debugcon_isa_realizefn;
39bffca2 128 dc->props = debugcon_isa_properties;
125ee0ed 129 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
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130}
131
8c43a6f0 132static const TypeInfo debugcon_isa_info = {
e8ba1ce9 133 .name = TYPE_ISA_DEBUGCON_DEVICE,
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134 .parent = TYPE_ISA_DEVICE,
135 .instance_size = sizeof(ISADebugconState),
136 .class_init = debugcon_isa_class_initfn,
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137};
138
83f7d43a 139static void debugcon_register_types(void)
c9f398e5 140{
39bffca2 141 type_register_static(&debugcon_isa_info);
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142}
143
83f7d43a 144type_init(debugcon_register_types)