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Commit | Line | Data |
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e80cfcfc | 1 | /* |
b4ed08e0 | 2 | * QEMU ESCC (Z8030/Z8530/Z85C30/SCC/ESCC) serial port emulation |
5fafdf24 | 3 | * |
8be1f5c8 | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
5fafdf24 | 5 | * |
e80cfcfc FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
6c319c82 | 24 | |
0430891c | 25 | #include "qemu/osdep.h" |
83c9f4ca PB |
26 | #include "hw/hw.h" |
27 | #include "hw/sysbus.h" | |
0d09e41a | 28 | #include "hw/char/escc.h" |
4d43a603 | 29 | #include "chardev/char-fe.h" |
7566c6ef | 30 | #include "chardev/char-serial.h" |
28ecbaee | 31 | #include "ui/console.h" |
65e7545e | 32 | #include "ui/input.h" |
30c2f238 | 33 | #include "trace.h" |
e80cfcfc FB |
34 | |
35 | /* | |
09330e90 BS |
36 | * Chipset docs: |
37 | * "Z80C30/Z85C30/Z80230/Z85230/Z85233 SCC/ESCC User Manual", | |
38 | * http://www.zilog.com/docs/serial/scc_escc_um.pdf | |
39 | * | |
b4ed08e0 | 40 | * On Sparc32 this is the serial port, mouse and keyboard part of chip STP2001 |
e80cfcfc FB |
41 | * (Slave I/O), also produced as NCR89C105. See |
42 | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt | |
5fafdf24 | 43 | * |
e80cfcfc FB |
44 | * The serial ports implement full AMD AM8530 or Zilog Z8530 chips, |
45 | * mouse and keyboard ports don't implement all functions and they are | |
46 | * only asynchronous. There is no DMA. | |
47 | * | |
b4ed08e0 BS |
48 | * Z85C30 is also used on PowerMacs. There are some small differences |
49 | * between Sparc version (sunzilog) and PowerMac (pmac): | |
50 | * Offset between control and data registers | |
51 | * There is some kind of lockup bug, but we can ignore it | |
52 | * CTS is inverted | |
53 | * DMA on pmac using DBDMA chip | |
54 | * pmac can do IRDA and faster rates, sunzilog can only do 38400 | |
55 | * pmac baud rate generator clock is 3.6864 MHz, sunzilog 4.9152 MHz | |
e80cfcfc FB |
56 | */ |
57 | ||
715748fa FB |
58 | /* |
59 | * Modifications: | |
60 | * 2006-Aug-10 Igor Kovalenko : Renamed KBDQueue to SERIOQueue, implemented | |
61 | * serial mouse queue. | |
62 | * Implemented serial mouse protocol. | |
9fc391f8 AT |
63 | * |
64 | * 2010-May-23 Artyom Tarasenko: Reworked IUS logic | |
715748fa FB |
65 | */ |
66 | ||
8be1f5c8 FB |
67 | typedef enum { |
68 | chn_a, chn_b, | |
8e39a033 | 69 | } ChnID; |
8be1f5c8 | 70 | |
35db099d FB |
71 | #define CHN_C(s) ((s)->chn == chn_b? 'b' : 'a') |
72 | ||
8be1f5c8 FB |
73 | typedef enum { |
74 | ser, kbd, mouse, | |
8e39a033 | 75 | } ChnType; |
8be1f5c8 | 76 | |
715748fa | 77 | #define SERIO_QUEUE_SIZE 256 |
8be1f5c8 FB |
78 | |
79 | typedef struct { | |
715748fa | 80 | uint8_t data[SERIO_QUEUE_SIZE]; |
8be1f5c8 | 81 | int rptr, wptr, count; |
715748fa | 82 | } SERIOQueue; |
8be1f5c8 | 83 | |
12abac85 | 84 | #define SERIAL_REGS 16 |
e80cfcfc | 85 | typedef struct ChannelState { |
d537cf6c | 86 | qemu_irq irq; |
22548760 | 87 | uint32_t rxint, txint, rxint_under_svc, txint_under_svc; |
8be1f5c8 | 88 | struct ChannelState *otherchn; |
d7b95534 BS |
89 | uint32_t reg; |
90 | uint8_t wregs[SERIAL_REGS], rregs[SERIAL_REGS]; | |
715748fa | 91 | SERIOQueue queue; |
becdfa00 | 92 | CharBackend chr; |
bbbb2f0a | 93 | int e0_mode, led_mode, caps_lock_mode, num_lock_mode; |
577390ff | 94 | int disabled; |
b4ed08e0 | 95 | int clock; |
bdb78cae | 96 | uint32_t vmstate_dummy; |
d7b95534 BS |
97 | ChnID chn; // this channel, A (base+4) or B (base+0) |
98 | ChnType type; | |
99 | uint8_t rx, tx; | |
65e7545e | 100 | QemuInputHandlerState *hs; |
e80cfcfc FB |
101 | } ChannelState; |
102 | ||
81069b20 AF |
103 | #define ESCC(obj) OBJECT_CHECK(ESCCState, (obj), TYPE_ESCC) |
104 | ||
3cf63ff2 | 105 | typedef struct ESCCState { |
81069b20 AF |
106 | SysBusDevice parent_obj; |
107 | ||
e80cfcfc | 108 | struct ChannelState chn[2]; |
ec02f7de | 109 | uint32_t it_shift; |
23c5e4ca | 110 | MemoryRegion mmio; |
ee6847d1 GH |
111 | uint32_t disabled; |
112 | uint32_t frequency; | |
3cf63ff2 | 113 | } ESCCState; |
e80cfcfc | 114 | |
12abac85 BS |
115 | #define SERIAL_CTRL 0 |
116 | #define SERIAL_DATA 1 | |
117 | ||
118 | #define W_CMD 0 | |
119 | #define CMD_PTR_MASK 0x07 | |
120 | #define CMD_CMD_MASK 0x38 | |
121 | #define CMD_HI 0x08 | |
122 | #define CMD_CLR_TXINT 0x28 | |
123 | #define CMD_CLR_IUS 0x38 | |
124 | #define W_INTR 1 | |
125 | #define INTR_INTALL 0x01 | |
126 | #define INTR_TXINT 0x02 | |
127 | #define INTR_RXMODEMSK 0x18 | |
128 | #define INTR_RXINT1ST 0x08 | |
129 | #define INTR_RXINTALL 0x10 | |
130 | #define W_IVEC 2 | |
131 | #define W_RXCTRL 3 | |
132 | #define RXCTRL_RXEN 0x01 | |
133 | #define W_TXCTRL1 4 | |
134 | #define TXCTRL1_PAREN 0x01 | |
135 | #define TXCTRL1_PAREV 0x02 | |
136 | #define TXCTRL1_1STOP 0x04 | |
137 | #define TXCTRL1_1HSTOP 0x08 | |
138 | #define TXCTRL1_2STOP 0x0c | |
139 | #define TXCTRL1_STPMSK 0x0c | |
140 | #define TXCTRL1_CLK1X 0x00 | |
141 | #define TXCTRL1_CLK16X 0x40 | |
142 | #define TXCTRL1_CLK32X 0x80 | |
143 | #define TXCTRL1_CLK64X 0xc0 | |
144 | #define TXCTRL1_CLKMSK 0xc0 | |
145 | #define W_TXCTRL2 5 | |
146 | #define TXCTRL2_TXEN 0x08 | |
147 | #define TXCTRL2_BITMSK 0x60 | |
148 | #define TXCTRL2_5BITS 0x00 | |
149 | #define TXCTRL2_7BITS 0x20 | |
150 | #define TXCTRL2_6BITS 0x40 | |
151 | #define TXCTRL2_8BITS 0x60 | |
152 | #define W_SYNC1 6 | |
153 | #define W_SYNC2 7 | |
154 | #define W_TXBUF 8 | |
155 | #define W_MINTR 9 | |
156 | #define MINTR_STATUSHI 0x10 | |
157 | #define MINTR_RST_MASK 0xc0 | |
158 | #define MINTR_RST_B 0x40 | |
159 | #define MINTR_RST_A 0x80 | |
160 | #define MINTR_RST_ALL 0xc0 | |
161 | #define W_MISC1 10 | |
162 | #define W_CLOCK 11 | |
163 | #define CLOCK_TRXC 0x08 | |
164 | #define W_BRGLO 12 | |
165 | #define W_BRGHI 13 | |
166 | #define W_MISC2 14 | |
167 | #define MISC2_PLLDIS 0x30 | |
168 | #define W_EXTINT 15 | |
169 | #define EXTINT_DCD 0x08 | |
170 | #define EXTINT_SYNCINT 0x10 | |
171 | #define EXTINT_CTSINT 0x20 | |
172 | #define EXTINT_TXUNDRN 0x40 | |
173 | #define EXTINT_BRKINT 0x80 | |
174 | ||
175 | #define R_STATUS 0 | |
176 | #define STATUS_RXAV 0x01 | |
177 | #define STATUS_ZERO 0x02 | |
178 | #define STATUS_TXEMPTY 0x04 | |
179 | #define STATUS_DCD 0x08 | |
180 | #define STATUS_SYNC 0x10 | |
181 | #define STATUS_CTS 0x20 | |
182 | #define STATUS_TXUNDRN 0x40 | |
183 | #define STATUS_BRK 0x80 | |
184 | #define R_SPEC 1 | |
185 | #define SPEC_ALLSENT 0x01 | |
186 | #define SPEC_BITS8 0x06 | |
187 | #define R_IVEC 2 | |
188 | #define IVEC_TXINTB 0x00 | |
189 | #define IVEC_LONOINT 0x06 | |
190 | #define IVEC_LORXINTA 0x0c | |
191 | #define IVEC_LORXINTB 0x04 | |
192 | #define IVEC_LOTXINTA 0x08 | |
193 | #define IVEC_HINOINT 0x60 | |
194 | #define IVEC_HIRXINTA 0x30 | |
195 | #define IVEC_HIRXINTB 0x20 | |
196 | #define IVEC_HITXINTA 0x10 | |
197 | #define R_INTR 3 | |
198 | #define INTR_EXTINTB 0x01 | |
199 | #define INTR_TXINTB 0x02 | |
200 | #define INTR_RXINTB 0x04 | |
201 | #define INTR_EXTINTA 0x08 | |
202 | #define INTR_TXINTA 0x10 | |
203 | #define INTR_RXINTA 0x20 | |
204 | #define R_IPEN 4 | |
205 | #define R_TXCTRL1 5 | |
206 | #define R_TXCTRL2 6 | |
207 | #define R_BC 7 | |
208 | #define R_RXBUF 8 | |
209 | #define R_RXCTRL 9 | |
210 | #define R_MISC 10 | |
211 | #define R_MISC1 11 | |
212 | #define R_BRGLO 12 | |
213 | #define R_BRGHI 13 | |
214 | #define R_MISC1I 14 | |
215 | #define R_EXTINT 15 | |
e80cfcfc | 216 | |
8be1f5c8 FB |
217 | static void handle_kbd_command(ChannelState *s, int val); |
218 | static int serial_can_receive(void *opaque); | |
219 | static void serial_receive_byte(ChannelState *s, int ch); | |
220 | ||
67deb562 BS |
221 | static void clear_queue(void *opaque) |
222 | { | |
223 | ChannelState *s = opaque; | |
224 | SERIOQueue *q = &s->queue; | |
225 | q->rptr = q->wptr = q->count = 0; | |
226 | } | |
227 | ||
8be1f5c8 FB |
228 | static void put_queue(void *opaque, int b) |
229 | { | |
230 | ChannelState *s = opaque; | |
715748fa | 231 | SERIOQueue *q = &s->queue; |
8be1f5c8 | 232 | |
30c2f238 | 233 | trace_escc_put_queue(CHN_C(s), b); |
715748fa | 234 | if (q->count >= SERIO_QUEUE_SIZE) |
8be1f5c8 FB |
235 | return; |
236 | q->data[q->wptr] = b; | |
715748fa | 237 | if (++q->wptr == SERIO_QUEUE_SIZE) |
8be1f5c8 FB |
238 | q->wptr = 0; |
239 | q->count++; | |
240 | serial_receive_byte(s, 0); | |
241 | } | |
242 | ||
243 | static uint32_t get_queue(void *opaque) | |
244 | { | |
245 | ChannelState *s = opaque; | |
715748fa | 246 | SERIOQueue *q = &s->queue; |
8be1f5c8 | 247 | int val; |
3b46e624 | 248 | |
8be1f5c8 | 249 | if (q->count == 0) { |
f930d07e | 250 | return 0; |
8be1f5c8 FB |
251 | } else { |
252 | val = q->data[q->rptr]; | |
715748fa | 253 | if (++q->rptr == SERIO_QUEUE_SIZE) |
8be1f5c8 FB |
254 | q->rptr = 0; |
255 | q->count--; | |
256 | } | |
30c2f238 | 257 | trace_escc_get_queue(CHN_C(s), val); |
8be1f5c8 | 258 | if (q->count > 0) |
f930d07e | 259 | serial_receive_byte(s, 0); |
8be1f5c8 FB |
260 | return val; |
261 | } | |
262 | ||
b4ed08e0 | 263 | static int escc_update_irq_chn(ChannelState *s) |
e80cfcfc | 264 | { |
9fc391f8 | 265 | if ((((s->wregs[W_INTR] & INTR_TXINT) && (s->txint == 1)) || |
12abac85 BS |
266 | // tx ints enabled, pending |
267 | ((((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINT1ST) || | |
268 | ((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINTALL)) && | |
f930d07e | 269 | s->rxint == 1) || // rx ints enabled, pending |
12abac85 BS |
270 | ((s->wregs[W_EXTINT] & EXTINT_BRKINT) && |
271 | (s->rregs[R_STATUS] & STATUS_BRK)))) { // break int e&p | |
e4a89056 | 272 | return 1; |
e80cfcfc | 273 | } |
e4a89056 FB |
274 | return 0; |
275 | } | |
276 | ||
b4ed08e0 | 277 | static void escc_update_irq(ChannelState *s) |
e4a89056 FB |
278 | { |
279 | int irq; | |
280 | ||
b4ed08e0 BS |
281 | irq = escc_update_irq_chn(s); |
282 | irq |= escc_update_irq_chn(s->otherchn); | |
e4a89056 | 283 | |
30c2f238 | 284 | trace_escc_update_irq(irq); |
d537cf6c | 285 | qemu_set_irq(s->irq, irq); |
e80cfcfc FB |
286 | } |
287 | ||
b4ed08e0 | 288 | static void escc_reset_chn(ChannelState *s) |
e80cfcfc FB |
289 | { |
290 | int i; | |
291 | ||
292 | s->reg = 0; | |
8f180a43 | 293 | for (i = 0; i < SERIAL_REGS; i++) { |
f930d07e BS |
294 | s->rregs[i] = 0; |
295 | s->wregs[i] = 0; | |
e80cfcfc | 296 | } |
12abac85 BS |
297 | s->wregs[W_TXCTRL1] = TXCTRL1_1STOP; // 1X divisor, 1 stop bit, no parity |
298 | s->wregs[W_MINTR] = MINTR_RST_ALL; | |
299 | s->wregs[W_CLOCK] = CLOCK_TRXC; // Synch mode tx clock = TRxC | |
300 | s->wregs[W_MISC2] = MISC2_PLLDIS; // PLL disabled | |
301 | s->wregs[W_EXTINT] = EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT | | |
302 | EXTINT_TXUNDRN | EXTINT_BRKINT; // Enable most interrupts | |
577390ff | 303 | if (s->disabled) |
12abac85 BS |
304 | s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC | |
305 | STATUS_CTS | STATUS_TXUNDRN; | |
577390ff | 306 | else |
12abac85 | 307 | s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_TXUNDRN; |
f48c537d | 308 | s->rregs[R_SPEC] = SPEC_BITS8 | SPEC_ALLSENT; |
e80cfcfc FB |
309 | |
310 | s->rx = s->tx = 0; | |
311 | s->rxint = s->txint = 0; | |
e4a89056 | 312 | s->rxint_under_svc = s->txint_under_svc = 0; |
bbbb2f0a | 313 | s->e0_mode = s->led_mode = s->caps_lock_mode = s->num_lock_mode = 0; |
67deb562 | 314 | clear_queue(s); |
e80cfcfc FB |
315 | } |
316 | ||
bdb78cae | 317 | static void escc_reset(DeviceState *d) |
e80cfcfc | 318 | { |
81069b20 | 319 | ESCCState *s = ESCC(d); |
bdb78cae | 320 | |
b4ed08e0 BS |
321 | escc_reset_chn(&s->chn[0]); |
322 | escc_reset_chn(&s->chn[1]); | |
e80cfcfc FB |
323 | } |
324 | ||
ba3c64fb FB |
325 | static inline void set_rxint(ChannelState *s) |
326 | { | |
327 | s->rxint = 1; | |
9fc391f8 AT |
328 | /* XXX: missing daisy chainnig: chn_b rx should have a lower priority |
329 | than chn_a rx/tx/special_condition service*/ | |
330 | s->rxint_under_svc = 1; | |
331 | if (s->chn == chn_a) { | |
12abac85 | 332 | s->rregs[R_INTR] |= INTR_RXINTA; |
9fc391f8 AT |
333 | if (s->wregs[W_MINTR] & MINTR_STATUSHI) |
334 | s->otherchn->rregs[R_IVEC] = IVEC_HIRXINTA; | |
335 | else | |
336 | s->otherchn->rregs[R_IVEC] = IVEC_LORXINTA; | |
337 | } else { | |
12abac85 | 338 | s->otherchn->rregs[R_INTR] |= INTR_RXINTB; |
9fc391f8 AT |
339 | if (s->wregs[W_MINTR] & MINTR_STATUSHI) |
340 | s->rregs[R_IVEC] = IVEC_HIRXINTB; | |
341 | else | |
342 | s->rregs[R_IVEC] = IVEC_LORXINTB; | |
343 | } | |
b4ed08e0 | 344 | escc_update_irq(s); |
ba3c64fb FB |
345 | } |
346 | ||
80637a6a BS |
347 | static inline void set_txint(ChannelState *s) |
348 | { | |
349 | s->txint = 1; | |
350 | if (!s->rxint_under_svc) { | |
351 | s->txint_under_svc = 1; | |
352 | if (s->chn == chn_a) { | |
f53671c0 AJ |
353 | if (s->wregs[W_INTR] & INTR_TXINT) { |
354 | s->rregs[R_INTR] |= INTR_TXINTA; | |
355 | } | |
80637a6a BS |
356 | if (s->wregs[W_MINTR] & MINTR_STATUSHI) |
357 | s->otherchn->rregs[R_IVEC] = IVEC_HITXINTA; | |
358 | else | |
359 | s->otherchn->rregs[R_IVEC] = IVEC_LOTXINTA; | |
360 | } else { | |
361 | s->rregs[R_IVEC] = IVEC_TXINTB; | |
f53671c0 AJ |
362 | if (s->wregs[W_INTR] & INTR_TXINT) { |
363 | s->otherchn->rregs[R_INTR] |= INTR_TXINTB; | |
364 | } | |
80637a6a | 365 | } |
b4ed08e0 | 366 | escc_update_irq(s); |
9fc391f8 | 367 | } |
80637a6a BS |
368 | } |
369 | ||
370 | static inline void clr_rxint(ChannelState *s) | |
371 | { | |
372 | s->rxint = 0; | |
373 | s->rxint_under_svc = 0; | |
374 | if (s->chn == chn_a) { | |
375 | if (s->wregs[W_MINTR] & MINTR_STATUSHI) | |
376 | s->otherchn->rregs[R_IVEC] = IVEC_HINOINT; | |
377 | else | |
378 | s->otherchn->rregs[R_IVEC] = IVEC_LONOINT; | |
379 | s->rregs[R_INTR] &= ~INTR_RXINTA; | |
380 | } else { | |
381 | if (s->wregs[W_MINTR] & MINTR_STATUSHI) | |
382 | s->rregs[R_IVEC] = IVEC_HINOINT; | |
383 | else | |
384 | s->rregs[R_IVEC] = IVEC_LONOINT; | |
385 | s->otherchn->rregs[R_INTR] &= ~INTR_RXINTB; | |
386 | } | |
387 | if (s->txint) | |
388 | set_txint(s); | |
b4ed08e0 | 389 | escc_update_irq(s); |
80637a6a BS |
390 | } |
391 | ||
ba3c64fb FB |
392 | static inline void clr_txint(ChannelState *s) |
393 | { | |
394 | s->txint = 0; | |
e4a89056 | 395 | s->txint_under_svc = 0; |
b9652ca3 | 396 | if (s->chn == chn_a) { |
12abac85 BS |
397 | if (s->wregs[W_MINTR] & MINTR_STATUSHI) |
398 | s->otherchn->rregs[R_IVEC] = IVEC_HINOINT; | |
b9652ca3 | 399 | else |
12abac85 BS |
400 | s->otherchn->rregs[R_IVEC] = IVEC_LONOINT; |
401 | s->rregs[R_INTR] &= ~INTR_TXINTA; | |
b9652ca3 | 402 | } else { |
9fc391f8 | 403 | s->otherchn->rregs[R_INTR] &= ~INTR_TXINTB; |
12abac85 BS |
404 | if (s->wregs[W_MINTR] & MINTR_STATUSHI) |
405 | s->rregs[R_IVEC] = IVEC_HINOINT; | |
b9652ca3 | 406 | else |
12abac85 BS |
407 | s->rregs[R_IVEC] = IVEC_LONOINT; |
408 | s->otherchn->rregs[R_INTR] &= ~INTR_TXINTB; | |
b9652ca3 | 409 | } |
e4a89056 FB |
410 | if (s->rxint) |
411 | set_rxint(s); | |
b4ed08e0 | 412 | escc_update_irq(s); |
ba3c64fb FB |
413 | } |
414 | ||
b4ed08e0 | 415 | static void escc_update_parameters(ChannelState *s) |
35db099d FB |
416 | { |
417 | int speed, parity, data_bits, stop_bits; | |
418 | QEMUSerialSetParams ssp; | |
419 | ||
30650701 | 420 | if (!qemu_chr_fe_backend_connected(&s->chr) || s->type != ser) |
35db099d FB |
421 | return; |
422 | ||
12abac85 BS |
423 | if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREN) { |
424 | if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREV) | |
35db099d FB |
425 | parity = 'E'; |
426 | else | |
427 | parity = 'O'; | |
428 | } else { | |
429 | parity = 'N'; | |
430 | } | |
12abac85 | 431 | if ((s->wregs[W_TXCTRL1] & TXCTRL1_STPMSK) == TXCTRL1_2STOP) |
35db099d FB |
432 | stop_bits = 2; |
433 | else | |
434 | stop_bits = 1; | |
12abac85 BS |
435 | switch (s->wregs[W_TXCTRL2] & TXCTRL2_BITMSK) { |
436 | case TXCTRL2_5BITS: | |
35db099d FB |
437 | data_bits = 5; |
438 | break; | |
12abac85 | 439 | case TXCTRL2_7BITS: |
35db099d FB |
440 | data_bits = 7; |
441 | break; | |
12abac85 | 442 | case TXCTRL2_6BITS: |
35db099d FB |
443 | data_bits = 6; |
444 | break; | |
445 | default: | |
12abac85 | 446 | case TXCTRL2_8BITS: |
35db099d FB |
447 | data_bits = 8; |
448 | break; | |
449 | } | |
b4ed08e0 | 450 | speed = s->clock / ((s->wregs[W_BRGLO] | (s->wregs[W_BRGHI] << 8)) + 2); |
12abac85 BS |
451 | switch (s->wregs[W_TXCTRL1] & TXCTRL1_CLKMSK) { |
452 | case TXCTRL1_CLK1X: | |
35db099d | 453 | break; |
12abac85 | 454 | case TXCTRL1_CLK16X: |
35db099d FB |
455 | speed /= 16; |
456 | break; | |
12abac85 | 457 | case TXCTRL1_CLK32X: |
35db099d FB |
458 | speed /= 32; |
459 | break; | |
460 | default: | |
12abac85 | 461 | case TXCTRL1_CLK64X: |
35db099d FB |
462 | speed /= 64; |
463 | break; | |
464 | } | |
465 | ssp.speed = speed; | |
466 | ssp.parity = parity; | |
467 | ssp.data_bits = data_bits; | |
468 | ssp.stop_bits = stop_bits; | |
30c2f238 | 469 | trace_escc_update_parameters(CHN_C(s), speed, parity, data_bits, stop_bits); |
5345fdb4 | 470 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
35db099d FB |
471 | } |
472 | ||
a8170e5e | 473 | static void escc_mem_write(void *opaque, hwaddr addr, |
23c5e4ca | 474 | uint64_t val, unsigned size) |
e80cfcfc | 475 | { |
3cf63ff2 | 476 | ESCCState *serial = opaque; |
e80cfcfc FB |
477 | ChannelState *s; |
478 | uint32_t saddr; | |
479 | int newreg, channel; | |
480 | ||
481 | val &= 0xff; | |
b4ed08e0 BS |
482 | saddr = (addr >> serial->it_shift) & 1; |
483 | channel = (addr >> (serial->it_shift + 1)) & 1; | |
b3ceef24 | 484 | s = &serial->chn[channel]; |
e80cfcfc | 485 | switch (saddr) { |
12abac85 | 486 | case SERIAL_CTRL: |
30c2f238 | 487 | trace_escc_mem_writeb_ctrl(CHN_C(s), s->reg, val & 0xff); |
f930d07e BS |
488 | newreg = 0; |
489 | switch (s->reg) { | |
12abac85 BS |
490 | case W_CMD: |
491 | newreg = val & CMD_PTR_MASK; | |
492 | val &= CMD_CMD_MASK; | |
f930d07e | 493 | switch (val) { |
12abac85 BS |
494 | case CMD_HI: |
495 | newreg |= CMD_HI; | |
f930d07e | 496 | break; |
12abac85 | 497 | case CMD_CLR_TXINT: |
ba3c64fb | 498 | clr_txint(s); |
f930d07e | 499 | break; |
12abac85 | 500 | case CMD_CLR_IUS: |
9fc391f8 AT |
501 | if (s->rxint_under_svc) { |
502 | s->rxint_under_svc = 0; | |
503 | if (s->txint) { | |
504 | set_txint(s); | |
505 | } | |
506 | } else if (s->txint_under_svc) { | |
507 | s->txint_under_svc = 0; | |
508 | } | |
509 | escc_update_irq(s); | |
f930d07e BS |
510 | break; |
511 | default: | |
512 | break; | |
513 | } | |
514 | break; | |
12abac85 BS |
515 | case W_INTR ... W_RXCTRL: |
516 | case W_SYNC1 ... W_TXBUF: | |
517 | case W_MISC1 ... W_CLOCK: | |
518 | case W_MISC2 ... W_EXTINT: | |
f930d07e BS |
519 | s->wregs[s->reg] = val; |
520 | break; | |
12abac85 BS |
521 | case W_TXCTRL1: |
522 | case W_TXCTRL2: | |
796d8286 | 523 | s->wregs[s->reg] = val; |
b4ed08e0 | 524 | escc_update_parameters(s); |
796d8286 | 525 | break; |
12abac85 BS |
526 | case W_BRGLO: |
527 | case W_BRGHI: | |
f930d07e | 528 | s->wregs[s->reg] = val; |
796d8286 | 529 | s->rregs[s->reg] = val; |
b4ed08e0 | 530 | escc_update_parameters(s); |
f930d07e | 531 | break; |
12abac85 BS |
532 | case W_MINTR: |
533 | switch (val & MINTR_RST_MASK) { | |
f930d07e BS |
534 | case 0: |
535 | default: | |
536 | break; | |
12abac85 | 537 | case MINTR_RST_B: |
b4ed08e0 | 538 | escc_reset_chn(&serial->chn[0]); |
f930d07e | 539 | return; |
12abac85 | 540 | case MINTR_RST_A: |
b4ed08e0 | 541 | escc_reset_chn(&serial->chn[1]); |
f930d07e | 542 | return; |
12abac85 | 543 | case MINTR_RST_ALL: |
81069b20 | 544 | escc_reset(DEVICE(serial)); |
f930d07e BS |
545 | return; |
546 | } | |
547 | break; | |
548 | default: | |
549 | break; | |
550 | } | |
551 | if (s->reg == 0) | |
552 | s->reg = newreg; | |
553 | else | |
554 | s->reg = 0; | |
555 | break; | |
12abac85 | 556 | case SERIAL_DATA: |
30c2f238 | 557 | trace_escc_mem_writeb_data(CHN_C(s), val); |
96c4f569 | 558 | s->tx = val; |
12abac85 | 559 | if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { // tx enabled |
30650701 | 560 | if (qemu_chr_fe_backend_connected(&s->chr)) { |
6ab3fc32 DB |
561 | /* XXX this blocks entire thread. Rewrite to use |
562 | * qemu_chr_fe_write and background I/O callbacks */ | |
5345fdb4 | 563 | qemu_chr_fe_write_all(&s->chr, &s->tx, 1); |
becdfa00 | 564 | } else if (s->type == kbd && !s->disabled) { |
f930d07e BS |
565 | handle_kbd_command(s, val); |
566 | } | |
567 | } | |
12abac85 BS |
568 | s->rregs[R_STATUS] |= STATUS_TXEMPTY; // Tx buffer empty |
569 | s->rregs[R_SPEC] |= SPEC_ALLSENT; // All sent | |
96c4f569 | 570 | set_txint(s); |
f930d07e | 571 | break; |
e80cfcfc | 572 | default: |
f930d07e | 573 | break; |
e80cfcfc FB |
574 | } |
575 | } | |
576 | ||
a8170e5e | 577 | static uint64_t escc_mem_read(void *opaque, hwaddr addr, |
23c5e4ca | 578 | unsigned size) |
e80cfcfc | 579 | { |
3cf63ff2 | 580 | ESCCState *serial = opaque; |
e80cfcfc FB |
581 | ChannelState *s; |
582 | uint32_t saddr; | |
583 | uint32_t ret; | |
584 | int channel; | |
585 | ||
b4ed08e0 BS |
586 | saddr = (addr >> serial->it_shift) & 1; |
587 | channel = (addr >> (serial->it_shift + 1)) & 1; | |
b3ceef24 | 588 | s = &serial->chn[channel]; |
e80cfcfc | 589 | switch (saddr) { |
12abac85 | 590 | case SERIAL_CTRL: |
30c2f238 | 591 | trace_escc_mem_readb_ctrl(CHN_C(s), s->reg, s->rregs[s->reg]); |
f930d07e BS |
592 | ret = s->rregs[s->reg]; |
593 | s->reg = 0; | |
594 | return ret; | |
12abac85 BS |
595 | case SERIAL_DATA: |
596 | s->rregs[R_STATUS] &= ~STATUS_RXAV; | |
ba3c64fb | 597 | clr_rxint(s); |
f930d07e BS |
598 | if (s->type == kbd || s->type == mouse) |
599 | ret = get_queue(s); | |
600 | else | |
601 | ret = s->rx; | |
30c2f238 | 602 | trace_escc_mem_readb_data(CHN_C(s), ret); |
fa394ed6 | 603 | qemu_chr_fe_accept_input(&s->chr); |
f930d07e | 604 | return ret; |
e80cfcfc | 605 | default: |
f930d07e | 606 | break; |
e80cfcfc FB |
607 | } |
608 | return 0; | |
609 | } | |
610 | ||
23c5e4ca AK |
611 | static const MemoryRegionOps escc_mem_ops = { |
612 | .read = escc_mem_read, | |
613 | .write = escc_mem_write, | |
614 | .endianness = DEVICE_NATIVE_ENDIAN, | |
615 | .valid = { | |
616 | .min_access_size = 1, | |
617 | .max_access_size = 1, | |
618 | }, | |
619 | }; | |
620 | ||
e80cfcfc FB |
621 | static int serial_can_receive(void *opaque) |
622 | { | |
623 | ChannelState *s = opaque; | |
e4a89056 FB |
624 | int ret; |
625 | ||
12abac85 BS |
626 | if (((s->wregs[W_RXCTRL] & RXCTRL_RXEN) == 0) // Rx not enabled |
627 | || ((s->rregs[R_STATUS] & STATUS_RXAV) == STATUS_RXAV)) | |
628 | // char already available | |
f930d07e | 629 | ret = 0; |
e80cfcfc | 630 | else |
f930d07e | 631 | ret = 1; |
e4a89056 | 632 | return ret; |
e80cfcfc FB |
633 | } |
634 | ||
635 | static void serial_receive_byte(ChannelState *s, int ch) | |
636 | { | |
30c2f238 | 637 | trace_escc_serial_receive_byte(CHN_C(s), ch); |
12abac85 | 638 | s->rregs[R_STATUS] |= STATUS_RXAV; |
e80cfcfc | 639 | s->rx = ch; |
ba3c64fb | 640 | set_rxint(s); |
e80cfcfc FB |
641 | } |
642 | ||
643 | static void serial_receive_break(ChannelState *s) | |
644 | { | |
12abac85 | 645 | s->rregs[R_STATUS] |= STATUS_BRK; |
b4ed08e0 | 646 | escc_update_irq(s); |
e80cfcfc FB |
647 | } |
648 | ||
649 | static void serial_receive1(void *opaque, const uint8_t *buf, int size) | |
650 | { | |
651 | ChannelState *s = opaque; | |
652 | serial_receive_byte(s, buf[0]); | |
653 | } | |
654 | ||
655 | static void serial_event(void *opaque, int event) | |
656 | { | |
657 | ChannelState *s = opaque; | |
658 | if (event == CHR_EVENT_BREAK) | |
659 | serial_receive_break(s); | |
660 | } | |
661 | ||
bdb78cae BS |
662 | static const VMStateDescription vmstate_escc_chn = { |
663 | .name ="escc_chn", | |
664 | .version_id = 2, | |
665 | .minimum_version_id = 1, | |
3aff6c2f | 666 | .fields = (VMStateField[]) { |
bdb78cae BS |
667 | VMSTATE_UINT32(vmstate_dummy, ChannelState), |
668 | VMSTATE_UINT32(reg, ChannelState), | |
669 | VMSTATE_UINT32(rxint, ChannelState), | |
670 | VMSTATE_UINT32(txint, ChannelState), | |
671 | VMSTATE_UINT32(rxint_under_svc, ChannelState), | |
672 | VMSTATE_UINT32(txint_under_svc, ChannelState), | |
673 | VMSTATE_UINT8(rx, ChannelState), | |
674 | VMSTATE_UINT8(tx, ChannelState), | |
675 | VMSTATE_BUFFER(wregs, ChannelState), | |
676 | VMSTATE_BUFFER(rregs, ChannelState), | |
677 | VMSTATE_END_OF_LIST() | |
e4a89056 | 678 | } |
bdb78cae | 679 | }; |
e80cfcfc | 680 | |
bdb78cae BS |
681 | static const VMStateDescription vmstate_escc = { |
682 | .name ="escc", | |
683 | .version_id = 2, | |
684 | .minimum_version_id = 1, | |
3aff6c2f | 685 | .fields = (VMStateField[]) { |
3cf63ff2 | 686 | VMSTATE_STRUCT_ARRAY(chn, ESCCState, 2, 2, vmstate_escc_chn, |
bdb78cae BS |
687 | ChannelState), |
688 | VMSTATE_END_OF_LIST() | |
689 | } | |
690 | }; | |
e80cfcfc | 691 | |
a8170e5e | 692 | MemoryRegion *escc_init(hwaddr base, qemu_irq irqA, qemu_irq irqB, |
0ec7b3e7 | 693 | Chardev *chrA, Chardev *chrB, |
aeeb69c7 | 694 | int clock, int it_shift) |
e80cfcfc | 695 | { |
6c319c82 BS |
696 | DeviceState *dev; |
697 | SysBusDevice *s; | |
3cf63ff2 | 698 | ESCCState *d; |
6c319c82 | 699 | |
81069b20 | 700 | dev = qdev_create(NULL, TYPE_ESCC); |
ee6847d1 GH |
701 | qdev_prop_set_uint32(dev, "disabled", 0); |
702 | qdev_prop_set_uint32(dev, "frequency", clock); | |
703 | qdev_prop_set_uint32(dev, "it_shift", it_shift); | |
bc19fcaa BS |
704 | qdev_prop_set_chr(dev, "chrB", chrB); |
705 | qdev_prop_set_chr(dev, "chrA", chrA); | |
ee6847d1 GH |
706 | qdev_prop_set_uint32(dev, "chnBtype", ser); |
707 | qdev_prop_set_uint32(dev, "chnAtype", ser); | |
e23a1b33 | 708 | qdev_init_nofail(dev); |
1356b98d | 709 | s = SYS_BUS_DEVICE(dev); |
e1a0e47f AJ |
710 | sysbus_connect_irq(s, 0, irqB); |
711 | sysbus_connect_irq(s, 1, irqA); | |
6c319c82 BS |
712 | if (base) { |
713 | sysbus_mmio_map(s, 0, base); | |
e80cfcfc | 714 | } |
6c319c82 | 715 | |
81069b20 | 716 | d = ESCC(s); |
23c5e4ca | 717 | return &d->mmio; |
e80cfcfc FB |
718 | } |
719 | ||
8be1f5c8 | 720 | |
65e7545e GH |
721 | static void sunkbd_handle_event(DeviceState *dev, QemuConsole *src, |
722 | InputEvent *evt) | |
e80cfcfc | 723 | { |
65e7545e GH |
724 | ChannelState *s = (ChannelState *)dev; |
725 | int qcode, keycode; | |
b5a1b443 | 726 | InputKeyEvent *key; |
65e7545e | 727 | |
568c73a4 | 728 | assert(evt->type == INPUT_EVENT_KIND_KEY); |
32bafa8f | 729 | key = evt->u.key.data; |
b5a1b443 | 730 | qcode = qemu_input_key_value_to_qcode(key->key); |
977c736f | 731 | trace_escc_sunkbd_event_in(qcode, QKeyCode_str(qcode), |
b5a1b443 | 732 | key->down); |
65e7545e GH |
733 | |
734 | if (qcode == Q_KEY_CODE_CAPS_LOCK) { | |
b5a1b443 | 735 | if (key->down) { |
65e7545e GH |
736 | s->caps_lock_mode ^= 1; |
737 | if (s->caps_lock_mode == 2) { | |
738 | return; /* Drop second press */ | |
739 | } | |
740 | } else { | |
741 | s->caps_lock_mode ^= 2; | |
742 | if (s->caps_lock_mode == 3) { | |
743 | return; /* Drop first release */ | |
744 | } | |
745 | } | |
43febf49 | 746 | } |
65e7545e GH |
747 | |
748 | if (qcode == Q_KEY_CODE_NUM_LOCK) { | |
b5a1b443 | 749 | if (key->down) { |
65e7545e GH |
750 | s->num_lock_mode ^= 1; |
751 | if (s->num_lock_mode == 2) { | |
752 | return; /* Drop second press */ | |
753 | } | |
754 | } else { | |
755 | s->num_lock_mode ^= 2; | |
756 | if (s->num_lock_mode == 3) { | |
757 | return; /* Drop first release */ | |
758 | } | |
759 | } | |
760 | } | |
761 | ||
e709a61a DB |
762 | if (qcode > qemu_input_map_qcode_to_sun_len) { |
763 | return; | |
764 | } | |
765 | ||
766 | keycode = qemu_input_map_qcode_to_sun[qcode]; | |
b5a1b443 | 767 | if (!key->down) { |
65e7545e | 768 | keycode |= 0x80; |
43febf49 | 769 | } |
65e7545e GH |
770 | trace_escc_sunkbd_event_out(keycode); |
771 | put_queue(s, keycode); | |
8be1f5c8 FB |
772 | } |
773 | ||
65e7545e GH |
774 | static QemuInputHandler sunkbd_handler = { |
775 | .name = "sun keyboard", | |
776 | .mask = INPUT_EVENT_MASK_KEY, | |
777 | .event = sunkbd_handle_event, | |
778 | }; | |
779 | ||
8be1f5c8 FB |
780 | static void handle_kbd_command(ChannelState *s, int val) |
781 | { | |
30c2f238 | 782 | trace_escc_kbd_command(val); |
43febf49 BS |
783 | if (s->led_mode) { // Ignore led byte |
784 | s->led_mode = 0; | |
785 | return; | |
786 | } | |
8be1f5c8 FB |
787 | switch (val) { |
788 | case 1: // Reset, return type code | |
67deb562 | 789 | clear_queue(s); |
f930d07e BS |
790 | put_queue(s, 0xff); |
791 | put_queue(s, 4); // Type 4 | |
792 | put_queue(s, 0x7f); | |
793 | break; | |
43febf49 BS |
794 | case 0xe: // Set leds |
795 | s->led_mode = 1; | |
796 | break; | |
8be1f5c8 | 797 | case 7: // Query layout |
67deb562 BS |
798 | case 0xf: |
799 | clear_queue(s); | |
f930d07e | 800 | put_queue(s, 0xfe); |
59e7a130 | 801 | put_queue(s, 0x21); /* en-us layout */ |
f930d07e | 802 | break; |
8be1f5c8 | 803 | default: |
f930d07e | 804 | break; |
8be1f5c8 | 805 | } |
e80cfcfc FB |
806 | } |
807 | ||
5fafdf24 | 808 | static void sunmouse_event(void *opaque, |
e80cfcfc FB |
809 | int dx, int dy, int dz, int buttons_state) |
810 | { | |
811 | ChannelState *s = opaque; | |
812 | int ch; | |
813 | ||
30c2f238 | 814 | trace_escc_sunmouse_event(dx, dy, buttons_state); |
715748fa FB |
815 | ch = 0x80 | 0x7; /* protocol start byte, no buttons pressed */ |
816 | ||
817 | if (buttons_state & MOUSE_EVENT_LBUTTON) | |
818 | ch ^= 0x4; | |
819 | if (buttons_state & MOUSE_EVENT_MBUTTON) | |
820 | ch ^= 0x2; | |
821 | if (buttons_state & MOUSE_EVENT_RBUTTON) | |
822 | ch ^= 0x1; | |
823 | ||
824 | put_queue(s, ch); | |
825 | ||
826 | ch = dx; | |
827 | ||
828 | if (ch > 127) | |
a0d98a71 | 829 | ch = 127; |
715748fa | 830 | else if (ch < -127) |
a0d98a71 | 831 | ch = -127; |
715748fa FB |
832 | |
833 | put_queue(s, ch & 0xff); | |
834 | ||
835 | ch = -dy; | |
836 | ||
837 | if (ch > 127) | |
084bd071 | 838 | ch = 127; |
715748fa | 839 | else if (ch < -127) |
084bd071 | 840 | ch = -127; |
715748fa FB |
841 | |
842 | put_queue(s, ch & 0xff); | |
843 | ||
844 | // MSC protocol specify two extra motion bytes | |
845 | ||
846 | put_queue(s, 0); | |
847 | put_queue(s, 0); | |
e80cfcfc FB |
848 | } |
849 | ||
a8170e5e | 850 | void slavio_serial_ms_kbd_init(hwaddr base, qemu_irq irq, |
b4ed08e0 | 851 | int disabled, int clock, int it_shift) |
e80cfcfc | 852 | { |
6c319c82 BS |
853 | DeviceState *dev; |
854 | SysBusDevice *s; | |
855 | ||
81069b20 | 856 | dev = qdev_create(NULL, TYPE_ESCC); |
ee6847d1 GH |
857 | qdev_prop_set_uint32(dev, "disabled", disabled); |
858 | qdev_prop_set_uint32(dev, "frequency", clock); | |
859 | qdev_prop_set_uint32(dev, "it_shift", it_shift); | |
bc19fcaa BS |
860 | qdev_prop_set_chr(dev, "chrB", NULL); |
861 | qdev_prop_set_chr(dev, "chrA", NULL); | |
ee6847d1 GH |
862 | qdev_prop_set_uint32(dev, "chnBtype", mouse); |
863 | qdev_prop_set_uint32(dev, "chnAtype", kbd); | |
e23a1b33 | 864 | qdev_init_nofail(dev); |
1356b98d | 865 | s = SYS_BUS_DEVICE(dev); |
6c319c82 BS |
866 | sysbus_connect_irq(s, 0, irq); |
867 | sysbus_connect_irq(s, 1, irq); | |
868 | sysbus_mmio_map(s, 0, base); | |
869 | } | |
b4ed08e0 | 870 | |
e7c91369 | 871 | static void escc_init1(Object *obj) |
6c319c82 | 872 | { |
e7c91369 XZ |
873 | ESCCState *s = ESCC(obj); |
874 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
6c319c82 | 875 | unsigned int i; |
ee6847d1 | 876 | |
8be1f5c8 | 877 | for (i = 0; i < 2; i++) { |
6c319c82 | 878 | sysbus_init_irq(dev, &s->chn[i].irq); |
f930d07e | 879 | s->chn[i].chn = 1 - i; |
8be1f5c8 FB |
880 | } |
881 | s->chn[0].otherchn = &s->chn[1]; | |
882 | s->chn[1].otherchn = &s->chn[0]; | |
e80cfcfc | 883 | |
750ecd44 | 884 | sysbus_init_mmio(dev, &s->mmio); |
e7c91369 XZ |
885 | } |
886 | ||
887 | static void escc_realize(DeviceState *dev, Error **errp) | |
888 | { | |
889 | ESCCState *s = ESCC(dev); | |
890 | unsigned int i; | |
891 | ||
4b3eec91 XZ |
892 | s->chn[0].disabled = s->disabled; |
893 | s->chn[1].disabled = s->disabled; | |
894 | ||
895 | memory_region_init_io(&s->mmio, OBJECT(dev), &escc_mem_ops, s, "escc", | |
896 | ESCC_SIZE << s->it_shift); | |
897 | ||
e7c91369 | 898 | for (i = 0; i < 2; i++) { |
30650701 | 899 | if (qemu_chr_fe_backend_connected(&s->chn[i].chr)) { |
4b3eec91 | 900 | s->chn[i].clock = s->frequency / 2; |
5345fdb4 | 901 | qemu_chr_fe_set_handlers(&s->chn[i].chr, serial_can_receive, |
81517ba3 | 902 | serial_receive1, serial_event, NULL, |
39ab61c6 | 903 | &s->chn[i], NULL, true); |
e7c91369 XZ |
904 | } |
905 | } | |
e80cfcfc | 906 | |
6c319c82 BS |
907 | if (s->chn[0].type == mouse) { |
908 | qemu_add_mouse_event_handler(sunmouse_event, &s->chn[0], 0, | |
909 | "QEMU Sun Mouse"); | |
910 | } | |
911 | if (s->chn[1].type == kbd) { | |
65e7545e GH |
912 | s->chn[1].hs = qemu_input_handler_register((DeviceState *)(&s->chn[1]), |
913 | &sunkbd_handler); | |
6c319c82 | 914 | } |
e80cfcfc | 915 | } |
6c319c82 | 916 | |
999e12bb | 917 | static Property escc_properties[] = { |
3cf63ff2 PB |
918 | DEFINE_PROP_UINT32("frequency", ESCCState, frequency, 0), |
919 | DEFINE_PROP_UINT32("it_shift", ESCCState, it_shift, 0), | |
920 | DEFINE_PROP_UINT32("disabled", ESCCState, disabled, 0), | |
921 | DEFINE_PROP_UINT32("chnBtype", ESCCState, chn[0].type, 0), | |
922 | DEFINE_PROP_UINT32("chnAtype", ESCCState, chn[1].type, 0), | |
923 | DEFINE_PROP_CHR("chrB", ESCCState, chn[0].chr), | |
924 | DEFINE_PROP_CHR("chrA", ESCCState, chn[1].chr), | |
999e12bb AL |
925 | DEFINE_PROP_END_OF_LIST(), |
926 | }; | |
927 | ||
928 | static void escc_class_init(ObjectClass *klass, void *data) | |
929 | { | |
39bffca2 | 930 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 931 | |
39bffca2 | 932 | dc->reset = escc_reset; |
e7c91369 | 933 | dc->realize = escc_realize; |
39bffca2 AL |
934 | dc->vmsd = &vmstate_escc; |
935 | dc->props = escc_properties; | |
f8d4c07c | 936 | set_bit(DEVICE_CATEGORY_INPUT, dc->categories); |
999e12bb AL |
937 | } |
938 | ||
8c43a6f0 | 939 | static const TypeInfo escc_info = { |
81069b20 | 940 | .name = TYPE_ESCC, |
39bffca2 | 941 | .parent = TYPE_SYS_BUS_DEVICE, |
3cf63ff2 | 942 | .instance_size = sizeof(ESCCState), |
e7c91369 | 943 | .instance_init = escc_init1, |
39bffca2 | 944 | .class_init = escc_class_init, |
6c319c82 BS |
945 | }; |
946 | ||
83f7d43a | 947 | static void escc_register_types(void) |
6c319c82 | 948 | { |
39bffca2 | 949 | type_register_static(&escc_info); |
6c319c82 BS |
950 | } |
951 | ||
83f7d43a | 952 | type_init(escc_register_types) |