[mirror_qemu.git] / hw / char / mcf_uart.c

/*
 * ColdFire UART emulation.
 *
 * Copyright (c) 2007 CodeSourcery.
 *
 * This code is licensed under the GPL
 */
#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/m68k/mcf.h"
#include "sysemu/char.h"
#include "exec/address-spaces.h"
#include "qapi/error.h"

typedef struct {
    MemoryRegion iomem;
    uint8_t mr[2];
    uint8_t sr;
    uint8_t isr;
    uint8_t imr;
    uint8_t bg1;
    uint8_t bg2;
    uint8_t fifo[4];
    uint8_t tb;
    int current_mr;
    int fifo_len;
    int tx_enabled;
    int rx_enabled;
    qemu_irq irq;
    CharBackend chr;
} mcf_uart_state;

/* UART Status Register bits.  */
#define MCF_UART_RxRDY  0x01
#define MCF_UART_FFULL  0x02
#define MCF_UART_TxRDY  0x04
#define MCF_UART_TxEMP  0x08
#define MCF_UART_OE     0x10
#define MCF_UART_PE     0x20
#define MCF_UART_FE     0x40
#define MCF_UART_RB     0x80

/* Interrupt flags.  */
#define MCF_UART_TxINT  0x01
#define MCF_UART_RxINT  0x02
#define MCF_UART_DBINT  0x04
#define MCF_UART_COSINT 0x80

/* UMR1 flags.  */
#define MCF_UART_BC0    0x01
#define MCF_UART_BC1    0x02
#define MCF_UART_PT     0x04
#define MCF_UART_PM0    0x08
#define MCF_UART_PM1    0x10
#define MCF_UART_ERR    0x20
#define MCF_UART_RxIRQ  0x40
#define MCF_UART_RxRTS  0x80

static void mcf_uart_update(mcf_uart_state *s)
{
    s->isr &= ~(MCF_UART_TxINT | MCF_UART_RxINT);
    if (s->sr & MCF_UART_TxRDY)
        s->isr |= MCF_UART_TxINT;
    if ((s->sr & ((s->mr[0] & MCF_UART_RxIRQ)
                  ? MCF_UART_FFULL : MCF_UART_RxRDY)) != 0)
        s->isr |= MCF_UART_RxINT;

    qemu_set_irq(s->irq, (s->isr & s->imr) != 0);
}

uint64_t mcf_uart_read(void *opaque, hwaddr addr,
                       unsigned size)
{
    mcf_uart_state *s = (mcf_uart_state *)opaque;
    switch (addr & 0x3f) {
    case 0x00:
        return s->mr[s->current_mr];
    case 0x04:
        return s->sr;
    case 0x0c:
        {
            uint8_t val;
            int i;

            if (s->fifo_len == 0)
                return 0;

            val = s->fifo[0];
            s->fifo_len--;
            for (i = 0; i < s->fifo_len; i++)
                s->fifo[i] = s->fifo[i + 1];
            s->sr &= ~MCF_UART_FFULL;
            if (s->fifo_len == 0)
                s->sr &= ~MCF_UART_RxRDY;
            mcf_uart_update(s);
            qemu_chr_fe_accept_input(&s->chr);
            return val;
        }
    case 0x10:
        /* TODO: Implement IPCR.  */
        return 0;
    case 0x14:
        return s->isr;
    case 0x18:
        return s->bg1;
    case 0x1c:
        return s->bg2;
    default:
        return 0;
    }
}

/* Update TxRDY flag and set data if present and enabled.  */
static void mcf_uart_do_tx(mcf_uart_state *s)
{
    if (s->tx_enabled && (s->sr & MCF_UART_TxEMP) == 0) {
        if (s->chr.chr) {
            /* XXX this blocks entire thread. Rewrite to use
             * qemu_chr_fe_write and background I/O callbacks */
            qemu_chr_fe_write_all(&s->chr, (unsigned char *)&s->tb, 1);
        }
        s->sr |= MCF_UART_TxEMP;
    }
    if (s->tx_enabled) {
        s->sr |= MCF_UART_TxRDY;
    } else {
        s->sr &= ~MCF_UART_TxRDY;
    }
}

static void mcf_do_command(mcf_uart_state *s, uint8_t cmd)
{
    /* Misc command.  */
    switch ((cmd >> 4) & 7) {
    case 0: /* No-op.  */
        break;
    case 1: /* Reset mode register pointer.  */
        s->current_mr = 0;
        break;
    case 2: /* Reset receiver.  */
        s->rx_enabled = 0;
        s->fifo_len = 0;
        s->sr &= ~(MCF_UART_RxRDY | MCF_UART_FFULL);
        break;
    case 3: /* Reset transmitter.  */
        s->tx_enabled = 0;
        s->sr |= MCF_UART_TxEMP;
        s->sr &= ~MCF_UART_TxRDY;
        break;
    case 4: /* Reset error status.  */
        break;
    case 5: /* Reset break-change interrupt.  */
        s->isr &= ~MCF_UART_DBINT;
        break;
    case 6: /* Start break.  */
    case 7: /* Stop break.  */
        break;
    }

    /* Transmitter command.  */
    switch ((cmd >> 2) & 3) {
    case 0: /* No-op.  */
        break;
    case 1: /* Enable.  */
        s->tx_enabled = 1;
        mcf_uart_do_tx(s);
        break;
    case 2: /* Disable.  */
        s->tx_enabled = 0;
        mcf_uart_do_tx(s);
        break;
    case 3: /* Reserved.  */
        fprintf(stderr, "mcf_uart: Bad TX command\n");
        break;
    }

    /* Receiver command.  */
    switch (cmd & 3) {
    case 0: /* No-op.  */
        break;
    case 1: /* Enable.  */
        s->rx_enabled = 1;
        break;
    case 2:
        s->rx_enabled = 0;
        break;
    case 3: /* Reserved.  */
        fprintf(stderr, "mcf_uart: Bad RX command\n");
        break;
    }
}

void mcf_uart_write(void *opaque, hwaddr addr,
                    uint64_t val, unsigned size)
{
    mcf_uart_state *s = (mcf_uart_state *)opaque;
    switch (addr & 0x3f) {
    case 0x00:
        s->mr[s->current_mr] = val;
        s->current_mr = 1;
        break;
    case 0x04:
        /* CSR is ignored.  */
        break;
    case 0x08: /* Command Register.  */
        mcf_do_command(s, val);
        break;
    case 0x0c: /* Transmit Buffer.  */
        s->sr &= ~MCF_UART_TxEMP;
        s->tb = val;
        mcf_uart_do_tx(s);
        break;
    case 0x10:
        /* ACR is ignored.  */
        break;
    case 0x14:
        s->imr = val;
        break;
    default:
        break;
    }
    mcf_uart_update(s);
}

static void mcf_uart_reset(mcf_uart_state *s)
{
    s->fifo_len = 0;
    s->mr[0] = 0;
    s->mr[1] = 0;
    s->sr = MCF_UART_TxEMP;
    s->tx_enabled = 0;
    s->rx_enabled = 0;
    s->isr = 0;
    s->imr = 0;
}

static void mcf_uart_push_byte(mcf_uart_state *s, uint8_t data)
{
    /* Break events overwrite the last byte if the fifo is full.  */
    if (s->fifo_len == 4)
        s->fifo_len--;

    s->fifo[s->fifo_len] = data;
    s->fifo_len++;
    s->sr |= MCF_UART_RxRDY;
    if (s->fifo_len == 4)
        s->sr |= MCF_UART_FFULL;

    mcf_uart_update(s);
}

static void mcf_uart_event(void *opaque, int event)
{
    mcf_uart_state *s = (mcf_uart_state *)opaque;

    switch (event) {
    case CHR_EVENT_BREAK:
        s->isr |= MCF_UART_DBINT;
        mcf_uart_push_byte(s, 0);
        break;
    default:
        break;
    }
}

static int mcf_uart_can_receive(void *opaque)
{
    mcf_uart_state *s = (mcf_uart_state *)opaque;

    return s->rx_enabled && (s->sr & MCF_UART_FFULL) == 0;
}

static void mcf_uart_receive(void *opaque, const uint8_t *buf, int size)
{
    mcf_uart_state *s = (mcf_uart_state *)opaque;

    mcf_uart_push_byte(s, buf[0]);
}

void *mcf_uart_init(qemu_irq irq, CharDriverState *chr)
{
    mcf_uart_state *s;

    s = g_malloc0(sizeof(mcf_uart_state));
    s->irq = irq;
    if (chr) {
        qemu_chr_fe_init(&s->chr, chr, &error_abort);
        qemu_chr_fe_claim_no_fail(chr);
        qemu_chr_fe_set_handlers(&s->chr, mcf_uart_can_receive,
                                 mcf_uart_receive, mcf_uart_event, s, NULL);
    }
    mcf_uart_reset(s);
    return s;
}

static const MemoryRegionOps mcf_uart_ops = {
    .read = mcf_uart_read,
    .write = mcf_uart_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

void mcf_uart_mm_init(MemoryRegion *sysmem,
                      hwaddr base,
                      qemu_irq irq,
                      CharDriverState *chr)
{
    mcf_uart_state *s;

    s = mcf_uart_init(irq, chr);
    memory_region_init_io(&s->iomem, NULL, &mcf_uart_ops, s, "uart", 0x40);
    memory_region_add_subregion(sysmem, base, &s->iomem);
}
Commit	Line	Data
5fafdf24	1	/*
20dcee94 PB	2	* ColdFire UART emulation.
	3	*
	4	* Copyright (c) 2007 CodeSourcery.
	5	*
8e31bf38	6	* This code is licensed under the GPL
20dcee94	7	*/
0430891c	8	#include "qemu/osdep.h"
83c9f4ca	9	#include "hw/hw.h"
0d09e41a	10	#include "hw/m68k/mcf.h"
dccfcd0e	11	#include "sysemu/char.h"
022c62cb	12	#include "exec/address-spaces.h"
32a6ebec	13	#include "qapi/error.h"
20dcee94 PB	14
20dcee94 PB	15	typedef struct {
aa6e4986	16	MemoryRegion iomem;
20dcee94 PB	17	uint8_t mr[2];
	18	uint8_t sr;
	19	uint8_t isr;
	20	uint8_t imr;
	21	uint8_t bg1;
	22	uint8_t bg2;
	23	uint8_t fifo[4];
	24	uint8_t tb;
	25	int current_mr;
	26	int fifo_len;
	27	int tx_enabled;
	28	int rx_enabled;
	29	qemu_irq irq;
32a6ebec	30	CharBackend chr;
20dcee94 PB	31	} mcf_uart_state;
	32
	33	/* UART Status Register bits. */
	34	#define MCF_UART_RxRDY 0x01
	35	#define MCF_UART_FFULL 0x02
	36	#define MCF_UART_TxRDY 0x04
	37	#define MCF_UART_TxEMP 0x08
	38	#define MCF_UART_OE 0x10
	39	#define MCF_UART_PE 0x20
	40	#define MCF_UART_FE 0x40
	41	#define MCF_UART_RB 0x80
	42
	43	/* Interrupt flags. */
	44	#define MCF_UART_TxINT 0x01
	45	#define MCF_UART_RxINT 0x02
	46	#define MCF_UART_DBINT 0x04
	47	#define MCF_UART_COSINT 0x80
	48
	49	/* UMR1 flags. */
	50	#define MCF_UART_BC0 0x01
	51	#define MCF_UART_BC1 0x02
	52	#define MCF_UART_PT 0x04
	53	#define MCF_UART_PM0 0x08
	54	#define MCF_UART_PM1 0x10
	55	#define MCF_UART_ERR 0x20
	56	#define MCF_UART_RxIRQ 0x40
	57	#define MCF_UART_RxRTS 0x80
	58
	59	static void mcf_uart_update(mcf_uart_state *s)
	60	{
	61	s->isr &= ~(MCF_UART_TxINT \| MCF_UART_RxINT);
	62	if (s->sr & MCF_UART_TxRDY)
	63	s->isr \|= MCF_UART_TxINT;
	64	if ((s->sr & ((s->mr[0] & MCF_UART_RxIRQ)
	65	? MCF_UART_FFULL : MCF_UART_RxRDY)) != 0)
	66	s->isr \|= MCF_UART_RxINT;
	67
	68	qemu_set_irq(s->irq, (s->isr & s->imr) != 0);
	69	}
	70
a8170e5e	71	uint64_t mcf_uart_read(void *opaque, hwaddr addr,
aa6e4986	72	unsigned size)
20dcee94 PB	73	{
	74	mcf_uart_state s = (mcf_uart_state )opaque;
	75	switch (addr & 0x3f) {
	76	case 0x00:
	77	return s->mr[s->current_mr];
	78	case 0x04:
	79	return s->sr;
	80	case 0x0c:
	81	{
	82	uint8_t val;
	83	int i;
	84
	85	if (s->fifo_len == 0)
	86	return 0;
	87
	88	val = s->fifo[0];
	89	s->fifo_len--;
	90	for (i = 0; i < s->fifo_len; i++)
	91	s->fifo[i] = s->fifo[i + 1];
	92	s->sr &= ~MCF_UART_FFULL;
	93	if (s->fifo_len == 0)
	94	s->sr &= ~MCF_UART_RxRDY;
	95	mcf_uart_update(s);
5345fdb4	96	qemu_chr_fe_accept_input(&s->chr);
20dcee94 PB	97	return val;
	98	}
	99	case 0x10:
	100	/* TODO: Implement IPCR. */
	101	return 0;
	102	case 0x14:
	103	return s->isr;
	104	case 0x18:
	105	return s->bg1;
	106	case 0x1c:
	107	return s->bg2;
	108	default:
	109	return 0;
	110	}
	111	}
	112
	113	/* Update TxRDY flag and set data if present and enabled. */
	114	static void mcf_uart_do_tx(mcf_uart_state *s)
	115	{
	116	if (s->tx_enabled && (s->sr & MCF_UART_TxEMP) == 0) {
32a6ebec	117	if (s->chr.chr) {
6ab3fc32 DB	118	/* XXX this blocks entire thread. Rewrite to use
6ab3fc32 DB	119	* qemu_chr_fe_write and background I/O callbacks */
5345fdb4	120	qemu_chr_fe_write_all(&s->chr, (unsigned char *)&s->tb, 1);
32a6ebec	121	}
20dcee94 PB	122	s->sr \|= MCF_UART_TxEMP;
	123	}
	124	if (s->tx_enabled) {
	125	s->sr \|= MCF_UART_TxRDY;
	126	} else {
	127	s->sr &= ~MCF_UART_TxRDY;
	128	}
	129	}
	130
	131	static void mcf_do_command(mcf_uart_state *s, uint8_t cmd)
	132	{
	133	/* Misc command. */
491ffc1f	134	switch ((cmd >> 4) & 7) {
20dcee94 PB	135	case 0: /* No-op. */
	136	break;
	137	case 1: /* Reset mode register pointer. */
	138	s->current_mr = 0;
	139	break;
	140	case 2: /* Reset receiver. */
	141	s->rx_enabled = 0;
	142	s->fifo_len = 0;
	143	s->sr &= ~(MCF_UART_RxRDY \| MCF_UART_FFULL);
	144	break;
	145	case 3: /* Reset transmitter. */
	146	s->tx_enabled = 0;
	147	s->sr \|= MCF_UART_TxEMP;
	148	s->sr &= ~MCF_UART_TxRDY;
	149	break;
	150	case 4: /* Reset error status. */
	151	break;
	152	case 5: /* Reset break-change interrupt. */
	153	s->isr &= ~MCF_UART_DBINT;
	154	break;
	155	case 6: /* Start break. */
	156	case 7: /* Stop break. */
	157	break;
	158	}
	159
	160	/* Transmitter command. */
	161	switch ((cmd >> 2) & 3) {
	162	case 0: /* No-op. */
	163	break;
	164	case 1: /* Enable. */
	165	s->tx_enabled = 1;
	166	mcf_uart_do_tx(s);
	167	break;
	168	case 2: /* Disable. */
	169	s->tx_enabled = 0;
	170	mcf_uart_do_tx(s);
	171	break;
	172	case 3: /* Reserved. */
	173	fprintf(stderr, "mcf_uart: Bad TX command\n");
	174	break;
	175	}
	176
	177	/* Receiver command. */
	178	switch (cmd & 3) {
	179	case 0: /* No-op. */
	180	break;
	181	case 1: /* Enable. */
	182	s->rx_enabled = 1;
	183	break;
	184	case 2:
	185	s->rx_enabled = 0;
	186	break;
	187	case 3: /* Reserved. */
	188	fprintf(stderr, "mcf_uart: Bad RX command\n");
	189	break;
	190	}
	191	}
	192
a8170e5e	193	void mcf_uart_write(void *opaque, hwaddr addr,
aa6e4986	194	uint64_t val, unsigned size)
20dcee94 PB	195	{
	196	mcf_uart_state s = (mcf_uart_state )opaque;
	197	switch (addr & 0x3f) {
	198	case 0x00:
	199	s->mr[s->current_mr] = val;
	200	s->current_mr = 1;
	201	break;
	202	case 0x04:
	203	/* CSR is ignored. */
	204	break;
	205	case 0x08: /* Command Register. */
	206	mcf_do_command(s, val);
	207	break;
	208	case 0x0c: /* Transmit Buffer. */
	209	s->sr &= ~MCF_UART_TxEMP;
	210	s->tb = val;
	211	mcf_uart_do_tx(s);
	212	break;
	213	case 0x10:
	214	/* ACR is ignored. */
	215	break;
	216	case 0x14:
	217	s->imr = val;
	218	break;
	219	default:
	220	break;
	221	}
	222	mcf_uart_update(s);
	223	}
	224
	225	static void mcf_uart_reset(mcf_uart_state *s)
	226	{
	227	s->fifo_len = 0;
	228	s->mr[0] = 0;
	229	s->mr[1] = 0;
	230	s->sr = MCF_UART_TxEMP;
	231	s->tx_enabled = 0;
	232	s->rx_enabled = 0;
	233	s->isr = 0;
	234	s->imr = 0;
	235	}
	236
	237	static void mcf_uart_push_byte(mcf_uart_state *s, uint8_t data)
	238	{
	239	/* Break events overwrite the last byte if the fifo is full. */
	240	if (s->fifo_len == 4)
	241	s->fifo_len--;
	242
	243	s->fifo[s->fifo_len] = data;
	244	s->fifo_len++;
	245	s->sr \|= MCF_UART_RxRDY;
	246	if (s->fifo_len == 4)
	247	s->sr \|= MCF_UART_FFULL;
	248
	249	mcf_uart_update(s);
	250	}
	251
	252	static void mcf_uart_event(void *opaque, int event)
	253	{
	254	mcf_uart_state s = (mcf_uart_state )opaque;
	255
	256	switch (event) {
	257	case CHR_EVENT_BREAK:
	258	s->isr \|= MCF_UART_DBINT;
259	mcf_uart_push_byte(s, 0);
260	break;
261	default:
262	break;
263	}
264	}
265
266	static int mcf_uart_can_receive(void *opaque)
267	{
268	mcf_uart_state s = (mcf_uart_state )opaque;
269
270	return s->rx_enabled && (s->sr & MCF_UART_FFULL) == 0;
271	}
272
273	static void mcf_uart_receive(void opaque, const uint8_t buf, int size)
274	{
275	mcf_uart_state s = (mcf_uart_state )opaque;
276
277	mcf_uart_push_byte(s, buf[0]);
278	}
279
280	void mcf_uart_init(qemu_irq irq, CharDriverState chr)
281	{
282	mcf_uart_state *s;
283
7267c094	284	s = g_malloc0(sizeof(mcf_uart_state));
20dcee94 PB	285	s->irq = irq;
20dcee94 PB	286	if (chr) {
32a6ebec	287	qemu_chr_fe_init(&s->chr, chr, &error_abort);
456d6069	288	qemu_chr_fe_claim_no_fail(chr);
5345fdb4 MAL	289	qemu_chr_fe_set_handlers(&s->chr, mcf_uart_can_receive,
5345fdb4 MAL	290	mcf_uart_receive, mcf_uart_event, s, NULL);
20dcee94 PB	291	}
	292	mcf_uart_reset(s);
	293	return s;
	294	}
	295
aa6e4986 BC	296	static const MemoryRegionOps mcf_uart_ops = {
	297	.read = mcf_uart_read,
	298	.write = mcf_uart_write,
	299	.endianness = DEVICE_NATIVE_ENDIAN,
20dcee94 PB	300	};
20dcee94 PB	301
aa6e4986	302	void mcf_uart_mm_init(MemoryRegion *sysmem,
a8170e5e	303	hwaddr base,
aa6e4986	304	qemu_irq irq,
20dcee94 PB	305	CharDriverState *chr)
	306	{
	307	mcf_uart_state *s;
20dcee94 PB	308
20dcee94 PB	309	s = mcf_uart_init(irq, chr);
2c9b15ca	310	memory_region_init_io(&s->iomem, NULL, &mcf_uart_ops, s, "uart", 0x40);
aa6e4986	311	memory_region_add_subregion(sysmem, base, &s->iomem);
20dcee94	312	}