[mirror_qemu.git] / hw / char / mcf_uart.c

/*
 * ColdFire UART emulation.
 *
 * Copyright (c) 2007 CodeSourcery.
 *
 * This code is licensed under the GPL
 */

#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/sysbus.h"
#include "qemu/module.h"
#include "qapi/error.h"
#include "hw/m68k/mcf.h"
#include "hw/qdev-properties.h"
#include "chardev/char-fe.h"
#include "qom/object.h"

struct mcf_uart_state {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    uint8_t mr[2];
    uint8_t sr;
    uint8_t isr;
    uint8_t imr;
    uint8_t bg1;
    uint8_t bg2;
    uint8_t fifo[4];
    uint8_t tb;
    int current_mr;
    int fifo_len;
    int tx_enabled;
    int rx_enabled;
    qemu_irq irq;
    CharBackend chr;
};
typedef struct mcf_uart_state mcf_uart_state;

#define TYPE_MCF_UART "mcf-uart"
DECLARE_INSTANCE_CHECKER(mcf_uart_state, MCF_UART,
                         TYPE_MCF_UART)

/* UART Status Register bits.  */
#define MCF_UART_RxRDY  0x01
#define MCF_UART_FFULL  0x02
#define MCF_UART_TxRDY  0x04
#define MCF_UART_TxEMP  0x08
#define MCF_UART_OE     0x10
#define MCF_UART_PE     0x20
#define MCF_UART_FE     0x40
#define MCF_UART_RB     0x80

/* Interrupt flags.  */
#define MCF_UART_TxINT  0x01
#define MCF_UART_RxINT  0x02
#define MCF_UART_DBINT  0x04
#define MCF_UART_COSINT 0x80

/* UMR1 flags.  */
#define MCF_UART_BC0    0x01
#define MCF_UART_BC1    0x02
#define MCF_UART_PT     0x04
#define MCF_UART_PM0    0x08
#define MCF_UART_PM1    0x10
#define MCF_UART_ERR    0x20
#define MCF_UART_RxIRQ  0x40
#define MCF_UART_RxRTS  0x80

static void mcf_uart_update(mcf_uart_state *s)
{
    s->isr &= ~(MCF_UART_TxINT | MCF_UART_RxINT);
    if (s->sr & MCF_UART_TxRDY)
        s->isr |= MCF_UART_TxINT;
    if ((s->sr & ((s->mr[0] & MCF_UART_RxIRQ)
                  ? MCF_UART_FFULL : MCF_UART_RxRDY)) != 0)
        s->isr |= MCF_UART_RxINT;

    qemu_set_irq(s->irq, (s->isr & s->imr) != 0);
}

uint64_t mcf_uart_read(void *opaque, hwaddr addr,
                       unsigned size)
{
    mcf_uart_state *s = (mcf_uart_state *)opaque;
    switch (addr & 0x3f) {
    case 0x00:
        return s->mr[s->current_mr];
    case 0x04:
        return s->sr;
    case 0x0c:
        {
            uint8_t val;
            int i;

            if (s->fifo_len == 0)
                return 0;

            val = s->fifo[0];
            s->fifo_len--;
            for (i = 0; i < s->fifo_len; i++)
                s->fifo[i] = s->fifo[i + 1];
            s->sr &= ~MCF_UART_FFULL;
            if (s->fifo_len == 0)
                s->sr &= ~MCF_UART_RxRDY;
            mcf_uart_update(s);
            qemu_chr_fe_accept_input(&s->chr);
            return val;
        }
    case 0x10:
        /* TODO: Implement IPCR.  */
        return 0;
    case 0x14:
        return s->isr;
    case 0x18:
        return s->bg1;
    case 0x1c:
        return s->bg2;
    default:
        return 0;
    }
}

/* Update TxRDY flag and set data if present and enabled.  */
static void mcf_uart_do_tx(mcf_uart_state *s)
{
    if (s->tx_enabled && (s->sr & MCF_UART_TxEMP) == 0) {
        /* XXX this blocks entire thread. Rewrite to use
         * qemu_chr_fe_write and background I/O callbacks */
        qemu_chr_fe_write_all(&s->chr, (unsigned char *)&s->tb, 1);
        s->sr |= MCF_UART_TxEMP;
    }
    if (s->tx_enabled) {
        s->sr |= MCF_UART_TxRDY;
    } else {
        s->sr &= ~MCF_UART_TxRDY;
    }
}

static void mcf_do_command(mcf_uart_state *s, uint8_t cmd)
{
    /* Misc command.  */
    switch ((cmd >> 4) & 7) {
    case 0: /* No-op.  */
        break;
    case 1: /* Reset mode register pointer.  */
        s->current_mr = 0;
        break;
    case 2: /* Reset receiver.  */
        s->rx_enabled = 0;
        s->fifo_len = 0;
        s->sr &= ~(MCF_UART_RxRDY | MCF_UART_FFULL);
        break;
    case 3: /* Reset transmitter.  */
        s->tx_enabled = 0;
        s->sr |= MCF_UART_TxEMP;
        s->sr &= ~MCF_UART_TxRDY;
        break;
    case 4: /* Reset error status.  */
        break;
    case 5: /* Reset break-change interrupt.  */
        s->isr &= ~MCF_UART_DBINT;
        break;
    case 6: /* Start break.  */
    case 7: /* Stop break.  */
        break;
    }

    /* Transmitter command.  */
    switch ((cmd >> 2) & 3) {
    case 0: /* No-op.  */
        break;
    case 1: /* Enable.  */
        s->tx_enabled = 1;
        mcf_uart_do_tx(s);
        break;
    case 2: /* Disable.  */
        s->tx_enabled = 0;
        mcf_uart_do_tx(s);
        break;
    case 3: /* Reserved.  */
        fprintf(stderr, "mcf_uart: Bad TX command\n");
        break;
    }

    /* Receiver command.  */
    switch (cmd & 3) {
    case 0: /* No-op.  */
        break;
    case 1: /* Enable.  */
        s->rx_enabled = 1;
        break;
    case 2:
        s->rx_enabled = 0;
        break;
    case 3: /* Reserved.  */
        fprintf(stderr, "mcf_uart: Bad RX command\n");
        break;
    }
}

void mcf_uart_write(void *opaque, hwaddr addr,
                    uint64_t val, unsigned size)
{
    mcf_uart_state *s = (mcf_uart_state *)opaque;
    switch (addr & 0x3f) {
    case 0x00:
        s->mr[s->current_mr] = val;
        s->current_mr = 1;
        break;
    case 0x04:
        /* CSR is ignored.  */
        break;
    case 0x08: /* Command Register.  */
        mcf_do_command(s, val);
        break;
    case 0x0c: /* Transmit Buffer.  */
        s->sr &= ~MCF_UART_TxEMP;
        s->tb = val;
        mcf_uart_do_tx(s);
        break;
    case 0x10:
        /* ACR is ignored.  */
        break;
    case 0x14:
        s->imr = val;
        break;
    default:
        break;
    }
    mcf_uart_update(s);
}

static void mcf_uart_reset(DeviceState *dev)
{
    mcf_uart_state *s = MCF_UART(dev);

    s->fifo_len = 0;
    s->mr[0] = 0;
    s->mr[1] = 0;
    s->sr = MCF_UART_TxEMP;
    s->tx_enabled = 0;
    s->rx_enabled = 0;
    s->isr = 0;
    s->imr = 0;
}

static void mcf_uart_push_byte(mcf_uart_state *s, uint8_t data)
{
    /* Break events overwrite the last byte if the fifo is full.  */
    if (s->fifo_len == 4)
        s->fifo_len--;

    s->fifo[s->fifo_len] = data;
    s->fifo_len++;
    s->sr |= MCF_UART_RxRDY;
    if (s->fifo_len == 4)
        s->sr |= MCF_UART_FFULL;

    mcf_uart_update(s);
}

static void mcf_uart_event(void *opaque, QEMUChrEvent event)
{
    mcf_uart_state *s = (mcf_uart_state *)opaque;

    switch (event) {
    case CHR_EVENT_BREAK:
        s->isr |= MCF_UART_DBINT;
        mcf_uart_push_byte(s, 0);
        break;
    default:
        break;
    }
}

static int mcf_uart_can_receive(void *opaque)
{
    mcf_uart_state *s = (mcf_uart_state *)opaque;

    return s->rx_enabled && (s->sr & MCF_UART_FFULL) == 0;
}

static void mcf_uart_receive(void *opaque, const uint8_t *buf, int size)
{
    mcf_uart_state *s = (mcf_uart_state *)opaque;

    mcf_uart_push_byte(s, buf[0]);
}

static const MemoryRegionOps mcf_uart_ops = {
    .read = mcf_uart_read,
    .write = mcf_uart_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void mcf_uart_instance_init(Object *obj)
{
    SysBusDevice *dev = SYS_BUS_DEVICE(obj);
    mcf_uart_state *s = MCF_UART(dev);

    memory_region_init_io(&s->iomem, obj, &mcf_uart_ops, s, "uart", 0x40);
    sysbus_init_mmio(dev, &s->iomem);

    sysbus_init_irq(dev, &s->irq);
}

static void mcf_uart_realize(DeviceState *dev, Error **errp)
{
    mcf_uart_state *s = MCF_UART(dev);

    qemu_chr_fe_set_handlers(&s->chr, mcf_uart_can_receive, mcf_uart_receive,
                             mcf_uart_event, NULL, s, NULL, true);
}

static Property mcf_uart_properties[] = {
    DEFINE_PROP_CHR("chardev", mcf_uart_state, chr),
    DEFINE_PROP_END_OF_LIST(),
};

static void mcf_uart_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize = mcf_uart_realize;
    dc->reset = mcf_uart_reset;
    device_class_set_props(dc, mcf_uart_properties);
    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}

static const TypeInfo mcf_uart_info = {
    .name          = TYPE_MCF_UART,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(mcf_uart_state),
    .instance_init = mcf_uart_instance_init,
    .class_init    = mcf_uart_class_init,
};

static void mcf_uart_register(void)
{
    type_register_static(&mcf_uart_info);
}

type_init(mcf_uart_register)

void *mcf_uart_init(qemu_irq irq, Chardev *chrdrv)
{
    DeviceState  *dev;

    dev = qdev_new(TYPE_MCF_UART);
    if (chrdrv) {
        qdev_prop_set_chr(dev, "chardev", chrdrv);
    }
    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);

    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);

    return dev;
}

void mcf_uart_mm_init(hwaddr base, qemu_irq irq, Chardev *chrdrv)
{
    DeviceState  *dev;

    dev = mcf_uart_init(irq, chrdrv);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
}
Commit	Line	Data
5fafdf24	1	/*
20dcee94 PB	2	* ColdFire UART emulation.
	3	*
	4	* Copyright (c) 2007 CodeSourcery.
	5	*
8e31bf38	6	* This code is licensed under the GPL
20dcee94	7	*/
0b8fa32f	8
0430891c	9	#include "qemu/osdep.h"
64552b6b	10	#include "hw/irq.h"
d9ff1d35	11	#include "hw/sysbus.h"
0b8fa32f	12	#include "qemu/module.h"
3e80f690	13	#include "qapi/error.h"
0d09e41a	14	#include "hw/m68k/mcf.h"
a27bd6c7	15	#include "hw/qdev-properties.h"
4d43a603	16	#include "chardev/char-fe.h"
db1015e9	17	#include "qom/object.h"
20dcee94	18
db1015e9	19	struct mcf_uart_state {
d9ff1d35 TH	20	SysBusDevice parent_obj;
d9ff1d35 TH	21
aa6e4986	22	MemoryRegion iomem;
20dcee94 PB	23	uint8_t mr[2];
	24	uint8_t sr;
	25	uint8_t isr;
	26	uint8_t imr;
	27	uint8_t bg1;
	28	uint8_t bg2;
	29	uint8_t fifo[4];
	30	uint8_t tb;
	31	int current_mr;
	32	int fifo_len;
	33	int tx_enabled;
	34	int rx_enabled;
	35	qemu_irq irq;
32a6ebec	36	CharBackend chr;
db1015e9 EH	37	};
db1015e9 EH	38	typedef struct mcf_uart_state mcf_uart_state;
20dcee94	39
d9ff1d35	40	#define TYPE_MCF_UART "mcf-uart"
8110fa1d EH	41	DECLARE_INSTANCE_CHECKER(mcf_uart_state, MCF_UART,
8110fa1d EH	42	TYPE_MCF_UART)
d9ff1d35	43
20dcee94 PB	44	/* UART Status Register bits. */
	45	#define MCF_UART_RxRDY 0x01
	46	#define MCF_UART_FFULL 0x02
	47	#define MCF_UART_TxRDY 0x04
	48	#define MCF_UART_TxEMP 0x08
	49	#define MCF_UART_OE 0x10
	50	#define MCF_UART_PE 0x20
	51	#define MCF_UART_FE 0x40
	52	#define MCF_UART_RB 0x80
	53
	54	/* Interrupt flags. */
	55	#define MCF_UART_TxINT 0x01
	56	#define MCF_UART_RxINT 0x02
	57	#define MCF_UART_DBINT 0x04
	58	#define MCF_UART_COSINT 0x80
	59
	60	/* UMR1 flags. */
	61	#define MCF_UART_BC0 0x01
	62	#define MCF_UART_BC1 0x02
	63	#define MCF_UART_PT 0x04
	64	#define MCF_UART_PM0 0x08
	65	#define MCF_UART_PM1 0x10
	66	#define MCF_UART_ERR 0x20
	67	#define MCF_UART_RxIRQ 0x40
	68	#define MCF_UART_RxRTS 0x80
	69
	70	static void mcf_uart_update(mcf_uart_state *s)
	71	{
	72	s->isr &= ~(MCF_UART_TxINT \| MCF_UART_RxINT);
	73	if (s->sr & MCF_UART_TxRDY)
	74	s->isr \|= MCF_UART_TxINT;
	75	if ((s->sr & ((s->mr[0] & MCF_UART_RxIRQ)
	76	? MCF_UART_FFULL : MCF_UART_RxRDY)) != 0)
	77	s->isr \|= MCF_UART_RxINT;
	78
	79	qemu_set_irq(s->irq, (s->isr & s->imr) != 0);
	80	}
	81
a8170e5e	82	uint64_t mcf_uart_read(void *opaque, hwaddr addr,
aa6e4986	83	unsigned size)
20dcee94 PB	84	{
	85	mcf_uart_state s = (mcf_uart_state )opaque;
	86	switch (addr & 0x3f) {
	87	case 0x00:
	88	return s->mr[s->current_mr];
	89	case 0x04:
	90	return s->sr;
	91	case 0x0c:
	92	{
	93	uint8_t val;
	94	int i;
	95
	96	if (s->fifo_len == 0)
	97	return 0;
	98
	99	val = s->fifo[0];
	100	s->fifo_len--;
	101	for (i = 0; i < s->fifo_len; i++)
	102	s->fifo[i] = s->fifo[i + 1];
	103	s->sr &= ~MCF_UART_FFULL;
	104	if (s->fifo_len == 0)
	105	s->sr &= ~MCF_UART_RxRDY;
	106	mcf_uart_update(s);
5345fdb4	107	qemu_chr_fe_accept_input(&s->chr);
20dcee94 PB	108	return val;
	109	}
	110	case 0x10:
	111	/* TODO: Implement IPCR. */
	112	return 0;
	113	case 0x14:
	114	return s->isr;
	115	case 0x18:
	116	return s->bg1;
	117	case 0x1c:
	118	return s->bg2;
	119	default:
	120	return 0;
	121	}
	122	}
	123
	124	/* Update TxRDY flag and set data if present and enabled. */
	125	static void mcf_uart_do_tx(mcf_uart_state *s)
	126	{
	127	if (s->tx_enabled && (s->sr & MCF_UART_TxEMP) == 0) {
fa394ed6 MAL	128	/* XXX this blocks entire thread. Rewrite to use
	129	* qemu_chr_fe_write and background I/O callbacks */
	130	qemu_chr_fe_write_all(&s->chr, (unsigned char *)&s->tb, 1);
20dcee94 PB	131	s->sr \|= MCF_UART_TxEMP;
	132	}
	133	if (s->tx_enabled) {
	134	s->sr \|= MCF_UART_TxRDY;
	135	} else {
	136	s->sr &= ~MCF_UART_TxRDY;
	137	}
	138	}
	139
	140	static void mcf_do_command(mcf_uart_state *s, uint8_t cmd)
	141	{
	142	/* Misc command. */
491ffc1f	143	switch ((cmd >> 4) & 7) {
20dcee94 PB	144	case 0: /* No-op. */
	145	break;
	146	case 1: /* Reset mode register pointer. */
	147	s->current_mr = 0;
	148	break;
	149	case 2: /* Reset receiver. */
	150	s->rx_enabled = 0;
	151	s->fifo_len = 0;
	152	s->sr &= ~(MCF_UART_RxRDY \| MCF_UART_FFULL);
	153	break;
	154	case 3: /* Reset transmitter. */
	155	s->tx_enabled = 0;
	156	s->sr \|= MCF_UART_TxEMP;
	157	s->sr &= ~MCF_UART_TxRDY;
	158	break;
	159	case 4: /* Reset error status. */
	160	break;
	161	case 5: /* Reset break-change interrupt. */
	162	s->isr &= ~MCF_UART_DBINT;
	163	break;
	164	case 6: /* Start break. */
	165	case 7: /* Stop break. */
	166	break;
	167	}
	168
	169	/* Transmitter command. */
	170	switch ((cmd >> 2) & 3) {
	171	case 0: /* No-op. */
	172	break;
	173	case 1: /* Enable. */
	174	s->tx_enabled = 1;
	175	mcf_uart_do_tx(s);
	176	break;
	177	case 2: /* Disable. */
	178	s->tx_enabled = 0;
	179	mcf_uart_do_tx(s);
	180	break;
	181	case 3: /* Reserved. */
	182	fprintf(stderr, "mcf_uart: Bad TX command\n");
	183	break;
	184	}
	185
	186	/* Receiver command. */
	187	switch (cmd & 3) {
	188	case 0: /* No-op. */
	189	break;
	190	case 1: /* Enable. */
	191	s->rx_enabled = 1;
	192	break;
	193	case 2:
	194	s->rx_enabled = 0;
	195	break;
	196	case 3: /* Reserved. */
	197	fprintf(stderr, "mcf_uart: Bad RX command\n");
	198	break;
	199	}
	200	}
	201
a8170e5e	202	void mcf_uart_write(void *opaque, hwaddr addr,
aa6e4986	203	uint64_t val, unsigned size)
20dcee94 PB	204	{
	205	mcf_uart_state s = (mcf_uart_state )opaque;
	206	switch (addr & 0x3f) {
	207	case 0x00:
	208	s->mr[s->current_mr] = val;
	209	s->current_mr = 1;
	210	break;
	211	case 0x04:
	212	/* CSR is ignored. */
	213	break;
	214	case 0x08: /* Command Register. */
	215	mcf_do_command(s, val);
	216	break;
	217	case 0x0c: /* Transmit Buffer. */
	218	s->sr &= ~MCF_UART_TxEMP;
	219	s->tb = val;
	220	mcf_uart_do_tx(s);
	221	break;
	222	case 0x10:
	223	/* ACR is ignored. */
	224	break;
	225	case 0x14:
	226	s->imr = val;
	227	break;
	228	default:
	229	break;
	230	}
	231	mcf_uart_update(s);
	232	}
	233
d9ff1d35	234	static void mcf_uart_reset(DeviceState *dev)
20dcee94	235	{
d9ff1d35 TH	236	mcf_uart_state *s = MCF_UART(dev);
d9ff1d35 TH	237
20dcee94 PB	238	s->fifo_len = 0;
	239	s->mr[0] = 0;
	240	s->mr[1] = 0;
	241	s->sr = MCF_UART_TxEMP;
	242	s->tx_enabled = 0;
	243	s->rx_enabled = 0;
	244	s->isr = 0;
	245	s->imr = 0;
	246	}
	247
	248	static void mcf_uart_push_byte(mcf_uart_state *s, uint8_t data)
	249	{
	250	/* Break events overwrite the last byte if the fifo is full. */
	251	if (s->fifo_len == 4)
	252	s->fifo_len--;
	253
	254	s->fifo[s->fifo_len] = data;
	255	s->fifo_len++;
	256	s->sr \|= MCF_UART_RxRDY;
	257	if (s->fifo_len == 4)
	258	s->sr \|= MCF_UART_FFULL;
	259
	260	mcf_uart_update(s);
	261	}
	262
083b266f	263	static void mcf_uart_event(void *opaque, QEMUChrEvent event)
20dcee94 PB	264	{
	265	mcf_uart_state s = (mcf_uart_state )opaque;
	266
	267	switch (event) {
	268	case CHR_EVENT_BREAK:
	269	s->isr \|= MCF_UART_DBINT;
	270	mcf_uart_push_byte(s, 0);
	271	break;
	272	default:
	273	break;
	274	}
	275	}
	276
	277	static int mcf_uart_can_receive(void *opaque)
	278	{
	279	mcf_uart_state s = (mcf_uart_state )opaque;
	280
	281	return s->rx_enabled && (s->sr & MCF_UART_FFULL) == 0;
	282	}
	283
	284	static void mcf_uart_receive(void opaque, const uint8_t buf, int size)
	285	{
	286	mcf_uart_state s = (mcf_uart_state )opaque;
	287
	288	mcf_uart_push_byte(s, buf[0]);
	289	}
	290
aa6e4986 BC	291	static const MemoryRegionOps mcf_uart_ops = {
	292	.read = mcf_uart_read,
	293	.write = mcf_uart_write,
	294	.endianness = DEVICE_NATIVE_ENDIAN,
20dcee94 PB	295	};
20dcee94 PB	296
d9ff1d35 TH	297	static void mcf_uart_instance_init(Object *obj)
	298	{
	299	SysBusDevice *dev = SYS_BUS_DEVICE(obj);
	300	mcf_uart_state *s = MCF_UART(dev);
	301
	302	memory_region_init_io(&s->iomem, obj, &mcf_uart_ops, s, "uart", 0x40);
	303	sysbus_init_mmio(dev, &s->iomem);
	304
	305	sysbus_init_irq(dev, &s->irq);
	306	}
	307
	308	static void mcf_uart_realize(DeviceState dev, Error *errp)
	309	{
	310	mcf_uart_state *s = MCF_UART(dev);
	311
	312	qemu_chr_fe_set_handlers(&s->chr, mcf_uart_can_receive, mcf_uart_receive,
81517ba3	313	mcf_uart_event, NULL, s, NULL, true);
d9ff1d35 TH	314	}
	315
	316	static Property mcf_uart_properties[] = {
	317	DEFINE_PROP_CHR("chardev", mcf_uart_state, chr),
	318	DEFINE_PROP_END_OF_LIST(),
	319	};
	320
	321	static void mcf_uart_class_init(ObjectClass oc, void data)
	322	{
	323	DeviceClass *dc = DEVICE_CLASS(oc);
	324
	325	dc->realize = mcf_uart_realize;
	326	dc->reset = mcf_uart_reset;
4f67d30b	327	device_class_set_props(dc, mcf_uart_properties);
d9ff1d35 TH	328	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
	329	}
	330
	331	static const TypeInfo mcf_uart_info = {
	332	.name = TYPE_MCF_UART,
	333	.parent = TYPE_SYS_BUS_DEVICE,
	334	.instance_size = sizeof(mcf_uart_state),
	335	.instance_init = mcf_uart_instance_init,
	336	.class_init = mcf_uart_class_init,
	337	};
	338
	339	static void mcf_uart_register(void)
	340	{
	341	type_register_static(&mcf_uart_info);
	342	}
	343
	344	type_init(mcf_uart_register)
	345
	346	void mcf_uart_init(qemu_irq irq, Chardev chrdrv)
	347	{
	348	DeviceState *dev;
	349
3e80f690	350	dev = qdev_new(TYPE_MCF_UART);
d9ff1d35 TH	351	if (chrdrv) {
	352	qdev_prop_set_chr(dev, "chardev", chrdrv);
	353	}
3c6ef471	354	sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
d9ff1d35 TH	355
	356	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
	357
	358	return dev;
	359	}
	360
	361	void mcf_uart_mm_init(hwaddr base, qemu_irq irq, Chardev *chrdrv)
20dcee94	362	{
d9ff1d35	363	DeviceState *dev;
20dcee94	364
d9ff1d35 TH	365	dev = mcf_uart_init(irq, chrdrv);
d9ff1d35 TH	366	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
20dcee94	367	}