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883de16b MW |
1 | /* |
2 | * QEMU model of the Milkymist UART block. | |
3 | * | |
4 | * Copyright (c) 2010 Michael Walle <michael@walle.cc> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | * | |
19 | * | |
20 | * Specification available at: | |
21 | * http://www.milkymist.org/socdoc/uart.pdf | |
22 | */ | |
23 | ||
83c9f4ca PB |
24 | #include "hw/hw.h" |
25 | #include "hw/sysbus.h" | |
883de16b | 26 | #include "trace.h" |
dccfcd0e | 27 | #include "sysemu/char.h" |
1de7afc9 | 28 | #include "qemu/error-report.h" |
883de16b MW |
29 | |
30 | enum { | |
31 | R_RXTX = 0, | |
32 | R_DIV, | |
fcfa3397 MW |
33 | R_STAT, |
34 | R_CTRL, | |
35 | R_DBG, | |
883de16b MW |
36 | R_MAX |
37 | }; | |
38 | ||
fcfa3397 MW |
39 | enum { |
40 | STAT_THRE = (1<<0), | |
41 | STAT_RX_EVT = (1<<1), | |
42 | STAT_TX_EVT = (1<<2), | |
43 | }; | |
44 | ||
45 | enum { | |
46 | CTRL_RX_IRQ_EN = (1<<0), | |
47 | CTRL_TX_IRQ_EN = (1<<1), | |
48 | CTRL_THRU_EN = (1<<2), | |
49 | }; | |
50 | ||
51 | enum { | |
52 | DBG_BREAK_EN = (1<<0), | |
53 | }; | |
54 | ||
79bbe8bf AF |
55 | #define TYPE_MILKYMIST_UART "milkymist-uart" |
56 | #define MILKYMIST_UART(obj) \ | |
57 | OBJECT_CHECK(MilkymistUartState, (obj), TYPE_MILKYMIST_UART) | |
58 | ||
883de16b | 59 | struct MilkymistUartState { |
79bbe8bf AF |
60 | SysBusDevice parent_obj; |
61 | ||
5adb30d3 | 62 | MemoryRegion regs_region; |
883de16b | 63 | CharDriverState *chr; |
fcfa3397 | 64 | qemu_irq irq; |
883de16b MW |
65 | |
66 | uint32_t regs[R_MAX]; | |
67 | }; | |
68 | typedef struct MilkymistUartState MilkymistUartState; | |
69 | ||
fcfa3397 MW |
70 | static void uart_update_irq(MilkymistUartState *s) |
71 | { | |
72 | int rx_event = s->regs[R_STAT] & STAT_RX_EVT; | |
73 | int tx_event = s->regs[R_STAT] & STAT_TX_EVT; | |
74 | int rx_irq_en = s->regs[R_CTRL] & CTRL_RX_IRQ_EN; | |
75 | int tx_irq_en = s->regs[R_CTRL] & CTRL_TX_IRQ_EN; | |
76 | ||
77 | if ((rx_irq_en && rx_event) || (tx_irq_en && tx_event)) { | |
78 | trace_milkymist_uart_raise_irq(); | |
79 | qemu_irq_raise(s->irq); | |
80 | } else { | |
81 | trace_milkymist_uart_lower_irq(); | |
82 | qemu_irq_lower(s->irq); | |
83 | } | |
84 | } | |
85 | ||
a8170e5e | 86 | static uint64_t uart_read(void *opaque, hwaddr addr, |
5adb30d3 | 87 | unsigned size) |
883de16b MW |
88 | { |
89 | MilkymistUartState *s = opaque; | |
90 | uint32_t r = 0; | |
91 | ||
92 | addr >>= 2; | |
93 | switch (addr) { | |
94 | case R_RXTX: | |
fcfa3397 MW |
95 | r = s->regs[addr]; |
96 | break; | |
883de16b | 97 | case R_DIV: |
fcfa3397 MW |
98 | case R_STAT: |
99 | case R_CTRL: | |
100 | case R_DBG: | |
883de16b MW |
101 | r = s->regs[addr]; |
102 | break; | |
103 | ||
104 | default: | |
105 | error_report("milkymist_uart: read access to unknown register 0x" | |
106 | TARGET_FMT_plx, addr << 2); | |
107 | break; | |
108 | } | |
109 | ||
110 | trace_milkymist_uart_memory_read(addr << 2, r); | |
111 | ||
112 | return r; | |
113 | } | |
114 | ||
a8170e5e | 115 | static void uart_write(void *opaque, hwaddr addr, uint64_t value, |
5adb30d3 | 116 | unsigned size) |
883de16b MW |
117 | { |
118 | MilkymistUartState *s = opaque; | |
119 | unsigned char ch = value; | |
120 | ||
121 | trace_milkymist_uart_memory_write(addr, value); | |
122 | ||
123 | addr >>= 2; | |
124 | switch (addr) { | |
125 | case R_RXTX: | |
126 | if (s->chr) { | |
2cc6e0a1 | 127 | qemu_chr_fe_write(s->chr, &ch, 1); |
883de16b | 128 | } |
fcfa3397 | 129 | s->regs[R_STAT] |= STAT_TX_EVT; |
883de16b MW |
130 | break; |
131 | case R_DIV: | |
fcfa3397 MW |
132 | case R_CTRL: |
133 | case R_DBG: | |
883de16b MW |
134 | s->regs[addr] = value; |
135 | break; | |
136 | ||
fcfa3397 MW |
137 | case R_STAT: |
138 | /* write one to clear bits */ | |
139 | s->regs[addr] &= ~(value & (STAT_RX_EVT | STAT_TX_EVT)); | |
44ac582d | 140 | qemu_chr_accept_input(s->chr); |
fcfa3397 MW |
141 | break; |
142 | ||
883de16b MW |
143 | default: |
144 | error_report("milkymist_uart: write access to unknown register 0x" | |
145 | TARGET_FMT_plx, addr << 2); | |
146 | break; | |
147 | } | |
fcfa3397 MW |
148 | |
149 | uart_update_irq(s); | |
883de16b MW |
150 | } |
151 | ||
5adb30d3 MW |
152 | static const MemoryRegionOps uart_mmio_ops = { |
153 | .read = uart_read, | |
154 | .write = uart_write, | |
155 | .valid = { | |
156 | .min_access_size = 4, | |
157 | .max_access_size = 4, | |
158 | }, | |
159 | .endianness = DEVICE_NATIVE_ENDIAN, | |
883de16b MW |
160 | }; |
161 | ||
162 | static void uart_rx(void *opaque, const uint8_t *buf, int size) | |
163 | { | |
164 | MilkymistUartState *s = opaque; | |
165 | ||
fcfa3397 MW |
166 | assert(!(s->regs[R_STAT] & STAT_RX_EVT)); |
167 | ||
168 | s->regs[R_STAT] |= STAT_RX_EVT; | |
883de16b | 169 | s->regs[R_RXTX] = *buf; |
fcfa3397 MW |
170 | |
171 | uart_update_irq(s); | |
883de16b MW |
172 | } |
173 | ||
174 | static int uart_can_rx(void *opaque) | |
175 | { | |
fcfa3397 MW |
176 | MilkymistUartState *s = opaque; |
177 | ||
178 | return !(s->regs[R_STAT] & STAT_RX_EVT); | |
883de16b MW |
179 | } |
180 | ||
181 | static void uart_event(void *opaque, int event) | |
182 | { | |
183 | } | |
184 | ||
185 | static void milkymist_uart_reset(DeviceState *d) | |
186 | { | |
79bbe8bf | 187 | MilkymistUartState *s = MILKYMIST_UART(d); |
883de16b MW |
188 | int i; |
189 | ||
190 | for (i = 0; i < R_MAX; i++) { | |
191 | s->regs[i] = 0; | |
192 | } | |
fcfa3397 MW |
193 | |
194 | /* THRE is always set */ | |
195 | s->regs[R_STAT] = STAT_THRE; | |
883de16b MW |
196 | } |
197 | ||
198 | static int milkymist_uart_init(SysBusDevice *dev) | |
199 | { | |
79bbe8bf | 200 | MilkymistUartState *s = MILKYMIST_UART(dev); |
883de16b | 201 | |
fcfa3397 | 202 | sysbus_init_irq(dev, &s->irq); |
883de16b | 203 | |
300b1fc6 | 204 | memory_region_init_io(&s->regs_region, OBJECT(s), &uart_mmio_ops, s, |
79bbe8bf | 205 | "milkymist-uart", R_MAX * 4); |
750ecd44 | 206 | sysbus_init_mmio(dev, &s->regs_region); |
883de16b | 207 | |
0beb4942 | 208 | s->chr = qemu_char_get_next_serial(); |
883de16b MW |
209 | if (s->chr) { |
210 | qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s); | |
211 | } | |
212 | ||
213 | return 0; | |
214 | } | |
215 | ||
216 | static const VMStateDescription vmstate_milkymist_uart = { | |
217 | .name = "milkymist-uart", | |
218 | .version_id = 1, | |
219 | .minimum_version_id = 1, | |
220 | .minimum_version_id_old = 1, | |
221 | .fields = (VMStateField[]) { | |
222 | VMSTATE_UINT32_ARRAY(regs, MilkymistUartState, R_MAX), | |
223 | VMSTATE_END_OF_LIST() | |
224 | } | |
225 | }; | |
226 | ||
999e12bb AL |
227 | static void milkymist_uart_class_init(ObjectClass *klass, void *data) |
228 | { | |
39bffca2 | 229 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
230 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
231 | ||
232 | k->init = milkymist_uart_init; | |
39bffca2 AL |
233 | dc->reset = milkymist_uart_reset; |
234 | dc->vmsd = &vmstate_milkymist_uart; | |
999e12bb AL |
235 | } |
236 | ||
8c43a6f0 | 237 | static const TypeInfo milkymist_uart_info = { |
79bbe8bf | 238 | .name = TYPE_MILKYMIST_UART, |
39bffca2 AL |
239 | .parent = TYPE_SYS_BUS_DEVICE, |
240 | .instance_size = sizeof(MilkymistUartState), | |
241 | .class_init = milkymist_uart_class_init, | |
883de16b MW |
242 | }; |
243 | ||
83f7d43a | 244 | static void milkymist_uart_register_types(void) |
883de16b | 245 | { |
39bffca2 | 246 | type_register_static(&milkymist_uart_info); |
883de16b MW |
247 | } |
248 | ||
83f7d43a | 249 | type_init(milkymist_uart_register_types) |