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Commit | Line | Data |
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6508fe59 FB |
1 | /* |
2 | * QEMU Parallel PORT emulation | |
5fafdf24 | 3 | * |
e57a8c0e | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
5867c88a | 5 | * Copyright (c) 2007 Marko Kohtala |
5fafdf24 | 6 | * |
6508fe59 FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
0b8fa32f | 25 | |
b6a0aa05 | 26 | #include "qemu/osdep.h" |
da34e65c | 27 | #include "qapi/error.h" |
0b8fa32f | 28 | #include "qemu/module.h" |
7566c6ef | 29 | #include "chardev/char-parallel.h" |
4d43a603 | 30 | #include "chardev/char-fe.h" |
ed003c8c | 31 | #include "hw/acpi/aml-build.h" |
64552b6b | 32 | #include "hw/irq.h" |
0d09e41a | 33 | #include "hw/isa/isa.h" |
a27bd6c7 | 34 | #include "hw/qdev-properties.h" |
ce35e229 | 35 | #include "hw/qdev-properties-system.h" |
d6454270 | 36 | #include "migration/vmstate.h" |
bb3d5ea8 | 37 | #include "hw/char/parallel.h" |
71e8a915 | 38 | #include "sysemu/reset.h" |
9c17d615 | 39 | #include "sysemu/sysemu.h" |
cb2d721c | 40 | #include "trace.h" |
db1015e9 | 41 | #include "qom/object.h" |
6508fe59 FB |
42 | |
43 | //#define DEBUG_PARALLEL | |
44 | ||
5867c88a | 45 | #ifdef DEBUG_PARALLEL |
001faf32 | 46 | #define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__) |
5867c88a | 47 | #else |
001faf32 | 48 | #define pdebug(fmt, ...) ((void)0) |
5867c88a TS |
49 | #endif |
50 | ||
51 | #define PARA_REG_DATA 0 | |
52 | #define PARA_REG_STS 1 | |
53 | #define PARA_REG_CTR 2 | |
54 | #define PARA_REG_EPP_ADDR 3 | |
55 | #define PARA_REG_EPP_DATA 4 | |
56 | ||
6508fe59 FB |
57 | /* |
58 | * These are the definitions for the Printer Status Register | |
59 | */ | |
60 | #define PARA_STS_BUSY 0x80 /* Busy complement */ | |
61 | #define PARA_STS_ACK 0x40 /* Acknowledge */ | |
62 | #define PARA_STS_PAPER 0x20 /* Out of paper */ | |
63 | #define PARA_STS_ONLINE 0x10 /* Online */ | |
64 | #define PARA_STS_ERROR 0x08 /* Error complement */ | |
5867c88a | 65 | #define PARA_STS_TMOUT 0x01 /* EPP timeout */ |
6508fe59 FB |
66 | |
67 | /* | |
68 | * These are the definitions for the Printer Control Register | |
69 | */ | |
5867c88a | 70 | #define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */ |
6508fe59 FB |
71 | #define PARA_CTR_INTEN 0x10 /* IRQ Enable */ |
72 | #define PARA_CTR_SELECT 0x08 /* Select In complement */ | |
73 | #define PARA_CTR_INIT 0x04 /* Initialize Printer complement */ | |
74 | #define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */ | |
75 | #define PARA_CTR_STROBE 0x01 /* Strobe complement */ | |
76 | ||
5867c88a TS |
77 | #define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE) |
78 | ||
defdb20e | 79 | typedef struct ParallelState { |
63858cd9 | 80 | MemoryRegion iomem; |
5867c88a TS |
81 | uint8_t dataw; |
82 | uint8_t datar; | |
83 | uint8_t status; | |
6508fe59 | 84 | uint8_t control; |
d537cf6c | 85 | qemu_irq irq; |
6508fe59 | 86 | int irq_pending; |
becdfa00 | 87 | CharBackend chr; |
e57a8c0e | 88 | int hw_driver; |
5867c88a TS |
89 | int epp_timeout; |
90 | uint32_t last_read_offset; /* For debugging */ | |
d60532ca | 91 | /* Memory-mapped interface */ |
d60532ca | 92 | int it_shift; |
e305a165 | 93 | PortioList portio_list; |
defdb20e | 94 | } ParallelState; |
6508fe59 | 95 | |
b0dc5ee6 | 96 | #define TYPE_ISA_PARALLEL "isa-parallel" |
8063396b | 97 | OBJECT_DECLARE_SIMPLE_TYPE(ISAParallelState, ISA_PARALLEL) |
b0dc5ee6 | 98 | |
db1015e9 | 99 | struct ISAParallelState { |
b0dc5ee6 AF |
100 | ISADevice parent_obj; |
101 | ||
e8ee28fb | 102 | uint32_t index; |
021f0674 GH |
103 | uint32_t iobase; |
104 | uint32_t isairq; | |
105 | ParallelState state; | |
db1015e9 | 106 | }; |
021f0674 | 107 | |
6508fe59 FB |
108 | static void parallel_update_irq(ParallelState *s) |
109 | { | |
110 | if (s->irq_pending) | |
d537cf6c | 111 | qemu_irq_raise(s->irq); |
6508fe59 | 112 | else |
d537cf6c | 113 | qemu_irq_lower(s->irq); |
6508fe59 FB |
114 | } |
115 | ||
5867c88a TS |
116 | static void |
117 | parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val) | |
6508fe59 FB |
118 | { |
119 | ParallelState *s = opaque; | |
3b46e624 | 120 | |
5867c88a | 121 | addr &= 7; |
cb2d721c | 122 | trace_parallel_ioport_write("SW", addr, val); |
5867c88a TS |
123 | switch(addr) { |
124 | case PARA_REG_DATA: | |
0fa7f157 TS |
125 | s->dataw = val; |
126 | parallel_update_irq(s); | |
5867c88a TS |
127 | break; |
128 | case PARA_REG_CTR: | |
52ccc5e0 | 129 | val |= 0xc0; |
0fa7f157 TS |
130 | if ((val & PARA_CTR_INIT) == 0 ) { |
131 | s->status = PARA_STS_BUSY; | |
132 | s->status |= PARA_STS_ACK; | |
133 | s->status |= PARA_STS_ONLINE; | |
134 | s->status |= PARA_STS_ERROR; | |
135 | } | |
136 | else if (val & PARA_CTR_SELECT) { | |
137 | if (val & PARA_CTR_STROBE) { | |
138 | s->status &= ~PARA_STS_BUSY; | |
139 | if ((s->control & PARA_CTR_STROBE) == 0) | |
6ab3fc32 DB |
140 | /* XXX this blocks entire thread. Rewrite to use |
141 | * qemu_chr_fe_write and background I/O callbacks */ | |
5345fdb4 | 142 | qemu_chr_fe_write_all(&s->chr, &s->dataw, 1); |
0fa7f157 TS |
143 | } else { |
144 | if (s->control & PARA_CTR_INTEN) { | |
145 | s->irq_pending = 1; | |
146 | } | |
147 | } | |
148 | } | |
149 | parallel_update_irq(s); | |
150 | s->control = val; | |
5867c88a TS |
151 | break; |
152 | } | |
153 | } | |
154 | ||
155 | static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val) | |
156 | { | |
157 | ParallelState *s = opaque; | |
158 | uint8_t parm = val; | |
563e3c6e | 159 | int dir; |
5867c88a TS |
160 | |
161 | /* Sometimes programs do several writes for timing purposes on old | |
162 | HW. Take care not to waste time on writes that do nothing. */ | |
163 | ||
164 | s->last_read_offset = ~0U; | |
165 | ||
6508fe59 | 166 | addr &= 7; |
cb2d721c | 167 | trace_parallel_ioport_write("HW", addr, val); |
6508fe59 | 168 | switch(addr) { |
5867c88a TS |
169 | case PARA_REG_DATA: |
170 | if (s->dataw == val) | |
0fa7f157 TS |
171 | return; |
172 | pdebug("wd%02x\n", val); | |
5345fdb4 | 173 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm); |
0fa7f157 | 174 | s->dataw = val; |
6508fe59 | 175 | break; |
5867c88a | 176 | case PARA_REG_STS: |
0fa7f157 TS |
177 | pdebug("ws%02x\n", val); |
178 | if (val & PARA_STS_TMOUT) | |
179 | s->epp_timeout = 0; | |
180 | break; | |
5867c88a TS |
181 | case PARA_REG_CTR: |
182 | val |= 0xc0; | |
183 | if (s->control == val) | |
0fa7f157 TS |
184 | return; |
185 | pdebug("wc%02x\n", val); | |
563e3c6e AJ |
186 | |
187 | if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) { | |
188 | if (val & PARA_CTR_DIR) { | |
189 | dir = 1; | |
190 | } else { | |
191 | dir = 0; | |
192 | } | |
5345fdb4 | 193 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_DATA_DIR, &dir); |
563e3c6e AJ |
194 | parm &= ~PARA_CTR_DIR; |
195 | } | |
196 | ||
5345fdb4 | 197 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm); |
0fa7f157 | 198 | s->control = val; |
6508fe59 | 199 | break; |
5867c88a | 200 | case PARA_REG_EPP_ADDR: |
0fa7f157 TS |
201 | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) |
202 | /* Controls not correct for EPP address cycle, so do nothing */ | |
203 | pdebug("wa%02x s\n", val); | |
204 | else { | |
205 | struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; | |
5345fdb4 | 206 | if (qemu_chr_fe_ioctl(&s->chr, |
becdfa00 | 207 | CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) { |
0fa7f157 TS |
208 | s->epp_timeout = 1; |
209 | pdebug("wa%02x t\n", val); | |
210 | } | |
211 | else | |
212 | pdebug("wa%02x\n", val); | |
213 | } | |
214 | break; | |
5867c88a | 215 | case PARA_REG_EPP_DATA: |
0fa7f157 TS |
216 | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) |
217 | /* Controls not correct for EPP data cycle, so do nothing */ | |
218 | pdebug("we%02x s\n", val); | |
219 | else { | |
220 | struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; | |
5345fdb4 | 221 | if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) { |
0fa7f157 TS |
222 | s->epp_timeout = 1; |
223 | pdebug("we%02x t\n", val); | |
224 | } | |
225 | else | |
226 | pdebug("we%02x\n", val); | |
227 | } | |
228 | break; | |
5867c88a TS |
229 | } |
230 | } | |
231 | ||
232 | static void | |
233 | parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val) | |
234 | { | |
235 | ParallelState *s = opaque; | |
236 | uint16_t eppdata = cpu_to_le16(val); | |
237 | int err; | |
238 | struct ParallelIOArg ioarg = { | |
0fa7f157 | 239 | .buffer = &eppdata, .count = sizeof(eppdata) |
5867c88a | 240 | }; |
cb2d721c PMD |
241 | |
242 | trace_parallel_ioport_write("EPP", addr, val); | |
5867c88a | 243 | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) { |
0fa7f157 TS |
244 | /* Controls not correct for EPP data cycle, so do nothing */ |
245 | pdebug("we%04x s\n", val); | |
246 | return; | |
5867c88a | 247 | } |
5345fdb4 | 248 | err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); |
5867c88a | 249 | if (err) { |
0fa7f157 TS |
250 | s->epp_timeout = 1; |
251 | pdebug("we%04x t\n", val); | |
5867c88a TS |
252 | } |
253 | else | |
0fa7f157 | 254 | pdebug("we%04x\n", val); |
5867c88a TS |
255 | } |
256 | ||
257 | static void | |
258 | parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val) | |
259 | { | |
260 | ParallelState *s = opaque; | |
261 | uint32_t eppdata = cpu_to_le32(val); | |
262 | int err; | |
263 | struct ParallelIOArg ioarg = { | |
0fa7f157 | 264 | .buffer = &eppdata, .count = sizeof(eppdata) |
5867c88a | 265 | }; |
cb2d721c PMD |
266 | |
267 | trace_parallel_ioport_write("EPP", addr, val); | |
5867c88a | 268 | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) { |
0fa7f157 TS |
269 | /* Controls not correct for EPP data cycle, so do nothing */ |
270 | pdebug("we%08x s\n", val); | |
271 | return; | |
5867c88a | 272 | } |
5345fdb4 | 273 | err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); |
5867c88a | 274 | if (err) { |
0fa7f157 TS |
275 | s->epp_timeout = 1; |
276 | pdebug("we%08x t\n", val); | |
6508fe59 | 277 | } |
5867c88a | 278 | else |
0fa7f157 | 279 | pdebug("we%08x\n", val); |
6508fe59 FB |
280 | } |
281 | ||
5867c88a | 282 | static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr) |
6508fe59 FB |
283 | { |
284 | ParallelState *s = opaque; | |
285 | uint32_t ret = 0xff; | |
286 | ||
287 | addr &= 7; | |
288 | switch(addr) { | |
5867c88a | 289 | case PARA_REG_DATA: |
0fa7f157 TS |
290 | if (s->control & PARA_CTR_DIR) |
291 | ret = s->datar; | |
292 | else | |
293 | ret = s->dataw; | |
6508fe59 | 294 | break; |
5867c88a | 295 | case PARA_REG_STS: |
0fa7f157 TS |
296 | ret = s->status; |
297 | s->irq_pending = 0; | |
298 | if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) { | |
299 | /* XXX Fixme: wait 5 microseconds */ | |
300 | if (s->status & PARA_STS_ACK) | |
301 | s->status &= ~PARA_STS_ACK; | |
302 | else { | |
303 | /* XXX Fixme: wait 5 microseconds */ | |
304 | s->status |= PARA_STS_ACK; | |
305 | s->status |= PARA_STS_BUSY; | |
306 | } | |
307 | } | |
308 | parallel_update_irq(s); | |
6508fe59 | 309 | break; |
5867c88a | 310 | case PARA_REG_CTR: |
6508fe59 FB |
311 | ret = s->control; |
312 | break; | |
313 | } | |
cb2d721c | 314 | trace_parallel_ioport_read("SW", addr, ret); |
5867c88a TS |
315 | return ret; |
316 | } | |
317 | ||
318 | static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr) | |
319 | { | |
320 | ParallelState *s = opaque; | |
321 | uint8_t ret = 0xff; | |
322 | addr &= 7; | |
323 | switch(addr) { | |
324 | case PARA_REG_DATA: | |
5345fdb4 | 325 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_DATA, &ret); |
0fa7f157 TS |
326 | if (s->last_read_offset != addr || s->datar != ret) |
327 | pdebug("rd%02x\n", ret); | |
5867c88a TS |
328 | s->datar = ret; |
329 | break; | |
330 | case PARA_REG_STS: | |
5345fdb4 | 331 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &ret); |
0fa7f157 TS |
332 | ret &= ~PARA_STS_TMOUT; |
333 | if (s->epp_timeout) | |
334 | ret |= PARA_STS_TMOUT; | |
335 | if (s->last_read_offset != addr || s->status != ret) | |
336 | pdebug("rs%02x\n", ret); | |
337 | s->status = ret; | |
5867c88a TS |
338 | break; |
339 | case PARA_REG_CTR: | |
340 | /* s->control has some bits fixed to 1. It is zero only when | |
0fa7f157 TS |
341 | it has not been yet written to. */ |
342 | if (s->control == 0) { | |
5345fdb4 | 343 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret); |
0fa7f157 TS |
344 | if (s->last_read_offset != addr) |
345 | pdebug("rc%02x\n", ret); | |
346 | s->control = ret; | |
347 | } | |
348 | else { | |
349 | ret = s->control; | |
350 | if (s->last_read_offset != addr) | |
351 | pdebug("rc%02x\n", ret); | |
352 | } | |
5867c88a TS |
353 | break; |
354 | case PARA_REG_EPP_ADDR: | |
becdfa00 MAL |
355 | if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) != |
356 | (PARA_CTR_DIR | PARA_CTR_INIT)) | |
0fa7f157 TS |
357 | /* Controls not correct for EPP addr cycle, so do nothing */ |
358 | pdebug("ra%02x s\n", ret); | |
359 | else { | |
360 | struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; | |
5345fdb4 | 361 | if (qemu_chr_fe_ioctl(&s->chr, |
becdfa00 | 362 | CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) { |
0fa7f157 TS |
363 | s->epp_timeout = 1; |
364 | pdebug("ra%02x t\n", ret); | |
365 | } | |
366 | else | |
367 | pdebug("ra%02x\n", ret); | |
368 | } | |
369 | break; | |
5867c88a | 370 | case PARA_REG_EPP_DATA: |
becdfa00 MAL |
371 | if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) != |
372 | (PARA_CTR_DIR | PARA_CTR_INIT)) | |
0fa7f157 TS |
373 | /* Controls not correct for EPP data cycle, so do nothing */ |
374 | pdebug("re%02x s\n", ret); | |
375 | else { | |
376 | struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; | |
5345fdb4 | 377 | if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) { |
0fa7f157 TS |
378 | s->epp_timeout = 1; |
379 | pdebug("re%02x t\n", ret); | |
380 | } | |
381 | else | |
382 | pdebug("re%02x\n", ret); | |
383 | } | |
384 | break; | |
5867c88a | 385 | } |
cb2d721c | 386 | trace_parallel_ioport_read("HW", addr, ret); |
5867c88a TS |
387 | s->last_read_offset = addr; |
388 | return ret; | |
389 | } | |
390 | ||
391 | static uint32_t | |
392 | parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr) | |
393 | { | |
394 | ParallelState *s = opaque; | |
395 | uint32_t ret; | |
396 | uint16_t eppdata = ~0; | |
397 | int err; | |
398 | struct ParallelIOArg ioarg = { | |
0fa7f157 | 399 | .buffer = &eppdata, .count = sizeof(eppdata) |
5867c88a TS |
400 | }; |
401 | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) { | |
0fa7f157 TS |
402 | /* Controls not correct for EPP data cycle, so do nothing */ |
403 | pdebug("re%04x s\n", eppdata); | |
404 | return eppdata; | |
5867c88a | 405 | } |
5345fdb4 | 406 | err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); |
5867c88a TS |
407 | ret = le16_to_cpu(eppdata); |
408 | ||
409 | if (err) { | |
0fa7f157 TS |
410 | s->epp_timeout = 1; |
411 | pdebug("re%04x t\n", ret); | |
5867c88a TS |
412 | } |
413 | else | |
0fa7f157 | 414 | pdebug("re%04x\n", ret); |
cb2d721c | 415 | trace_parallel_ioport_read("EPP", addr, ret); |
5867c88a TS |
416 | return ret; |
417 | } | |
418 | ||
419 | static uint32_t | |
420 | parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr) | |
421 | { | |
422 | ParallelState *s = opaque; | |
423 | uint32_t ret; | |
424 | uint32_t eppdata = ~0U; | |
425 | int err; | |
426 | struct ParallelIOArg ioarg = { | |
0fa7f157 | 427 | .buffer = &eppdata, .count = sizeof(eppdata) |
5867c88a TS |
428 | }; |
429 | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) { | |
0fa7f157 TS |
430 | /* Controls not correct for EPP data cycle, so do nothing */ |
431 | pdebug("re%08x s\n", eppdata); | |
432 | return eppdata; | |
5867c88a | 433 | } |
5345fdb4 | 434 | err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); |
5867c88a TS |
435 | ret = le32_to_cpu(eppdata); |
436 | ||
437 | if (err) { | |
0fa7f157 TS |
438 | s->epp_timeout = 1; |
439 | pdebug("re%08x t\n", ret); | |
5867c88a TS |
440 | } |
441 | else | |
0fa7f157 | 442 | pdebug("re%08x\n", ret); |
cb2d721c | 443 | trace_parallel_ioport_read("EPP", addr, ret); |
5867c88a TS |
444 | return ret; |
445 | } | |
446 | ||
447 | static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val) | |
448 | { | |
cb2d721c | 449 | trace_parallel_ioport_write("ECP", addr & 7, val); |
7f5b7d3e | 450 | pdebug("wecp%d=%02x\n", addr & 7, val); |
5867c88a TS |
451 | } |
452 | ||
453 | static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr) | |
454 | { | |
455 | uint8_t ret = 0xff; | |
7f5b7d3e | 456 | |
cb2d721c | 457 | trace_parallel_ioport_read("ECP", addr & 7, ret); |
7f5b7d3e | 458 | pdebug("recp%d:%02x\n", addr & 7, ret); |
6508fe59 FB |
459 | return ret; |
460 | } | |
461 | ||
33093a0a | 462 | static void parallel_reset(void *opaque) |
6508fe59 | 463 | { |
33093a0a AJ |
464 | ParallelState *s = opaque; |
465 | ||
5867c88a TS |
466 | s->datar = ~0; |
467 | s->dataw = ~0; | |
6508fe59 FB |
468 | s->status = PARA_STS_BUSY; |
469 | s->status |= PARA_STS_ACK; | |
470 | s->status |= PARA_STS_ONLINE; | |
471 | s->status |= PARA_STS_ERROR; | |
52ccc5e0 | 472 | s->status |= PARA_STS_TMOUT; |
6508fe59 FB |
473 | s->control = PARA_CTR_SELECT; |
474 | s->control |= PARA_CTR_INIT; | |
52ccc5e0 | 475 | s->control |= 0xc0; |
5867c88a | 476 | s->irq_pending = 0; |
5867c88a TS |
477 | s->hw_driver = 0; |
478 | s->epp_timeout = 0; | |
479 | s->last_read_offset = ~0U; | |
d60532ca TS |
480 | } |
481 | ||
e8ee28fb GH |
482 | static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
483 | ||
1922abd0 RH |
484 | static const MemoryRegionPortio isa_parallel_portio_hw_list[] = { |
485 | { 0, 8, 1, | |
486 | .read = parallel_ioport_read_hw, | |
487 | .write = parallel_ioport_write_hw }, | |
488 | { 4, 1, 2, | |
489 | .read = parallel_ioport_eppdata_read_hw2, | |
490 | .write = parallel_ioport_eppdata_write_hw2 }, | |
491 | { 4, 1, 4, | |
492 | .read = parallel_ioport_eppdata_read_hw4, | |
493 | .write = parallel_ioport_eppdata_write_hw4 }, | |
494 | { 0x400, 8, 1, | |
495 | .read = parallel_ioport_ecp_read, | |
496 | .write = parallel_ioport_ecp_write }, | |
497 | PORTIO_END_OF_LIST(), | |
498 | }; | |
499 | ||
500 | static const MemoryRegionPortio isa_parallel_portio_sw_list[] = { | |
501 | { 0, 8, 1, | |
502 | .read = parallel_ioport_read_sw, | |
503 | .write = parallel_ioport_write_sw }, | |
504 | PORTIO_END_OF_LIST(), | |
505 | }; | |
506 | ||
461a2753 PD |
507 | |
508 | static const VMStateDescription vmstate_parallel_isa = { | |
509 | .name = "parallel_isa", | |
510 | .version_id = 1, | |
511 | .minimum_version_id = 1, | |
512 | .fields = (VMStateField[]) { | |
513 | VMSTATE_UINT8(state.dataw, ISAParallelState), | |
514 | VMSTATE_UINT8(state.datar, ISAParallelState), | |
515 | VMSTATE_UINT8(state.status, ISAParallelState), | |
516 | VMSTATE_UINT8(state.control, ISAParallelState), | |
517 | VMSTATE_INT32(state.irq_pending, ISAParallelState), | |
518 | VMSTATE_INT32(state.epp_timeout, ISAParallelState), | |
519 | VMSTATE_END_OF_LIST() | |
520 | } | |
521 | }; | |
522 | ||
98fab4c1 PH |
523 | static int parallel_can_receive(void *opaque) |
524 | { | |
525 | return 1; | |
526 | } | |
461a2753 | 527 | |
db895a1e | 528 | static void parallel_isa_realizefn(DeviceState *dev, Error **errp) |
d60532ca | 529 | { |
e8ee28fb | 530 | static int index; |
db895a1e | 531 | ISADevice *isadev = ISA_DEVICE(dev); |
b0dc5ee6 | 532 | ISAParallelState *isa = ISA_PARALLEL(dev); |
021f0674 | 533 | ParallelState *s = &isa->state; |
e8ee28fb | 534 | int base; |
d60532ca TS |
535 | uint8_t dummy; |
536 | ||
30650701 | 537 | if (!qemu_chr_fe_backend_connected(&s->chr)) { |
db895a1e AF |
538 | error_setg(errp, "Can't create parallel device, empty char device"); |
539 | return; | |
021f0674 GH |
540 | } |
541 | ||
db895a1e | 542 | if (isa->index == -1) { |
e8ee28fb | 543 | isa->index = index; |
db895a1e AF |
544 | } |
545 | if (isa->index >= MAX_PARALLEL_PORTS) { | |
546 | error_setg(errp, "Max. supported number of parallel ports is %d.", | |
547 | MAX_PARALLEL_PORTS); | |
548 | return; | |
549 | } | |
550 | if (isa->iobase == -1) { | |
e8ee28fb | 551 | isa->iobase = isa_parallel_io[isa->index]; |
db895a1e | 552 | } |
e8ee28fb GH |
553 | index++; |
554 | ||
555 | base = isa->iobase; | |
db895a1e | 556 | isa_init_irq(isadev, &s->irq, isa->isairq); |
a08d4367 | 557 | qemu_register_reset(parallel_reset, s); |
6508fe59 | 558 | |
98fab4c1 PH |
559 | qemu_chr_fe_set_handlers(&s->chr, parallel_can_receive, NULL, |
560 | NULL, NULL, s, NULL, true); | |
5345fdb4 | 561 | if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) { |
5867c88a | 562 | s->hw_driver = 1; |
0fa7f157 | 563 | s->status = dummy; |
5867c88a TS |
564 | } |
565 | ||
e305a165 | 566 | isa_register_portio_list(isadev, &s->portio_list, base, |
1922abd0 RH |
567 | (s->hw_driver |
568 | ? &isa_parallel_portio_hw_list[0] | |
569 | : &isa_parallel_portio_sw_list[0]), | |
570 | s, "parallel"); | |
021f0674 GH |
571 | } |
572 | ||
ed003c8c GH |
573 | static void parallel_isa_build_aml(ISADevice *isadev, Aml *scope) |
574 | { | |
575 | ISAParallelState *isa = ISA_PARALLEL(isadev); | |
576 | Aml *dev; | |
577 | Aml *crs; | |
578 | ||
579 | crs = aml_resource_template(); | |
580 | aml_append(crs, aml_io(AML_DECODE16, isa->iobase, isa->iobase, 0x08, 0x08)); | |
581 | aml_append(crs, aml_irq_no_flags(isa->isairq)); | |
582 | ||
583 | dev = aml_device("LPT%d", isa->index + 1); | |
584 | aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400"))); | |
585 | aml_append(dev, aml_name_decl("_UID", aml_int(isa->index + 1))); | |
586 | aml_append(dev, aml_name_decl("_STA", aml_int(0xf))); | |
587 | aml_append(dev, aml_name_decl("_CRS", crs)); | |
588 | ||
589 | aml_append(scope, dev); | |
590 | } | |
591 | ||
d60532ca | 592 | /* Memory mapped interface */ |
05b4940b | 593 | static uint64_t parallel_mm_readfn(void *opaque, hwaddr addr, unsigned size) |
d60532ca TS |
594 | { |
595 | ParallelState *s = opaque; | |
596 | ||
05b4940b PM |
597 | return parallel_ioport_read_sw(s, addr >> s->it_shift) & |
598 | MAKE_64BIT_MASK(0, size * 8); | |
d60532ca TS |
599 | } |
600 | ||
05b4940b PM |
601 | static void parallel_mm_writefn(void *opaque, hwaddr addr, |
602 | uint64_t value, unsigned size) | |
d60532ca TS |
603 | { |
604 | ParallelState *s = opaque; | |
605 | ||
05b4940b PM |
606 | parallel_ioport_write_sw(s, addr >> s->it_shift, |
607 | value & MAKE_64BIT_MASK(0, size * 8)); | |
d60532ca TS |
608 | } |
609 | ||
63858cd9 | 610 | static const MemoryRegionOps parallel_mm_ops = { |
05b4940b PM |
611 | .read = parallel_mm_readfn, |
612 | .write = parallel_mm_writefn, | |
613 | .valid.min_access_size = 1, | |
614 | .valid.max_access_size = 4, | |
63858cd9 | 615 | .endianness = DEVICE_NATIVE_ENDIAN, |
d60532ca TS |
616 | }; |
617 | ||
618 | /* If fd is zero, it means that the parallel device uses the console */ | |
63858cd9 | 619 | bool parallel_mm_init(MemoryRegion *address_space, |
a8170e5e | 620 | hwaddr base, int it_shift, qemu_irq irq, |
0ec7b3e7 | 621 | Chardev *chr) |
d60532ca TS |
622 | { |
623 | ParallelState *s; | |
d60532ca | 624 | |
7267c094 | 625 | s = g_malloc0(sizeof(ParallelState)); |
33093a0a | 626 | s->irq = irq; |
becdfa00 | 627 | qemu_chr_fe_init(&s->chr, chr, &error_abort); |
d60532ca | 628 | s->it_shift = it_shift; |
a08d4367 | 629 | qemu_register_reset(parallel_reset, s); |
d60532ca | 630 | |
2c9b15ca | 631 | memory_region_init_io(&s->iomem, NULL, ¶llel_mm_ops, s, |
63858cd9 AK |
632 | "parallel", 8 << it_shift); |
633 | memory_region_add_subregion(address_space, base, &s->iomem); | |
defdb20e | 634 | return true; |
d60532ca | 635 | } |
021f0674 | 636 | |
39bffca2 AL |
637 | static Property parallel_isa_properties[] = { |
638 | DEFINE_PROP_UINT32("index", ISAParallelState, index, -1), | |
c7bcc85d | 639 | DEFINE_PROP_UINT32("iobase", ISAParallelState, iobase, -1), |
39bffca2 AL |
640 | DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7), |
641 | DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr), | |
642 | DEFINE_PROP_END_OF_LIST(), | |
643 | }; | |
644 | ||
8f04ee08 AL |
645 | static void parallel_isa_class_initfn(ObjectClass *klass, void *data) |
646 | { | |
39bffca2 | 647 | DeviceClass *dc = DEVICE_CLASS(klass); |
ed003c8c | 648 | ISADeviceClass *isa = ISA_DEVICE_CLASS(klass); |
db895a1e AF |
649 | |
650 | dc->realize = parallel_isa_realizefn; | |
461a2753 | 651 | dc->vmsd = &vmstate_parallel_isa; |
ed003c8c | 652 | isa->build_aml = parallel_isa_build_aml; |
4f67d30b | 653 | device_class_set_props(dc, parallel_isa_properties); |
125ee0ed | 654 | set_bit(DEVICE_CATEGORY_INPUT, dc->categories); |
8f04ee08 AL |
655 | } |
656 | ||
8c43a6f0 | 657 | static const TypeInfo parallel_isa_info = { |
b0dc5ee6 | 658 | .name = TYPE_ISA_PARALLEL, |
39bffca2 AL |
659 | .parent = TYPE_ISA_DEVICE, |
660 | .instance_size = sizeof(ISAParallelState), | |
661 | .class_init = parallel_isa_class_initfn, | |
021f0674 GH |
662 | }; |
663 | ||
83f7d43a | 664 | static void parallel_register_types(void) |
021f0674 | 665 | { |
39bffca2 | 666 | type_register_static(¶llel_isa_info); |
021f0674 GH |
667 | } |
668 | ||
83f7d43a | 669 | type_init(parallel_register_types) |