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Commit | Line | Data |
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6508fe59 FB |
1 | /* |
2 | * QEMU Parallel PORT emulation | |
5fafdf24 | 3 | * |
e57a8c0e | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
5867c88a | 5 | * Copyright (c) 2007 Marko Kohtala |
5fafdf24 | 6 | * |
6508fe59 FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
b6a0aa05 | 25 | #include "qemu/osdep.h" |
da34e65c | 26 | #include "qapi/error.h" |
83c9f4ca | 27 | #include "hw/hw.h" |
7566c6ef | 28 | #include "chardev/char-parallel.h" |
4d43a603 | 29 | #include "chardev/char-fe.h" |
0d09e41a PB |
30 | #include "hw/isa/isa.h" |
31 | #include "hw/i386/pc.h" | |
9c17d615 | 32 | #include "sysemu/sysemu.h" |
6508fe59 FB |
33 | |
34 | //#define DEBUG_PARALLEL | |
35 | ||
5867c88a | 36 | #ifdef DEBUG_PARALLEL |
001faf32 | 37 | #define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__) |
5867c88a | 38 | #else |
001faf32 | 39 | #define pdebug(fmt, ...) ((void)0) |
5867c88a TS |
40 | #endif |
41 | ||
42 | #define PARA_REG_DATA 0 | |
43 | #define PARA_REG_STS 1 | |
44 | #define PARA_REG_CTR 2 | |
45 | #define PARA_REG_EPP_ADDR 3 | |
46 | #define PARA_REG_EPP_DATA 4 | |
47 | ||
6508fe59 FB |
48 | /* |
49 | * These are the definitions for the Printer Status Register | |
50 | */ | |
51 | #define PARA_STS_BUSY 0x80 /* Busy complement */ | |
52 | #define PARA_STS_ACK 0x40 /* Acknowledge */ | |
53 | #define PARA_STS_PAPER 0x20 /* Out of paper */ | |
54 | #define PARA_STS_ONLINE 0x10 /* Online */ | |
55 | #define PARA_STS_ERROR 0x08 /* Error complement */ | |
5867c88a | 56 | #define PARA_STS_TMOUT 0x01 /* EPP timeout */ |
6508fe59 FB |
57 | |
58 | /* | |
59 | * These are the definitions for the Printer Control Register | |
60 | */ | |
5867c88a | 61 | #define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */ |
6508fe59 FB |
62 | #define PARA_CTR_INTEN 0x10 /* IRQ Enable */ |
63 | #define PARA_CTR_SELECT 0x08 /* Select In complement */ | |
64 | #define PARA_CTR_INIT 0x04 /* Initialize Printer complement */ | |
65 | #define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */ | |
66 | #define PARA_CTR_STROBE 0x01 /* Strobe complement */ | |
67 | ||
5867c88a TS |
68 | #define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE) |
69 | ||
defdb20e | 70 | typedef struct ParallelState { |
63858cd9 | 71 | MemoryRegion iomem; |
5867c88a TS |
72 | uint8_t dataw; |
73 | uint8_t datar; | |
74 | uint8_t status; | |
6508fe59 | 75 | uint8_t control; |
d537cf6c | 76 | qemu_irq irq; |
6508fe59 | 77 | int irq_pending; |
becdfa00 | 78 | CharBackend chr; |
e57a8c0e | 79 | int hw_driver; |
5867c88a TS |
80 | int epp_timeout; |
81 | uint32_t last_read_offset; /* For debugging */ | |
d60532ca | 82 | /* Memory-mapped interface */ |
d60532ca | 83 | int it_shift; |
e305a165 | 84 | PortioList portio_list; |
defdb20e | 85 | } ParallelState; |
6508fe59 | 86 | |
b0dc5ee6 AF |
87 | #define TYPE_ISA_PARALLEL "isa-parallel" |
88 | #define ISA_PARALLEL(obj) \ | |
89 | OBJECT_CHECK(ISAParallelState, (obj), TYPE_ISA_PARALLEL) | |
90 | ||
021f0674 | 91 | typedef struct ISAParallelState { |
b0dc5ee6 AF |
92 | ISADevice parent_obj; |
93 | ||
e8ee28fb | 94 | uint32_t index; |
021f0674 GH |
95 | uint32_t iobase; |
96 | uint32_t isairq; | |
97 | ParallelState state; | |
98 | } ISAParallelState; | |
99 | ||
6508fe59 FB |
100 | static void parallel_update_irq(ParallelState *s) |
101 | { | |
102 | if (s->irq_pending) | |
d537cf6c | 103 | qemu_irq_raise(s->irq); |
6508fe59 | 104 | else |
d537cf6c | 105 | qemu_irq_lower(s->irq); |
6508fe59 FB |
106 | } |
107 | ||
5867c88a TS |
108 | static void |
109 | parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val) | |
6508fe59 FB |
110 | { |
111 | ParallelState *s = opaque; | |
3b46e624 | 112 | |
5867c88a TS |
113 | pdebug("write addr=0x%02x val=0x%02x\n", addr, val); |
114 | ||
115 | addr &= 7; | |
116 | switch(addr) { | |
117 | case PARA_REG_DATA: | |
0fa7f157 TS |
118 | s->dataw = val; |
119 | parallel_update_irq(s); | |
5867c88a TS |
120 | break; |
121 | case PARA_REG_CTR: | |
52ccc5e0 | 122 | val |= 0xc0; |
0fa7f157 TS |
123 | if ((val & PARA_CTR_INIT) == 0 ) { |
124 | s->status = PARA_STS_BUSY; | |
125 | s->status |= PARA_STS_ACK; | |
126 | s->status |= PARA_STS_ONLINE; | |
127 | s->status |= PARA_STS_ERROR; | |
128 | } | |
129 | else if (val & PARA_CTR_SELECT) { | |
130 | if (val & PARA_CTR_STROBE) { | |
131 | s->status &= ~PARA_STS_BUSY; | |
132 | if ((s->control & PARA_CTR_STROBE) == 0) | |
6ab3fc32 DB |
133 | /* XXX this blocks entire thread. Rewrite to use |
134 | * qemu_chr_fe_write and background I/O callbacks */ | |
5345fdb4 | 135 | qemu_chr_fe_write_all(&s->chr, &s->dataw, 1); |
0fa7f157 TS |
136 | } else { |
137 | if (s->control & PARA_CTR_INTEN) { | |
138 | s->irq_pending = 1; | |
139 | } | |
140 | } | |
141 | } | |
142 | parallel_update_irq(s); | |
143 | s->control = val; | |
5867c88a TS |
144 | break; |
145 | } | |
146 | } | |
147 | ||
148 | static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val) | |
149 | { | |
150 | ParallelState *s = opaque; | |
151 | uint8_t parm = val; | |
563e3c6e | 152 | int dir; |
5867c88a TS |
153 | |
154 | /* Sometimes programs do several writes for timing purposes on old | |
155 | HW. Take care not to waste time on writes that do nothing. */ | |
156 | ||
157 | s->last_read_offset = ~0U; | |
158 | ||
6508fe59 | 159 | addr &= 7; |
6508fe59 | 160 | switch(addr) { |
5867c88a TS |
161 | case PARA_REG_DATA: |
162 | if (s->dataw == val) | |
0fa7f157 TS |
163 | return; |
164 | pdebug("wd%02x\n", val); | |
5345fdb4 | 165 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm); |
0fa7f157 | 166 | s->dataw = val; |
6508fe59 | 167 | break; |
5867c88a | 168 | case PARA_REG_STS: |
0fa7f157 TS |
169 | pdebug("ws%02x\n", val); |
170 | if (val & PARA_STS_TMOUT) | |
171 | s->epp_timeout = 0; | |
172 | break; | |
5867c88a TS |
173 | case PARA_REG_CTR: |
174 | val |= 0xc0; | |
175 | if (s->control == val) | |
0fa7f157 TS |
176 | return; |
177 | pdebug("wc%02x\n", val); | |
563e3c6e AJ |
178 | |
179 | if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) { | |
180 | if (val & PARA_CTR_DIR) { | |
181 | dir = 1; | |
182 | } else { | |
183 | dir = 0; | |
184 | } | |
5345fdb4 | 185 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_DATA_DIR, &dir); |
563e3c6e AJ |
186 | parm &= ~PARA_CTR_DIR; |
187 | } | |
188 | ||
5345fdb4 | 189 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm); |
0fa7f157 | 190 | s->control = val; |
6508fe59 | 191 | break; |
5867c88a | 192 | case PARA_REG_EPP_ADDR: |
0fa7f157 TS |
193 | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) |
194 | /* Controls not correct for EPP address cycle, so do nothing */ | |
195 | pdebug("wa%02x s\n", val); | |
196 | else { | |
197 | struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; | |
5345fdb4 | 198 | if (qemu_chr_fe_ioctl(&s->chr, |
becdfa00 | 199 | CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) { |
0fa7f157 TS |
200 | s->epp_timeout = 1; |
201 | pdebug("wa%02x t\n", val); | |
202 | } | |
203 | else | |
204 | pdebug("wa%02x\n", val); | |
205 | } | |
206 | break; | |
5867c88a | 207 | case PARA_REG_EPP_DATA: |
0fa7f157 TS |
208 | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) |
209 | /* Controls not correct for EPP data cycle, so do nothing */ | |
210 | pdebug("we%02x s\n", val); | |
211 | else { | |
212 | struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 }; | |
5345fdb4 | 213 | if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) { |
0fa7f157 TS |
214 | s->epp_timeout = 1; |
215 | pdebug("we%02x t\n", val); | |
216 | } | |
217 | else | |
218 | pdebug("we%02x\n", val); | |
219 | } | |
220 | break; | |
5867c88a TS |
221 | } |
222 | } | |
223 | ||
224 | static void | |
225 | parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val) | |
226 | { | |
227 | ParallelState *s = opaque; | |
228 | uint16_t eppdata = cpu_to_le16(val); | |
229 | int err; | |
230 | struct ParallelIOArg ioarg = { | |
0fa7f157 | 231 | .buffer = &eppdata, .count = sizeof(eppdata) |
5867c88a TS |
232 | }; |
233 | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) { | |
0fa7f157 TS |
234 | /* Controls not correct for EPP data cycle, so do nothing */ |
235 | pdebug("we%04x s\n", val); | |
236 | return; | |
5867c88a | 237 | } |
5345fdb4 | 238 | err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); |
5867c88a | 239 | if (err) { |
0fa7f157 TS |
240 | s->epp_timeout = 1; |
241 | pdebug("we%04x t\n", val); | |
5867c88a TS |
242 | } |
243 | else | |
0fa7f157 | 244 | pdebug("we%04x\n", val); |
5867c88a TS |
245 | } |
246 | ||
247 | static void | |
248 | parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val) | |
249 | { | |
250 | ParallelState *s = opaque; | |
251 | uint32_t eppdata = cpu_to_le32(val); | |
252 | int err; | |
253 | struct ParallelIOArg ioarg = { | |
0fa7f157 | 254 | .buffer = &eppdata, .count = sizeof(eppdata) |
5867c88a TS |
255 | }; |
256 | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) { | |
0fa7f157 TS |
257 | /* Controls not correct for EPP data cycle, so do nothing */ |
258 | pdebug("we%08x s\n", val); | |
259 | return; | |
5867c88a | 260 | } |
5345fdb4 | 261 | err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg); |
5867c88a | 262 | if (err) { |
0fa7f157 TS |
263 | s->epp_timeout = 1; |
264 | pdebug("we%08x t\n", val); | |
6508fe59 | 265 | } |
5867c88a | 266 | else |
0fa7f157 | 267 | pdebug("we%08x\n", val); |
6508fe59 FB |
268 | } |
269 | ||
5867c88a | 270 | static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr) |
6508fe59 FB |
271 | { |
272 | ParallelState *s = opaque; | |
273 | uint32_t ret = 0xff; | |
274 | ||
275 | addr &= 7; | |
276 | switch(addr) { | |
5867c88a | 277 | case PARA_REG_DATA: |
0fa7f157 TS |
278 | if (s->control & PARA_CTR_DIR) |
279 | ret = s->datar; | |
280 | else | |
281 | ret = s->dataw; | |
6508fe59 | 282 | break; |
5867c88a | 283 | case PARA_REG_STS: |
0fa7f157 TS |
284 | ret = s->status; |
285 | s->irq_pending = 0; | |
286 | if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) { | |
287 | /* XXX Fixme: wait 5 microseconds */ | |
288 | if (s->status & PARA_STS_ACK) | |
289 | s->status &= ~PARA_STS_ACK; | |
290 | else { | |
291 | /* XXX Fixme: wait 5 microseconds */ | |
292 | s->status |= PARA_STS_ACK; | |
293 | s->status |= PARA_STS_BUSY; | |
294 | } | |
295 | } | |
296 | parallel_update_irq(s); | |
6508fe59 | 297 | break; |
5867c88a | 298 | case PARA_REG_CTR: |
6508fe59 FB |
299 | ret = s->control; |
300 | break; | |
301 | } | |
5867c88a TS |
302 | pdebug("read addr=0x%02x val=0x%02x\n", addr, ret); |
303 | return ret; | |
304 | } | |
305 | ||
306 | static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr) | |
307 | { | |
308 | ParallelState *s = opaque; | |
309 | uint8_t ret = 0xff; | |
310 | addr &= 7; | |
311 | switch(addr) { | |
312 | case PARA_REG_DATA: | |
5345fdb4 | 313 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_DATA, &ret); |
0fa7f157 TS |
314 | if (s->last_read_offset != addr || s->datar != ret) |
315 | pdebug("rd%02x\n", ret); | |
5867c88a TS |
316 | s->datar = ret; |
317 | break; | |
318 | case PARA_REG_STS: | |
5345fdb4 | 319 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &ret); |
0fa7f157 TS |
320 | ret &= ~PARA_STS_TMOUT; |
321 | if (s->epp_timeout) | |
322 | ret |= PARA_STS_TMOUT; | |
323 | if (s->last_read_offset != addr || s->status != ret) | |
324 | pdebug("rs%02x\n", ret); | |
325 | s->status = ret; | |
5867c88a TS |
326 | break; |
327 | case PARA_REG_CTR: | |
328 | /* s->control has some bits fixed to 1. It is zero only when | |
0fa7f157 TS |
329 | it has not been yet written to. */ |
330 | if (s->control == 0) { | |
5345fdb4 | 331 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret); |
0fa7f157 TS |
332 | if (s->last_read_offset != addr) |
333 | pdebug("rc%02x\n", ret); | |
334 | s->control = ret; | |
335 | } | |
336 | else { | |
337 | ret = s->control; | |
338 | if (s->last_read_offset != addr) | |
339 | pdebug("rc%02x\n", ret); | |
340 | } | |
5867c88a TS |
341 | break; |
342 | case PARA_REG_EPP_ADDR: | |
becdfa00 MAL |
343 | if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) != |
344 | (PARA_CTR_DIR | PARA_CTR_INIT)) | |
0fa7f157 TS |
345 | /* Controls not correct for EPP addr cycle, so do nothing */ |
346 | pdebug("ra%02x s\n", ret); | |
347 | else { | |
348 | struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; | |
5345fdb4 | 349 | if (qemu_chr_fe_ioctl(&s->chr, |
becdfa00 | 350 | CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) { |
0fa7f157 TS |
351 | s->epp_timeout = 1; |
352 | pdebug("ra%02x t\n", ret); | |
353 | } | |
354 | else | |
355 | pdebug("ra%02x\n", ret); | |
356 | } | |
357 | break; | |
5867c88a | 358 | case PARA_REG_EPP_DATA: |
becdfa00 MAL |
359 | if ((s->control & (PARA_CTR_DIR | PARA_CTR_SIGNAL)) != |
360 | (PARA_CTR_DIR | PARA_CTR_INIT)) | |
0fa7f157 TS |
361 | /* Controls not correct for EPP data cycle, so do nothing */ |
362 | pdebug("re%02x s\n", ret); | |
363 | else { | |
364 | struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 }; | |
5345fdb4 | 365 | if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) { |
0fa7f157 TS |
366 | s->epp_timeout = 1; |
367 | pdebug("re%02x t\n", ret); | |
368 | } | |
369 | else | |
370 | pdebug("re%02x\n", ret); | |
371 | } | |
372 | break; | |
5867c88a TS |
373 | } |
374 | s->last_read_offset = addr; | |
375 | return ret; | |
376 | } | |
377 | ||
378 | static uint32_t | |
379 | parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr) | |
380 | { | |
381 | ParallelState *s = opaque; | |
382 | uint32_t ret; | |
383 | uint16_t eppdata = ~0; | |
384 | int err; | |
385 | struct ParallelIOArg ioarg = { | |
0fa7f157 | 386 | .buffer = &eppdata, .count = sizeof(eppdata) |
5867c88a TS |
387 | }; |
388 | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) { | |
0fa7f157 TS |
389 | /* Controls not correct for EPP data cycle, so do nothing */ |
390 | pdebug("re%04x s\n", eppdata); | |
391 | return eppdata; | |
5867c88a | 392 | } |
5345fdb4 | 393 | err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); |
5867c88a TS |
394 | ret = le16_to_cpu(eppdata); |
395 | ||
396 | if (err) { | |
0fa7f157 TS |
397 | s->epp_timeout = 1; |
398 | pdebug("re%04x t\n", ret); | |
5867c88a TS |
399 | } |
400 | else | |
0fa7f157 | 401 | pdebug("re%04x\n", ret); |
5867c88a TS |
402 | return ret; |
403 | } | |
404 | ||
405 | static uint32_t | |
406 | parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr) | |
407 | { | |
408 | ParallelState *s = opaque; | |
409 | uint32_t ret; | |
410 | uint32_t eppdata = ~0U; | |
411 | int err; | |
412 | struct ParallelIOArg ioarg = { | |
0fa7f157 | 413 | .buffer = &eppdata, .count = sizeof(eppdata) |
5867c88a TS |
414 | }; |
415 | if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) { | |
0fa7f157 TS |
416 | /* Controls not correct for EPP data cycle, so do nothing */ |
417 | pdebug("re%08x s\n", eppdata); | |
418 | return eppdata; | |
5867c88a | 419 | } |
5345fdb4 | 420 | err = qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg); |
5867c88a TS |
421 | ret = le32_to_cpu(eppdata); |
422 | ||
423 | if (err) { | |
0fa7f157 TS |
424 | s->epp_timeout = 1; |
425 | pdebug("re%08x t\n", ret); | |
5867c88a TS |
426 | } |
427 | else | |
0fa7f157 | 428 | pdebug("re%08x\n", ret); |
5867c88a TS |
429 | return ret; |
430 | } | |
431 | ||
432 | static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val) | |
433 | { | |
7f5b7d3e | 434 | pdebug("wecp%d=%02x\n", addr & 7, val); |
5867c88a TS |
435 | } |
436 | ||
437 | static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr) | |
438 | { | |
439 | uint8_t ret = 0xff; | |
7f5b7d3e BS |
440 | |
441 | pdebug("recp%d:%02x\n", addr & 7, ret); | |
6508fe59 FB |
442 | return ret; |
443 | } | |
444 | ||
33093a0a | 445 | static void parallel_reset(void *opaque) |
6508fe59 | 446 | { |
33093a0a AJ |
447 | ParallelState *s = opaque; |
448 | ||
5867c88a TS |
449 | s->datar = ~0; |
450 | s->dataw = ~0; | |
6508fe59 FB |
451 | s->status = PARA_STS_BUSY; |
452 | s->status |= PARA_STS_ACK; | |
453 | s->status |= PARA_STS_ONLINE; | |
454 | s->status |= PARA_STS_ERROR; | |
52ccc5e0 | 455 | s->status |= PARA_STS_TMOUT; |
6508fe59 FB |
456 | s->control = PARA_CTR_SELECT; |
457 | s->control |= PARA_CTR_INIT; | |
52ccc5e0 | 458 | s->control |= 0xc0; |
5867c88a | 459 | s->irq_pending = 0; |
5867c88a TS |
460 | s->hw_driver = 0; |
461 | s->epp_timeout = 0; | |
462 | s->last_read_offset = ~0U; | |
d60532ca TS |
463 | } |
464 | ||
e8ee28fb GH |
465 | static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
466 | ||
1922abd0 RH |
467 | static const MemoryRegionPortio isa_parallel_portio_hw_list[] = { |
468 | { 0, 8, 1, | |
469 | .read = parallel_ioport_read_hw, | |
470 | .write = parallel_ioport_write_hw }, | |
471 | { 4, 1, 2, | |
472 | .read = parallel_ioport_eppdata_read_hw2, | |
473 | .write = parallel_ioport_eppdata_write_hw2 }, | |
474 | { 4, 1, 4, | |
475 | .read = parallel_ioport_eppdata_read_hw4, | |
476 | .write = parallel_ioport_eppdata_write_hw4 }, | |
477 | { 0x400, 8, 1, | |
478 | .read = parallel_ioport_ecp_read, | |
479 | .write = parallel_ioport_ecp_write }, | |
480 | PORTIO_END_OF_LIST(), | |
481 | }; | |
482 | ||
483 | static const MemoryRegionPortio isa_parallel_portio_sw_list[] = { | |
484 | { 0, 8, 1, | |
485 | .read = parallel_ioport_read_sw, | |
486 | .write = parallel_ioport_write_sw }, | |
487 | PORTIO_END_OF_LIST(), | |
488 | }; | |
489 | ||
461a2753 PD |
490 | |
491 | static const VMStateDescription vmstate_parallel_isa = { | |
492 | .name = "parallel_isa", | |
493 | .version_id = 1, | |
494 | .minimum_version_id = 1, | |
495 | .fields = (VMStateField[]) { | |
496 | VMSTATE_UINT8(state.dataw, ISAParallelState), | |
497 | VMSTATE_UINT8(state.datar, ISAParallelState), | |
498 | VMSTATE_UINT8(state.status, ISAParallelState), | |
499 | VMSTATE_UINT8(state.control, ISAParallelState), | |
500 | VMSTATE_INT32(state.irq_pending, ISAParallelState), | |
501 | VMSTATE_INT32(state.epp_timeout, ISAParallelState), | |
502 | VMSTATE_END_OF_LIST() | |
503 | } | |
504 | }; | |
505 | ||
506 | ||
db895a1e | 507 | static void parallel_isa_realizefn(DeviceState *dev, Error **errp) |
d60532ca | 508 | { |
e8ee28fb | 509 | static int index; |
db895a1e | 510 | ISADevice *isadev = ISA_DEVICE(dev); |
b0dc5ee6 | 511 | ISAParallelState *isa = ISA_PARALLEL(dev); |
021f0674 | 512 | ParallelState *s = &isa->state; |
e8ee28fb | 513 | int base; |
d60532ca TS |
514 | uint8_t dummy; |
515 | ||
5345fdb4 | 516 | if (!qemu_chr_fe_get_driver(&s->chr)) { |
db895a1e AF |
517 | error_setg(errp, "Can't create parallel device, empty char device"); |
518 | return; | |
021f0674 GH |
519 | } |
520 | ||
db895a1e | 521 | if (isa->index == -1) { |
e8ee28fb | 522 | isa->index = index; |
db895a1e AF |
523 | } |
524 | if (isa->index >= MAX_PARALLEL_PORTS) { | |
525 | error_setg(errp, "Max. supported number of parallel ports is %d.", | |
526 | MAX_PARALLEL_PORTS); | |
527 | return; | |
528 | } | |
529 | if (isa->iobase == -1) { | |
e8ee28fb | 530 | isa->iobase = isa_parallel_io[isa->index]; |
db895a1e | 531 | } |
e8ee28fb GH |
532 | index++; |
533 | ||
534 | base = isa->iobase; | |
db895a1e | 535 | isa_init_irq(isadev, &s->irq, isa->isairq); |
a08d4367 | 536 | qemu_register_reset(parallel_reset, s); |
6508fe59 | 537 | |
5345fdb4 | 538 | if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) { |
5867c88a | 539 | s->hw_driver = 1; |
0fa7f157 | 540 | s->status = dummy; |
5867c88a TS |
541 | } |
542 | ||
e305a165 | 543 | isa_register_portio_list(isadev, &s->portio_list, base, |
1922abd0 RH |
544 | (s->hw_driver |
545 | ? &isa_parallel_portio_hw_list[0] | |
546 | : &isa_parallel_portio_sw_list[0]), | |
547 | s, "parallel"); | |
021f0674 GH |
548 | } |
549 | ||
d60532ca | 550 | /* Memory mapped interface */ |
a8170e5e | 551 | static uint32_t parallel_mm_readb (void *opaque, hwaddr addr) |
d60532ca TS |
552 | { |
553 | ParallelState *s = opaque; | |
554 | ||
8da3ff18 | 555 | return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF; |
d60532ca TS |
556 | } |
557 | ||
9596ebb7 | 558 | static void parallel_mm_writeb (void *opaque, |
a8170e5e | 559 | hwaddr addr, uint32_t value) |
d60532ca TS |
560 | { |
561 | ParallelState *s = opaque; | |
562 | ||
8da3ff18 | 563 | parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF); |
d60532ca TS |
564 | } |
565 | ||
a8170e5e | 566 | static uint32_t parallel_mm_readw (void *opaque, hwaddr addr) |
d60532ca TS |
567 | { |
568 | ParallelState *s = opaque; | |
569 | ||
8da3ff18 | 570 | return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF; |
d60532ca TS |
571 | } |
572 | ||
9596ebb7 | 573 | static void parallel_mm_writew (void *opaque, |
a8170e5e | 574 | hwaddr addr, uint32_t value) |
d60532ca TS |
575 | { |
576 | ParallelState *s = opaque; | |
577 | ||
8da3ff18 | 578 | parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF); |
d60532ca TS |
579 | } |
580 | ||
a8170e5e | 581 | static uint32_t parallel_mm_readl (void *opaque, hwaddr addr) |
d60532ca TS |
582 | { |
583 | ParallelState *s = opaque; | |
584 | ||
8da3ff18 | 585 | return parallel_ioport_read_sw(s, addr >> s->it_shift); |
d60532ca TS |
586 | } |
587 | ||
9596ebb7 | 588 | static void parallel_mm_writel (void *opaque, |
a8170e5e | 589 | hwaddr addr, uint32_t value) |
d60532ca TS |
590 | { |
591 | ParallelState *s = opaque; | |
592 | ||
8da3ff18 | 593 | parallel_ioport_write_sw(s, addr >> s->it_shift, value); |
d60532ca TS |
594 | } |
595 | ||
63858cd9 AK |
596 | static const MemoryRegionOps parallel_mm_ops = { |
597 | .old_mmio = { | |
598 | .read = { parallel_mm_readb, parallel_mm_readw, parallel_mm_readl }, | |
599 | .write = { parallel_mm_writeb, parallel_mm_writew, parallel_mm_writel }, | |
600 | }, | |
601 | .endianness = DEVICE_NATIVE_ENDIAN, | |
d60532ca TS |
602 | }; |
603 | ||
604 | /* If fd is zero, it means that the parallel device uses the console */ | |
63858cd9 | 605 | bool parallel_mm_init(MemoryRegion *address_space, |
a8170e5e | 606 | hwaddr base, int it_shift, qemu_irq irq, |
0ec7b3e7 | 607 | Chardev *chr) |
d60532ca TS |
608 | { |
609 | ParallelState *s; | |
d60532ca | 610 | |
7267c094 | 611 | s = g_malloc0(sizeof(ParallelState)); |
33093a0a | 612 | s->irq = irq; |
becdfa00 | 613 | qemu_chr_fe_init(&s->chr, chr, &error_abort); |
d60532ca | 614 | s->it_shift = it_shift; |
a08d4367 | 615 | qemu_register_reset(parallel_reset, s); |
d60532ca | 616 | |
2c9b15ca | 617 | memory_region_init_io(&s->iomem, NULL, ¶llel_mm_ops, s, |
63858cd9 AK |
618 | "parallel", 8 << it_shift); |
619 | memory_region_add_subregion(address_space, base, &s->iomem); | |
defdb20e | 620 | return true; |
d60532ca | 621 | } |
021f0674 | 622 | |
39bffca2 AL |
623 | static Property parallel_isa_properties[] = { |
624 | DEFINE_PROP_UINT32("index", ISAParallelState, index, -1), | |
c7bcc85d | 625 | DEFINE_PROP_UINT32("iobase", ISAParallelState, iobase, -1), |
39bffca2 AL |
626 | DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7), |
627 | DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr), | |
628 | DEFINE_PROP_END_OF_LIST(), | |
629 | }; | |
630 | ||
8f04ee08 AL |
631 | static void parallel_isa_class_initfn(ObjectClass *klass, void *data) |
632 | { | |
39bffca2 | 633 | DeviceClass *dc = DEVICE_CLASS(klass); |
db895a1e AF |
634 | |
635 | dc->realize = parallel_isa_realizefn; | |
461a2753 | 636 | dc->vmsd = &vmstate_parallel_isa; |
39bffca2 | 637 | dc->props = parallel_isa_properties; |
125ee0ed | 638 | set_bit(DEVICE_CATEGORY_INPUT, dc->categories); |
8f04ee08 AL |
639 | } |
640 | ||
8c43a6f0 | 641 | static const TypeInfo parallel_isa_info = { |
b0dc5ee6 | 642 | .name = TYPE_ISA_PARALLEL, |
39bffca2 AL |
643 | .parent = TYPE_ISA_DEVICE, |
644 | .instance_size = sizeof(ISAParallelState), | |
645 | .class_init = parallel_isa_class_initfn, | |
021f0674 GH |
646 | }; |
647 | ||
83f7d43a | 648 | static void parallel_register_types(void) |
021f0674 | 649 | { |
39bffca2 | 650 | type_register_static(¶llel_isa_info); |
021f0674 GH |
651 | } |
652 | ||
83f7d43a | 653 | type_init(parallel_register_types) |