[mirror_qemu.git] / hw / char / serial-pci-multi.c

/*
 * QEMU 16550A multi UART emulation
 *
 * SPDX-License-Identifier: MIT
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 * Copyright (c) 2008 Citrix Systems, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/* see docs/specs/pci-serial.txt */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/char/serial.h"
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"

#define PCI_SERIAL_MAX_PORTS 4

typedef struct PCIMultiSerialState {
    PCIDevice    dev;
    MemoryRegion iobar;
    uint32_t     ports;
    char         *name[PCI_SERIAL_MAX_PORTS];
    SerialState  state[PCI_SERIAL_MAX_PORTS];
    uint32_t     level[PCI_SERIAL_MAX_PORTS];
    qemu_irq     *irqs;
    uint8_t      prog_if;
} PCIMultiSerialState;

static void multi_serial_pci_exit(PCIDevice *dev)
{
    PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
    SerialState *s;
    int i;

    for (i = 0; i < pci->ports; i++) {
        s = pci->state + i;
        qdev_unrealize(DEVICE(s));
        memory_region_del_subregion(&pci->iobar, &s->io);
        g_free(pci->name[i]);
    }
    qemu_free_irqs(pci->irqs, pci->ports);
}

static void multi_serial_irq_mux(void *opaque, int n, int level)
{
    PCIMultiSerialState *pci = opaque;
    int i, pending = 0;

    pci->level[n] = level;
    for (i = 0; i < pci->ports; i++) {
        if (pci->level[i]) {
            pending = 1;
        }
    }
    pci_set_irq(&pci->dev, pending);
}

static size_t multi_serial_get_port_count(PCIDeviceClass *pc)
{
    switch (pc->device_id) {
    case 0x0003:
        return 2;
    case 0x0004:
        return 4;
    }

    g_assert_not_reached();
}


static void multi_serial_pci_realize(PCIDevice *dev, Error **errp)
{
    PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
    PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
    SerialState *s;
    size_t i, nports = multi_serial_get_port_count(pc);

    pci->dev.config[PCI_CLASS_PROG] = pci->prog_if;
    pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
    memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * nports);
    pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar);
    pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci, nports);

    for (i = 0; i < nports; i++) {
        s = pci->state + i;
        if (!qdev_realize(DEVICE(s), NULL, errp)) {
            multi_serial_pci_exit(dev);
            return;
        }
        s->irq = pci->irqs[i];
        pci->name[i] = g_strdup_printf("uart #%zu", i + 1);
        memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s,
                              pci->name[i], 8);
        memory_region_add_subregion(&pci->iobar, 8 * i, &s->io);
        pci->ports++;
    }
}

static const VMStateDescription vmstate_pci_multi_serial = {
    .name = "pci-serial-multi",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_PCI_DEVICE(dev, PCIMultiSerialState),
        VMSTATE_STRUCT_ARRAY(state, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS,
                             0, vmstate_serial, SerialState),
        VMSTATE_UINT32_ARRAY(level, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS),
        VMSTATE_END_OF_LIST()
    }
};

static Property multi_2x_serial_pci_properties[] = {
    DEFINE_PROP_CHR("chardev1",  PCIMultiSerialState, state[0].chr),
    DEFINE_PROP_CHR("chardev2",  PCIMultiSerialState, state[1].chr),
    DEFINE_PROP_UINT8("prog_if",  PCIMultiSerialState, prog_if, 0x02),
    DEFINE_PROP_END_OF_LIST(),
};

static Property multi_4x_serial_pci_properties[] = {
    DEFINE_PROP_CHR("chardev1",  PCIMultiSerialState, state[0].chr),
    DEFINE_PROP_CHR("chardev2",  PCIMultiSerialState, state[1].chr),
    DEFINE_PROP_CHR("chardev3",  PCIMultiSerialState, state[2].chr),
    DEFINE_PROP_CHR("chardev4",  PCIMultiSerialState, state[3].chr),
    DEFINE_PROP_UINT8("prog_if",  PCIMultiSerialState, prog_if, 0x02),
    DEFINE_PROP_END_OF_LIST(),
};

static void multi_2x_serial_pci_class_initfn(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
    pc->realize = multi_serial_pci_realize;
    pc->exit = multi_serial_pci_exit;
    pc->vendor_id = PCI_VENDOR_ID_REDHAT;
    pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL2;
    pc->revision = 1;
    pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
    dc->vmsd = &vmstate_pci_multi_serial;
    device_class_set_props(dc, multi_2x_serial_pci_properties);
    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}

static void multi_4x_serial_pci_class_initfn(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
    pc->realize = multi_serial_pci_realize;
    pc->exit = multi_serial_pci_exit;
    pc->vendor_id = PCI_VENDOR_ID_REDHAT;
    pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL4;
    pc->revision = 1;
    pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
    dc->vmsd = &vmstate_pci_multi_serial;
    device_class_set_props(dc, multi_4x_serial_pci_properties);
    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}

static void multi_serial_init(Object *o)
{
    PCIDevice *dev = PCI_DEVICE(o);
    PCIMultiSerialState *pms = DO_UPCAST(PCIMultiSerialState, dev, dev);
    size_t i, nports = multi_serial_get_port_count(PCI_DEVICE_GET_CLASS(dev));

    for (i = 0; i < nports; i++) {
        object_initialize_child(o, "serial[*]", &pms->state[i], TYPE_SERIAL);
    }
}

static const TypeInfo multi_2x_serial_pci_info = {
    .name          = "pci-serial-2x",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIMultiSerialState),
    .instance_init = multi_serial_init,
    .class_init    = multi_2x_serial_pci_class_initfn,
    .interfaces = (InterfaceInfo[]) {
        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
        { },
    },
};

static const TypeInfo multi_4x_serial_pci_info = {
    .name          = "pci-serial-4x",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIMultiSerialState),
    .instance_init = multi_serial_init,
    .class_init    = multi_4x_serial_pci_class_initfn,
    .interfaces = (InterfaceInfo[]) {
        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
        { },
    },
};

static void multi_serial_pci_register_types(void)
{
    type_register_static(&multi_2x_serial_pci_info);
    type_register_static(&multi_4x_serial_pci_info);
}

type_init(multi_serial_pci_register_types)
Commit	Line	Data
d09ecd8c TH	1	/*
	2	* QEMU 16550A multi UART emulation
	3	*
	4	* SPDX-License-Identifier: MIT
	5	*
	6	* Copyright (c) 2003-2004 Fabrice Bellard
	7	* Copyright (c) 2008 Citrix Systems, Inc.
	8	*
	9	* Permission is hereby granted, free of charge, to any person obtaining a copy
	10	* of this software and associated documentation files (the "Software"), to deal
	11	* in the Software without restriction, including without limitation the rights
	12	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	13	* copies of the Software, and to permit persons to whom the Software is
	14	* furnished to do so, subject to the following conditions:
	15	*
	16	* The above copyright notice and this permission notice shall be included in
	17	* all copies or substantial portions of the Software.
	18	*
	19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	20	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	21	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	22	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	23	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	24	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	25	* THE SOFTWARE.
	26	*/
	27
	28	/* see docs/specs/pci-serial.txt */
	29
	30	#include "qemu/osdep.h"
	31	#include "qapi/error.h"
	32	#include "hw/char/serial.h"
64552b6b	33	#include "hw/irq.h"
d09ecd8c	34	#include "hw/pci/pci.h"
a27bd6c7	35	#include "hw/qdev-properties.h"
d6454270	36	#include "migration/vmstate.h"
d09ecd8c TH	37
	38	#define PCI_SERIAL_MAX_PORTS 4
	39
	40	typedef struct PCIMultiSerialState {
	41	PCIDevice dev;
	42	MemoryRegion iobar;
	43	uint32_t ports;
	44	char *name[PCI_SERIAL_MAX_PORTS];
	45	SerialState state[PCI_SERIAL_MAX_PORTS];
	46	uint32_t level[PCI_SERIAL_MAX_PORTS];
	47	qemu_irq *irqs;
	48	uint8_t prog_if;
	49	} PCIMultiSerialState;
	50
	51	static void multi_serial_pci_exit(PCIDevice *dev)
	52	{
	53	PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
	54	SerialState *s;
	55	int i;
	56
	57	for (i = 0; i < pci->ports; i++) {
	58	s = pci->state + i;
981c3dcd	59	qdev_unrealize(DEVICE(s));
d09ecd8c TH	60	memory_region_del_subregion(&pci->iobar, &s->io);
	61	g_free(pci->name[i]);
	62	}
	63	qemu_free_irqs(pci->irqs, pci->ports);
	64	}
	65
	66	static void multi_serial_irq_mux(void *opaque, int n, int level)
	67	{
	68	PCIMultiSerialState *pci = opaque;
	69	int i, pending = 0;
	70
	71	pci->level[n] = level;
	72	for (i = 0; i < pci->ports; i++) {
	73	if (pci->level[i]) {
	74	pending = 1;
	75	}
	76	}
	77	pci_set_irq(&pci->dev, pending);
	78	}
	79
4305d482 MAL	80	static size_t multi_serial_get_port_count(PCIDeviceClass *pc)
	81	{
	82	switch (pc->device_id) {
	83	case 0x0003:
	84	return 2;
	85	case 0x0004:
	86	return 4;
	87	}
	88
	89	g_assert_not_reached();
	90	}
	91
	92
d09ecd8c TH	93	static void multi_serial_pci_realize(PCIDevice dev, Error *errp)
	94	{
	95	PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
	96	PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
	97	SerialState *s;
4305d482	98	size_t i, nports = multi_serial_get_port_count(pc);
d09ecd8c TH	99
	100	pci->dev.config[PCI_CLASS_PROG] = pci->prog_if;
	101	pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
4305d482	102	memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * nports);
d09ecd8c	103	pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar);
4305d482	104	pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci, nports);
d09ecd8c	105
4305d482	106	for (i = 0; i < nports; i++) {
d09ecd8c	107	s = pci->state + i;
668f62ec	108	if (!qdev_realize(DEVICE(s), NULL, errp)) {
d09ecd8c TH	109	multi_serial_pci_exit(dev);
	110	return;
	111	}
	112	s->irq = pci->irqs[i];
4305d482	113	pci->name[i] = g_strdup_printf("uart #%zu", i + 1);
d09ecd8c TH	114	memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s,
	115	pci->name[i], 8);
	116	memory_region_add_subregion(&pci->iobar, 8 * i, &s->io);
	117	pci->ports++;
	118	}
	119	}
	120
	121	static const VMStateDescription vmstate_pci_multi_serial = {
	122	.name = "pci-serial-multi",
	123	.version_id = 1,
	124	.minimum_version_id = 1,
	125	.fields = (VMStateField[]) {
	126	VMSTATE_PCI_DEVICE(dev, PCIMultiSerialState),
	127	VMSTATE_STRUCT_ARRAY(state, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS,
	128	0, vmstate_serial, SerialState),
	129	VMSTATE_UINT32_ARRAY(level, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS),
	130	VMSTATE_END_OF_LIST()
	131	}
	132	};
	133
	134	static Property multi_2x_serial_pci_properties[] = {
	135	DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr),
	136	DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr),
	137	DEFINE_PROP_UINT8("prog_if", PCIMultiSerialState, prog_if, 0x02),
	138	DEFINE_PROP_END_OF_LIST(),
	139	};
	140
	141	static Property multi_4x_serial_pci_properties[] = {
	142	DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr),
	143	DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr),
	144	DEFINE_PROP_CHR("chardev3", PCIMultiSerialState, state[2].chr),
	145	DEFINE_PROP_CHR("chardev4", PCIMultiSerialState, state[3].chr),
	146	DEFINE_PROP_UINT8("prog_if", PCIMultiSerialState, prog_if, 0x02),
	147	DEFINE_PROP_END_OF_LIST(),
	148	};
	149
	150	static void multi_2x_serial_pci_class_initfn(ObjectClass klass, void data)
	151	{
	152	DeviceClass *dc = DEVICE_CLASS(klass);
	153	PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
	154	pc->realize = multi_serial_pci_realize;
	155	pc->exit = multi_serial_pci_exit;
	156	pc->vendor_id = PCI_VENDOR_ID_REDHAT;
	157	pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL2;
	158	pc->revision = 1;
	159	pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
	160	dc->vmsd = &vmstate_pci_multi_serial;
4f67d30b	161	device_class_set_props(dc, multi_2x_serial_pci_properties);
d09ecd8c TH	162	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
	163	}
	164
	165	static void multi_4x_serial_pci_class_initfn(ObjectClass klass, void data)
	166	{
	167	DeviceClass *dc = DEVICE_CLASS(klass);
	168	PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
	169	pc->realize = multi_serial_pci_realize;
	170	pc->exit = multi_serial_pci_exit;
	171	pc->vendor_id = PCI_VENDOR_ID_REDHAT;
	172	pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL4;
	173	pc->revision = 1;
	174	pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
	175	dc->vmsd = &vmstate_pci_multi_serial;
4f67d30b	176	device_class_set_props(dc, multi_4x_serial_pci_properties);
d09ecd8c TH	177	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
	178	}
	179
7781b88e MAL	180	static void multi_serial_init(Object *o)
	181	{
	182	PCIDevice *dev = PCI_DEVICE(o);
	183	PCIMultiSerialState *pms = DO_UPCAST(PCIMultiSerialState, dev, dev);
	184	size_t i, nports = multi_serial_get_port_count(PCI_DEVICE_GET_CLASS(dev));
	185
	186	for (i = 0; i < nports; i++) {
9fc7fc4d	187	object_initialize_child(o, "serial[*]", &pms->state[i], TYPE_SERIAL);
7781b88e MAL	188	}
	189	}
	190
d09ecd8c TH	191	static const TypeInfo multi_2x_serial_pci_info = {
	192	.name = "pci-serial-2x",
	193	.parent = TYPE_PCI_DEVICE,
	194	.instance_size = sizeof(PCIMultiSerialState),
7781b88e	195	.instance_init = multi_serial_init,
d09ecd8c TH	196	.class_init = multi_2x_serial_pci_class_initfn,
	197	.interfaces = (InterfaceInfo[]) {
	198	{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
	199	{ },
	200	},
	201	};
	202
	203	static const TypeInfo multi_4x_serial_pci_info = {
	204	.name = "pci-serial-4x",
	205	.parent = TYPE_PCI_DEVICE,
	206	.instance_size = sizeof(PCIMultiSerialState),
7781b88e	207	.instance_init = multi_serial_init,
d09ecd8c TH	208	.class_init = multi_4x_serial_pci_class_initfn,
	209	.interfaces = (InterfaceInfo[]) {
	210	{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
	211	{ },
	212	},
	213	};
	214
	215	static void multi_serial_pci_register_types(void)
	216	{
	217	type_register_static(&multi_2x_serial_pci_info);
	218	type_register_static(&multi_4x_serial_pci_info);
	219	}
	220
	221	type_init(multi_serial_pci_register_types)