[mirror_qemu.git] / hw / char / serial-pci.c

/*
 * QEMU 16550A UART emulation
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 * Copyright (c) 2008 Citrix Systems, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/* see docs/specs/pci-serial.txt */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/char/serial.h"
#include "hw/pci/pci.h"

#define PCI_SERIAL_MAX_PORTS 4

typedef struct PCISerialState {
    PCIDevice dev;
    SerialState state;
    uint8_t prog_if;
} PCISerialState;

typedef struct PCIMultiSerialState {
    PCIDevice    dev;
    MemoryRegion iobar;
    uint32_t     ports;
    char         *name[PCI_SERIAL_MAX_PORTS];
    SerialState  state[PCI_SERIAL_MAX_PORTS];
    uint32_t     level[PCI_SERIAL_MAX_PORTS];
    qemu_irq     *irqs;
    uint8_t      prog_if;
} PCIMultiSerialState;

static void multi_serial_pci_exit(PCIDevice *dev);

static void serial_pci_realize(PCIDevice *dev, Error **errp)
{
    PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev);
    SerialState *s = &pci->state;
    Error *err = NULL;

    s->baudbase = 115200;
    serial_realize_core(s, &err);
    if (err != NULL) {
        error_propagate(errp, err);
        return;
    }

    pci->dev.config[PCI_CLASS_PROG] = pci->prog_if;
    pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
    s->irq = pci_allocate_irq(&pci->dev);

    memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s, "serial", 8);
    pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
}

static void multi_serial_irq_mux(void *opaque, int n, int level)
{
    PCIMultiSerialState *pci = opaque;
    int i, pending = 0;

    pci->level[n] = level;
    for (i = 0; i < pci->ports; i++) {
        if (pci->level[i]) {
            pending = 1;
        }
    }
    pci_set_irq(&pci->dev, pending);
}

static void multi_serial_pci_realize(PCIDevice *dev, Error **errp)
{
    PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
    PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
    SerialState *s;
    Error *err = NULL;
    int i, nr_ports = 0;

    switch (pc->device_id) {
    case 0x0003:
        nr_ports = 2;
        break;
    case 0x0004:
        nr_ports = 4;
        break;
    }
    assert(nr_ports > 0);
    assert(nr_ports <= PCI_SERIAL_MAX_PORTS);

    pci->dev.config[PCI_CLASS_PROG] = pci->prog_if;
    pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
    memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * nr_ports);
    pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar);
    pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci,
                                   nr_ports);

    for (i = 0; i < nr_ports; i++) {
        s = pci->state + i;
        s->baudbase = 115200;
        serial_realize_core(s, &err);
        if (err != NULL) {
            error_propagate(errp, err);
            multi_serial_pci_exit(dev);
            return;
        }
        s->irq = pci->irqs[i];
        pci->name[i] = g_strdup_printf("uart #%d", i+1);
        memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s,
                              pci->name[i], 8);
        memory_region_add_subregion(&pci->iobar, 8 * i, &s->io);
        pci->ports++;
    }
}

static void serial_pci_exit(PCIDevice *dev)
{
    PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev);
    SerialState *s = &pci->state;

    serial_exit_core(s);
    qemu_free_irq(s->irq);
}

static void multi_serial_pci_exit(PCIDevice *dev)
{
    PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
    SerialState *s;
    int i;

    for (i = 0; i < pci->ports; i++) {
        s = pci->state + i;
        serial_exit_core(s);
        memory_region_del_subregion(&pci->iobar, &s->io);
        g_free(pci->name[i]);
    }
    qemu_free_irqs(pci->irqs, pci->ports);
}

static const VMStateDescription vmstate_pci_serial = {
    .name = "pci-serial",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_PCI_DEVICE(dev, PCISerialState),
        VMSTATE_STRUCT(state, PCISerialState, 0, vmstate_serial, SerialState),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pci_multi_serial = {
    .name = "pci-serial-multi",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_PCI_DEVICE(dev, PCIMultiSerialState),
        VMSTATE_STRUCT_ARRAY(state, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS,
                             0, vmstate_serial, SerialState),
        VMSTATE_UINT32_ARRAY(level, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS),
        VMSTATE_END_OF_LIST()
    }
};

static Property serial_pci_properties[] = {
    DEFINE_PROP_CHR("chardev",  PCISerialState, state.chr),
    DEFINE_PROP_UINT8("prog_if",  PCISerialState, prog_if, 0x02),
    DEFINE_PROP_END_OF_LIST(),
};

static Property multi_2x_serial_pci_properties[] = {
    DEFINE_PROP_CHR("chardev1",  PCIMultiSerialState, state[0].chr),
    DEFINE_PROP_CHR("chardev2",  PCIMultiSerialState, state[1].chr),
    DEFINE_PROP_UINT8("prog_if",  PCIMultiSerialState, prog_if, 0x02),
    DEFINE_PROP_END_OF_LIST(),
};

static Property multi_4x_serial_pci_properties[] = {
    DEFINE_PROP_CHR("chardev1",  PCIMultiSerialState, state[0].chr),
    DEFINE_PROP_CHR("chardev2",  PCIMultiSerialState, state[1].chr),
    DEFINE_PROP_CHR("chardev3",  PCIMultiSerialState, state[2].chr),
    DEFINE_PROP_CHR("chardev4",  PCIMultiSerialState, state[3].chr),
    DEFINE_PROP_UINT8("prog_if",  PCIMultiSerialState, prog_if, 0x02),
    DEFINE_PROP_END_OF_LIST(),
};

static void serial_pci_class_initfn(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
    pc->realize = serial_pci_realize;
    pc->exit = serial_pci_exit;
    pc->vendor_id = PCI_VENDOR_ID_REDHAT;
    pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL;
    pc->revision = 1;
    pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
    dc->vmsd = &vmstate_pci_serial;
    dc->props = serial_pci_properties;
    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}

static void multi_2x_serial_pci_class_initfn(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
    pc->realize = multi_serial_pci_realize;
    pc->exit = multi_serial_pci_exit;
    pc->vendor_id = PCI_VENDOR_ID_REDHAT;
    pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL2;
    pc->revision = 1;
    pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
    dc->vmsd = &vmstate_pci_multi_serial;
    dc->props = multi_2x_serial_pci_properties;
    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}

static void multi_4x_serial_pci_class_initfn(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
    pc->realize = multi_serial_pci_realize;
    pc->exit = multi_serial_pci_exit;
    pc->vendor_id = PCI_VENDOR_ID_REDHAT;
    pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL4;
    pc->revision = 1;
    pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
    dc->vmsd = &vmstate_pci_multi_serial;
    dc->props = multi_4x_serial_pci_properties;
    set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}

static const TypeInfo serial_pci_info = {
    .name          = "pci-serial",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCISerialState),
    .class_init    = serial_pci_class_initfn,
};

static const TypeInfo multi_2x_serial_pci_info = {
    .name          = "pci-serial-2x",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIMultiSerialState),
    .class_init    = multi_2x_serial_pci_class_initfn,
};

static const TypeInfo multi_4x_serial_pci_info = {
    .name          = "pci-serial-4x",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIMultiSerialState),
    .class_init    = multi_4x_serial_pci_class_initfn,
};

static void serial_pci_register_types(void)
{
    type_register_static(&serial_pci_info);
    type_register_static(&multi_2x_serial_pci_info);
    type_register_static(&multi_4x_serial_pci_info);
}

type_init(serial_pci_register_types)
Commit	Line	Data
419ad672 GH	1	/*
	2	* QEMU 16550A UART emulation
	3	*
	4	* Copyright (c) 2003-2004 Fabrice Bellard
	5	* Copyright (c) 2008 Citrix Systems, Inc.
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25
90734e02 GH	26	/* see docs/specs/pci-serial.txt */
90734e02 GH	27
b6a0aa05	28	#include "qemu/osdep.h"
da34e65c	29	#include "qapi/error.h"
0d09e41a	30	#include "hw/char/serial.h"
83c9f4ca	31	#include "hw/pci/pci.h"
419ad672	32
d66bbea4 GH	33	#define PCI_SERIAL_MAX_PORTS 4
d66bbea4 GH	34
419ad672 GH	35	typedef struct PCISerialState {
	36	PCIDevice dev;
	37	SerialState state;
13cc2c3e	38	uint8_t prog_if;
419ad672 GH	39	} PCISerialState;
419ad672 GH	40
d66bbea4 GH	41	typedef struct PCIMultiSerialState {
	42	PCIDevice dev;
	43	MemoryRegion iobar;
	44	uint32_t ports;
	45	char *name[PCI_SERIAL_MAX_PORTS];
	46	SerialState state[PCI_SERIAL_MAX_PORTS];
	47	uint32_t level[PCI_SERIAL_MAX_PORTS];
	48	qemu_irq *irqs;
13cc2c3e	49	uint8_t prog_if;
d66bbea4 GH	50	} PCIMultiSerialState;
d66bbea4 GH	51
a48da7b5 GH	52	static void multi_serial_pci_exit(PCIDevice *dev);
a48da7b5 GH	53
28d85904	54	static void serial_pci_realize(PCIDevice dev, Error *errp)
419ad672 GH	55	{
	56	PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev);
	57	SerialState *s = &pci->state;
db895a1e	58	Error *err = NULL;
419ad672 GH	59
419ad672 GH	60	s->baudbase = 115200;
db895a1e AF	61	serial_realize_core(s, &err);
db895a1e AF	62	if (err != NULL) {
28d85904 MA	63	error_propagate(errp, err);
28d85904 MA	64	return;
db895a1e	65	}
419ad672	66
13cc2c3e	67	pci->dev.config[PCI_CLASS_PROG] = pci->prog_if;
419ad672	68	pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
9e64f8a3	69	s->irq = pci_allocate_irq(&pci->dev);
419ad672	70
300b1fc6	71	memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s, "serial", 8);
419ad672	72	pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
419ad672 GH	73	}
419ad672 GH	74
d66bbea4 GH	75	static void multi_serial_irq_mux(void *opaque, int n, int level)
	76	{
	77	PCIMultiSerialState *pci = opaque;
	78	int i, pending = 0;
	79
	80	pci->level[n] = level;
	81	for (i = 0; i < pci->ports; i++) {
	82	if (pci->level[i]) {
	83	pending = 1;
	84	}
	85	}
9e64f8a3	86	pci_set_irq(&pci->dev, pending);
d66bbea4 GH	87	}
d66bbea4 GH	88
28d85904	89	static void multi_serial_pci_realize(PCIDevice dev, Error *errp)
d66bbea4 GH	90	{
	91	PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
	92	PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
	93	SerialState *s;
db895a1e	94	Error *err = NULL;
a48da7b5	95	int i, nr_ports = 0;
d66bbea4 GH	96
	97	switch (pc->device_id) {
	98	case 0x0003:
a48da7b5	99	nr_ports = 2;
d66bbea4 GH	100	break;
d66bbea4 GH	101	case 0x0004:
a48da7b5	102	nr_ports = 4;
d66bbea4 GH	103	break;
d66bbea4 GH	104	}
a48da7b5 GH	105	assert(nr_ports > 0);
a48da7b5 GH	106	assert(nr_ports <= PCI_SERIAL_MAX_PORTS);
d66bbea4	107
13cc2c3e	108	pci->dev.config[PCI_CLASS_PROG] = pci->prog_if;
d66bbea4	109	pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
a48da7b5	110	memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * nr_ports);
d66bbea4 GH	111	pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar);
d66bbea4 GH	112	pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci,
a48da7b5	113	nr_ports);
d66bbea4	114
a48da7b5	115	for (i = 0; i < nr_ports; i++) {
d66bbea4 GH	116	s = pci->state + i;
d66bbea4 GH	117	s->baudbase = 115200;
db895a1e AF	118	serial_realize_core(s, &err);
db895a1e AF	119	if (err != NULL) {
28d85904	120	error_propagate(errp, err);
a48da7b5	121	multi_serial_pci_exit(dev);
28d85904	122	return;
db895a1e	123	}
d66bbea4 GH	124	s->irq = pci->irqs[i];
d66bbea4 GH	125	pci->name[i] = g_strdup_printf("uart #%d", i+1);
300b1fc6 PB	126	memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s,
300b1fc6 PB	127	pci->name[i], 8);
d66bbea4	128	memory_region_add_subregion(&pci->iobar, 8 * i, &s->io);
a48da7b5	129	pci->ports++;
d66bbea4	130	}
d66bbea4 GH	131	}
d66bbea4 GH	132
419ad672 GH	133	static void serial_pci_exit(PCIDevice *dev)
	134	{
	135	PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev);
	136	SerialState *s = &pci->state;
	137
	138	serial_exit_core(s);
9e64f8a3	139	qemu_free_irq(s->irq);
419ad672 GH	140	}
419ad672 GH	141
d66bbea4 GH	142	static void multi_serial_pci_exit(PCIDevice *dev)
	143	{
	144	PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
	145	SerialState *s;
	146	int i;
	147
	148	for (i = 0; i < pci->ports; i++) {
	149	s = pci->state + i;
	150	serial_exit_core(s);
7497bce6	151	memory_region_del_subregion(&pci->iobar, &s->io);
d66bbea4 GH	152	g_free(pci->name[i]);
d66bbea4 GH	153	}
f173d57a	154	qemu_free_irqs(pci->irqs, pci->ports);
d66bbea4 GH	155	}
d66bbea4 GH	156
419ad672 GH	157	static const VMStateDescription vmstate_pci_serial = {
	158	.name = "pci-serial",
	159	.version_id = 1,
	160	.minimum_version_id = 1,
d49805ae	161	.fields = (VMStateField[]) {
419ad672 GH	162	VMSTATE_PCI_DEVICE(dev, PCISerialState),
	163	VMSTATE_STRUCT(state, PCISerialState, 0, vmstate_serial, SerialState),
	164	VMSTATE_END_OF_LIST()
	165	}
	166	};
	167
d66bbea4 GH	168	static const VMStateDescription vmstate_pci_multi_serial = {
	169	.name = "pci-serial-multi",
	170	.version_id = 1,
	171	.minimum_version_id = 1,
d49805ae	172	.fields = (VMStateField[]) {
d66bbea4 GH	173	VMSTATE_PCI_DEVICE(dev, PCIMultiSerialState),
	174	VMSTATE_STRUCT_ARRAY(state, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS,
	175	0, vmstate_serial, SerialState),
	176	VMSTATE_UINT32_ARRAY(level, PCIMultiSerialState, PCI_SERIAL_MAX_PORTS),
	177	VMSTATE_END_OF_LIST()
	178	}
	179	};
	180
419ad672 GH	181	static Property serial_pci_properties[] = {
419ad672 GH	182	DEFINE_PROP_CHR("chardev", PCISerialState, state.chr),
13cc2c3e	183	DEFINE_PROP_UINT8("prog_if", PCISerialState, prog_if, 0x02),
419ad672 GH	184	DEFINE_PROP_END_OF_LIST(),
	185	};
	186
d66bbea4 GH	187	static Property multi_2x_serial_pci_properties[] = {
	188	DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr),
	189	DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr),
13cc2c3e	190	DEFINE_PROP_UINT8("prog_if", PCIMultiSerialState, prog_if, 0x02),
d66bbea4 GH	191	DEFINE_PROP_END_OF_LIST(),
	192	};
	193
	194	static Property multi_4x_serial_pci_properties[] = {
	195	DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr),
	196	DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr),
	197	DEFINE_PROP_CHR("chardev3", PCIMultiSerialState, state[2].chr),
	198	DEFINE_PROP_CHR("chardev4", PCIMultiSerialState, state[3].chr),
13cc2c3e	199	DEFINE_PROP_UINT8("prog_if", PCIMultiSerialState, prog_if, 0x02),
d66bbea4 GH	200	DEFINE_PROP_END_OF_LIST(),
	201	};
	202
419ad672 GH	203	static void serial_pci_class_initfn(ObjectClass klass, void data)
	204	{
	205	DeviceClass *dc = DEVICE_CLASS(klass);
	206	PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
28d85904	207	pc->realize = serial_pci_realize;
419ad672	208	pc->exit = serial_pci_exit;
5c03a254 PB	209	pc->vendor_id = PCI_VENDOR_ID_REDHAT;
5c03a254 PB	210	pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL;
419ad672 GH	211	pc->revision = 1;
	212	pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
	213	dc->vmsd = &vmstate_pci_serial;
	214	dc->props = serial_pci_properties;
125ee0ed	215	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
419ad672 GH	216	}
419ad672 GH	217
d66bbea4 GH	218	static void multi_2x_serial_pci_class_initfn(ObjectClass klass, void data)
	219	{
	220	DeviceClass *dc = DEVICE_CLASS(klass);
	221	PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
28d85904	222	pc->realize = multi_serial_pci_realize;
d66bbea4	223	pc->exit = multi_serial_pci_exit;
5c03a254 PB	224	pc->vendor_id = PCI_VENDOR_ID_REDHAT;
5c03a254 PB	225	pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL2;
d66bbea4 GH	226	pc->revision = 1;
	227	pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
	228	dc->vmsd = &vmstate_pci_multi_serial;
	229	dc->props = multi_2x_serial_pci_properties;
125ee0ed	230	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
d66bbea4 GH	231	}
	232
	233	static void multi_4x_serial_pci_class_initfn(ObjectClass klass, void data)
	234	{
	235	DeviceClass *dc = DEVICE_CLASS(klass);
	236	PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
28d85904	237	pc->realize = multi_serial_pci_realize;
d66bbea4	238	pc->exit = multi_serial_pci_exit;
5c03a254 PB	239	pc->vendor_id = PCI_VENDOR_ID_REDHAT;
5c03a254 PB	240	pc->device_id = PCI_DEVICE_ID_REDHAT_SERIAL4;
d66bbea4 GH	241	pc->revision = 1;
	242	pc->class_id = PCI_CLASS_COMMUNICATION_SERIAL;
	243	dc->vmsd = &vmstate_pci_multi_serial;
	244	dc->props = multi_4x_serial_pci_properties;
125ee0ed	245	set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
d66bbea4 GH	246	}
d66bbea4 GH	247
8c43a6f0	248	static const TypeInfo serial_pci_info = {
419ad672 GH	249	.name = "pci-serial",
	250	.parent = TYPE_PCI_DEVICE,
	251	.instance_size = sizeof(PCISerialState),
	252	.class_init = serial_pci_class_initfn,
	253	};
	254
8c43a6f0	255	static const TypeInfo multi_2x_serial_pci_info = {
d66bbea4 GH	256	.name = "pci-serial-2x",
	257	.parent = TYPE_PCI_DEVICE,
	258	.instance_size = sizeof(PCIMultiSerialState),
	259	.class_init = multi_2x_serial_pci_class_initfn,
	260	};
	261
8c43a6f0	262	static const TypeInfo multi_4x_serial_pci_info = {
d66bbea4 GH	263	.name = "pci-serial-4x",
	264	.parent = TYPE_PCI_DEVICE,
	265	.instance_size = sizeof(PCIMultiSerialState),
	266	.class_init = multi_4x_serial_pci_class_initfn,
	267	};
	268
419ad672 GH	269	static void serial_pci_register_types(void)
	270	{
	271	type_register_static(&serial_pci_info);
d66bbea4 GH	272	type_register_static(&multi_2x_serial_pci_info);
d66bbea4 GH	273	type_register_static(&multi_4x_serial_pci_info);
419ad672 GH	274	}
	275
	276	type_init(serial_pci_register_types)