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Commit | Line | Data |
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80cabfad | 1 | /* |
81174dae | 2 | * QEMU 16550A UART emulation |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
81174dae | 5 | * Copyright (c) 2008 Citrix Systems, Inc. |
5fafdf24 | 6 | * |
80cabfad FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
488cb996 | 25 | |
b6a0aa05 | 26 | #include "qemu/osdep.h" |
0d09e41a | 27 | #include "hw/char/serial.h" |
dccfcd0e | 28 | #include "sysemu/char.h" |
da34e65c | 29 | #include "qapi/error.h" |
1de7afc9 | 30 | #include "qemu/timer.h" |
022c62cb | 31 | #include "exec/address-spaces.h" |
4a44d85e | 32 | #include "qemu/error-report.h" |
80cabfad FB |
33 | |
34 | //#define DEBUG_SERIAL | |
35 | ||
36 | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ | |
37 | ||
38 | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ | |
39 | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ | |
40 | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ | |
41 | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ | |
42 | ||
43 | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ | |
44 | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ | |
45 | ||
46 | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ | |
47 | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ | |
48 | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ | |
49 | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ | |
81174dae AL |
50 | #define UART_IIR_CTI 0x0C /* Character Timeout Indication */ |
51 | ||
52 | #define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */ | |
53 | #define UART_IIR_FE 0xC0 /* Fifo enabled */ | |
80cabfad FB |
54 | |
55 | /* | |
56 | * These are the definitions for the Modem Control Register | |
57 | */ | |
58 | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ | |
59 | #define UART_MCR_OUT2 0x08 /* Out2 complement */ | |
60 | #define UART_MCR_OUT1 0x04 /* Out1 complement */ | |
61 | #define UART_MCR_RTS 0x02 /* RTS complement */ | |
62 | #define UART_MCR_DTR 0x01 /* DTR complement */ | |
63 | ||
64 | /* | |
65 | * These are the definitions for the Modem Status Register | |
66 | */ | |
67 | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ | |
68 | #define UART_MSR_RI 0x40 /* Ring Indicator */ | |
69 | #define UART_MSR_DSR 0x20 /* Data Set Ready */ | |
70 | #define UART_MSR_CTS 0x10 /* Clear to Send */ | |
71 | #define UART_MSR_DDCD 0x08 /* Delta DCD */ | |
72 | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ | |
73 | #define UART_MSR_DDSR 0x02 /* Delta DSR */ | |
74 | #define UART_MSR_DCTS 0x01 /* Delta CTS */ | |
75 | #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ | |
76 | ||
77 | #define UART_LSR_TEMT 0x40 /* Transmitter empty */ | |
78 | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ | |
79 | #define UART_LSR_BI 0x10 /* Break interrupt indicator */ | |
80 | #define UART_LSR_FE 0x08 /* Frame error indicator */ | |
81 | #define UART_LSR_PE 0x04 /* Parity error indicator */ | |
82 | #define UART_LSR_OE 0x02 /* Overrun error indicator */ | |
83 | #define UART_LSR_DR 0x01 /* Receiver data ready */ | |
81174dae | 84 | #define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */ |
80cabfad | 85 | |
81174dae AL |
86 | /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */ |
87 | ||
88 | #define UART_FCR_ITL_1 0x00 /* 1 byte ITL */ | |
89 | #define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */ | |
90 | #define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */ | |
91 | #define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */ | |
92 | ||
93 | #define UART_FCR_DMS 0x08 /* DMA Mode Select */ | |
94 | #define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */ | |
95 | #define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */ | |
96 | #define UART_FCR_FE 0x01 /* FIFO Enable */ | |
97 | ||
81174dae AL |
98 | #define MAX_XMIT_RETRY 4 |
99 | ||
b6601141 MN |
100 | #ifdef DEBUG_SERIAL |
101 | #define DPRINTF(fmt, ...) \ | |
46411f86 | 102 | do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0) |
b6601141 MN |
103 | #else |
104 | #define DPRINTF(fmt, ...) \ | |
46411f86 | 105 | do {} while (0) |
b6601141 MN |
106 | #endif |
107 | ||
81174dae | 108 | static void serial_receive1(void *opaque, const uint8_t *buf, int size); |
b0585e7e | 109 | static void serial_xmit(SerialState *s); |
b2a5160c | 110 | |
8e8638fa | 111 | static inline void recv_fifo_put(SerialState *s, uint8_t chr) |
80cabfad | 112 | { |
71e605f8 | 113 | /* Receive overruns do not overwrite FIFO contents. */ |
8e8638fa PC |
114 | if (!fifo8_is_full(&s->recv_fifo)) { |
115 | fifo8_push(&s->recv_fifo, chr); | |
116 | } else { | |
71e605f8 | 117 | s->lsr |= UART_LSR_OE; |
8e8638fa | 118 | } |
81174dae | 119 | } |
6936bfe5 | 120 | |
81174dae AL |
121 | static void serial_update_irq(SerialState *s) |
122 | { | |
123 | uint8_t tmp_iir = UART_IIR_NO_INT; | |
124 | ||
81174dae AL |
125 | if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) { |
126 | tmp_iir = UART_IIR_RLSI; | |
5628a626 | 127 | } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) { |
c9a33054 AZ |
128 | /* Note that(s->ier & UART_IER_RDI) can mask this interrupt, |
129 | * this is not in the specification but is observed on existing | |
130 | * hardware. */ | |
81174dae | 131 | tmp_iir = UART_IIR_CTI; |
2d6ee8e7 JL |
132 | } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) && |
133 | (!(s->fcr & UART_FCR_FE) || | |
8e8638fa | 134 | s->recv_fifo.num >= s->recv_fifo_itl)) { |
2d6ee8e7 | 135 | tmp_iir = UART_IIR_RDI; |
81174dae AL |
136 | } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) { |
137 | tmp_iir = UART_IIR_THRI; | |
138 | } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) { | |
139 | tmp_iir = UART_IIR_MSI; | |
140 | } | |
141 | ||
142 | s->iir = tmp_iir | (s->iir & 0xF0); | |
143 | ||
144 | if (tmp_iir != UART_IIR_NO_INT) { | |
145 | qemu_irq_raise(s->irq); | |
146 | } else { | |
147 | qemu_irq_lower(s->irq); | |
6936bfe5 | 148 | } |
6936bfe5 AJ |
149 | } |
150 | ||
f8d179e3 FB |
151 | static void serial_update_parameters(SerialState *s) |
152 | { | |
81174dae | 153 | int speed, parity, data_bits, stop_bits, frame_size; |
2122c51a | 154 | QEMUSerialSetParams ssp; |
f8d179e3 | 155 | |
3592fe0c | 156 | if (s->divider == 0 || s->divider > s->baudbase) { |
81174dae | 157 | return; |
3592fe0c | 158 | } |
81174dae | 159 | |
718b8aec | 160 | /* Start bit. */ |
81174dae | 161 | frame_size = 1; |
f8d179e3 | 162 | if (s->lcr & 0x08) { |
718b8aec SW |
163 | /* Parity bit. */ |
164 | frame_size++; | |
f8d179e3 FB |
165 | if (s->lcr & 0x10) |
166 | parity = 'E'; | |
167 | else | |
168 | parity = 'O'; | |
169 | } else { | |
170 | parity = 'N'; | |
171 | } | |
5fafdf24 | 172 | if (s->lcr & 0x04) |
f8d179e3 FB |
173 | stop_bits = 2; |
174 | else | |
175 | stop_bits = 1; | |
81174dae | 176 | |
f8d179e3 | 177 | data_bits = (s->lcr & 0x03) + 5; |
81174dae | 178 | frame_size += data_bits + stop_bits; |
b6cd0ea1 | 179 | speed = s->baudbase / s->divider; |
2122c51a FB |
180 | ssp.speed = speed; |
181 | ssp.parity = parity; | |
182 | ssp.data_bits = data_bits; | |
183 | ssp.stop_bits = stop_bits; | |
73bcb24d | 184 | s->char_transmit_time = (NANOSECONDS_PER_SECOND / speed) * frame_size; |
5345fdb4 | 185 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
b6601141 MN |
186 | |
187 | DPRINTF("speed=%d parity=%c data=%d stop=%d\n", | |
f8d179e3 | 188 | speed, parity, data_bits, stop_bits); |
f8d179e3 FB |
189 | } |
190 | ||
81174dae AL |
191 | static void serial_update_msl(SerialState *s) |
192 | { | |
193 | uint8_t omsr; | |
194 | int flags; | |
195 | ||
bc72ad67 | 196 | timer_del(s->modem_status_poll); |
81174dae | 197 | |
5345fdb4 | 198 | if (qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_GET_TIOCM, |
becdfa00 | 199 | &flags) == -ENOTSUP) { |
81174dae AL |
200 | s->poll_msl = -1; |
201 | return; | |
202 | } | |
203 | ||
204 | omsr = s->msr; | |
205 | ||
206 | s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS; | |
207 | s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR; | |
208 | s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD; | |
209 | s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI; | |
210 | ||
211 | if (s->msr != omsr) { | |
212 | /* Set delta bits */ | |
213 | s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4)); | |
214 | /* UART_MSR_TERI only if change was from 1 -> 0 */ | |
215 | if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI)) | |
216 | s->msr &= ~UART_MSR_TERI; | |
217 | serial_update_irq(s); | |
218 | } | |
219 | ||
220 | /* The real 16550A apparently has a 250ns response latency to line status changes. | |
221 | We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */ | |
222 | ||
73bcb24d RS |
223 | if (s->poll_msl) { |
224 | timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + | |
225 | NANOSECONDS_PER_SECOND / 100); | |
226 | } | |
81174dae AL |
227 | } |
228 | ||
b0585e7e PB |
229 | static gboolean serial_watch_cb(GIOChannel *chan, GIOCondition cond, |
230 | void *opaque) | |
81174dae AL |
231 | { |
232 | SerialState *s = opaque; | |
a1df76da | 233 | s->watch_tag = 0; |
b0585e7e PB |
234 | serial_xmit(s); |
235 | return FALSE; | |
236 | } | |
81174dae | 237 | |
b0585e7e PB |
238 | static void serial_xmit(SerialState *s) |
239 | { | |
f702e62a | 240 | do { |
0d931d70 | 241 | assert(!(s->lsr & UART_LSR_TEMT)); |
807464d8 | 242 | if (s->tsr_retry == 0) { |
0d931d70 PB |
243 | assert(!(s->lsr & UART_LSR_THRE)); |
244 | ||
f702e62a | 245 | if (s->fcr & UART_FCR_FE) { |
0d931d70 | 246 | assert(!fifo8_is_empty(&s->xmit_fifo)); |
f702e62a KB |
247 | s->tsr = fifo8_pop(&s->xmit_fifo); |
248 | if (!s->xmit_fifo.num) { | |
249 | s->lsr |= UART_LSR_THRE; | |
250 | } | |
f702e62a KB |
251 | } else { |
252 | s->tsr = s->thr; | |
81174dae | 253 | s->lsr |= UART_LSR_THRE; |
0d931d70 PB |
254 | } |
255 | if ((s->lsr & UART_LSR_THRE) && !s->thr_ipending) { | |
256 | s->thr_ipending = 1; | |
257 | serial_update_irq(s); | |
7f4f0a22 | 258 | } |
81174dae | 259 | } |
81174dae | 260 | |
f702e62a KB |
261 | if (s->mcr & UART_MCR_LOOP) { |
262 | /* in loopback mode, say that we just received a char */ | |
263 | serial_receive1(s, &s->tsr, 1); | |
5345fdb4 | 264 | } else if (qemu_chr_fe_write(&s->chr, &s->tsr, 1) != 1 && |
a1df76da PB |
265 | s->tsr_retry < MAX_XMIT_RETRY) { |
266 | assert(s->watch_tag == 0); | |
becdfa00 | 267 | s->watch_tag = |
5345fdb4 | 268 | qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, |
becdfa00 | 269 | serial_watch_cb, s); |
a1df76da | 270 | if (s->watch_tag > 0) { |
f702e62a | 271 | s->tsr_retry++; |
b0585e7e | 272 | return; |
f702e62a | 273 | } |
81174dae | 274 | } |
bce933b8 | 275 | s->tsr_retry = 0; |
0d931d70 | 276 | |
f702e62a KB |
277 | /* Transmit another byte if it is already available. It is only |
278 | possible when FIFO is enabled and not empty. */ | |
0d931d70 | 279 | } while (!(s->lsr & UART_LSR_THRE)); |
81174dae | 280 | |
bc72ad67 | 281 | s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
0d931d70 | 282 | s->lsr |= UART_LSR_TEMT; |
81174dae AL |
283 | } |
284 | ||
7385b275 PD |
285 | /* Setter for FCR. |
286 | is_load flag means, that value is set while loading VM state | |
287 | and interrupt should not be invoked */ | |
288 | static void serial_write_fcr(SerialState *s, uint8_t val) | |
289 | { | |
290 | /* Set fcr - val only has the bits that are supposed to "stick" */ | |
291 | s->fcr = val; | |
292 | ||
293 | if (val & UART_FCR_FE) { | |
294 | s->iir |= UART_IIR_FE; | |
295 | /* Set recv_fifo trigger Level */ | |
296 | switch (val & 0xC0) { | |
297 | case UART_FCR_ITL_1: | |
298 | s->recv_fifo_itl = 1; | |
299 | break; | |
300 | case UART_FCR_ITL_2: | |
301 | s->recv_fifo_itl = 4; | |
302 | break; | |
303 | case UART_FCR_ITL_3: | |
304 | s->recv_fifo_itl = 8; | |
305 | break; | |
306 | case UART_FCR_ITL_4: | |
307 | s->recv_fifo_itl = 14; | |
308 | break; | |
309 | } | |
310 | } else { | |
311 | s->iir &= ~UART_IIR_FE; | |
312 | } | |
313 | } | |
314 | ||
5ec3a23e AG |
315 | static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val, |
316 | unsigned size) | |
80cabfad | 317 | { |
b41a2cd1 | 318 | SerialState *s = opaque; |
3b46e624 | 319 | |
80cabfad | 320 | addr &= 7; |
8b4a8988 | 321 | DPRINTF("write addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 "\n", addr, val); |
80cabfad FB |
322 | switch(addr) { |
323 | default: | |
324 | case 0: | |
325 | if (s->lcr & UART_LCR_DLAB) { | |
326 | s->divider = (s->divider & 0xff00) | val; | |
f8d179e3 | 327 | serial_update_parameters(s); |
80cabfad | 328 | } else { |
81174dae AL |
329 | s->thr = (uint8_t) val; |
330 | if(s->fcr & UART_FCR_FE) { | |
8e8638fa PC |
331 | /* xmit overruns overwrite data, so make space if needed */ |
332 | if (fifo8_is_full(&s->xmit_fifo)) { | |
333 | fifo8_pop(&s->xmit_fifo); | |
334 | } | |
335 | fifo8_push(&s->xmit_fifo, s->thr); | |
6936bfe5 | 336 | } |
b5601df7 PC |
337 | s->thr_ipending = 0; |
338 | s->lsr &= ~UART_LSR_THRE; | |
0d931d70 | 339 | s->lsr &= ~UART_LSR_TEMT; |
b5601df7 | 340 | serial_update_irq(s); |
807464d8 | 341 | if (s->tsr_retry == 0) { |
b0585e7e | 342 | serial_xmit(s); |
f702e62a | 343 | } |
80cabfad FB |
344 | } |
345 | break; | |
346 | case 1: | |
347 | if (s->lcr & UART_LCR_DLAB) { | |
348 | s->divider = (s->divider & 0x00ff) | (val << 8); | |
f8d179e3 | 349 | serial_update_parameters(s); |
80cabfad | 350 | } else { |
1645b8ee | 351 | uint8_t changed = (s->ier ^ val) & 0x0f; |
60e336db | 352 | s->ier = val & 0x0f; |
81174dae | 353 | /* If the backend device is a real serial port, turn polling of the modem |
1645b8ee PB |
354 | * status lines on physical port on or off depending on UART_IER_MSI state. |
355 | */ | |
356 | if ((changed & UART_IER_MSI) && s->poll_msl >= 0) { | |
81174dae AL |
357 | if (s->ier & UART_IER_MSI) { |
358 | s->poll_msl = 1; | |
359 | serial_update_msl(s); | |
360 | } else { | |
bc72ad67 | 361 | timer_del(s->modem_status_poll); |
81174dae AL |
362 | s->poll_msl = 0; |
363 | } | |
364 | } | |
4e02b0fc PB |
365 | |
366 | /* Turning on the THRE interrupt on IER can trigger the interrupt | |
367 | * if LSR.THRE=1, even if it had been masked before by reading IIR. | |
368 | * This is not in the datasheet, but Windows relies on it. It is | |
369 | * unclear if THRE has to be resampled every time THRI becomes | |
370 | * 1, or only on the rising edge. Bochs does the latter, and Windows | |
1645b8ee PB |
371 | * always toggles IER to all zeroes and back to all ones, so do the |
372 | * same. | |
4e02b0fc PB |
373 | * |
374 | * If IER.THRI is zero, thr_ipending is not used. Set it to zero | |
375 | * so that the thr_ipending subsection is not migrated. | |
376 | */ | |
1645b8ee PB |
377 | if (changed & UART_IER_THRI) { |
378 | if ((s->ier & UART_IER_THRI) && (s->lsr & UART_LSR_THRE)) { | |
379 | s->thr_ipending = 1; | |
380 | } else { | |
381 | s->thr_ipending = 0; | |
382 | } | |
383 | } | |
384 | ||
385 | if (changed) { | |
386 | serial_update_irq(s); | |
60e336db | 387 | } |
80cabfad FB |
388 | } |
389 | break; | |
390 | case 2: | |
81174dae | 391 | /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */ |
7385b275 | 392 | if ((val ^ s->fcr) & UART_FCR_FE) { |
81174dae | 393 | val |= UART_FCR_XFR | UART_FCR_RFR; |
7385b275 | 394 | } |
81174dae AL |
395 | |
396 | /* FIFO clear */ | |
397 | ||
398 | if (val & UART_FCR_RFR) { | |
023c3a97 | 399 | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
bc72ad67 | 400 | timer_del(s->fifo_timeout_timer); |
7385b275 | 401 | s->timeout_ipending = 0; |
8e8638fa | 402 | fifo8_reset(&s->recv_fifo); |
81174dae AL |
403 | } |
404 | ||
405 | if (val & UART_FCR_XFR) { | |
023c3a97 PB |
406 | s->lsr |= UART_LSR_THRE; |
407 | s->thr_ipending = 1; | |
8e8638fa | 408 | fifo8_reset(&s->xmit_fifo); |
81174dae AL |
409 | } |
410 | ||
7385b275 | 411 | serial_write_fcr(s, val & 0xC9); |
81174dae | 412 | serial_update_irq(s); |
80cabfad FB |
413 | break; |
414 | case 3: | |
f8d179e3 FB |
415 | { |
416 | int break_enable; | |
417 | s->lcr = val; | |
418 | serial_update_parameters(s); | |
419 | break_enable = (val >> 6) & 1; | |
420 | if (break_enable != s->last_break_enable) { | |
421 | s->last_break_enable = break_enable; | |
5345fdb4 MAL |
422 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK, |
423 | &break_enable); | |
f8d179e3 FB |
424 | } |
425 | } | |
80cabfad FB |
426 | break; |
427 | case 4: | |
81174dae AL |
428 | { |
429 | int flags; | |
430 | int old_mcr = s->mcr; | |
431 | s->mcr = val & 0x1f; | |
432 | if (val & UART_MCR_LOOP) | |
433 | break; | |
434 | ||
435 | if (s->poll_msl >= 0 && old_mcr != s->mcr) { | |
436 | ||
5345fdb4 | 437 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_GET_TIOCM, &flags); |
81174dae AL |
438 | |
439 | flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR); | |
440 | ||
441 | if (val & UART_MCR_RTS) | |
442 | flags |= CHR_TIOCM_RTS; | |
443 | if (val & UART_MCR_DTR) | |
444 | flags |= CHR_TIOCM_DTR; | |
445 | ||
5345fdb4 | 446 | qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_TIOCM, &flags); |
81174dae AL |
447 | /* Update the modem status after a one-character-send wait-time, since there may be a response |
448 | from the device/computer at the other end of the serial line */ | |
bc72ad67 | 449 | timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time); |
81174dae AL |
450 | } |
451 | } | |
80cabfad FB |
452 | break; |
453 | case 5: | |
454 | break; | |
455 | case 6: | |
80cabfad FB |
456 | break; |
457 | case 7: | |
458 | s->scr = val; | |
459 | break; | |
460 | } | |
461 | } | |
462 | ||
5ec3a23e | 463 | static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size) |
80cabfad | 464 | { |
b41a2cd1 | 465 | SerialState *s = opaque; |
80cabfad FB |
466 | uint32_t ret; |
467 | ||
468 | addr &= 7; | |
469 | switch(addr) { | |
470 | default: | |
471 | case 0: | |
472 | if (s->lcr & UART_LCR_DLAB) { | |
5fafdf24 | 473 | ret = s->divider & 0xff; |
80cabfad | 474 | } else { |
81174dae | 475 | if(s->fcr & UART_FCR_FE) { |
b165b0d8 | 476 | ret = fifo8_is_empty(&s->recv_fifo) ? |
8e8638fa PC |
477 | 0 : fifo8_pop(&s->recv_fifo); |
478 | if (s->recv_fifo.num == 0) { | |
81174dae | 479 | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
7f4f0a22 | 480 | } else { |
bc72ad67 | 481 | timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4); |
7f4f0a22 | 482 | } |
81174dae AL |
483 | s->timeout_ipending = 0; |
484 | } else { | |
485 | ret = s->rbr; | |
486 | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); | |
487 | } | |
b41a2cd1 | 488 | serial_update_irq(s); |
b2a5160c AZ |
489 | if (!(s->mcr & UART_MCR_LOOP)) { |
490 | /* in loopback mode, don't receive any data */ | |
5345fdb4 | 491 | qemu_chr_fe_accept_input(&s->chr); |
b2a5160c | 492 | } |
80cabfad FB |
493 | } |
494 | break; | |
495 | case 1: | |
496 | if (s->lcr & UART_LCR_DLAB) { | |
497 | ret = (s->divider >> 8) & 0xff; | |
498 | } else { | |
499 | ret = s->ier; | |
500 | } | |
501 | break; | |
502 | case 2: | |
503 | ret = s->iir; | |
cdee7bdf | 504 | if ((ret & UART_IIR_ID) == UART_IIR_THRI) { |
80cabfad | 505 | s->thr_ipending = 0; |
71e605f8 JG |
506 | serial_update_irq(s); |
507 | } | |
80cabfad FB |
508 | break; |
509 | case 3: | |
510 | ret = s->lcr; | |
511 | break; | |
512 | case 4: | |
513 | ret = s->mcr; | |
514 | break; | |
515 | case 5: | |
516 | ret = s->lsr; | |
71e605f8 JG |
517 | /* Clear break and overrun interrupts */ |
518 | if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) { | |
519 | s->lsr &= ~(UART_LSR_BI|UART_LSR_OE); | |
81174dae AL |
520 | serial_update_irq(s); |
521 | } | |
80cabfad FB |
522 | break; |
523 | case 6: | |
524 | if (s->mcr & UART_MCR_LOOP) { | |
525 | /* in loopback, the modem output pins are connected to the | |
526 | inputs */ | |
527 | ret = (s->mcr & 0x0c) << 4; | |
528 | ret |= (s->mcr & 0x02) << 3; | |
529 | ret |= (s->mcr & 0x01) << 5; | |
530 | } else { | |
81174dae AL |
531 | if (s->poll_msl >= 0) |
532 | serial_update_msl(s); | |
80cabfad | 533 | ret = s->msr; |
81174dae AL |
534 | /* Clear delta bits & msr int after read, if they were set */ |
535 | if (s->msr & UART_MSR_ANY_DELTA) { | |
536 | s->msr &= 0xF0; | |
537 | serial_update_irq(s); | |
538 | } | |
80cabfad FB |
539 | } |
540 | break; | |
541 | case 7: | |
542 | ret = s->scr; | |
543 | break; | |
544 | } | |
8b4a8988 | 545 | DPRINTF("read addr=0x%" HWADDR_PRIx " val=0x%02x\n", addr, ret); |
80cabfad FB |
546 | return ret; |
547 | } | |
548 | ||
82c643ff | 549 | static int serial_can_receive(SerialState *s) |
80cabfad | 550 | { |
81174dae | 551 | if(s->fcr & UART_FCR_FE) { |
8e8638fa | 552 | if (s->recv_fifo.num < UART_FIFO_LENGTH) { |
7f4f0a22 PC |
553 | /* |
554 | * Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 | |
555 | * if above. If UART_FIFO_LENGTH - fifo.count is advertised the | |
556 | * effect will be to almost always fill the fifo completely before | |
557 | * the guest has a chance to respond, effectively overriding the ITL | |
558 | * that the guest has set. | |
559 | */ | |
8e8638fa PC |
560 | return (s->recv_fifo.num <= s->recv_fifo_itl) ? |
561 | s->recv_fifo_itl - s->recv_fifo.num : 1; | |
7f4f0a22 PC |
562 | } else { |
563 | return 0; | |
564 | } | |
81174dae | 565 | } else { |
7f4f0a22 | 566 | return !(s->lsr & UART_LSR_DR); |
81174dae | 567 | } |
80cabfad FB |
568 | } |
569 | ||
82c643ff | 570 | static void serial_receive_break(SerialState *s) |
80cabfad | 571 | { |
80cabfad | 572 | s->rbr = 0; |
40ff1624 | 573 | /* When the LSR_DR is set a null byte is pushed into the fifo */ |
8e8638fa | 574 | recv_fifo_put(s, '\0'); |
80cabfad | 575 | s->lsr |= UART_LSR_BI | UART_LSR_DR; |
b41a2cd1 | 576 | serial_update_irq(s); |
80cabfad FB |
577 | } |
578 | ||
81174dae AL |
579 | /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */ |
580 | static void fifo_timeout_int (void *opaque) { | |
581 | SerialState *s = opaque; | |
8e8638fa | 582 | if (s->recv_fifo.num) { |
81174dae AL |
583 | s->timeout_ipending = 1; |
584 | serial_update_irq(s); | |
585 | } | |
586 | } | |
587 | ||
b41a2cd1 | 588 | static int serial_can_receive1(void *opaque) |
80cabfad | 589 | { |
b41a2cd1 FB |
590 | SerialState *s = opaque; |
591 | return serial_can_receive(s); | |
592 | } | |
593 | ||
594 | static void serial_receive1(void *opaque, const uint8_t *buf, int size) | |
595 | { | |
596 | SerialState *s = opaque; | |
9826fd59 GH |
597 | |
598 | if (s->wakeup) { | |
599 | qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER); | |
600 | } | |
81174dae AL |
601 | if(s->fcr & UART_FCR_FE) { |
602 | int i; | |
603 | for (i = 0; i < size; i++) { | |
8e8638fa | 604 | recv_fifo_put(s, buf[i]); |
81174dae AL |
605 | } |
606 | s->lsr |= UART_LSR_DR; | |
607 | /* call the timeout receive callback in 4 char transmit time */ | |
bc72ad67 | 608 | timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4); |
81174dae | 609 | } else { |
71e605f8 JG |
610 | if (s->lsr & UART_LSR_DR) |
611 | s->lsr |= UART_LSR_OE; | |
81174dae AL |
612 | s->rbr = buf[0]; |
613 | s->lsr |= UART_LSR_DR; | |
614 | } | |
615 | serial_update_irq(s); | |
b41a2cd1 | 616 | } |
80cabfad | 617 | |
82c643ff FB |
618 | static void serial_event(void *opaque, int event) |
619 | { | |
620 | SerialState *s = opaque; | |
b6601141 | 621 | DPRINTF("event %x\n", event); |
82c643ff FB |
622 | if (event == CHR_EVENT_BREAK) |
623 | serial_receive_break(s); | |
624 | } | |
625 | ||
d4bfa4d7 | 626 | static void serial_pre_save(void *opaque) |
8738a8d0 | 627 | { |
d4bfa4d7 | 628 | SerialState *s = opaque; |
747791f1 | 629 | s->fcr_vmstate = s->fcr; |
8738a8d0 FB |
630 | } |
631 | ||
7385b275 PD |
632 | static int serial_pre_load(void *opaque) |
633 | { | |
634 | SerialState *s = opaque; | |
635 | s->thr_ipending = -1; | |
636 | s->poll_msl = -1; | |
637 | return 0; | |
638 | } | |
639 | ||
e59fb374 | 640 | static int serial_post_load(void *opaque, int version_id) |
747791f1 JQ |
641 | { |
642 | SerialState *s = opaque; | |
81174dae | 643 | |
4c18ce94 JQ |
644 | if (version_id < 3) { |
645 | s->fcr_vmstate = 0; | |
646 | } | |
7385b275 PD |
647 | if (s->thr_ipending == -1) { |
648 | s->thr_ipending = ((s->iir & UART_IIR_ID) == UART_IIR_THRI); | |
649 | } | |
9f34a35e PB |
650 | |
651 | if (s->tsr_retry > 0) { | |
652 | /* tsr_retry > 0 implies LSR.TEMT = 0 (transmitter not empty). */ | |
653 | if (s->lsr & UART_LSR_TEMT) { | |
654 | error_report("inconsistent state in serial device " | |
655 | "(tsr empty, tsr_retry=%d", s->tsr_retry); | |
656 | return -1; | |
657 | } | |
658 | ||
659 | if (s->tsr_retry > MAX_XMIT_RETRY) { | |
660 | s->tsr_retry = MAX_XMIT_RETRY; | |
661 | } | |
662 | ||
663 | assert(s->watch_tag == 0); | |
5345fdb4 | 664 | s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP, |
9f34a35e PB |
665 | serial_watch_cb, s); |
666 | } else { | |
667 | /* tsr_retry == 0 implies LSR.TEMT = 1 (transmitter empty). */ | |
668 | if (!(s->lsr & UART_LSR_TEMT)) { | |
669 | error_report("inconsistent state in serial device " | |
670 | "(tsr not empty, tsr_retry=0"); | |
671 | return -1; | |
672 | } | |
807464d8 PB |
673 | } |
674 | ||
7385b275 | 675 | s->last_break_enable = (s->lcr >> 6) & 1; |
81174dae | 676 | /* Initialize fcr via setter to perform essential side-effects */ |
7385b275 | 677 | serial_write_fcr(s, s->fcr_vmstate); |
9a7c4878 | 678 | serial_update_parameters(s); |
8738a8d0 FB |
679 | return 0; |
680 | } | |
681 | ||
7385b275 PD |
682 | static bool serial_thr_ipending_needed(void *opaque) |
683 | { | |
684 | SerialState *s = opaque; | |
bfa73628 PB |
685 | |
686 | if (s->ier & UART_IER_THRI) { | |
687 | bool expected_value = ((s->iir & UART_IIR_ID) == UART_IIR_THRI); | |
688 | return s->thr_ipending != expected_value; | |
689 | } else { | |
690 | /* LSR.THRE will be sampled again when the interrupt is | |
691 | * enabled. thr_ipending is not used in this case, do | |
692 | * not migrate it. | |
693 | */ | |
694 | return false; | |
695 | } | |
7385b275 PD |
696 | } |
697 | ||
92013cf8 | 698 | static const VMStateDescription vmstate_serial_thr_ipending = { |
7385b275 PD |
699 | .name = "serial/thr_ipending", |
700 | .version_id = 1, | |
701 | .minimum_version_id = 1, | |
5cd8cada | 702 | .needed = serial_thr_ipending_needed, |
7385b275 PD |
703 | .fields = (VMStateField[]) { |
704 | VMSTATE_INT32(thr_ipending, SerialState), | |
705 | VMSTATE_END_OF_LIST() | |
706 | } | |
707 | }; | |
708 | ||
709 | static bool serial_tsr_needed(void *opaque) | |
710 | { | |
711 | SerialState *s = (SerialState *)opaque; | |
712 | return s->tsr_retry != 0; | |
713 | } | |
714 | ||
92013cf8 | 715 | static const VMStateDescription vmstate_serial_tsr = { |
7385b275 PD |
716 | .name = "serial/tsr", |
717 | .version_id = 1, | |
718 | .minimum_version_id = 1, | |
5cd8cada | 719 | .needed = serial_tsr_needed, |
7385b275 | 720 | .fields = (VMStateField[]) { |
807464d8 | 721 | VMSTATE_UINT32(tsr_retry, SerialState), |
7385b275 PD |
722 | VMSTATE_UINT8(thr, SerialState), |
723 | VMSTATE_UINT8(tsr, SerialState), | |
724 | VMSTATE_END_OF_LIST() | |
725 | } | |
726 | }; | |
727 | ||
728 | static bool serial_recv_fifo_needed(void *opaque) | |
729 | { | |
730 | SerialState *s = (SerialState *)opaque; | |
731 | return !fifo8_is_empty(&s->recv_fifo); | |
732 | ||
733 | } | |
734 | ||
92013cf8 | 735 | static const VMStateDescription vmstate_serial_recv_fifo = { |
7385b275 PD |
736 | .name = "serial/recv_fifo", |
737 | .version_id = 1, | |
738 | .minimum_version_id = 1, | |
5cd8cada | 739 | .needed = serial_recv_fifo_needed, |
7385b275 PD |
740 | .fields = (VMStateField[]) { |
741 | VMSTATE_STRUCT(recv_fifo, SerialState, 1, vmstate_fifo8, Fifo8), | |
742 | VMSTATE_END_OF_LIST() | |
743 | } | |
744 | }; | |
745 | ||
746 | static bool serial_xmit_fifo_needed(void *opaque) | |
747 | { | |
748 | SerialState *s = (SerialState *)opaque; | |
749 | return !fifo8_is_empty(&s->xmit_fifo); | |
750 | } | |
751 | ||
92013cf8 | 752 | static const VMStateDescription vmstate_serial_xmit_fifo = { |
7385b275 PD |
753 | .name = "serial/xmit_fifo", |
754 | .version_id = 1, | |
755 | .minimum_version_id = 1, | |
5cd8cada | 756 | .needed = serial_xmit_fifo_needed, |
7385b275 PD |
757 | .fields = (VMStateField[]) { |
758 | VMSTATE_STRUCT(xmit_fifo, SerialState, 1, vmstate_fifo8, Fifo8), | |
759 | VMSTATE_END_OF_LIST() | |
760 | } | |
761 | }; | |
762 | ||
763 | static bool serial_fifo_timeout_timer_needed(void *opaque) | |
764 | { | |
765 | SerialState *s = (SerialState *)opaque; | |
766 | return timer_pending(s->fifo_timeout_timer); | |
767 | } | |
768 | ||
92013cf8 | 769 | static const VMStateDescription vmstate_serial_fifo_timeout_timer = { |
7385b275 PD |
770 | .name = "serial/fifo_timeout_timer", |
771 | .version_id = 1, | |
772 | .minimum_version_id = 1, | |
5cd8cada | 773 | .needed = serial_fifo_timeout_timer_needed, |
7385b275 | 774 | .fields = (VMStateField[]) { |
e720677e | 775 | VMSTATE_TIMER_PTR(fifo_timeout_timer, SerialState), |
7385b275 PD |
776 | VMSTATE_END_OF_LIST() |
777 | } | |
778 | }; | |
779 | ||
780 | static bool serial_timeout_ipending_needed(void *opaque) | |
781 | { | |
782 | SerialState *s = (SerialState *)opaque; | |
783 | return s->timeout_ipending != 0; | |
784 | } | |
785 | ||
92013cf8 | 786 | static const VMStateDescription vmstate_serial_timeout_ipending = { |
7385b275 PD |
787 | .name = "serial/timeout_ipending", |
788 | .version_id = 1, | |
789 | .minimum_version_id = 1, | |
5cd8cada | 790 | .needed = serial_timeout_ipending_needed, |
7385b275 PD |
791 | .fields = (VMStateField[]) { |
792 | VMSTATE_INT32(timeout_ipending, SerialState), | |
793 | VMSTATE_END_OF_LIST() | |
794 | } | |
795 | }; | |
796 | ||
797 | static bool serial_poll_needed(void *opaque) | |
798 | { | |
799 | SerialState *s = (SerialState *)opaque; | |
800 | return s->poll_msl >= 0; | |
801 | } | |
802 | ||
92013cf8 | 803 | static const VMStateDescription vmstate_serial_poll = { |
7385b275 PD |
804 | .name = "serial/poll", |
805 | .version_id = 1, | |
5cd8cada | 806 | .needed = serial_poll_needed, |
7385b275 PD |
807 | .minimum_version_id = 1, |
808 | .fields = (VMStateField[]) { | |
809 | VMSTATE_INT32(poll_msl, SerialState), | |
e720677e | 810 | VMSTATE_TIMER_PTR(modem_status_poll, SerialState), |
7385b275 PD |
811 | VMSTATE_END_OF_LIST() |
812 | } | |
813 | }; | |
814 | ||
488cb996 | 815 | const VMStateDescription vmstate_serial = { |
747791f1 JQ |
816 | .name = "serial", |
817 | .version_id = 3, | |
818 | .minimum_version_id = 2, | |
819 | .pre_save = serial_pre_save, | |
7385b275 | 820 | .pre_load = serial_pre_load, |
747791f1 | 821 | .post_load = serial_post_load, |
d49805ae | 822 | .fields = (VMStateField[]) { |
747791f1 JQ |
823 | VMSTATE_UINT16_V(divider, SerialState, 2), |
824 | VMSTATE_UINT8(rbr, SerialState), | |
825 | VMSTATE_UINT8(ier, SerialState), | |
826 | VMSTATE_UINT8(iir, SerialState), | |
827 | VMSTATE_UINT8(lcr, SerialState), | |
828 | VMSTATE_UINT8(mcr, SerialState), | |
829 | VMSTATE_UINT8(lsr, SerialState), | |
830 | VMSTATE_UINT8(msr, SerialState), | |
831 | VMSTATE_UINT8(scr, SerialState), | |
832 | VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3), | |
833 | VMSTATE_END_OF_LIST() | |
7385b275 | 834 | }, |
5cd8cada JQ |
835 | .subsections = (const VMStateDescription*[]) { |
836 | &vmstate_serial_thr_ipending, | |
837 | &vmstate_serial_tsr, | |
838 | &vmstate_serial_recv_fifo, | |
839 | &vmstate_serial_xmit_fifo, | |
840 | &vmstate_serial_fifo_timeout_timer, | |
841 | &vmstate_serial_timeout_ipending, | |
842 | &vmstate_serial_poll, | |
843 | NULL | |
747791f1 JQ |
844 | } |
845 | }; | |
846 | ||
b2a5160c AZ |
847 | static void serial_reset(void *opaque) |
848 | { | |
849 | SerialState *s = opaque; | |
850 | ||
a1df76da PB |
851 | if (s->watch_tag > 0) { |
852 | g_source_remove(s->watch_tag); | |
853 | s->watch_tag = 0; | |
854 | } | |
855 | ||
b2a5160c AZ |
856 | s->rbr = 0; |
857 | s->ier = 0; | |
858 | s->iir = UART_IIR_NO_INT; | |
859 | s->lcr = 0; | |
b2a5160c AZ |
860 | s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
861 | s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS; | |
718b8aec | 862 | /* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */ |
81174dae AL |
863 | s->divider = 0x0C; |
864 | s->mcr = UART_MCR_OUT2; | |
b2a5160c | 865 | s->scr = 0; |
81174dae | 866 | s->tsr_retry = 0; |
73bcb24d | 867 | s->char_transmit_time = (NANOSECONDS_PER_SECOND / 9600) * 10; |
81174dae AL |
868 | s->poll_msl = 0; |
869 | ||
7385b275 PD |
870 | s->timeout_ipending = 0; |
871 | timer_del(s->fifo_timeout_timer); | |
872 | timer_del(s->modem_status_poll); | |
873 | ||
8e8638fa PC |
874 | fifo8_reset(&s->recv_fifo); |
875 | fifo8_reset(&s->xmit_fifo); | |
81174dae | 876 | |
bc72ad67 | 877 | s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
b2a5160c AZ |
878 | |
879 | s->thr_ipending = 0; | |
880 | s->last_break_enable = 0; | |
881 | qemu_irq_lower(s->irq); | |
a30cf876 PB |
882 | |
883 | serial_update_msl(s); | |
884 | s->msr &= ~UART_MSR_ANY_DELTA; | |
b2a5160c AZ |
885 | } |
886 | ||
db895a1e | 887 | void serial_realize_core(SerialState *s, Error **errp) |
81174dae | 888 | { |
5345fdb4 | 889 | if (!qemu_chr_fe_get_driver(&s->chr)) { |
db895a1e AF |
890 | error_setg(errp, "Can't create serial device, empty char device"); |
891 | return; | |
387f4a5a AJ |
892 | } |
893 | ||
bc72ad67 | 894 | s->modem_status_poll = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) serial_update_msl, s); |
81174dae | 895 | |
bc72ad67 | 896 | s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) fifo_timeout_int, s); |
a08d4367 | 897 | qemu_register_reset(serial_reset, s); |
81174dae | 898 | |
5345fdb4 | 899 | qemu_chr_fe_set_handlers(&s->chr, serial_can_receive1, serial_receive1, |
39ab61c6 | 900 | serial_event, s, NULL, true); |
8e8638fa PC |
901 | fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH); |
902 | fifo8_create(&s->xmit_fifo, UART_FIFO_LENGTH); | |
4df7961f | 903 | serial_reset(s); |
81174dae AL |
904 | } |
905 | ||
419ad672 GH |
906 | void serial_exit_core(SerialState *s) |
907 | { | |
c39860e6 | 908 | qemu_chr_fe_deinit(&s->chr); |
419ad672 GH |
909 | qemu_unregister_reset(serial_reset, s); |
910 | } | |
911 | ||
038eaf82 SW |
912 | /* Change the main reference oscillator frequency. */ |
913 | void serial_set_frequency(SerialState *s, uint32_t frequency) | |
914 | { | |
915 | s->baudbase = frequency; | |
916 | serial_update_parameters(s); | |
917 | } | |
918 | ||
488cb996 | 919 | const MemoryRegionOps serial_io_ops = { |
5ec3a23e AG |
920 | .read = serial_ioport_read, |
921 | .write = serial_ioport_write, | |
922 | .impl = { | |
923 | .min_access_size = 1, | |
924 | .max_access_size = 1, | |
925 | }, | |
926 | .endianness = DEVICE_LITTLE_ENDIAN, | |
a941ae45 RH |
927 | }; |
928 | ||
b6cd0ea1 | 929 | SerialState *serial_init(int base, qemu_irq irq, int baudbase, |
568fd159 | 930 | CharDriverState *chr, MemoryRegion *system_io) |
b41a2cd1 FB |
931 | { |
932 | SerialState *s; | |
933 | ||
7267c094 | 934 | s = g_malloc0(sizeof(SerialState)); |
6936bfe5 | 935 | |
ac0be998 GH |
936 | s->irq = irq; |
937 | s->baudbase = baudbase; | |
becdfa00 | 938 | qemu_chr_fe_init(&s->chr, chr, &error_abort); |
007b0657 | 939 | serial_realize_core(s, &error_fatal); |
b41a2cd1 | 940 | |
0be71e32 | 941 | vmstate_register(NULL, base, &vmstate_serial, s); |
8738a8d0 | 942 | |
2c9b15ca | 943 | memory_region_init_io(&s->io, NULL, &serial_io_ops, s, "serial", 8); |
568fd159 | 944 | memory_region_add_subregion(system_io, base, &s->io); |
5ec3a23e | 945 | |
b41a2cd1 | 946 | return s; |
80cabfad | 947 | } |
e5d13e2f FB |
948 | |
949 | /* Memory mapped interface */ | |
a8170e5e | 950 | static uint64_t serial_mm_read(void *opaque, hwaddr addr, |
8e8ffc44 | 951 | unsigned size) |
e5d13e2f FB |
952 | { |
953 | SerialState *s = opaque; | |
5ec3a23e | 954 | return serial_ioport_read(s, addr >> s->it_shift, 1); |
e5d13e2f FB |
955 | } |
956 | ||
a8170e5e | 957 | static void serial_mm_write(void *opaque, hwaddr addr, |
8e8ffc44 | 958 | uint64_t value, unsigned size) |
2d48377a BS |
959 | { |
960 | SerialState *s = opaque; | |
8e8ffc44 | 961 | value &= ~0u >> (32 - (size * 8)); |
5ec3a23e | 962 | serial_ioport_write(s, addr >> s->it_shift, value, 1); |
2d48377a BS |
963 | } |
964 | ||
8e8ffc44 RH |
965 | static const MemoryRegionOps serial_mm_ops[3] = { |
966 | [DEVICE_NATIVE_ENDIAN] = { | |
967 | .read = serial_mm_read, | |
968 | .write = serial_mm_write, | |
969 | .endianness = DEVICE_NATIVE_ENDIAN, | |
970 | }, | |
971 | [DEVICE_LITTLE_ENDIAN] = { | |
972 | .read = serial_mm_read, | |
973 | .write = serial_mm_write, | |
974 | .endianness = DEVICE_LITTLE_ENDIAN, | |
975 | }, | |
976 | [DEVICE_BIG_ENDIAN] = { | |
977 | .read = serial_mm_read, | |
978 | .write = serial_mm_write, | |
979 | .endianness = DEVICE_BIG_ENDIAN, | |
980 | }, | |
e5d13e2f FB |
981 | }; |
982 | ||
39186d8a | 983 | SerialState *serial_mm_init(MemoryRegion *address_space, |
a8170e5e | 984 | hwaddr base, int it_shift, |
39186d8a RH |
985 | qemu_irq irq, int baudbase, |
986 | CharDriverState *chr, enum device_endian end) | |
e5d13e2f FB |
987 | { |
988 | SerialState *s; | |
e5d13e2f | 989 | |
7267c094 | 990 | s = g_malloc0(sizeof(SerialState)); |
81174dae | 991 | |
e5d13e2f | 992 | s->it_shift = it_shift; |
ac0be998 GH |
993 | s->irq = irq; |
994 | s->baudbase = baudbase; | |
becdfa00 | 995 | qemu_chr_fe_init(&s->chr, chr, &error_abort); |
e5d13e2f | 996 | |
007b0657 | 997 | serial_realize_core(s, &error_fatal); |
0be71e32 | 998 | vmstate_register(NULL, base, &vmstate_serial, s); |
e5d13e2f | 999 | |
2c9b15ca | 1000 | memory_region_init_io(&s->io, NULL, &serial_mm_ops[end], s, |
8e8ffc44 | 1001 | "serial", 8 << it_shift); |
39186d8a | 1002 | memory_region_add_subregion(address_space, base, &s->io); |
e5d13e2f FB |
1003 | return s; |
1004 | } |