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Commit | Line | Data |
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80cabfad | 1 | /* |
81174dae | 2 | * QEMU 16550A UART emulation |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
81174dae | 5 | * Copyright (c) 2008 Citrix Systems, Inc. |
5fafdf24 | 6 | * |
80cabfad FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
488cb996 | 25 | |
b6a0aa05 | 26 | #include "qemu/osdep.h" |
0d09e41a | 27 | #include "hw/char/serial.h" |
dccfcd0e | 28 | #include "sysemu/char.h" |
da34e65c | 29 | #include "qapi/error.h" |
1de7afc9 | 30 | #include "qemu/timer.h" |
022c62cb | 31 | #include "exec/address-spaces.h" |
4a44d85e | 32 | #include "qemu/error-report.h" |
80cabfad FB |
33 | |
34 | //#define DEBUG_SERIAL | |
35 | ||
36 | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ | |
37 | ||
38 | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ | |
39 | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ | |
40 | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ | |
41 | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ | |
42 | ||
43 | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ | |
44 | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ | |
45 | ||
46 | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ | |
47 | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ | |
48 | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ | |
49 | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ | |
81174dae AL |
50 | #define UART_IIR_CTI 0x0C /* Character Timeout Indication */ |
51 | ||
52 | #define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */ | |
53 | #define UART_IIR_FE 0xC0 /* Fifo enabled */ | |
80cabfad FB |
54 | |
55 | /* | |
56 | * These are the definitions for the Modem Control Register | |
57 | */ | |
58 | #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ | |
59 | #define UART_MCR_OUT2 0x08 /* Out2 complement */ | |
60 | #define UART_MCR_OUT1 0x04 /* Out1 complement */ | |
61 | #define UART_MCR_RTS 0x02 /* RTS complement */ | |
62 | #define UART_MCR_DTR 0x01 /* DTR complement */ | |
63 | ||
64 | /* | |
65 | * These are the definitions for the Modem Status Register | |
66 | */ | |
67 | #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ | |
68 | #define UART_MSR_RI 0x40 /* Ring Indicator */ | |
69 | #define UART_MSR_DSR 0x20 /* Data Set Ready */ | |
70 | #define UART_MSR_CTS 0x10 /* Clear to Send */ | |
71 | #define UART_MSR_DDCD 0x08 /* Delta DCD */ | |
72 | #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ | |
73 | #define UART_MSR_DDSR 0x02 /* Delta DSR */ | |
74 | #define UART_MSR_DCTS 0x01 /* Delta CTS */ | |
75 | #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ | |
76 | ||
77 | #define UART_LSR_TEMT 0x40 /* Transmitter empty */ | |
78 | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ | |
79 | #define UART_LSR_BI 0x10 /* Break interrupt indicator */ | |
80 | #define UART_LSR_FE 0x08 /* Frame error indicator */ | |
81 | #define UART_LSR_PE 0x04 /* Parity error indicator */ | |
82 | #define UART_LSR_OE 0x02 /* Overrun error indicator */ | |
83 | #define UART_LSR_DR 0x01 /* Receiver data ready */ | |
81174dae | 84 | #define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */ |
80cabfad | 85 | |
81174dae AL |
86 | /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */ |
87 | ||
88 | #define UART_FCR_ITL_1 0x00 /* 1 byte ITL */ | |
89 | #define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */ | |
90 | #define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */ | |
91 | #define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */ | |
92 | ||
93 | #define UART_FCR_DMS 0x08 /* DMA Mode Select */ | |
94 | #define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */ | |
95 | #define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */ | |
96 | #define UART_FCR_FE 0x01 /* FIFO Enable */ | |
97 | ||
81174dae AL |
98 | #define MAX_XMIT_RETRY 4 |
99 | ||
b6601141 MN |
100 | #ifdef DEBUG_SERIAL |
101 | #define DPRINTF(fmt, ...) \ | |
46411f86 | 102 | do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0) |
b6601141 MN |
103 | #else |
104 | #define DPRINTF(fmt, ...) \ | |
46411f86 | 105 | do {} while (0) |
b6601141 MN |
106 | #endif |
107 | ||
81174dae | 108 | static void serial_receive1(void *opaque, const uint8_t *buf, int size); |
b2a5160c | 109 | |
8e8638fa | 110 | static inline void recv_fifo_put(SerialState *s, uint8_t chr) |
80cabfad | 111 | { |
71e605f8 | 112 | /* Receive overruns do not overwrite FIFO contents. */ |
8e8638fa PC |
113 | if (!fifo8_is_full(&s->recv_fifo)) { |
114 | fifo8_push(&s->recv_fifo, chr); | |
115 | } else { | |
71e605f8 | 116 | s->lsr |= UART_LSR_OE; |
8e8638fa | 117 | } |
81174dae | 118 | } |
6936bfe5 | 119 | |
81174dae AL |
120 | static void serial_update_irq(SerialState *s) |
121 | { | |
122 | uint8_t tmp_iir = UART_IIR_NO_INT; | |
123 | ||
81174dae AL |
124 | if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) { |
125 | tmp_iir = UART_IIR_RLSI; | |
5628a626 | 126 | } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) { |
c9a33054 AZ |
127 | /* Note that(s->ier & UART_IER_RDI) can mask this interrupt, |
128 | * this is not in the specification but is observed on existing | |
129 | * hardware. */ | |
81174dae | 130 | tmp_iir = UART_IIR_CTI; |
2d6ee8e7 JL |
131 | } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) && |
132 | (!(s->fcr & UART_FCR_FE) || | |
8e8638fa | 133 | s->recv_fifo.num >= s->recv_fifo_itl)) { |
2d6ee8e7 | 134 | tmp_iir = UART_IIR_RDI; |
81174dae AL |
135 | } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) { |
136 | tmp_iir = UART_IIR_THRI; | |
137 | } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) { | |
138 | tmp_iir = UART_IIR_MSI; | |
139 | } | |
140 | ||
141 | s->iir = tmp_iir | (s->iir & 0xF0); | |
142 | ||
143 | if (tmp_iir != UART_IIR_NO_INT) { | |
144 | qemu_irq_raise(s->irq); | |
145 | } else { | |
146 | qemu_irq_lower(s->irq); | |
6936bfe5 | 147 | } |
6936bfe5 AJ |
148 | } |
149 | ||
f8d179e3 FB |
150 | static void serial_update_parameters(SerialState *s) |
151 | { | |
81174dae | 152 | int speed, parity, data_bits, stop_bits, frame_size; |
2122c51a | 153 | QEMUSerialSetParams ssp; |
f8d179e3 | 154 | |
81174dae AL |
155 | if (s->divider == 0) |
156 | return; | |
157 | ||
718b8aec | 158 | /* Start bit. */ |
81174dae | 159 | frame_size = 1; |
f8d179e3 | 160 | if (s->lcr & 0x08) { |
718b8aec SW |
161 | /* Parity bit. */ |
162 | frame_size++; | |
f8d179e3 FB |
163 | if (s->lcr & 0x10) |
164 | parity = 'E'; | |
165 | else | |
166 | parity = 'O'; | |
167 | } else { | |
168 | parity = 'N'; | |
169 | } | |
5fafdf24 | 170 | if (s->lcr & 0x04) |
f8d179e3 FB |
171 | stop_bits = 2; |
172 | else | |
173 | stop_bits = 1; | |
81174dae | 174 | |
f8d179e3 | 175 | data_bits = (s->lcr & 0x03) + 5; |
81174dae | 176 | frame_size += data_bits + stop_bits; |
b6cd0ea1 | 177 | speed = s->baudbase / s->divider; |
2122c51a FB |
178 | ssp.speed = speed; |
179 | ssp.parity = parity; | |
180 | ssp.data_bits = data_bits; | |
181 | ssp.stop_bits = stop_bits; | |
6ee093c9 | 182 | s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size; |
41084f1b | 183 | qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); |
b6601141 MN |
184 | |
185 | DPRINTF("speed=%d parity=%c data=%d stop=%d\n", | |
f8d179e3 | 186 | speed, parity, data_bits, stop_bits); |
f8d179e3 FB |
187 | } |
188 | ||
81174dae AL |
189 | static void serial_update_msl(SerialState *s) |
190 | { | |
191 | uint8_t omsr; | |
192 | int flags; | |
193 | ||
bc72ad67 | 194 | timer_del(s->modem_status_poll); |
81174dae | 195 | |
41084f1b | 196 | if (qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) { |
81174dae AL |
197 | s->poll_msl = -1; |
198 | return; | |
199 | } | |
200 | ||
201 | omsr = s->msr; | |
202 | ||
203 | s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS; | |
204 | s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR; | |
205 | s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD; | |
206 | s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI; | |
207 | ||
208 | if (s->msr != omsr) { | |
209 | /* Set delta bits */ | |
210 | s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4)); | |
211 | /* UART_MSR_TERI only if change was from 1 -> 0 */ | |
212 | if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI)) | |
213 | s->msr &= ~UART_MSR_TERI; | |
214 | serial_update_irq(s); | |
215 | } | |
216 | ||
217 | /* The real 16550A apparently has a 250ns response latency to line status changes. | |
218 | We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */ | |
219 | ||
220 | if (s->poll_msl) | |
bc72ad67 | 221 | timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + get_ticks_per_sec() / 100); |
81174dae AL |
222 | } |
223 | ||
fcfb4d6a | 224 | static gboolean serial_xmit(GIOChannel *chan, GIOCondition cond, void *opaque) |
81174dae AL |
225 | { |
226 | SerialState *s = opaque; | |
81174dae | 227 | |
f702e62a | 228 | do { |
0d931d70 | 229 | assert(!(s->lsr & UART_LSR_TEMT)); |
f702e62a | 230 | if (s->tsr_retry <= 0) { |
0d931d70 PB |
231 | assert(!(s->lsr & UART_LSR_THRE)); |
232 | ||
f702e62a | 233 | if (s->fcr & UART_FCR_FE) { |
0d931d70 | 234 | assert(!fifo8_is_empty(&s->xmit_fifo)); |
f702e62a KB |
235 | s->tsr = fifo8_pop(&s->xmit_fifo); |
236 | if (!s->xmit_fifo.num) { | |
237 | s->lsr |= UART_LSR_THRE; | |
238 | } | |
f702e62a KB |
239 | } else { |
240 | s->tsr = s->thr; | |
81174dae | 241 | s->lsr |= UART_LSR_THRE; |
0d931d70 PB |
242 | } |
243 | if ((s->lsr & UART_LSR_THRE) && !s->thr_ipending) { | |
244 | s->thr_ipending = 1; | |
245 | serial_update_irq(s); | |
7f4f0a22 | 246 | } |
81174dae | 247 | } |
81174dae | 248 | |
f702e62a KB |
249 | if (s->mcr & UART_MCR_LOOP) { |
250 | /* in loopback mode, say that we just received a char */ | |
251 | serial_receive1(s, &s->tsr, 1); | |
252 | } else if (qemu_chr_fe_write(s->chr, &s->tsr, 1) != 1) { | |
253 | if (s->tsr_retry >= 0 && s->tsr_retry < MAX_XMIT_RETRY && | |
254 | qemu_chr_fe_add_watch(s->chr, G_IO_OUT|G_IO_HUP, | |
255 | serial_xmit, s) > 0) { | |
256 | s->tsr_retry++; | |
257 | return FALSE; | |
258 | } | |
259 | s->tsr_retry = 0; | |
260 | } else { | |
261 | s->tsr_retry = 0; | |
81174dae | 262 | } |
0d931d70 | 263 | |
f702e62a KB |
264 | /* Transmit another byte if it is already available. It is only |
265 | possible when FIFO is enabled and not empty. */ | |
0d931d70 | 266 | } while (!(s->lsr & UART_LSR_THRE)); |
81174dae | 267 | |
bc72ad67 | 268 | s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
0d931d70 | 269 | s->lsr |= UART_LSR_TEMT; |
fcfb4d6a AL |
270 | |
271 | return FALSE; | |
81174dae AL |
272 | } |
273 | ||
274 | ||
7385b275 PD |
275 | /* Setter for FCR. |
276 | is_load flag means, that value is set while loading VM state | |
277 | and interrupt should not be invoked */ | |
278 | static void serial_write_fcr(SerialState *s, uint8_t val) | |
279 | { | |
280 | /* Set fcr - val only has the bits that are supposed to "stick" */ | |
281 | s->fcr = val; | |
282 | ||
283 | if (val & UART_FCR_FE) { | |
284 | s->iir |= UART_IIR_FE; | |
285 | /* Set recv_fifo trigger Level */ | |
286 | switch (val & 0xC0) { | |
287 | case UART_FCR_ITL_1: | |
288 | s->recv_fifo_itl = 1; | |
289 | break; | |
290 | case UART_FCR_ITL_2: | |
291 | s->recv_fifo_itl = 4; | |
292 | break; | |
293 | case UART_FCR_ITL_3: | |
294 | s->recv_fifo_itl = 8; | |
295 | break; | |
296 | case UART_FCR_ITL_4: | |
297 | s->recv_fifo_itl = 14; | |
298 | break; | |
299 | } | |
300 | } else { | |
301 | s->iir &= ~UART_IIR_FE; | |
302 | } | |
303 | } | |
304 | ||
5ec3a23e AG |
305 | static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val, |
306 | unsigned size) | |
80cabfad | 307 | { |
b41a2cd1 | 308 | SerialState *s = opaque; |
3b46e624 | 309 | |
80cabfad | 310 | addr &= 7; |
8b4a8988 | 311 | DPRINTF("write addr=0x%" HWADDR_PRIx " val=0x%" PRIx64 "\n", addr, val); |
80cabfad FB |
312 | switch(addr) { |
313 | default: | |
314 | case 0: | |
315 | if (s->lcr & UART_LCR_DLAB) { | |
316 | s->divider = (s->divider & 0xff00) | val; | |
f8d179e3 | 317 | serial_update_parameters(s); |
80cabfad | 318 | } else { |
81174dae AL |
319 | s->thr = (uint8_t) val; |
320 | if(s->fcr & UART_FCR_FE) { | |
8e8638fa PC |
321 | /* xmit overruns overwrite data, so make space if needed */ |
322 | if (fifo8_is_full(&s->xmit_fifo)) { | |
323 | fifo8_pop(&s->xmit_fifo); | |
324 | } | |
325 | fifo8_push(&s->xmit_fifo, s->thr); | |
6936bfe5 | 326 | } |
b5601df7 PC |
327 | s->thr_ipending = 0; |
328 | s->lsr &= ~UART_LSR_THRE; | |
0d931d70 | 329 | s->lsr &= ~UART_LSR_TEMT; |
b5601df7 | 330 | serial_update_irq(s); |
f702e62a KB |
331 | if (s->tsr_retry <= 0) { |
332 | serial_xmit(NULL, G_IO_OUT, s); | |
333 | } | |
80cabfad FB |
334 | } |
335 | break; | |
336 | case 1: | |
337 | if (s->lcr & UART_LCR_DLAB) { | |
338 | s->divider = (s->divider & 0x00ff) | (val << 8); | |
f8d179e3 | 339 | serial_update_parameters(s); |
80cabfad | 340 | } else { |
1645b8ee | 341 | uint8_t changed = (s->ier ^ val) & 0x0f; |
60e336db | 342 | s->ier = val & 0x0f; |
81174dae | 343 | /* If the backend device is a real serial port, turn polling of the modem |
1645b8ee PB |
344 | * status lines on physical port on or off depending on UART_IER_MSI state. |
345 | */ | |
346 | if ((changed & UART_IER_MSI) && s->poll_msl >= 0) { | |
81174dae AL |
347 | if (s->ier & UART_IER_MSI) { |
348 | s->poll_msl = 1; | |
349 | serial_update_msl(s); | |
350 | } else { | |
bc72ad67 | 351 | timer_del(s->modem_status_poll); |
81174dae AL |
352 | s->poll_msl = 0; |
353 | } | |
354 | } | |
4e02b0fc PB |
355 | |
356 | /* Turning on the THRE interrupt on IER can trigger the interrupt | |
357 | * if LSR.THRE=1, even if it had been masked before by reading IIR. | |
358 | * This is not in the datasheet, but Windows relies on it. It is | |
359 | * unclear if THRE has to be resampled every time THRI becomes | |
360 | * 1, or only on the rising edge. Bochs does the latter, and Windows | |
1645b8ee PB |
361 | * always toggles IER to all zeroes and back to all ones, so do the |
362 | * same. | |
4e02b0fc PB |
363 | * |
364 | * If IER.THRI is zero, thr_ipending is not used. Set it to zero | |
365 | * so that the thr_ipending subsection is not migrated. | |
366 | */ | |
1645b8ee PB |
367 | if (changed & UART_IER_THRI) { |
368 | if ((s->ier & UART_IER_THRI) && (s->lsr & UART_LSR_THRE)) { | |
369 | s->thr_ipending = 1; | |
370 | } else { | |
371 | s->thr_ipending = 0; | |
372 | } | |
373 | } | |
374 | ||
375 | if (changed) { | |
376 | serial_update_irq(s); | |
60e336db | 377 | } |
80cabfad FB |
378 | } |
379 | break; | |
380 | case 2: | |
81174dae | 381 | /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */ |
7385b275 | 382 | if ((val ^ s->fcr) & UART_FCR_FE) { |
81174dae | 383 | val |= UART_FCR_XFR | UART_FCR_RFR; |
7385b275 | 384 | } |
81174dae AL |
385 | |
386 | /* FIFO clear */ | |
387 | ||
388 | if (val & UART_FCR_RFR) { | |
023c3a97 | 389 | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
bc72ad67 | 390 | timer_del(s->fifo_timeout_timer); |
7385b275 | 391 | s->timeout_ipending = 0; |
8e8638fa | 392 | fifo8_reset(&s->recv_fifo); |
81174dae AL |
393 | } |
394 | ||
395 | if (val & UART_FCR_XFR) { | |
023c3a97 PB |
396 | s->lsr |= UART_LSR_THRE; |
397 | s->thr_ipending = 1; | |
8e8638fa | 398 | fifo8_reset(&s->xmit_fifo); |
81174dae AL |
399 | } |
400 | ||
7385b275 | 401 | serial_write_fcr(s, val & 0xC9); |
81174dae | 402 | serial_update_irq(s); |
80cabfad FB |
403 | break; |
404 | case 3: | |
f8d179e3 FB |
405 | { |
406 | int break_enable; | |
407 | s->lcr = val; | |
408 | serial_update_parameters(s); | |
409 | break_enable = (val >> 6) & 1; | |
410 | if (break_enable != s->last_break_enable) { | |
411 | s->last_break_enable = break_enable; | |
41084f1b | 412 | qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK, |
2122c51a | 413 | &break_enable); |
f8d179e3 FB |
414 | } |
415 | } | |
80cabfad FB |
416 | break; |
417 | case 4: | |
81174dae AL |
418 | { |
419 | int flags; | |
420 | int old_mcr = s->mcr; | |
421 | s->mcr = val & 0x1f; | |
422 | if (val & UART_MCR_LOOP) | |
423 | break; | |
424 | ||
425 | if (s->poll_msl >= 0 && old_mcr != s->mcr) { | |
426 | ||
41084f1b | 427 | qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags); |
81174dae AL |
428 | |
429 | flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR); | |
430 | ||
431 | if (val & UART_MCR_RTS) | |
432 | flags |= CHR_TIOCM_RTS; | |
433 | if (val & UART_MCR_DTR) | |
434 | flags |= CHR_TIOCM_DTR; | |
435 | ||
41084f1b | 436 | qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags); |
81174dae AL |
437 | /* Update the modem status after a one-character-send wait-time, since there may be a response |
438 | from the device/computer at the other end of the serial line */ | |
bc72ad67 | 439 | timer_mod(s->modem_status_poll, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time); |
81174dae AL |
440 | } |
441 | } | |
80cabfad FB |
442 | break; |
443 | case 5: | |
444 | break; | |
445 | case 6: | |
80cabfad FB |
446 | break; |
447 | case 7: | |
448 | s->scr = val; | |
449 | break; | |
450 | } | |
451 | } | |
452 | ||
5ec3a23e | 453 | static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size) |
80cabfad | 454 | { |
b41a2cd1 | 455 | SerialState *s = opaque; |
80cabfad FB |
456 | uint32_t ret; |
457 | ||
458 | addr &= 7; | |
459 | switch(addr) { | |
460 | default: | |
461 | case 0: | |
462 | if (s->lcr & UART_LCR_DLAB) { | |
5fafdf24 | 463 | ret = s->divider & 0xff; |
80cabfad | 464 | } else { |
81174dae | 465 | if(s->fcr & UART_FCR_FE) { |
b165b0d8 | 466 | ret = fifo8_is_empty(&s->recv_fifo) ? |
8e8638fa PC |
467 | 0 : fifo8_pop(&s->recv_fifo); |
468 | if (s->recv_fifo.num == 0) { | |
81174dae | 469 | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
7f4f0a22 | 470 | } else { |
bc72ad67 | 471 | timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4); |
7f4f0a22 | 472 | } |
81174dae AL |
473 | s->timeout_ipending = 0; |
474 | } else { | |
475 | ret = s->rbr; | |
476 | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); | |
477 | } | |
b41a2cd1 | 478 | serial_update_irq(s); |
b2a5160c AZ |
479 | if (!(s->mcr & UART_MCR_LOOP)) { |
480 | /* in loopback mode, don't receive any data */ | |
481 | qemu_chr_accept_input(s->chr); | |
482 | } | |
80cabfad FB |
483 | } |
484 | break; | |
485 | case 1: | |
486 | if (s->lcr & UART_LCR_DLAB) { | |
487 | ret = (s->divider >> 8) & 0xff; | |
488 | } else { | |
489 | ret = s->ier; | |
490 | } | |
491 | break; | |
492 | case 2: | |
493 | ret = s->iir; | |
cdee7bdf | 494 | if ((ret & UART_IIR_ID) == UART_IIR_THRI) { |
80cabfad | 495 | s->thr_ipending = 0; |
71e605f8 JG |
496 | serial_update_irq(s); |
497 | } | |
80cabfad FB |
498 | break; |
499 | case 3: | |
500 | ret = s->lcr; | |
501 | break; | |
502 | case 4: | |
503 | ret = s->mcr; | |
504 | break; | |
505 | case 5: | |
506 | ret = s->lsr; | |
71e605f8 JG |
507 | /* Clear break and overrun interrupts */ |
508 | if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) { | |
509 | s->lsr &= ~(UART_LSR_BI|UART_LSR_OE); | |
81174dae AL |
510 | serial_update_irq(s); |
511 | } | |
80cabfad FB |
512 | break; |
513 | case 6: | |
514 | if (s->mcr & UART_MCR_LOOP) { | |
515 | /* in loopback, the modem output pins are connected to the | |
516 | inputs */ | |
517 | ret = (s->mcr & 0x0c) << 4; | |
518 | ret |= (s->mcr & 0x02) << 3; | |
519 | ret |= (s->mcr & 0x01) << 5; | |
520 | } else { | |
81174dae AL |
521 | if (s->poll_msl >= 0) |
522 | serial_update_msl(s); | |
80cabfad | 523 | ret = s->msr; |
81174dae AL |
524 | /* Clear delta bits & msr int after read, if they were set */ |
525 | if (s->msr & UART_MSR_ANY_DELTA) { | |
526 | s->msr &= 0xF0; | |
527 | serial_update_irq(s); | |
528 | } | |
80cabfad FB |
529 | } |
530 | break; | |
531 | case 7: | |
532 | ret = s->scr; | |
533 | break; | |
534 | } | |
8b4a8988 | 535 | DPRINTF("read addr=0x%" HWADDR_PRIx " val=0x%02x\n", addr, ret); |
80cabfad FB |
536 | return ret; |
537 | } | |
538 | ||
82c643ff | 539 | static int serial_can_receive(SerialState *s) |
80cabfad | 540 | { |
81174dae | 541 | if(s->fcr & UART_FCR_FE) { |
8e8638fa | 542 | if (s->recv_fifo.num < UART_FIFO_LENGTH) { |
7f4f0a22 PC |
543 | /* |
544 | * Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 | |
545 | * if above. If UART_FIFO_LENGTH - fifo.count is advertised the | |
546 | * effect will be to almost always fill the fifo completely before | |
547 | * the guest has a chance to respond, effectively overriding the ITL | |
548 | * that the guest has set. | |
549 | */ | |
8e8638fa PC |
550 | return (s->recv_fifo.num <= s->recv_fifo_itl) ? |
551 | s->recv_fifo_itl - s->recv_fifo.num : 1; | |
7f4f0a22 PC |
552 | } else { |
553 | return 0; | |
554 | } | |
81174dae | 555 | } else { |
7f4f0a22 | 556 | return !(s->lsr & UART_LSR_DR); |
81174dae | 557 | } |
80cabfad FB |
558 | } |
559 | ||
82c643ff | 560 | static void serial_receive_break(SerialState *s) |
80cabfad | 561 | { |
80cabfad | 562 | s->rbr = 0; |
40ff1624 | 563 | /* When the LSR_DR is set a null byte is pushed into the fifo */ |
8e8638fa | 564 | recv_fifo_put(s, '\0'); |
80cabfad | 565 | s->lsr |= UART_LSR_BI | UART_LSR_DR; |
b41a2cd1 | 566 | serial_update_irq(s); |
80cabfad FB |
567 | } |
568 | ||
81174dae AL |
569 | /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */ |
570 | static void fifo_timeout_int (void *opaque) { | |
571 | SerialState *s = opaque; | |
8e8638fa | 572 | if (s->recv_fifo.num) { |
81174dae AL |
573 | s->timeout_ipending = 1; |
574 | serial_update_irq(s); | |
575 | } | |
576 | } | |
577 | ||
b41a2cd1 | 578 | static int serial_can_receive1(void *opaque) |
80cabfad | 579 | { |
b41a2cd1 FB |
580 | SerialState *s = opaque; |
581 | return serial_can_receive(s); | |
582 | } | |
583 | ||
584 | static void serial_receive1(void *opaque, const uint8_t *buf, int size) | |
585 | { | |
586 | SerialState *s = opaque; | |
9826fd59 GH |
587 | |
588 | if (s->wakeup) { | |
589 | qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER); | |
590 | } | |
81174dae AL |
591 | if(s->fcr & UART_FCR_FE) { |
592 | int i; | |
593 | for (i = 0; i < size; i++) { | |
8e8638fa | 594 | recv_fifo_put(s, buf[i]); |
81174dae AL |
595 | } |
596 | s->lsr |= UART_LSR_DR; | |
597 | /* call the timeout receive callback in 4 char transmit time */ | |
bc72ad67 | 598 | timer_mod(s->fifo_timeout_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 4); |
81174dae | 599 | } else { |
71e605f8 JG |
600 | if (s->lsr & UART_LSR_DR) |
601 | s->lsr |= UART_LSR_OE; | |
81174dae AL |
602 | s->rbr = buf[0]; |
603 | s->lsr |= UART_LSR_DR; | |
604 | } | |
605 | serial_update_irq(s); | |
b41a2cd1 | 606 | } |
80cabfad | 607 | |
82c643ff FB |
608 | static void serial_event(void *opaque, int event) |
609 | { | |
610 | SerialState *s = opaque; | |
b6601141 | 611 | DPRINTF("event %x\n", event); |
82c643ff FB |
612 | if (event == CHR_EVENT_BREAK) |
613 | serial_receive_break(s); | |
614 | } | |
615 | ||
d4bfa4d7 | 616 | static void serial_pre_save(void *opaque) |
8738a8d0 | 617 | { |
d4bfa4d7 | 618 | SerialState *s = opaque; |
747791f1 | 619 | s->fcr_vmstate = s->fcr; |
8738a8d0 FB |
620 | } |
621 | ||
7385b275 PD |
622 | static int serial_pre_load(void *opaque) |
623 | { | |
624 | SerialState *s = opaque; | |
625 | s->thr_ipending = -1; | |
626 | s->poll_msl = -1; | |
627 | return 0; | |
628 | } | |
629 | ||
e59fb374 | 630 | static int serial_post_load(void *opaque, int version_id) |
747791f1 JQ |
631 | { |
632 | SerialState *s = opaque; | |
81174dae | 633 | |
4c18ce94 JQ |
634 | if (version_id < 3) { |
635 | s->fcr_vmstate = 0; | |
636 | } | |
7385b275 PD |
637 | if (s->thr_ipending == -1) { |
638 | s->thr_ipending = ((s->iir & UART_IIR_ID) == UART_IIR_THRI); | |
639 | } | |
640 | s->last_break_enable = (s->lcr >> 6) & 1; | |
81174dae | 641 | /* Initialize fcr via setter to perform essential side-effects */ |
7385b275 | 642 | serial_write_fcr(s, s->fcr_vmstate); |
9a7c4878 | 643 | serial_update_parameters(s); |
8738a8d0 FB |
644 | return 0; |
645 | } | |
646 | ||
7385b275 PD |
647 | static bool serial_thr_ipending_needed(void *opaque) |
648 | { | |
649 | SerialState *s = opaque; | |
bfa73628 PB |
650 | |
651 | if (s->ier & UART_IER_THRI) { | |
652 | bool expected_value = ((s->iir & UART_IIR_ID) == UART_IIR_THRI); | |
653 | return s->thr_ipending != expected_value; | |
654 | } else { | |
655 | /* LSR.THRE will be sampled again when the interrupt is | |
656 | * enabled. thr_ipending is not used in this case, do | |
657 | * not migrate it. | |
658 | */ | |
659 | return false; | |
660 | } | |
7385b275 PD |
661 | } |
662 | ||
92013cf8 | 663 | static const VMStateDescription vmstate_serial_thr_ipending = { |
7385b275 PD |
664 | .name = "serial/thr_ipending", |
665 | .version_id = 1, | |
666 | .minimum_version_id = 1, | |
5cd8cada | 667 | .needed = serial_thr_ipending_needed, |
7385b275 PD |
668 | .fields = (VMStateField[]) { |
669 | VMSTATE_INT32(thr_ipending, SerialState), | |
670 | VMSTATE_END_OF_LIST() | |
671 | } | |
672 | }; | |
673 | ||
674 | static bool serial_tsr_needed(void *opaque) | |
675 | { | |
676 | SerialState *s = (SerialState *)opaque; | |
677 | return s->tsr_retry != 0; | |
678 | } | |
679 | ||
92013cf8 | 680 | static const VMStateDescription vmstate_serial_tsr = { |
7385b275 PD |
681 | .name = "serial/tsr", |
682 | .version_id = 1, | |
683 | .minimum_version_id = 1, | |
5cd8cada | 684 | .needed = serial_tsr_needed, |
7385b275 PD |
685 | .fields = (VMStateField[]) { |
686 | VMSTATE_INT32(tsr_retry, SerialState), | |
687 | VMSTATE_UINT8(thr, SerialState), | |
688 | VMSTATE_UINT8(tsr, SerialState), | |
689 | VMSTATE_END_OF_LIST() | |
690 | } | |
691 | }; | |
692 | ||
693 | static bool serial_recv_fifo_needed(void *opaque) | |
694 | { | |
695 | SerialState *s = (SerialState *)opaque; | |
696 | return !fifo8_is_empty(&s->recv_fifo); | |
697 | ||
698 | } | |
699 | ||
92013cf8 | 700 | static const VMStateDescription vmstate_serial_recv_fifo = { |
7385b275 PD |
701 | .name = "serial/recv_fifo", |
702 | .version_id = 1, | |
703 | .minimum_version_id = 1, | |
5cd8cada | 704 | .needed = serial_recv_fifo_needed, |
7385b275 PD |
705 | .fields = (VMStateField[]) { |
706 | VMSTATE_STRUCT(recv_fifo, SerialState, 1, vmstate_fifo8, Fifo8), | |
707 | VMSTATE_END_OF_LIST() | |
708 | } | |
709 | }; | |
710 | ||
711 | static bool serial_xmit_fifo_needed(void *opaque) | |
712 | { | |
713 | SerialState *s = (SerialState *)opaque; | |
714 | return !fifo8_is_empty(&s->xmit_fifo); | |
715 | } | |
716 | ||
92013cf8 | 717 | static const VMStateDescription vmstate_serial_xmit_fifo = { |
7385b275 PD |
718 | .name = "serial/xmit_fifo", |
719 | .version_id = 1, | |
720 | .minimum_version_id = 1, | |
5cd8cada | 721 | .needed = serial_xmit_fifo_needed, |
7385b275 PD |
722 | .fields = (VMStateField[]) { |
723 | VMSTATE_STRUCT(xmit_fifo, SerialState, 1, vmstate_fifo8, Fifo8), | |
724 | VMSTATE_END_OF_LIST() | |
725 | } | |
726 | }; | |
727 | ||
728 | static bool serial_fifo_timeout_timer_needed(void *opaque) | |
729 | { | |
730 | SerialState *s = (SerialState *)opaque; | |
731 | return timer_pending(s->fifo_timeout_timer); | |
732 | } | |
733 | ||
92013cf8 | 734 | static const VMStateDescription vmstate_serial_fifo_timeout_timer = { |
7385b275 PD |
735 | .name = "serial/fifo_timeout_timer", |
736 | .version_id = 1, | |
737 | .minimum_version_id = 1, | |
5cd8cada | 738 | .needed = serial_fifo_timeout_timer_needed, |
7385b275 | 739 | .fields = (VMStateField[]) { |
e720677e | 740 | VMSTATE_TIMER_PTR(fifo_timeout_timer, SerialState), |
7385b275 PD |
741 | VMSTATE_END_OF_LIST() |
742 | } | |
743 | }; | |
744 | ||
745 | static bool serial_timeout_ipending_needed(void *opaque) | |
746 | { | |
747 | SerialState *s = (SerialState *)opaque; | |
748 | return s->timeout_ipending != 0; | |
749 | } | |
750 | ||
92013cf8 | 751 | static const VMStateDescription vmstate_serial_timeout_ipending = { |
7385b275 PD |
752 | .name = "serial/timeout_ipending", |
753 | .version_id = 1, | |
754 | .minimum_version_id = 1, | |
5cd8cada | 755 | .needed = serial_timeout_ipending_needed, |
7385b275 PD |
756 | .fields = (VMStateField[]) { |
757 | VMSTATE_INT32(timeout_ipending, SerialState), | |
758 | VMSTATE_END_OF_LIST() | |
759 | } | |
760 | }; | |
761 | ||
762 | static bool serial_poll_needed(void *opaque) | |
763 | { | |
764 | SerialState *s = (SerialState *)opaque; | |
765 | return s->poll_msl >= 0; | |
766 | } | |
767 | ||
92013cf8 | 768 | static const VMStateDescription vmstate_serial_poll = { |
7385b275 PD |
769 | .name = "serial/poll", |
770 | .version_id = 1, | |
5cd8cada | 771 | .needed = serial_poll_needed, |
7385b275 PD |
772 | .minimum_version_id = 1, |
773 | .fields = (VMStateField[]) { | |
774 | VMSTATE_INT32(poll_msl, SerialState), | |
e720677e | 775 | VMSTATE_TIMER_PTR(modem_status_poll, SerialState), |
7385b275 PD |
776 | VMSTATE_END_OF_LIST() |
777 | } | |
778 | }; | |
779 | ||
488cb996 | 780 | const VMStateDescription vmstate_serial = { |
747791f1 JQ |
781 | .name = "serial", |
782 | .version_id = 3, | |
783 | .minimum_version_id = 2, | |
784 | .pre_save = serial_pre_save, | |
7385b275 | 785 | .pre_load = serial_pre_load, |
747791f1 | 786 | .post_load = serial_post_load, |
d49805ae | 787 | .fields = (VMStateField[]) { |
747791f1 JQ |
788 | VMSTATE_UINT16_V(divider, SerialState, 2), |
789 | VMSTATE_UINT8(rbr, SerialState), | |
790 | VMSTATE_UINT8(ier, SerialState), | |
791 | VMSTATE_UINT8(iir, SerialState), | |
792 | VMSTATE_UINT8(lcr, SerialState), | |
793 | VMSTATE_UINT8(mcr, SerialState), | |
794 | VMSTATE_UINT8(lsr, SerialState), | |
795 | VMSTATE_UINT8(msr, SerialState), | |
796 | VMSTATE_UINT8(scr, SerialState), | |
797 | VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3), | |
798 | VMSTATE_END_OF_LIST() | |
7385b275 | 799 | }, |
5cd8cada JQ |
800 | .subsections = (const VMStateDescription*[]) { |
801 | &vmstate_serial_thr_ipending, | |
802 | &vmstate_serial_tsr, | |
803 | &vmstate_serial_recv_fifo, | |
804 | &vmstate_serial_xmit_fifo, | |
805 | &vmstate_serial_fifo_timeout_timer, | |
806 | &vmstate_serial_timeout_ipending, | |
807 | &vmstate_serial_poll, | |
808 | NULL | |
747791f1 JQ |
809 | } |
810 | }; | |
811 | ||
b2a5160c AZ |
812 | static void serial_reset(void *opaque) |
813 | { | |
814 | SerialState *s = opaque; | |
815 | ||
b2a5160c AZ |
816 | s->rbr = 0; |
817 | s->ier = 0; | |
818 | s->iir = UART_IIR_NO_INT; | |
819 | s->lcr = 0; | |
b2a5160c AZ |
820 | s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
821 | s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS; | |
718b8aec | 822 | /* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */ |
81174dae AL |
823 | s->divider = 0x0C; |
824 | s->mcr = UART_MCR_OUT2; | |
b2a5160c | 825 | s->scr = 0; |
81174dae | 826 | s->tsr_retry = 0; |
718b8aec | 827 | s->char_transmit_time = (get_ticks_per_sec() / 9600) * 10; |
81174dae AL |
828 | s->poll_msl = 0; |
829 | ||
7385b275 PD |
830 | s->timeout_ipending = 0; |
831 | timer_del(s->fifo_timeout_timer); | |
832 | timer_del(s->modem_status_poll); | |
833 | ||
8e8638fa PC |
834 | fifo8_reset(&s->recv_fifo); |
835 | fifo8_reset(&s->xmit_fifo); | |
81174dae | 836 | |
bc72ad67 | 837 | s->last_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
b2a5160c AZ |
838 | |
839 | s->thr_ipending = 0; | |
840 | s->last_break_enable = 0; | |
841 | qemu_irq_lower(s->irq); | |
a30cf876 PB |
842 | |
843 | serial_update_msl(s); | |
844 | s->msr &= ~UART_MSR_ANY_DELTA; | |
b2a5160c AZ |
845 | } |
846 | ||
db895a1e | 847 | void serial_realize_core(SerialState *s, Error **errp) |
81174dae | 848 | { |
ac0be998 | 849 | if (!s->chr) { |
db895a1e AF |
850 | error_setg(errp, "Can't create serial device, empty char device"); |
851 | return; | |
387f4a5a AJ |
852 | } |
853 | ||
bc72ad67 | 854 | s->modem_status_poll = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) serial_update_msl, s); |
81174dae | 855 | |
bc72ad67 | 856 | s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) fifo_timeout_int, s); |
a08d4367 | 857 | qemu_register_reset(serial_reset, s); |
81174dae | 858 | |
b47543c4 AJ |
859 | qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1, |
860 | serial_event, s); | |
8e8638fa PC |
861 | fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH); |
862 | fifo8_create(&s->xmit_fifo, UART_FIFO_LENGTH); | |
4df7961f | 863 | serial_reset(s); |
81174dae AL |
864 | } |
865 | ||
419ad672 GH |
866 | void serial_exit_core(SerialState *s) |
867 | { | |
868 | qemu_chr_add_handlers(s->chr, NULL, NULL, NULL, NULL); | |
869 | qemu_unregister_reset(serial_reset, s); | |
870 | } | |
871 | ||
038eaf82 SW |
872 | /* Change the main reference oscillator frequency. */ |
873 | void serial_set_frequency(SerialState *s, uint32_t frequency) | |
874 | { | |
875 | s->baudbase = frequency; | |
876 | serial_update_parameters(s); | |
877 | } | |
878 | ||
488cb996 | 879 | const MemoryRegionOps serial_io_ops = { |
5ec3a23e AG |
880 | .read = serial_ioport_read, |
881 | .write = serial_ioport_write, | |
882 | .impl = { | |
883 | .min_access_size = 1, | |
884 | .max_access_size = 1, | |
885 | }, | |
886 | .endianness = DEVICE_LITTLE_ENDIAN, | |
a941ae45 RH |
887 | }; |
888 | ||
b6cd0ea1 | 889 | SerialState *serial_init(int base, qemu_irq irq, int baudbase, |
568fd159 | 890 | CharDriverState *chr, MemoryRegion *system_io) |
b41a2cd1 FB |
891 | { |
892 | SerialState *s; | |
893 | ||
7267c094 | 894 | s = g_malloc0(sizeof(SerialState)); |
6936bfe5 | 895 | |
ac0be998 GH |
896 | s->irq = irq; |
897 | s->baudbase = baudbase; | |
898 | s->chr = chr; | |
007b0657 | 899 | serial_realize_core(s, &error_fatal); |
b41a2cd1 | 900 | |
0be71e32 | 901 | vmstate_register(NULL, base, &vmstate_serial, s); |
8738a8d0 | 902 | |
2c9b15ca | 903 | memory_region_init_io(&s->io, NULL, &serial_io_ops, s, "serial", 8); |
568fd159 | 904 | memory_region_add_subregion(system_io, base, &s->io); |
5ec3a23e | 905 | |
b41a2cd1 | 906 | return s; |
80cabfad | 907 | } |
e5d13e2f FB |
908 | |
909 | /* Memory mapped interface */ | |
a8170e5e | 910 | static uint64_t serial_mm_read(void *opaque, hwaddr addr, |
8e8ffc44 | 911 | unsigned size) |
e5d13e2f FB |
912 | { |
913 | SerialState *s = opaque; | |
5ec3a23e | 914 | return serial_ioport_read(s, addr >> s->it_shift, 1); |
e5d13e2f FB |
915 | } |
916 | ||
a8170e5e | 917 | static void serial_mm_write(void *opaque, hwaddr addr, |
8e8ffc44 | 918 | uint64_t value, unsigned size) |
2d48377a BS |
919 | { |
920 | SerialState *s = opaque; | |
8e8ffc44 | 921 | value &= ~0u >> (32 - (size * 8)); |
5ec3a23e | 922 | serial_ioport_write(s, addr >> s->it_shift, value, 1); |
2d48377a BS |
923 | } |
924 | ||
8e8ffc44 RH |
925 | static const MemoryRegionOps serial_mm_ops[3] = { |
926 | [DEVICE_NATIVE_ENDIAN] = { | |
927 | .read = serial_mm_read, | |
928 | .write = serial_mm_write, | |
929 | .endianness = DEVICE_NATIVE_ENDIAN, | |
930 | }, | |
931 | [DEVICE_LITTLE_ENDIAN] = { | |
932 | .read = serial_mm_read, | |
933 | .write = serial_mm_write, | |
934 | .endianness = DEVICE_LITTLE_ENDIAN, | |
935 | }, | |
936 | [DEVICE_BIG_ENDIAN] = { | |
937 | .read = serial_mm_read, | |
938 | .write = serial_mm_write, | |
939 | .endianness = DEVICE_BIG_ENDIAN, | |
940 | }, | |
e5d13e2f FB |
941 | }; |
942 | ||
39186d8a | 943 | SerialState *serial_mm_init(MemoryRegion *address_space, |
a8170e5e | 944 | hwaddr base, int it_shift, |
39186d8a RH |
945 | qemu_irq irq, int baudbase, |
946 | CharDriverState *chr, enum device_endian end) | |
e5d13e2f FB |
947 | { |
948 | SerialState *s; | |
e5d13e2f | 949 | |
7267c094 | 950 | s = g_malloc0(sizeof(SerialState)); |
81174dae | 951 | |
e5d13e2f | 952 | s->it_shift = it_shift; |
ac0be998 GH |
953 | s->irq = irq; |
954 | s->baudbase = baudbase; | |
955 | s->chr = chr; | |
e5d13e2f | 956 | |
007b0657 | 957 | serial_realize_core(s, &error_fatal); |
0be71e32 | 958 | vmstate_register(NULL, base, &vmstate_serial, s); |
e5d13e2f | 959 | |
2c9b15ca | 960 | memory_region_init_io(&s->io, NULL, &serial_mm_ops[end], s, |
8e8ffc44 | 961 | "serial", 8 << it_shift); |
39186d8a | 962 | memory_region_add_subregion(address_space, base, &s->io); |
e5d13e2f FB |
963 | return s; |
964 | } |