[mirror_qemu.git] / hw / char / sh_serial.c

/*
 * QEMU SCI/SCIF serial port emulation
 *
 * Copyright (c) 2007 Magnus Damm
 *
 * Based on serial.c - QEMU 16450 UART emulation
 * Copyright (c) 2003-2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/sh4/sh.h"
#include "chardev/char-fe.h"
#include "qapi/error.h"
#include "qemu/timer.h"

//#define DEBUG_SERIAL

#define SH_SERIAL_FLAG_TEND (1 << 0)
#define SH_SERIAL_FLAG_TDE  (1 << 1)
#define SH_SERIAL_FLAG_RDF  (1 << 2)
#define SH_SERIAL_FLAG_BRK  (1 << 3)
#define SH_SERIAL_FLAG_DR   (1 << 4)

#define SH_RX_FIFO_LENGTH (16)

typedef struct {
    MemoryRegion iomem;
    MemoryRegion iomem_p4;
    MemoryRegion iomem_a7;
    uint8_t smr;
    uint8_t brr;
    uint8_t scr;
    uint8_t dr; /* ftdr / tdr */
    uint8_t sr; /* fsr / ssr */
    uint16_t fcr;
    uint8_t sptr;

    uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */
    uint8_t rx_cnt;
    uint8_t rx_tail;
    uint8_t rx_head;

    int freq;
    int feat;
    int flags;
    int rtrg;

    CharBackend chr;
    QEMUTimer *fifo_timeout_timer;
    uint64_t etu; /* Elementary Time Unit (ns) */

    qemu_irq eri;
    qemu_irq rxi;
    qemu_irq txi;
    qemu_irq tei;
    qemu_irq bri;
} sh_serial_state;

static void sh_serial_clear_fifo(sh_serial_state * s)
{
    memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
    s->rx_cnt = 0;
    s->rx_head = 0;
    s->rx_tail = 0;
}

static void sh_serial_write(void *opaque, hwaddr offs,
                            uint64_t val, unsigned size)
{
    sh_serial_state *s = opaque;
    unsigned char ch;

#ifdef DEBUG_SERIAL
    printf("sh_serial: write offs=0x%02x val=0x%02x\n",
           offs, val);
#endif
    switch(offs) {
    case 0x00: /* SMR */
        s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
        return;
    case 0x04: /* BRR */
        s->brr = val;
        return;
    case 0x08: /* SCR */
        /* TODO : For SH7751, SCIF mask should be 0xfb. */
        s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
        if (!(val & (1 << 5)))
            s->flags |= SH_SERIAL_FLAG_TEND;
        if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
            qemu_set_irq(s->txi, val & (1 << 7));
        }
        if (!(val & (1 << 6))) {
            qemu_set_irq(s->rxi, 0);
        }
        return;
    case 0x0c: /* FTDR / TDR */
        if (qemu_chr_fe_backend_connected(&s->chr)) {
            ch = val;
            /* XXX this blocks entire thread. Rewrite to use
             * qemu_chr_fe_write and background I/O callbacks */
            qemu_chr_fe_write_all(&s->chr, &ch, 1);
        }
        s->dr = val;
        s->flags &= ~SH_SERIAL_FLAG_TDE;
        return;
#if 0
    case 0x14: /* FRDR / RDR */
        ret = 0;
        break;
#endif
    }
    if (s->feat & SH_SERIAL_FEAT_SCIF) {
        switch(offs) {
        case 0x10: /* FSR */
            if (!(val & (1 << 6)))
                s->flags &= ~SH_SERIAL_FLAG_TEND;
            if (!(val & (1 << 5)))
                s->flags &= ~SH_SERIAL_FLAG_TDE;
            if (!(val & (1 << 4)))
                s->flags &= ~SH_SERIAL_FLAG_BRK;
            if (!(val & (1 << 1)))
                s->flags &= ~SH_SERIAL_FLAG_RDF;
            if (!(val & (1 << 0)))
                s->flags &= ~SH_SERIAL_FLAG_DR;

            if (!(val & (1 << 1)) || !(val & (1 << 0))) {
                if (s->rxi) {
                    qemu_set_irq(s->rxi, 0);
                }
            }
            return;
        case 0x18: /* FCR */
            s->fcr = val;
            switch ((val >> 6) & 3) {
            case 0:
                s->rtrg = 1;
                break;
            case 1:
                s->rtrg = 4;
                break;
            case 2:
                s->rtrg = 8;
                break;
            case 3:
                s->rtrg = 14;
                break;
            }
            if (val & (1 << 1)) {
                sh_serial_clear_fifo(s);
                s->sr &= ~(1 << 1);
            }

            return;
        case 0x20: /* SPTR */
            s->sptr = val & 0xf3;
            return;
        case 0x24: /* LSR */
            return;
        }
    }
    else {
        switch(offs) {
#if 0
        case 0x0c:
            ret = s->dr;
            break;
        case 0x10:
            ret = 0;
            break;
#endif
        case 0x1c:
            s->sptr = val & 0x8f;
            return;
        }
    }

    fprintf(stderr, "sh_serial: unsupported write to 0x%02"
            HWADDR_PRIx "\n", offs);
    abort();
}

static uint64_t sh_serial_read(void *opaque, hwaddr offs,
                               unsigned size)
{
    sh_serial_state *s = opaque;
    uint32_t ret = ~0;

#if 0
    switch(offs) {
    case 0x00:
        ret = s->smr;
        break;
    case 0x04:
        ret = s->brr;
        break;
    case 0x08:
        ret = s->scr;
        break;
    case 0x14:
        ret = 0;
        break;
    }
#endif
    if (s->feat & SH_SERIAL_FEAT_SCIF) {
        switch(offs) {
        case 0x00: /* SMR */
            ret = s->smr;
            break;
        case 0x08: /* SCR */
            ret = s->scr;
            break;
        case 0x10: /* FSR */
            ret = 0;
            if (s->flags & SH_SERIAL_FLAG_TEND)
                ret |= (1 << 6);
            if (s->flags & SH_SERIAL_FLAG_TDE)
                ret |= (1 << 5);
            if (s->flags & SH_SERIAL_FLAG_BRK)
                ret |= (1 << 4);
            if (s->flags & SH_SERIAL_FLAG_RDF)
                ret |= (1 << 1);
            if (s->flags & SH_SERIAL_FLAG_DR)
                ret |= (1 << 0);

            if (s->scr & (1 << 5))
                s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND;

            break;
        case 0x14:
            if (s->rx_cnt > 0) {
                ret = s->rx_fifo[s->rx_tail++];
                s->rx_cnt--;
                if (s->rx_tail == SH_RX_FIFO_LENGTH)
                    s->rx_tail = 0;
                if (s->rx_cnt < s->rtrg)
                    s->flags &= ~SH_SERIAL_FLAG_RDF;
            }
            break;
        case 0x18:
            ret = s->fcr;
            break;
        case 0x1c:
            ret = s->rx_cnt;
            break;
        case 0x20:
            ret = s->sptr;
            break;
        case 0x24:
            ret = 0;
            break;
        }
    }
    else {
        switch(offs) {
#if 0
        case 0x0c:
            ret = s->dr;
            break;
        case 0x10:
            ret = 0;
            break;
        case 0x14:
            ret = s->rx_fifo[0];
            break;
#endif
        case 0x1c:
            ret = s->sptr;
            break;
        }
    }
#ifdef DEBUG_SERIAL
    printf("sh_serial: read offs=0x%02x val=0x%x\n",
           offs, ret);
#endif

    if (ret & ~((1 << 16) - 1)) {
        fprintf(stderr, "sh_serial: unsupported read from 0x%02"
                HWADDR_PRIx "\n", offs);
        abort();
    }

    return ret;
}

static int sh_serial_can_receive(sh_serial_state *s)
{
    return s->scr & (1 << 4);
}

static void sh_serial_receive_break(sh_serial_state *s)
{
    if (s->feat & SH_SERIAL_FEAT_SCIF)
        s->sr |= (1 << 4);
}

static int sh_serial_can_receive1(void *opaque)
{
    sh_serial_state *s = opaque;
    return sh_serial_can_receive(s);
}

static void sh_serial_timeout_int(void *opaque)
{
    sh_serial_state *s = opaque;

    s->flags |= SH_SERIAL_FLAG_RDF;
    if (s->scr & (1 << 6) && s->rxi) {
        qemu_set_irq(s->rxi, 1);
    }
}

static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size)
{
    sh_serial_state *s = opaque;

    if (s->feat & SH_SERIAL_FEAT_SCIF) {
        int i;
        for (i = 0; i < size; i++) {
            if (s->rx_cnt < SH_RX_FIFO_LENGTH) {
                s->rx_fifo[s->rx_head++] = buf[i];
                if (s->rx_head == SH_RX_FIFO_LENGTH) {
                    s->rx_head = 0;
                }
                s->rx_cnt++;
                if (s->rx_cnt >= s->rtrg) {
                    s->flags |= SH_SERIAL_FLAG_RDF;
                    if (s->scr & (1 << 6) && s->rxi) {
                        timer_del(s->fifo_timeout_timer);
                        qemu_set_irq(s->rxi, 1);
                    }
                } else {
                    timer_mod(s->fifo_timeout_timer,
                        qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 15 * s->etu);
                }
            }
        }
    } else {
        s->rx_fifo[0] = buf[0];
    }
}

static void sh_serial_event(void *opaque, int event)
{
    sh_serial_state *s = opaque;
    if (event == CHR_EVENT_BREAK)
        sh_serial_receive_break(s);
}

static const MemoryRegionOps sh_serial_ops = {
    .read = sh_serial_read,
    .write = sh_serial_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

void sh_serial_init(MemoryRegion *sysmem,
                    hwaddr base, int feat,
                    uint32_t freq, Chardev *chr,
                    qemu_irq eri_source,
                    qemu_irq rxi_source,
                    qemu_irq txi_source,
                    qemu_irq tei_source,
                    qemu_irq bri_source)
{
    sh_serial_state *s;

    s = g_malloc0(sizeof(sh_serial_state));

    s->feat = feat;
    s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE;
    s->rtrg = 1;

    s->smr = 0;
    s->brr = 0xff;
    s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */
    s->sptr = 0;

    if (feat & SH_SERIAL_FEAT_SCIF) {
        s->fcr = 0;
    }
    else {
        s->dr = 0xff;
    }

    sh_serial_clear_fifo(s);

    memory_region_init_io(&s->iomem, NULL, &sh_serial_ops, s,
                          "serial", 0x100000000ULL);

    memory_region_init_alias(&s->iomem_p4, NULL, "serial-p4", &s->iomem,
                             0, 0x28);
    memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);

    memory_region_init_alias(&s->iomem_a7, NULL, "serial-a7", &s->iomem,
                             0, 0x28);
    memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);

    if (chr) {
        qemu_chr_fe_init(&s->chr, chr, &error_abort);
        qemu_chr_fe_set_handlers(&s->chr, sh_serial_can_receive1,
                                 sh_serial_receive1,
                                 sh_serial_event, NULL, s, NULL, true);
    }

    s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
                                         sh_serial_timeout_int, s);
    s->etu = NANOSECONDS_PER_SECOND / 9600;
    s->eri = eri_source;
    s->rxi = rxi_source;
    s->txi = txi_source;
    s->tei = tei_source;
    s->bri = bri_source;
}
Commit	Line	Data
2f062c72 TS	1	/*
	2	* QEMU SCI/SCIF serial port emulation
	3	*
	4	* Copyright (c) 2007 Magnus Damm
	5	*
	6	* Based on serial.c - QEMU 16450 UART emulation
	7	* Copyright (c) 2003-2004 Fabrice Bellard
	8	*
	9	* Permission is hereby granted, free of charge, to any person obtaining a copy
	10	* of this software and associated documentation files (the "Software"), to deal
	11	* in the Software without restriction, including without limitation the rights
	12	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	13	* copies of the Software, and to permit persons to whom the Software is
	14	* furnished to do so, subject to the following conditions:
	15	*
	16	* The above copyright notice and this permission notice shall be included in
	17	* all copies or substantial portions of the Software.
	18	*
	19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	20	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	21	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	22	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	23	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	24	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	25	* THE SOFTWARE.
	26	*/
0430891c	27	#include "qemu/osdep.h"
83c9f4ca	28	#include "hw/hw.h"
0d09e41a	29	#include "hw/sh4/sh.h"
4d43a603	30	#include "chardev/char-fe.h"
32a6ebec	31	#include "qapi/error.h"
71bb4ce1	32	#include "qemu/timer.h"
2f062c72 TS	33
	34	//#define DEBUG_SERIAL
	35
	36	#define SH_SERIAL_FLAG_TEND (1 << 0)
	37	#define SH_SERIAL_FLAG_TDE (1 << 1)
	38	#define SH_SERIAL_FLAG_RDF (1 << 2)
	39	#define SH_SERIAL_FLAG_BRK (1 << 3)
	40	#define SH_SERIAL_FLAG_DR (1 << 4)
	41
63242a00 AJ	42	#define SH_RX_FIFO_LENGTH (16)
63242a00 AJ	43
2f062c72	44	typedef struct {
9a9d0b81 BC	45	MemoryRegion iomem;
	46	MemoryRegion iomem_p4;
	47	MemoryRegion iomem_a7;
2f062c72 TS	48	uint8_t smr;
	49	uint8_t brr;
	50	uint8_t scr;
	51	uint8_t dr; /* ftdr / tdr */
	52	uint8_t sr; /* fsr / ssr */
	53	uint16_t fcr;
	54	uint8_t sptr;
	55
63242a00	56	uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */
2f062c72	57	uint8_t rx_cnt;
63242a00 AJ	58	uint8_t rx_tail;
63242a00 AJ	59	uint8_t rx_head;
2f062c72	60
2f062c72 TS	61	int freq;
	62	int feat;
	63	int flags;
63242a00	64	int rtrg;
2f062c72	65
32a6ebec	66	CharBackend chr;
71bb4ce1 GU	67	QEMUTimer *fifo_timeout_timer;
71bb4ce1 GU	68	uint64_t etu; /* Elementary Time Unit (ns) */
bf5b7423	69
4e7ed2d1 AJ	70	qemu_irq eri;
	71	qemu_irq rxi;
	72	qemu_irq txi;
	73	qemu_irq tei;
	74	qemu_irq bri;
2f062c72 TS	75	} sh_serial_state;
2f062c72 TS	76
63242a00 AJ	77	static void sh_serial_clear_fifo(sh_serial_state * s)
	78	{
	79	memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
	80	s->rx_cnt = 0;
	81	s->rx_head = 0;
	82	s->rx_tail = 0;
	83	}
	84
a8170e5e	85	static void sh_serial_write(void *opaque, hwaddr offs,
9a9d0b81	86	uint64_t val, unsigned size)
2f062c72 TS	87	{
	88	sh_serial_state *s = opaque;
	89	unsigned char ch;
	90
	91	#ifdef DEBUG_SERIAL
8da3ff18	92	printf("sh_serial: write offs=0x%02x val=0x%02x\n",
7d37435b	93	offs, val);
2f062c72 TS	94	#endif
	95	switch(offs) {
	96	case 0x00: /* SMR */
	97	s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
	98	return;
	99	case 0x04: /* BRR */
	100	s->brr = val;
7d37435b	101	return;
2f062c72	102	case 0x08: /* SCR */
63242a00	103	/* TODO : For SH7751, SCIF mask should be 0xfb. */
bf5b7423	104	s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
2f062c72 TS	105	if (!(val & (1 << 5)))
2f062c72 TS	106	s->flags \|= SH_SERIAL_FLAG_TEND;
bf5b7423	107	if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
7d37435b	108	qemu_set_irq(s->txi, val & (1 << 7));
bf5b7423	109	}
4e7ed2d1	110	if (!(val & (1 << 6))) {
7d37435b	111	qemu_set_irq(s->rxi, 0);
63242a00	112	}
2f062c72 TS	113	return;
2f062c72 TS	114	case 0x0c: /* FTDR / TDR */
30650701	115	if (qemu_chr_fe_backend_connected(&s->chr)) {
2f062c72	116	ch = val;
6ab3fc32 DB	117	/* XXX this blocks entire thread. Rewrite to use
6ab3fc32 DB	118	* qemu_chr_fe_write and background I/O callbacks */
5345fdb4	119	qemu_chr_fe_write_all(&s->chr, &ch, 1);
7d37435b PB	120	}
	121	s->dr = val;
	122	s->flags &= ~SH_SERIAL_FLAG_TDE;
2f062c72 TS	123	return;
	124	#if 0
	125	case 0x14: /* FRDR / RDR */
	126	ret = 0;
	127	break;
	128	#endif
	129	}
	130	if (s->feat & SH_SERIAL_FEAT_SCIF) {
	131	switch(offs) {
	132	case 0x10: /* FSR */
	133	if (!(val & (1 << 6)))
	134	s->flags &= ~SH_SERIAL_FLAG_TEND;
	135	if (!(val & (1 << 5)))
	136	s->flags &= ~SH_SERIAL_FLAG_TDE;
	137	if (!(val & (1 << 4)))
	138	s->flags &= ~SH_SERIAL_FLAG_BRK;
	139	if (!(val & (1 << 1)))
	140	s->flags &= ~SH_SERIAL_FLAG_RDF;
	141	if (!(val & (1 << 0)))
	142	s->flags &= ~SH_SERIAL_FLAG_DR;
63242a00 AJ	143
63242a00 AJ	144	if (!(val & (1 << 1)) \|\| !(val & (1 << 0))) {
4e7ed2d1 AJ	145	if (s->rxi) {
4e7ed2d1 AJ	146	qemu_set_irq(s->rxi, 0);
63242a00 AJ	147	}
63242a00 AJ	148	}
2f062c72 TS	149	return;
	150	case 0x18: /* FCR */
	151	s->fcr = val;
63242a00 AJ	152	switch ((val >> 6) & 3) {
	153	case 0:
	154	s->rtrg = 1;
	155	break;
	156	case 1:
	157	s->rtrg = 4;
	158	break;
	159	case 2:
	160	s->rtrg = 8;
	161	break;
	162	case 3:
	163	s->rtrg = 14;
	164	break;
	165	}
	166	if (val & (1 << 1)) {
	167	sh_serial_clear_fifo(s);
	168	s->sr &= ~(1 << 1);
	169	}
	170
2f062c72 TS	171	return;
2f062c72 TS	172	case 0x20: /* SPTR */
63242a00	173	s->sptr = val & 0xf3;
2f062c72 TS	174	return;
	175	case 0x24: /* LSR */
	176	return;
	177	}
	178	}
	179	else {
2f062c72	180	switch(offs) {
d1f193b0	181	#if 0
2f062c72 TS	182	case 0x0c:
	183	ret = s->dr;
	184	break;
	185	case 0x10:
	186	ret = 0;
	187	break;
d1f193b0	188	#endif
2f062c72	189	case 0x1c:
d1f193b0 AJ	190	s->sptr = val & 0x8f;
d1f193b0 AJ	191	return;
2f062c72	192	}
2f062c72 TS	193	}
2f062c72 TS	194
c1950a4e	195	fprintf(stderr, "sh_serial: unsupported write to 0x%02"
a8170e5e	196	HWADDR_PRIx "\n", offs);
43dc2a64	197	abort();
2f062c72 TS	198	}
2f062c72 TS	199
a8170e5e	200	static uint64_t sh_serial_read(void *opaque, hwaddr offs,
9a9d0b81	201	unsigned size)
2f062c72 TS	202	{
	203	sh_serial_state *s = opaque;
	204	uint32_t ret = ~0;
	205
	206	#if 0
	207	switch(offs) {
	208	case 0x00:
	209	ret = s->smr;
	210	break;
	211	case 0x04:
	212	ret = s->brr;
7d37435b	213	break;
2f062c72 TS	214	case 0x08:
	215	ret = s->scr;
	216	break;
	217	case 0x14:
	218	ret = 0;
	219	break;
	220	}
	221	#endif
	222	if (s->feat & SH_SERIAL_FEAT_SCIF) {
	223	switch(offs) {
bf5b7423 AJ	224	case 0x00: /* SMR */
	225	ret = s->smr;
	226	break;
	227	case 0x08: /* SCR */
	228	ret = s->scr;
	229	break;
2f062c72 TS	230	case 0x10: /* FSR */
	231	ret = 0;
	232	if (s->flags & SH_SERIAL_FLAG_TEND)
	233	ret \|= (1 << 6);
	234	if (s->flags & SH_SERIAL_FLAG_TDE)
	235	ret \|= (1 << 5);
	236	if (s->flags & SH_SERIAL_FLAG_BRK)
	237	ret \|= (1 << 4);
	238	if (s->flags & SH_SERIAL_FLAG_RDF)
	239	ret \|= (1 << 1);
	240	if (s->flags & SH_SERIAL_FLAG_DR)
	241	ret \|= (1 << 0);
	242
63242a00	243	if (s->scr & (1 << 5))
2f062c72 TS	244	s->flags \|= SH_SERIAL_FLAG_TDE \| SH_SERIAL_FLAG_TEND;
2f062c72 TS	245
63242a00 AJ	246	break;
	247	case 0x14:
	248	if (s->rx_cnt > 0) {
	249	ret = s->rx_fifo[s->rx_tail++];
	250	s->rx_cnt--;
	251	if (s->rx_tail == SH_RX_FIFO_LENGTH)
	252	s->rx_tail = 0;
	253	if (s->rx_cnt < s->rtrg)
	254	s->flags &= ~SH_SERIAL_FLAG_RDF;
	255	}
2f062c72	256	break;
2f062c72 TS	257	case 0x18:
	258	ret = s->fcr;
	259	break;
2f062c72 TS	260	case 0x1c:
	261	ret = s->rx_cnt;
	262	break;
	263	case 0x20:
	264	ret = s->sptr;
	265	break;
	266	case 0x24:
	267	ret = 0;
	268	break;
	269	}
	270	}
	271	else {
2f062c72	272	switch(offs) {
d1f193b0	273	#if 0
2f062c72 TS	274	case 0x0c:
	275	ret = s->dr;
	276	break;
	277	case 0x10:
	278	ret = 0;
	279	break;
63242a00 AJ	280	case 0x14:
	281	ret = s->rx_fifo[0];
	282	break;
d1f193b0	283	#endif
2f062c72 TS	284	case 0x1c:
	285	ret = s->sptr;
	286	break;
	287	}
2f062c72 TS	288	}
2f062c72 TS	289	#ifdef DEBUG_SERIAL
8da3ff18	290	printf("sh_serial: read offs=0x%02x val=0x%x\n",
7d37435b	291	offs, ret);
2f062c72 TS	292	#endif
	293
	294	if (ret & ~((1 << 16) - 1)) {
c1950a4e	295	fprintf(stderr, "sh_serial: unsupported read from 0x%02"
a8170e5e	296	HWADDR_PRIx "\n", offs);
43dc2a64	297	abort();
2f062c72 TS	298	}
	299
	300	return ret;
	301	}
	302
	303	static int sh_serial_can_receive(sh_serial_state *s)
	304	{
63242a00	305	return s->scr & (1 << 4);
2f062c72 TS	306	}
2f062c72 TS	307
2f062c72 TS	308	static void sh_serial_receive_break(sh_serial_state *s)
2f062c72 TS	309	{
63242a00 AJ	310	if (s->feat & SH_SERIAL_FEAT_SCIF)
63242a00 AJ	311	s->sr \|= (1 << 4);
2f062c72 TS	312	}
	313
	314	static int sh_serial_can_receive1(void *opaque)
	315	{
	316	sh_serial_state *s = opaque;
	317	return sh_serial_can_receive(s);
	318	}
	319
71bb4ce1 GU	320	static void sh_serial_timeout_int(void *opaque)
	321	{
	322	sh_serial_state *s = opaque;
	323
	324	s->flags \|= SH_SERIAL_FLAG_RDF;
	325	if (s->scr & (1 << 6) && s->rxi) {
	326	qemu_set_irq(s->rxi, 1);
	327	}
	328	}
	329
2f062c72 TS	330	static void sh_serial_receive1(void opaque, const uint8_t buf, int size)
	331	{
	332	sh_serial_state *s = opaque;
b7d2b020 AJ	333
	334	if (s->feat & SH_SERIAL_FEAT_SCIF) {
	335	int i;
	336	for (i = 0; i < size; i++) {
	337	if (s->rx_cnt < SH_RX_FIFO_LENGTH) {
	338	s->rx_fifo[s->rx_head++] = buf[i];
	339	if (s->rx_head == SH_RX_FIFO_LENGTH) {
	340	s->rx_head = 0;
	341	}
	342	s->rx_cnt++;
	343	if (s->rx_cnt >= s->rtrg) {
	344	s->flags \|= SH_SERIAL_FLAG_RDF;
	345	if (s->scr & (1 << 6) && s->rxi) {
71bb4ce1	346	timer_del(s->fifo_timeout_timer);
b7d2b020 AJ	347	qemu_set_irq(s->rxi, 1);
b7d2b020 AJ	348	}
71bb4ce1 GU	349	} else {
	350	timer_mod(s->fifo_timeout_timer,
	351	qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 15 * s->etu);
b7d2b020 AJ	352	}
	353	}
	354	}
	355	} else {
	356	s->rx_fifo[0] = buf[0];
	357	}
2f062c72 TS	358	}
	359
	360	static void sh_serial_event(void *opaque, int event)
	361	{
	362	sh_serial_state *s = opaque;
	363	if (event == CHR_EVENT_BREAK)
	364	sh_serial_receive_break(s);
	365	}
	366
9a9d0b81 BC	367	static const MemoryRegionOps sh_serial_ops = {
	368	.read = sh_serial_read,
	369	.write = sh_serial_write,
	370	.endianness = DEVICE_NATIVE_ENDIAN,
2f062c72 TS	371	};
2f062c72 TS	372
9a9d0b81	373	void sh_serial_init(MemoryRegion *sysmem,
a8170e5e	374	hwaddr base, int feat,
0ec7b3e7	375	uint32_t freq, Chardev *chr,
9a9d0b81 BC	376	qemu_irq eri_source,
	377	qemu_irq rxi_source,
	378	qemu_irq txi_source,
	379	qemu_irq tei_source,
	380	qemu_irq bri_source)
2f062c72 TS	381	{
2f062c72 TS	382	sh_serial_state *s;
2f062c72	383
7267c094	384	s = g_malloc0(sizeof(sh_serial_state));
2f062c72	385
2f062c72 TS	386	s->feat = feat;
2f062c72 TS	387	s->flags = SH_SERIAL_FLAG_TEND \| SH_SERIAL_FLAG_TDE;
63242a00	388	s->rtrg = 1;
2f062c72 TS	389
	390	s->smr = 0;
	391	s->brr = 0xff;
b7d35e65	392	s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */
2f062c72 TS	393	s->sptr = 0;
	394
	395	if (feat & SH_SERIAL_FEAT_SCIF) {
	396	s->fcr = 0;
	397	}
	398	else {
	399	s->dr = 0xff;
	400	}
	401
63242a00	402	sh_serial_clear_fifo(s);
2f062c72	403
2c9b15ca	404	memory_region_init_io(&s->iomem, NULL, &sh_serial_ops, s,
9a9d0b81 BC	405	"serial", 0x100000000ULL);
9a9d0b81 BC	406
2c9b15ca	407	memory_region_init_alias(&s->iomem_p4, NULL, "serial-p4", &s->iomem,
9a9d0b81 BC	408	0, 0x28);
	409	memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
	410
2c9b15ca	411	memory_region_init_alias(&s->iomem_a7, NULL, "serial-a7", &s->iomem,
9a9d0b81 BC	412	0, 0x28);
9a9d0b81 BC	413	memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
2f062c72	414
456d6069	415	if (chr) {
32a6ebec	416	qemu_chr_fe_init(&s->chr, chr, &error_abort);
5345fdb4 MAL	417	qemu_chr_fe_set_handlers(&s->chr, sh_serial_can_receive1,
5345fdb4 MAL	418	sh_serial_receive1,
81517ba3	419	sh_serial_event, NULL, s, NULL, true);
456d6069	420	}
bf5b7423	421
71bb4ce1 GU	422	s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
	423	sh_serial_timeout_int, s);
	424	s->etu = NANOSECONDS_PER_SECOND / 9600;
bf5b7423 AJ	425	s->eri = eri_source;
	426	s->rxi = rxi_source;
	427	s->txi = txi_source;
	428	s->tei = tei_source;
	429	s->bri = bri_source;
2f062c72	430	}