[mirror_qemu.git] / hw / char / sh_serial.c

/*
 * QEMU SCI/SCIF serial port emulation
 *
 * Copyright (c) 2007 Magnus Damm
 *
 * Based on serial.c - QEMU 16450 UART emulation
 * Copyright (c) 2003-2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/sh4/sh.h"
#include "sysemu/char.h"
#include "exec/address-spaces.h"
#include "qapi/error.h"

//#define DEBUG_SERIAL

#define SH_SERIAL_FLAG_TEND (1 << 0)
#define SH_SERIAL_FLAG_TDE  (1 << 1)
#define SH_SERIAL_FLAG_RDF  (1 << 2)
#define SH_SERIAL_FLAG_BRK  (1 << 3)
#define SH_SERIAL_FLAG_DR   (1 << 4)

#define SH_RX_FIFO_LENGTH (16)

typedef struct {
    MemoryRegion iomem;
    MemoryRegion iomem_p4;
    MemoryRegion iomem_a7;
    uint8_t smr;
    uint8_t brr;
    uint8_t scr;
    uint8_t dr; /* ftdr / tdr */
    uint8_t sr; /* fsr / ssr */
    uint16_t fcr;
    uint8_t sptr;

    uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */
    uint8_t rx_cnt;
    uint8_t rx_tail;
    uint8_t rx_head;

    int freq;
    int feat;
    int flags;
    int rtrg;

    CharBackend chr;

    qemu_irq eri;
    qemu_irq rxi;
    qemu_irq txi;
    qemu_irq tei;
    qemu_irq bri;
} sh_serial_state;

static void sh_serial_clear_fifo(sh_serial_state * s)
{
    memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
    s->rx_cnt = 0;
    s->rx_head = 0;
    s->rx_tail = 0;
}

static void sh_serial_write(void *opaque, hwaddr offs,
                            uint64_t val, unsigned size)
{
    sh_serial_state *s = opaque;
    unsigned char ch;

#ifdef DEBUG_SERIAL
    printf("sh_serial: write offs=0x%02x val=0x%02x\n",
	   offs, val);
#endif
    switch(offs) {
    case 0x00: /* SMR */
        s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
        return;
    case 0x04: /* BRR */
        s->brr = val;
	return;
    case 0x08: /* SCR */
        /* TODO : For SH7751, SCIF mask should be 0xfb. */
        s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
        if (!(val & (1 << 5)))
            s->flags |= SH_SERIAL_FLAG_TEND;
        if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
	    qemu_set_irq(s->txi, val & (1 << 7));
        }
        if (!(val & (1 << 6))) {
	    qemu_set_irq(s->rxi, 0);
        }
        return;
    case 0x0c: /* FTDR / TDR */
        if (s->chr.chr) {
            ch = val;
            /* XXX this blocks entire thread. Rewrite to use
             * qemu_chr_fe_write and background I/O callbacks */
            qemu_chr_fe_write_all(s->chr.chr, &ch, 1);
	}
	s->dr = val;
	s->flags &= ~SH_SERIAL_FLAG_TDE;
        return;
#if 0
    case 0x14: /* FRDR / RDR */
        ret = 0;
        break;
#endif
    }
    if (s->feat & SH_SERIAL_FEAT_SCIF) {
        switch(offs) {
        case 0x10: /* FSR */
            if (!(val & (1 << 6)))
                s->flags &= ~SH_SERIAL_FLAG_TEND;
            if (!(val & (1 << 5)))
                s->flags &= ~SH_SERIAL_FLAG_TDE;
            if (!(val & (1 << 4)))
                s->flags &= ~SH_SERIAL_FLAG_BRK;
            if (!(val & (1 << 1)))
                s->flags &= ~SH_SERIAL_FLAG_RDF;
            if (!(val & (1 << 0)))
                s->flags &= ~SH_SERIAL_FLAG_DR;

            if (!(val & (1 << 1)) || !(val & (1 << 0))) {
                if (s->rxi) {
                    qemu_set_irq(s->rxi, 0);
                }
            }
            return;
        case 0x18: /* FCR */
            s->fcr = val;
            switch ((val >> 6) & 3) {
            case 0:
                s->rtrg = 1;
                break;
            case 1:
                s->rtrg = 4;
                break;
            case 2:
                s->rtrg = 8;
                break;
            case 3:
                s->rtrg = 14;
                break;
            }
            if (val & (1 << 1)) {
                sh_serial_clear_fifo(s);
                s->sr &= ~(1 << 1);
            }

            return;
        case 0x20: /* SPTR */
            s->sptr = val & 0xf3;
            return;
        case 0x24: /* LSR */
            return;
        }
    }
    else {
        switch(offs) {
#if 0
        case 0x0c:
            ret = s->dr;
            break;
        case 0x10:
            ret = 0;
            break;
#endif
        case 0x1c:
            s->sptr = val & 0x8f;
            return;
        }
    }

    fprintf(stderr, "sh_serial: unsupported write to 0x%02"
            HWADDR_PRIx "\n", offs);
    abort();
}

static uint64_t sh_serial_read(void *opaque, hwaddr offs,
                               unsigned size)
{
    sh_serial_state *s = opaque;
    uint32_t ret = ~0;

#if 0
    switch(offs) {
    case 0x00:
        ret = s->smr;
        break;
    case 0x04:
        ret = s->brr;
	break;
    case 0x08:
        ret = s->scr;
        break;
    case 0x14:
        ret = 0;
        break;
    }
#endif
    if (s->feat & SH_SERIAL_FEAT_SCIF) {
        switch(offs) {
        case 0x00: /* SMR */
            ret = s->smr;
            break;
        case 0x08: /* SCR */
            ret = s->scr;
            break;
        case 0x10: /* FSR */
            ret = 0;
            if (s->flags & SH_SERIAL_FLAG_TEND)
                ret |= (1 << 6);
            if (s->flags & SH_SERIAL_FLAG_TDE)
                ret |= (1 << 5);
            if (s->flags & SH_SERIAL_FLAG_BRK)
                ret |= (1 << 4);
            if (s->flags & SH_SERIAL_FLAG_RDF)
                ret |= (1 << 1);
            if (s->flags & SH_SERIAL_FLAG_DR)
                ret |= (1 << 0);

            if (s->scr & (1 << 5))
                s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND;

            break;
        case 0x14:
            if (s->rx_cnt > 0) {
                ret = s->rx_fifo[s->rx_tail++];
                s->rx_cnt--;
                if (s->rx_tail == SH_RX_FIFO_LENGTH)
                    s->rx_tail = 0;
                if (s->rx_cnt < s->rtrg)
                    s->flags &= ~SH_SERIAL_FLAG_RDF;
            }
            break;
        case 0x18:
            ret = s->fcr;
            break;
        case 0x1c:
            ret = s->rx_cnt;
            break;
        case 0x20:
            ret = s->sptr;
            break;
        case 0x24:
            ret = 0;
            break;
        }
    }
    else {
        switch(offs) {
#if 0
        case 0x0c:
            ret = s->dr;
            break;
        case 0x10:
            ret = 0;
            break;
        case 0x14:
            ret = s->rx_fifo[0];
            break;
#endif
        case 0x1c:
            ret = s->sptr;
            break;
        }
    }
#ifdef DEBUG_SERIAL
    printf("sh_serial: read offs=0x%02x val=0x%x\n",
	   offs, ret);
#endif

    if (ret & ~((1 << 16) - 1)) {
        fprintf(stderr, "sh_serial: unsupported read from 0x%02"
                HWADDR_PRIx "\n", offs);
        abort();
    }

    return ret;
}

static int sh_serial_can_receive(sh_serial_state *s)
{
    return s->scr & (1 << 4);
}

static void sh_serial_receive_break(sh_serial_state *s)
{
    if (s->feat & SH_SERIAL_FEAT_SCIF)
        s->sr |= (1 << 4);
}

static int sh_serial_can_receive1(void *opaque)
{
    sh_serial_state *s = opaque;
    return sh_serial_can_receive(s);
}

static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size)
{
    sh_serial_state *s = opaque;

    if (s->feat & SH_SERIAL_FEAT_SCIF) {
        int i;
        for (i = 0; i < size; i++) {
            if (s->rx_cnt < SH_RX_FIFO_LENGTH) {
                s->rx_fifo[s->rx_head++] = buf[i];
                if (s->rx_head == SH_RX_FIFO_LENGTH) {
                    s->rx_head = 0;
                }
                s->rx_cnt++;
                if (s->rx_cnt >= s->rtrg) {
                    s->flags |= SH_SERIAL_FLAG_RDF;
                    if (s->scr & (1 << 6) && s->rxi) {
                        qemu_set_irq(s->rxi, 1);
                    }
                }
            }
        }
    } else {
        s->rx_fifo[0] = buf[0];
    }
}

static void sh_serial_event(void *opaque, int event)
{
    sh_serial_state *s = opaque;
    if (event == CHR_EVENT_BREAK)
        sh_serial_receive_break(s);
}

static const MemoryRegionOps sh_serial_ops = {
    .read = sh_serial_read,
    .write = sh_serial_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

void sh_serial_init(MemoryRegion *sysmem,
                    hwaddr base, int feat,
                    uint32_t freq, CharDriverState *chr,
                    qemu_irq eri_source,
                    qemu_irq rxi_source,
                    qemu_irq txi_source,
                    qemu_irq tei_source,
                    qemu_irq bri_source)
{
    sh_serial_state *s;

    s = g_malloc0(sizeof(sh_serial_state));

    s->feat = feat;
    s->flags = SH_SERIAL_FLAG_TEND | SH_SERIAL_FLAG_TDE;
    s->rtrg = 1;

    s->smr = 0;
    s->brr = 0xff;
    s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */
    s->sptr = 0;

    if (feat & SH_SERIAL_FEAT_SCIF) {
        s->fcr = 0;
    }
    else {
        s->dr = 0xff;
    }

    sh_serial_clear_fifo(s);

    memory_region_init_io(&s->iomem, NULL, &sh_serial_ops, s,
                          "serial", 0x100000000ULL);

    memory_region_init_alias(&s->iomem_p4, NULL, "serial-p4", &s->iomem,
                             0, 0x28);
    memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);

    memory_region_init_alias(&s->iomem_a7, NULL, "serial-a7", &s->iomem,
                             0, 0x28);
    memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);

    if (chr) {
        qemu_chr_fe_claim_no_fail(chr);
        qemu_chr_fe_init(&s->chr, chr, &error_abort);
        qemu_chr_add_handlers(chr, sh_serial_can_receive1, sh_serial_receive1,
			      sh_serial_event, s);
    }

    s->eri = eri_source;
    s->rxi = rxi_source;
    s->txi = txi_source;
    s->tei = tei_source;
    s->bri = bri_source;
}
Commit	Line	Data
2f062c72 TS	1	/*
	2	* QEMU SCI/SCIF serial port emulation
	3	*
	4	* Copyright (c) 2007 Magnus Damm
	5	*
	6	* Based on serial.c - QEMU 16450 UART emulation
	7	* Copyright (c) 2003-2004 Fabrice Bellard
	8	*
	9	* Permission is hereby granted, free of charge, to any person obtaining a copy
	10	* of this software and associated documentation files (the "Software"), to deal
	11	* in the Software without restriction, including without limitation the rights
	12	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	13	* copies of the Software, and to permit persons to whom the Software is
	14	* furnished to do so, subject to the following conditions:
	15	*
	16	* The above copyright notice and this permission notice shall be included in
	17	* all copies or substantial portions of the Software.
	18	*
	19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	20	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	21	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	22	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	23	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	24	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	25	* THE SOFTWARE.
	26	*/
0430891c	27	#include "qemu/osdep.h"
83c9f4ca	28	#include "hw/hw.h"
0d09e41a	29	#include "hw/sh4/sh.h"
dccfcd0e	30	#include "sysemu/char.h"
022c62cb	31	#include "exec/address-spaces.h"
32a6ebec	32	#include "qapi/error.h"
2f062c72 TS	33
	34	//#define DEBUG_SERIAL
	35
	36	#define SH_SERIAL_FLAG_TEND (1 << 0)
	37	#define SH_SERIAL_FLAG_TDE (1 << 1)
	38	#define SH_SERIAL_FLAG_RDF (1 << 2)
	39	#define SH_SERIAL_FLAG_BRK (1 << 3)
	40	#define SH_SERIAL_FLAG_DR (1 << 4)
	41
63242a00 AJ	42	#define SH_RX_FIFO_LENGTH (16)
63242a00 AJ	43
2f062c72	44	typedef struct {
9a9d0b81 BC	45	MemoryRegion iomem;
	46	MemoryRegion iomem_p4;
	47	MemoryRegion iomem_a7;
2f062c72 TS	48	uint8_t smr;
	49	uint8_t brr;
	50	uint8_t scr;
	51	uint8_t dr; /* ftdr / tdr */
	52	uint8_t sr; /* fsr / ssr */
	53	uint16_t fcr;
	54	uint8_t sptr;
	55
63242a00	56	uint8_t rx_fifo[SH_RX_FIFO_LENGTH]; /* frdr / rdr */
2f062c72	57	uint8_t rx_cnt;
63242a00 AJ	58	uint8_t rx_tail;
63242a00 AJ	59	uint8_t rx_head;
2f062c72	60
2f062c72 TS	61	int freq;
	62	int feat;
	63	int flags;
63242a00	64	int rtrg;
2f062c72	65
32a6ebec	66	CharBackend chr;
bf5b7423	67
4e7ed2d1 AJ	68	qemu_irq eri;
	69	qemu_irq rxi;
	70	qemu_irq txi;
	71	qemu_irq tei;
	72	qemu_irq bri;
2f062c72 TS	73	} sh_serial_state;
2f062c72 TS	74
63242a00 AJ	75	static void sh_serial_clear_fifo(sh_serial_state * s)
	76	{
	77	memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
	78	s->rx_cnt = 0;
	79	s->rx_head = 0;
	80	s->rx_tail = 0;
	81	}
	82
a8170e5e	83	static void sh_serial_write(void *opaque, hwaddr offs,
9a9d0b81	84	uint64_t val, unsigned size)
2f062c72 TS	85	{
	86	sh_serial_state *s = opaque;
	87	unsigned char ch;
	88
	89	#ifdef DEBUG_SERIAL
8da3ff18 PB	90	printf("sh_serial: write offs=0x%02x val=0x%02x\n",
8da3ff18 PB	91	offs, val);
2f062c72 TS	92	#endif
	93	switch(offs) {
	94	case 0x00: /* SMR */
	95	s->smr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0x7b : 0xff);
	96	return;
	97	case 0x04: /* BRR */
	98	s->brr = val;
	99	return;
	100	case 0x08: /* SCR */
63242a00	101	/* TODO : For SH7751, SCIF mask should be 0xfb. */
bf5b7423	102	s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
2f062c72 TS	103	if (!(val & (1 << 5)))
2f062c72 TS	104	s->flags \|= SH_SERIAL_FLAG_TEND;
bf5b7423	105	if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
4e7ed2d1	106	qemu_set_irq(s->txi, val & (1 << 7));
bf5b7423	107	}
4e7ed2d1 AJ	108	if (!(val & (1 << 6))) {
4e7ed2d1 AJ	109	qemu_set_irq(s->rxi, 0);
63242a00	110	}
2f062c72 TS	111	return;
2f062c72 TS	112	case 0x0c: /* FTDR / TDR */
32a6ebec	113	if (s->chr.chr) {
2f062c72	114	ch = val;
6ab3fc32 DB	115	/* XXX this blocks entire thread. Rewrite to use
6ab3fc32 DB	116	* qemu_chr_fe_write and background I/O callbacks */
32a6ebec	117	qemu_chr_fe_write_all(s->chr.chr, &ch, 1);
2f062c72 TS	118	}
	119	s->dr = val;
	120	s->flags &= ~SH_SERIAL_FLAG_TDE;
	121	return;
	122	#if 0
	123	case 0x14: /* FRDR / RDR */
	124	ret = 0;
	125	break;
	126	#endif
	127	}
	128	if (s->feat & SH_SERIAL_FEAT_SCIF) {
	129	switch(offs) {
	130	case 0x10: /* FSR */
	131	if (!(val & (1 << 6)))
	132	s->flags &= ~SH_SERIAL_FLAG_TEND;
	133	if (!(val & (1 << 5)))
	134	s->flags &= ~SH_SERIAL_FLAG_TDE;
	135	if (!(val & (1 << 4)))
	136	s->flags &= ~SH_SERIAL_FLAG_BRK;
	137	if (!(val & (1 << 1)))
	138	s->flags &= ~SH_SERIAL_FLAG_RDF;
	139	if (!(val & (1 << 0)))
	140	s->flags &= ~SH_SERIAL_FLAG_DR;
63242a00 AJ	141
63242a00 AJ	142	if (!(val & (1 << 1)) \|\| !(val & (1 << 0))) {
4e7ed2d1 AJ	143	if (s->rxi) {
4e7ed2d1 AJ	144	qemu_set_irq(s->rxi, 0);
63242a00 AJ	145	}
63242a00 AJ	146	}
2f062c72 TS	147	return;
	148	case 0x18: /* FCR */
	149	s->fcr = val;
63242a00 AJ	150	switch ((val >> 6) & 3) {
	151	case 0:
	152	s->rtrg = 1;
	153	break;
	154	case 1:
	155	s->rtrg = 4;
	156	break;
	157	case 2:
	158	s->rtrg = 8;
	159	break;
	160	case 3:
	161	s->rtrg = 14;
	162	break;
	163	}
	164	if (val & (1 << 1)) {
	165	sh_serial_clear_fifo(s);
	166	s->sr &= ~(1 << 1);
	167	}
	168
2f062c72 TS	169	return;
2f062c72 TS	170	case 0x20: /* SPTR */
63242a00	171	s->sptr = val & 0xf3;
2f062c72 TS	172	return;
	173	case 0x24: /* LSR */
	174	return;
	175	}
	176	}
	177	else {
2f062c72	178	switch(offs) {
d1f193b0	179	#if 0
2f062c72 TS	180	case 0x0c:
	181	ret = s->dr;
	182	break;
	183	case 0x10:
	184	ret = 0;
	185	break;
d1f193b0	186	#endif
2f062c72	187	case 0x1c:
d1f193b0 AJ	188	s->sptr = val & 0x8f;
d1f193b0 AJ	189	return;
2f062c72	190	}
2f062c72 TS	191	}
2f062c72 TS	192
c1950a4e	193	fprintf(stderr, "sh_serial: unsupported write to 0x%02"
a8170e5e	194	HWADDR_PRIx "\n", offs);
43dc2a64	195	abort();
2f062c72 TS	196	}
2f062c72 TS	197
a8170e5e	198	static uint64_t sh_serial_read(void *opaque, hwaddr offs,
9a9d0b81	199	unsigned size)
2f062c72 TS	200	{
	201	sh_serial_state *s = opaque;
	202	uint32_t ret = ~0;
	203
	204	#if 0
	205	switch(offs) {
	206	case 0x00:
	207	ret = s->smr;
	208	break;
	209	case 0x04:
	210	ret = s->brr;
	211	break;
	212	case 0x08:
	213	ret = s->scr;
	214	break;
	215	case 0x14:
	216	ret = 0;
	217	break;
	218	}
	219	#endif
	220	if (s->feat & SH_SERIAL_FEAT_SCIF) {
	221	switch(offs) {
bf5b7423 AJ	222	case 0x00: /* SMR */
	223	ret = s->smr;
	224	break;
	225	case 0x08: /* SCR */
	226	ret = s->scr;
	227	break;
2f062c72 TS	228	case 0x10: /* FSR */
	229	ret = 0;
	230	if (s->flags & SH_SERIAL_FLAG_TEND)
	231	ret \|= (1 << 6);
	232	if (s->flags & SH_SERIAL_FLAG_TDE)
	233	ret \|= (1 << 5);
	234	if (s->flags & SH_SERIAL_FLAG_BRK)
	235	ret \|= (1 << 4);
	236	if (s->flags & SH_SERIAL_FLAG_RDF)
	237	ret \|= (1 << 1);
	238	if (s->flags & SH_SERIAL_FLAG_DR)
	239	ret \|= (1 << 0);
	240
63242a00	241	if (s->scr & (1 << 5))
2f062c72 TS	242	s->flags \|= SH_SERIAL_FLAG_TDE \| SH_SERIAL_FLAG_TEND;
2f062c72 TS	243
63242a00 AJ	244	break;
	245	case 0x14:
	246	if (s->rx_cnt > 0) {
	247	ret = s->rx_fifo[s->rx_tail++];
	248	s->rx_cnt--;
	249	if (s->rx_tail == SH_RX_FIFO_LENGTH)
	250	s->rx_tail = 0;
	251	if (s->rx_cnt < s->rtrg)
	252	s->flags &= ~SH_SERIAL_FLAG_RDF;
	253	}
2f062c72	254	break;
2f062c72 TS	255	case 0x18:
	256	ret = s->fcr;
	257	break;
2f062c72 TS	258	case 0x1c:
	259	ret = s->rx_cnt;
	260	break;
	261	case 0x20:
	262	ret = s->sptr;
	263	break;
	264	case 0x24:
	265	ret = 0;
	266	break;
	267	}
	268	}
	269	else {
2f062c72	270	switch(offs) {
d1f193b0	271	#if 0
2f062c72 TS	272	case 0x0c:
	273	ret = s->dr;
	274	break;
	275	case 0x10:
	276	ret = 0;
	277	break;
63242a00 AJ	278	case 0x14:
	279	ret = s->rx_fifo[0];
	280	break;
d1f193b0	281	#endif
2f062c72 TS	282	case 0x1c:
	283	ret = s->sptr;
	284	break;
	285	}
2f062c72 TS	286	}
2f062c72 TS	287	#ifdef DEBUG_SERIAL
8da3ff18 PB	288	printf("sh_serial: read offs=0x%02x val=0x%x\n",
8da3ff18 PB	289	offs, ret);
2f062c72 TS	290	#endif
	291
	292	if (ret & ~((1 << 16) - 1)) {
c1950a4e	293	fprintf(stderr, "sh_serial: unsupported read from 0x%02"
a8170e5e	294	HWADDR_PRIx "\n", offs);
43dc2a64	295	abort();
2f062c72 TS	296	}
	297
	298	return ret;
	299	}
	300
	301	static int sh_serial_can_receive(sh_serial_state *s)
	302	{
63242a00	303	return s->scr & (1 << 4);
2f062c72 TS	304	}
2f062c72 TS	305
2f062c72 TS	306	static void sh_serial_receive_break(sh_serial_state *s)
2f062c72 TS	307	{
63242a00 AJ	308	if (s->feat & SH_SERIAL_FEAT_SCIF)
63242a00 AJ	309	s->sr \|= (1 << 4);
2f062c72 TS	310	}
	311
	312	static int sh_serial_can_receive1(void *opaque)
	313	{
	314	sh_serial_state *s = opaque;
	315	return sh_serial_can_receive(s);
	316	}
	317
	318	static void sh_serial_receive1(void opaque, const uint8_t buf, int size)
	319	{
	320	sh_serial_state *s = opaque;
b7d2b020 AJ	321
	322	if (s->feat & SH_SERIAL_FEAT_SCIF) {
	323	int i;
	324	for (i = 0; i < size; i++) {
	325	if (s->rx_cnt < SH_RX_FIFO_LENGTH) {
	326	s->rx_fifo[s->rx_head++] = buf[i];
	327	if (s->rx_head == SH_RX_FIFO_LENGTH) {
	328	s->rx_head = 0;
	329	}
	330	s->rx_cnt++;
	331	if (s->rx_cnt >= s->rtrg) {
	332	s->flags \|= SH_SERIAL_FLAG_RDF;
	333	if (s->scr & (1 << 6) && s->rxi) {
	334	qemu_set_irq(s->rxi, 1);
	335	}
	336	}
	337	}
	338	}
	339	} else {
	340	s->rx_fifo[0] = buf[0];
	341	}
2f062c72 TS	342	}
	343
	344	static void sh_serial_event(void *opaque, int event)
	345	{
	346	sh_serial_state *s = opaque;
	347	if (event == CHR_EVENT_BREAK)
	348	sh_serial_receive_break(s);
	349	}
	350
9a9d0b81 BC	351	static const MemoryRegionOps sh_serial_ops = {
	352	.read = sh_serial_read,
	353	.write = sh_serial_write,
	354	.endianness = DEVICE_NATIVE_ENDIAN,
2f062c72 TS	355	};
2f062c72 TS	356
9a9d0b81	357	void sh_serial_init(MemoryRegion *sysmem,
a8170e5e	358	hwaddr base, int feat,
9a9d0b81 BC	359	uint32_t freq, CharDriverState *chr,
	360	qemu_irq eri_source,
	361	qemu_irq rxi_source,
	362	qemu_irq txi_source,
	363	qemu_irq tei_source,
	364	qemu_irq bri_source)
2f062c72 TS	365	{
2f062c72 TS	366	sh_serial_state *s;
2f062c72	367
7267c094	368	s = g_malloc0(sizeof(sh_serial_state));
2f062c72	369
2f062c72 TS	370	s->feat = feat;
2f062c72 TS	371	s->flags = SH_SERIAL_FLAG_TEND \| SH_SERIAL_FLAG_TDE;
63242a00	372	s->rtrg = 1;
2f062c72 TS	373
	374	s->smr = 0;
	375	s->brr = 0xff;
b7d35e65	376	s->scr = 1 << 5; /* pretend that TX is enabled so early printk works */
2f062c72 TS	377	s->sptr = 0;
	378
	379	if (feat & SH_SERIAL_FEAT_SCIF) {
	380	s->fcr = 0;
	381	}
	382	else {
	383	s->dr = 0xff;
	384	}
	385
63242a00	386	sh_serial_clear_fifo(s);
2f062c72	387
2c9b15ca	388	memory_region_init_io(&s->iomem, NULL, &sh_serial_ops, s,
9a9d0b81 BC	389	"serial", 0x100000000ULL);
9a9d0b81 BC	390
2c9b15ca	391	memory_region_init_alias(&s->iomem_p4, NULL, "serial-p4", &s->iomem,
9a9d0b81 BC	392	0, 0x28);
	393	memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
	394
2c9b15ca	395	memory_region_init_alias(&s->iomem_a7, NULL, "serial-a7", &s->iomem,
9a9d0b81 BC	396	0, 0x28);
9a9d0b81 BC	397	memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
2f062c72	398
456d6069 HG	399	if (chr) {
456d6069 HG	400	qemu_chr_fe_claim_no_fail(chr);
32a6ebec	401	qemu_chr_fe_init(&s->chr, chr, &error_abort);
2f062c72 TS	402	qemu_chr_add_handlers(chr, sh_serial_can_receive1, sh_serial_receive1,
2f062c72 TS	403	sh_serial_event, s);
456d6069	404	}
bf5b7423 AJ	405
	406	s->eri = eri_source;
	407	s->rxi = rxi_source;
	408	s->txi = txi_source;
	409	s->tei = tei_source;
	410	s->bri = bri_source;
2f062c72	411	}