[mirror_qemu.git] / hw / char / stm32f2xx_usart.c

/*
 * STM32F2XX USART
 *
 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "hw/char/stm32f2xx_usart.h"
#include "qemu/log.h"

#ifndef STM_USART_ERR_DEBUG
#define STM_USART_ERR_DEBUG 0
#endif

#define DB_PRINT_L(lvl, fmt, args...) do { \
    if (STM_USART_ERR_DEBUG >= lvl) { \
        qemu_log("%s: " fmt, __func__, ## args); \
    } \
} while (0)

#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)

static int stm32f2xx_usart_can_receive(void *opaque)
{
    STM32F2XXUsartState *s = opaque;

    if (!(s->usart_sr & USART_SR_RXNE)) {
        return 1;
    }

    return 0;
}

static void stm32f2xx_usart_receive(void *opaque, const uint8_t *buf, int size)
{
    STM32F2XXUsartState *s = opaque;

    if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) {
        /* USART not enabled - drop the chars */
        DB_PRINT("Dropping the chars\n");
        return;
    }

    s->usart_dr = *buf;
    s->usart_sr |= USART_SR_RXNE;

    if (s->usart_cr1 & USART_CR1_RXNEIE) {
        qemu_set_irq(s->irq, 1);
    }

    DB_PRINT("Receiving: %c\n", s->usart_dr);
}

static void stm32f2xx_usart_reset(DeviceState *dev)
{
    STM32F2XXUsartState *s = STM32F2XX_USART(dev);

    s->usart_sr = USART_SR_RESET;
    s->usart_dr = 0x00000000;
    s->usart_brr = 0x00000000;
    s->usart_cr1 = 0x00000000;
    s->usart_cr2 = 0x00000000;
    s->usart_cr3 = 0x00000000;
    s->usart_gtpr = 0x00000000;

    qemu_set_irq(s->irq, 0);
}

static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
                                       unsigned int size)
{
    STM32F2XXUsartState *s = opaque;
    uint64_t retvalue;

    DB_PRINT("Read 0x%"HWADDR_PRIx"\n", addr);

    switch (addr) {
    case USART_SR:
        retvalue = s->usart_sr;
        qemu_chr_fe_accept_input(&s->chr);
        return retvalue;
    case USART_DR:
        DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr);
        s->usart_sr &= ~USART_SR_RXNE;
        qemu_chr_fe_accept_input(&s->chr);
        qemu_set_irq(s->irq, 0);
        return s->usart_dr & 0x3FF;
    case USART_BRR:
        return s->usart_brr;
    case USART_CR1:
        return s->usart_cr1;
    case USART_CR2:
        return s->usart_cr2;
    case USART_CR3:
        return s->usart_cr3;
    case USART_GTPR:
        return s->usart_gtpr;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
        return 0;
    }

    return 0;
}

static void stm32f2xx_usart_write(void *opaque, hwaddr addr,
                                  uint64_t val64, unsigned int size)
{
    STM32F2XXUsartState *s = opaque;
    uint32_t value = val64;
    unsigned char ch;

    DB_PRINT("Write 0x%" PRIx32 ", 0x%"HWADDR_PRIx"\n", value, addr);

    switch (addr) {
    case USART_SR:
        if (value <= 0x3FF) {
            /* I/O being synchronous, TXE is always set. In addition, it may
               only be set by hardware, so keep it set here. */
            s->usart_sr = value | USART_SR_TXE;
        } else {
            s->usart_sr &= value;
        }
        if (!(s->usart_sr & USART_SR_RXNE)) {
            qemu_set_irq(s->irq, 0);
        }
        return;
    case USART_DR:
        if (value < 0xF000) {
            ch = value;
            /* XXX this blocks entire thread. Rewrite to use
             * qemu_chr_fe_write and background I/O callbacks */
            qemu_chr_fe_write_all(&s->chr, &ch, 1);
            /* XXX I/O are currently synchronous, making it impossible for
               software to observe transient states where TXE or TC aren't
               set. Unlike TXE however, which is read-only, software may
               clear TC by writing 0 to the SR register, so set it again
               on each write. */
            s->usart_sr |= USART_SR_TC;
        }
        return;
    case USART_BRR:
        s->usart_brr = value;
        return;
    case USART_CR1:
        s->usart_cr1 = value;
            if (s->usart_cr1 & USART_CR1_RXNEIE &&
                s->usart_sr & USART_SR_RXNE) {
                qemu_set_irq(s->irq, 1);
            }
        return;
    case USART_CR2:
        s->usart_cr2 = value;
        return;
    case USART_CR3:
        s->usart_cr3 = value;
        return;
    case USART_GTPR:
        s->usart_gtpr = value;
        return;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
    }
}

static const MemoryRegionOps stm32f2xx_usart_ops = {
    .read = stm32f2xx_usart_read,
    .write = stm32f2xx_usart_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static Property stm32f2xx_usart_properties[] = {
    DEFINE_PROP_CHR("chardev", STM32F2XXUsartState, chr),
    DEFINE_PROP_END_OF_LIST(),
};

static void stm32f2xx_usart_init(Object *obj)
{
    STM32F2XXUsartState *s = STM32F2XX_USART(obj);

    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);

    memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s,
                          TYPE_STM32F2XX_USART, 0x400);
    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
}

static void stm32f2xx_usart_realize(DeviceState *dev, Error **errp)
{
    STM32F2XXUsartState *s = STM32F2XX_USART(dev);

    qemu_chr_fe_set_handlers(&s->chr, stm32f2xx_usart_can_receive,
                             stm32f2xx_usart_receive, NULL, NULL,
                             s, NULL, true);
}

static void stm32f2xx_usart_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->reset = stm32f2xx_usart_reset;
    dc->props = stm32f2xx_usart_properties;
    dc->realize = stm32f2xx_usart_realize;
}

static const TypeInfo stm32f2xx_usart_info = {
    .name          = TYPE_STM32F2XX_USART,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(STM32F2XXUsartState),
    .instance_init = stm32f2xx_usart_init,
    .class_init    = stm32f2xx_usart_class_init,
};

static void stm32f2xx_usart_register_types(void)
{
    type_register_static(&stm32f2xx_usart_info);
}

type_init(stm32f2xx_usart_register_types)
Commit	Line	Data
73af5d11 AF	1	/*
	2	* STM32F2XX USART
	3	*
	4	* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
17b7f2db	25	#include "qemu/osdep.h"
73af5d11	26	#include "hw/char/stm32f2xx_usart.h"
03dd024f	27	#include "qemu/log.h"
73af5d11 AF	28
	29	#ifndef STM_USART_ERR_DEBUG
	30	#define STM_USART_ERR_DEBUG 0
	31	#endif
	32
	33	#define DB_PRINT_L(lvl, fmt, args...) do { \
	34	if (STM_USART_ERR_DEBUG >= lvl) { \
	35	qemu_log("%s: " fmt, __func__, ## args); \
	36	} \
2562755e	37	} while (0)
73af5d11 AF	38
	39	#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
	40
	41	static int stm32f2xx_usart_can_receive(void *opaque)
	42	{
	43	STM32F2XXUsartState *s = opaque;
	44
	45	if (!(s->usart_sr & USART_SR_RXNE)) {
	46	return 1;
	47	}
	48
	49	return 0;
	50	}
	51
	52	static void stm32f2xx_usart_receive(void opaque, const uint8_t buf, int size)
	53	{
	54	STM32F2XXUsartState *s = opaque;
	55
73af5d11 AF	56	if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) {
	57	/* USART not enabled - drop the chars */
	58	DB_PRINT("Dropping the chars\n");
	59	return;
	60	}
	61
40766180	62	s->usart_dr = *buf;
73af5d11 AF	63	s->usart_sr \|= USART_SR_RXNE;
	64
	65	if (s->usart_cr1 & USART_CR1_RXNEIE) {
	66	qemu_set_irq(s->irq, 1);
	67	}
	68
	69	DB_PRINT("Receiving: %c\n", s->usart_dr);
	70	}
	71
	72	static void stm32f2xx_usart_reset(DeviceState *dev)
	73	{
	74	STM32F2XXUsartState *s = STM32F2XX_USART(dev);
	75
	76	s->usart_sr = USART_SR_RESET;
	77	s->usart_dr = 0x00000000;
	78	s->usart_brr = 0x00000000;
	79	s->usart_cr1 = 0x00000000;
	80	s->usart_cr2 = 0x00000000;
	81	s->usart_cr3 = 0x00000000;
	82	s->usart_gtpr = 0x00000000;
	83
	84	qemu_set_irq(s->irq, 0);
	85	}
	86
	87	static uint64_t stm32f2xx_usart_read(void *opaque, hwaddr addr,
	88	unsigned int size)
	89	{
	90	STM32F2XXUsartState *s = opaque;
	91	uint64_t retvalue;
	92
	93	DB_PRINT("Read 0x%"HWADDR_PRIx"\n", addr);
	94
	95	switch (addr) {
	96	case USART_SR:
	97	retvalue = s->usart_sr;
fa394ed6	98	qemu_chr_fe_accept_input(&s->chr);
73af5d11 AF	99	return retvalue;
	100	case USART_DR:
	101	DB_PRINT("Value: 0x%" PRIx32 ", %c\n", s->usart_dr, (char) s->usart_dr);
73af5d11	102	s->usart_sr &= ~USART_SR_RXNE;
fa394ed6	103	qemu_chr_fe_accept_input(&s->chr);
73af5d11 AF	104	qemu_set_irq(s->irq, 0);
	105	return s->usart_dr & 0x3FF;
	106	case USART_BRR:
	107	return s->usart_brr;
	108	case USART_CR1:
	109	return s->usart_cr1;
	110	case USART_CR2:
	111	return s->usart_cr2;
	112	case USART_CR3:
	113	return s->usart_cr3;
	114	case USART_GTPR:
	115	return s->usart_gtpr;
	116	default:
	117	qemu_log_mask(LOG_GUEST_ERROR,
	118	"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
	119	return 0;
	120	}
	121
	122	return 0;
	123	}
	124
	125	static void stm32f2xx_usart_write(void *opaque, hwaddr addr,
	126	uint64_t val64, unsigned int size)
	127	{
	128	STM32F2XXUsartState *s = opaque;
	129	uint32_t value = val64;
	130	unsigned char ch;
	131
	132	DB_PRINT("Write 0x%" PRIx32 ", 0x%"HWADDR_PRIx"\n", value, addr);
	133
	134	switch (addr) {
	135	case USART_SR:
	136	if (value <= 0x3FF) {
f6bfe45a RB	137	/* I/O being synchronous, TXE is always set. In addition, it may
	138	only be set by hardware, so keep it set here. */
	139	s->usart_sr = value \| USART_SR_TXE;
73af5d11 AF	140	} else {
	141	s->usart_sr &= value;
	142	}
	143	if (!(s->usart_sr & USART_SR_RXNE)) {
	144	qemu_set_irq(s->irq, 0);
	145	}
	146	return;
	147	case USART_DR:
	148	if (value < 0xF000) {
	149	ch = value;
fa394ed6 MAL	150	/* XXX this blocks entire thread. Rewrite to use
	151	* qemu_chr_fe_write and background I/O callbacks */
	152	qemu_chr_fe_write_all(&s->chr, &ch, 1);
f6bfe45a RB	153	/* XXX I/O are currently synchronous, making it impossible for
	154	software to observe transient states where TXE or TC aren't
	155	set. Unlike TXE however, which is read-only, software may
	156	clear TC by writing 0 to the SR register, so set it again
	157	on each write. */
73af5d11	158	s->usart_sr \|= USART_SR_TC;
73af5d11 AF	159	}
	160	return;
	161	case USART_BRR:
	162	s->usart_brr = value;
	163	return;
	164	case USART_CR1:
	165	s->usart_cr1 = value;
	166	if (s->usart_cr1 & USART_CR1_RXNEIE &&
	167	s->usart_sr & USART_SR_RXNE) {
	168	qemu_set_irq(s->irq, 1);
	169	}
	170	return;
	171	case USART_CR2:
	172	s->usart_cr2 = value;
	173	return;
	174	case USART_CR3:
	175	s->usart_cr3 = value;
	176	return;
	177	case USART_GTPR:
	178	s->usart_gtpr = value;
	179	return;
	180	default:
	181	qemu_log_mask(LOG_GUEST_ERROR,
	182	"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
	183	}
	184	}
	185
	186	static const MemoryRegionOps stm32f2xx_usart_ops = {
	187	.read = stm32f2xx_usart_read,
	188	.write = stm32f2xx_usart_write,
	189	.endianness = DEVICE_NATIVE_ENDIAN,
	190	};
	191
7bd43519 XZ	192	static Property stm32f2xx_usart_properties[] = {
	193	DEFINE_PROP_CHR("chardev", STM32F2XXUsartState, chr),
	194	DEFINE_PROP_END_OF_LIST(),
	195	};
	196
73af5d11 AF	197	static void stm32f2xx_usart_init(Object *obj)
	198	{
	199	STM32F2XXUsartState *s = STM32F2XX_USART(obj);
	200
	201	sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
	202
	203	memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s,
dd5d693e	204	TYPE_STM32F2XX_USART, 0x400);
73af5d11	205	sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
7bd43519	206	}
73af5d11	207
7bd43519 XZ	208	static void stm32f2xx_usart_realize(DeviceState dev, Error *errp)
	209	{
	210	STM32F2XXUsartState *s = STM32F2XX_USART(dev);
73af5d11	211
fa394ed6	212	qemu_chr_fe_set_handlers(&s->chr, stm32f2xx_usart_can_receive,
81517ba3 AN	213	stm32f2xx_usart_receive, NULL, NULL,
81517ba3 AN	214	s, NULL, true);
73af5d11 AF	215	}
	216
	217	static void stm32f2xx_usart_class_init(ObjectClass klass, void data)
	218	{
	219	DeviceClass *dc = DEVICE_CLASS(klass);
	220
	221	dc->reset = stm32f2xx_usart_reset;
7bd43519 XZ	222	dc->props = stm32f2xx_usart_properties;
7bd43519 XZ	223	dc->realize = stm32f2xx_usart_realize;
73af5d11 AF	224	}
	225
	226	static const TypeInfo stm32f2xx_usart_info = {
	227	.name = TYPE_STM32F2XX_USART,
	228	.parent = TYPE_SYS_BUS_DEVICE,
	229	.instance_size = sizeof(STM32F2XXUsartState),
	230	.instance_init = stm32f2xx_usart_init,
	231	.class_init = stm32f2xx_usart_class_init,
	232	};
	233
	234	static void stm32f2xx_usart_register_types(void)
	235	{
	236	type_register_static(&stm32f2xx_usart_info);
	237	}
	238
	239	type_init(stm32f2xx_usart_register_types)