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Commit | Line | Data |
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ee118d95 EI |
1 | /* |
2 | * QEMU model of Xilinx uartlite. | |
3 | * | |
4 | * Copyright (c) 2009 Edgar E. Iglesias. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
83c9f4ca | 25 | #include "hw/sysbus.h" |
dccfcd0e | 26 | #include "sysemu/char.h" |
ee118d95 EI |
27 | |
28 | #define DUART(x) | |
29 | ||
30 | #define R_RX 0 | |
31 | #define R_TX 1 | |
32 | #define R_STATUS 2 | |
33 | #define R_CTRL 3 | |
34 | #define R_MAX 4 | |
35 | ||
36 | #define STATUS_RXVALID 0x01 | |
37 | #define STATUS_RXFULL 0x02 | |
38 | #define STATUS_TXEMPTY 0x04 | |
39 | #define STATUS_TXFULL 0x08 | |
40 | #define STATUS_IE 0x10 | |
41 | #define STATUS_OVERRUN 0x20 | |
42 | #define STATUS_FRAME 0x40 | |
43 | #define STATUS_PARITY 0x80 | |
44 | ||
45 | #define CONTROL_RST_TX 0x01 | |
46 | #define CONTROL_RST_RX 0x02 | |
47 | #define CONTROL_IE 0x10 | |
48 | ||
24bf6c1f AF |
49 | #define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite" |
50 | #define XILINX_UARTLITE(obj) \ | |
51 | OBJECT_CHECK(XilinxUARTLite, (obj), TYPE_XILINX_UARTLITE) | |
52 | ||
144712ca | 53 | typedef struct XilinxUARTLite { |
24bf6c1f AF |
54 | SysBusDevice parent_obj; |
55 | ||
010f3f5f | 56 | MemoryRegion mmio; |
ee118d95 EI |
57 | CharDriverState *chr; |
58 | qemu_irq irq; | |
59 | ||
60 | uint8_t rx_fifo[8]; | |
61 | unsigned int rx_fifo_pos; | |
62 | unsigned int rx_fifo_len; | |
63 | ||
64 | uint32_t regs[R_MAX]; | |
144712ca | 65 | } XilinxUARTLite; |
ee118d95 | 66 | |
144712ca | 67 | static void uart_update_irq(XilinxUARTLite *s) |
ee118d95 EI |
68 | { |
69 | unsigned int irq; | |
70 | ||
71 | if (s->rx_fifo_len) | |
72 | s->regs[R_STATUS] |= STATUS_IE; | |
73 | ||
74 | irq = (s->regs[R_STATUS] & STATUS_IE) && (s->regs[R_CTRL] & CONTROL_IE); | |
75 | qemu_set_irq(s->irq, irq); | |
76 | } | |
77 | ||
144712ca | 78 | static void uart_update_status(XilinxUARTLite *s) |
ee118d95 EI |
79 | { |
80 | uint32_t r; | |
81 | ||
82 | r = s->regs[R_STATUS]; | |
83 | r &= ~7; | |
84 | r |= 1 << 2; /* Tx fifo is always empty. We are fast :) */ | |
85 | r |= (s->rx_fifo_len == sizeof (s->rx_fifo)) << 1; | |
86 | r |= (!!s->rx_fifo_len); | |
87 | s->regs[R_STATUS] = r; | |
88 | } | |
89 | ||
010f3f5f | 90 | static uint64_t |
a8170e5e | 91 | uart_read(void *opaque, hwaddr addr, unsigned int size) |
ee118d95 | 92 | { |
144712ca | 93 | XilinxUARTLite *s = opaque; |
ee118d95 EI |
94 | uint32_t r = 0; |
95 | addr >>= 2; | |
96 | switch (addr) | |
97 | { | |
98 | case R_RX: | |
99 | r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 7]; | |
100 | if (s->rx_fifo_len) | |
101 | s->rx_fifo_len--; | |
102 | uart_update_status(s); | |
103 | uart_update_irq(s); | |
80625b97 | 104 | qemu_chr_accept_input(s->chr); |
ee118d95 EI |
105 | break; |
106 | ||
107 | default: | |
108 | if (addr < ARRAY_SIZE(s->regs)) | |
109 | r = s->regs[addr]; | |
110 | DUART(qemu_log("%s addr=%x v=%x\n", __func__, addr, r)); | |
111 | break; | |
112 | } | |
113 | return r; | |
114 | } | |
115 | ||
116 | static void | |
a8170e5e | 117 | uart_write(void *opaque, hwaddr addr, |
010f3f5f | 118 | uint64_t val64, unsigned int size) |
ee118d95 | 119 | { |
144712ca | 120 | XilinxUARTLite *s = opaque; |
010f3f5f | 121 | uint32_t value = val64; |
ee118d95 EI |
122 | unsigned char ch = value; |
123 | ||
124 | addr >>= 2; | |
125 | switch (addr) | |
126 | { | |
127 | case R_STATUS: | |
128 | hw_error("write to UART STATUS?\n"); | |
129 | break; | |
130 | ||
131 | case R_CTRL: | |
132 | if (value & CONTROL_RST_RX) { | |
133 | s->rx_fifo_pos = 0; | |
134 | s->rx_fifo_len = 0; | |
135 | } | |
136 | s->regs[addr] = value; | |
137 | break; | |
138 | ||
139 | case R_TX: | |
140 | if (s->chr) | |
2cc6e0a1 | 141 | qemu_chr_fe_write(s->chr, &ch, 1); |
ee118d95 EI |
142 | |
143 | s->regs[addr] = value; | |
144 | ||
145 | /* hax. */ | |
146 | s->regs[R_STATUS] |= STATUS_IE; | |
147 | break; | |
148 | ||
149 | default: | |
150 | DUART(printf("%s addr=%x v=%x\n", __func__, addr, value)); | |
151 | if (addr < ARRAY_SIZE(s->regs)) | |
152 | s->regs[addr] = value; | |
153 | break; | |
154 | } | |
155 | uart_update_status(s); | |
156 | uart_update_irq(s); | |
157 | } | |
158 | ||
010f3f5f EI |
159 | static const MemoryRegionOps uart_ops = { |
160 | .read = uart_read, | |
161 | .write = uart_write, | |
162 | .endianness = DEVICE_NATIVE_ENDIAN, | |
163 | .valid = { | |
164 | .min_access_size = 1, | |
165 | .max_access_size = 4 | |
166 | } | |
ee118d95 EI |
167 | }; |
168 | ||
169 | static void uart_rx(void *opaque, const uint8_t *buf, int size) | |
170 | { | |
144712ca | 171 | XilinxUARTLite *s = opaque; |
ee118d95 EI |
172 | |
173 | /* Got a byte. */ | |
174 | if (s->rx_fifo_len >= 8) { | |
175 | printf("WARNING: UART dropped char.\n"); | |
176 | return; | |
177 | } | |
178 | s->rx_fifo[s->rx_fifo_pos] = *buf; | |
179 | s->rx_fifo_pos++; | |
180 | s->rx_fifo_pos &= 0x7; | |
181 | s->rx_fifo_len++; | |
182 | ||
183 | uart_update_status(s); | |
184 | uart_update_irq(s); | |
185 | } | |
186 | ||
187 | static int uart_can_rx(void *opaque) | |
188 | { | |
144712ca | 189 | XilinxUARTLite *s = opaque; |
ee118d95 | 190 | |
859cc10d | 191 | return s->rx_fifo_len < sizeof(s->rx_fifo); |
ee118d95 EI |
192 | } |
193 | ||
194 | static void uart_event(void *opaque, int event) | |
195 | { | |
196 | ||
197 | } | |
198 | ||
81a322d4 | 199 | static int xilinx_uartlite_init(SysBusDevice *dev) |
ee118d95 | 200 | { |
24bf6c1f | 201 | XilinxUARTLite *s = XILINX_UARTLITE(dev); |
ee118d95 EI |
202 | |
203 | sysbus_init_irq(dev, &s->irq); | |
204 | ||
205 | uart_update_status(s); | |
300b1fc6 PB |
206 | memory_region_init_io(&s->mmio, OBJECT(s), &uart_ops, s, |
207 | "xlnx.xps-uartlite", R_MAX * 4); | |
750ecd44 | 208 | sysbus_init_mmio(dev, &s->mmio); |
ee118d95 | 209 | |
0beb4942 | 210 | s->chr = qemu_char_get_next_serial(); |
ee118d95 EI |
211 | if (s->chr) |
212 | qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s); | |
81a322d4 | 213 | return 0; |
ee118d95 EI |
214 | } |
215 | ||
999e12bb AL |
216 | static void xilinx_uartlite_class_init(ObjectClass *klass, void *data) |
217 | { | |
218 | SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); | |
219 | ||
220 | sdc->init = xilinx_uartlite_init; | |
221 | } | |
222 | ||
8c43a6f0 | 223 | static const TypeInfo xilinx_uartlite_info = { |
24bf6c1f | 224 | .name = TYPE_XILINX_UARTLITE, |
39bffca2 | 225 | .parent = TYPE_SYS_BUS_DEVICE, |
144712ca | 226 | .instance_size = sizeof(XilinxUARTLite), |
39bffca2 | 227 | .class_init = xilinx_uartlite_class_init, |
999e12bb AL |
228 | }; |
229 | ||
83f7d43a | 230 | static void xilinx_uart_register_types(void) |
ee118d95 | 231 | { |
39bffca2 | 232 | type_register_static(&xilinx_uartlite_info); |
ee118d95 EI |
233 | } |
234 | ||
83f7d43a | 235 | type_init(xilinx_uart_register_types) |