[mirror_qemu.git] / hw / char / xilinx_uartlite.c

/*
 * QEMU model of Xilinx uartlite.
 *
 * Copyright (c) 2009 Edgar E. Iglesias.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "hw/sysbus.h"
#include "sysemu/char.h"

#define DUART(x)

#define R_RX            0
#define R_TX            1
#define R_STATUS        2
#define R_CTRL          3
#define R_MAX           4

#define STATUS_RXVALID    0x01
#define STATUS_RXFULL     0x02
#define STATUS_TXEMPTY    0x04
#define STATUS_TXFULL     0x08
#define STATUS_IE         0x10
#define STATUS_OVERRUN    0x20
#define STATUS_FRAME      0x40
#define STATUS_PARITY     0x80

#define CONTROL_RST_TX    0x01
#define CONTROL_RST_RX    0x02
#define CONTROL_IE        0x10

#define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite"
#define XILINX_UARTLITE(obj) \
    OBJECT_CHECK(XilinxUARTLite, (obj), TYPE_XILINX_UARTLITE)

typedef struct XilinxUARTLite {
    SysBusDevice parent_obj;

    MemoryRegion mmio;
    CharDriverState *chr;
    qemu_irq irq;

    uint8_t rx_fifo[8];
    unsigned int rx_fifo_pos;
    unsigned int rx_fifo_len;

    uint32_t regs[R_MAX];
} XilinxUARTLite;

static void uart_update_irq(XilinxUARTLite *s)
{
    unsigned int irq;

    if (s->rx_fifo_len)
        s->regs[R_STATUS] |= STATUS_IE;

    irq = (s->regs[R_STATUS] & STATUS_IE) && (s->regs[R_CTRL] & CONTROL_IE);
    qemu_set_irq(s->irq, irq);
}

static void uart_update_status(XilinxUARTLite *s)
{
    uint32_t r;

    r = s->regs[R_STATUS];
    r &= ~7;
    r |= 1 << 2; /* Tx fifo is always empty. We are fast :) */
    r |= (s->rx_fifo_len == sizeof (s->rx_fifo)) << 1;
    r |= (!!s->rx_fifo_len);
    s->regs[R_STATUS] = r;
}

static void xilinx_uartlite_reset(DeviceState *dev)
{
    uart_update_status(XILINX_UARTLITE(dev));
}

static uint64_t
uart_read(void *opaque, hwaddr addr, unsigned int size)
{
    XilinxUARTLite *s = opaque;
    uint32_t r = 0;
    addr >>= 2;
    switch (addr)
    {
        case R_RX:
            r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 7];
            if (s->rx_fifo_len)
                s->rx_fifo_len--;
            uart_update_status(s);
            uart_update_irq(s);
            qemu_chr_accept_input(s->chr);
            break;

        default:
            if (addr < ARRAY_SIZE(s->regs))
                r = s->regs[addr];
            DUART(qemu_log("%s addr=%x v=%x\n", __func__, addr, r));
            break;
    }
    return r;
}

static void
uart_write(void *opaque, hwaddr addr,
           uint64_t val64, unsigned int size)
{
    XilinxUARTLite *s = opaque;
    uint32_t value = val64;
    unsigned char ch = value;

    addr >>= 2;
    switch (addr)
    {
        case R_STATUS:
            hw_error("write to UART STATUS?\n");
            break;

        case R_CTRL:
            if (value & CONTROL_RST_RX) {
                s->rx_fifo_pos = 0;
                s->rx_fifo_len = 0;
            }
            s->regs[addr] = value;
            break;

        case R_TX:
            if (s->chr)
                qemu_chr_fe_write(s->chr, &ch, 1);

            s->regs[addr] = value;

            /* hax.  */
            s->regs[R_STATUS] |= STATUS_IE;
            break;

        default:
            DUART(printf("%s addr=%x v=%x\n", __func__, addr, value));
            if (addr < ARRAY_SIZE(s->regs))
                s->regs[addr] = value;
            break;
    }
    uart_update_status(s);
    uart_update_irq(s);
}

static const MemoryRegionOps uart_ops = {
    .read = uart_read,
    .write = uart_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 1,
        .max_access_size = 4
    }
};

static void uart_rx(void *opaque, const uint8_t *buf, int size)
{
    XilinxUARTLite *s = opaque;

    /* Got a byte.  */
    if (s->rx_fifo_len >= 8) {
        printf("WARNING: UART dropped char.\n");
        return;
    }
    s->rx_fifo[s->rx_fifo_pos] = *buf;
    s->rx_fifo_pos++;
    s->rx_fifo_pos &= 0x7;
    s->rx_fifo_len++;

    uart_update_status(s);
    uart_update_irq(s);
}

static int uart_can_rx(void *opaque)
{
    XilinxUARTLite *s = opaque;

    return s->rx_fifo_len < sizeof(s->rx_fifo);
}

static void uart_event(void *opaque, int event)
{

}

static void xilinx_uartlite_realize(DeviceState *dev, Error **errp)
{
    XilinxUARTLite *s = XILINX_UARTLITE(dev);

    s->chr = qemu_char_get_next_serial();
    if (s->chr)
        qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
}

static void xilinx_uartlite_init(Object *obj)
{
    XilinxUARTLite *s = XILINX_UARTLITE(obj);

    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);

    memory_region_init_io(&s->mmio, obj, &uart_ops, s,
                          "xlnx.xps-uartlite", R_MAX * 4);
    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
}

static void xilinx_uartlite_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->reset = xilinx_uartlite_reset;
    dc->realize = xilinx_uartlite_realize;
}

static const TypeInfo xilinx_uartlite_info = {
    .name          = TYPE_XILINX_UARTLITE,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(XilinxUARTLite),
    .instance_init = xilinx_uartlite_init,
    .class_init    = xilinx_uartlite_class_init,
};

static void xilinx_uart_register_types(void)
{
    type_register_static(&xilinx_uartlite_info);
}

type_init(xilinx_uart_register_types)
Commit	Line	Data
ee118d95 EI	1	/*
	2	* QEMU model of Xilinx uartlite.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
83c9f4ca	25	#include "hw/sysbus.h"
dccfcd0e	26	#include "sysemu/char.h"
ee118d95 EI	27
	28	#define DUART(x)
	29
	30	#define R_RX 0
	31	#define R_TX 1
	32	#define R_STATUS 2
	33	#define R_CTRL 3
	34	#define R_MAX 4
	35
	36	#define STATUS_RXVALID 0x01
	37	#define STATUS_RXFULL 0x02
	38	#define STATUS_TXEMPTY 0x04
	39	#define STATUS_TXFULL 0x08
	40	#define STATUS_IE 0x10
	41	#define STATUS_OVERRUN 0x20
	42	#define STATUS_FRAME 0x40
	43	#define STATUS_PARITY 0x80
	44
	45	#define CONTROL_RST_TX 0x01
	46	#define CONTROL_RST_RX 0x02
	47	#define CONTROL_IE 0x10
	48
24bf6c1f AF	49	#define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite"
	50	#define XILINX_UARTLITE(obj) \
	51	OBJECT_CHECK(XilinxUARTLite, (obj), TYPE_XILINX_UARTLITE)
	52
144712ca	53	typedef struct XilinxUARTLite {
24bf6c1f AF	54	SysBusDevice parent_obj;
24bf6c1f AF	55
010f3f5f	56	MemoryRegion mmio;
ee118d95 EI	57	CharDriverState *chr;
	58	qemu_irq irq;
	59
	60	uint8_t rx_fifo[8];
	61	unsigned int rx_fifo_pos;
	62	unsigned int rx_fifo_len;
	63
	64	uint32_t regs[R_MAX];
144712ca	65	} XilinxUARTLite;
ee118d95	66
144712ca	67	static void uart_update_irq(XilinxUARTLite *s)
ee118d95 EI	68	{
	69	unsigned int irq;
	70
	71	if (s->rx_fifo_len)
	72	s->regs[R_STATUS] \|= STATUS_IE;
	73
	74	irq = (s->regs[R_STATUS] & STATUS_IE) && (s->regs[R_CTRL] & CONTROL_IE);
	75	qemu_set_irq(s->irq, irq);
	76	}
	77
144712ca	78	static void uart_update_status(XilinxUARTLite *s)
ee118d95 EI	79	{
	80	uint32_t r;
	81
	82	r = s->regs[R_STATUS];
	83	r &= ~7;
	84	r \|= 1 << 2; /* Tx fifo is always empty. We are fast :) */
	85	r \|= (s->rx_fifo_len == sizeof (s->rx_fifo)) << 1;
	86	r \|= (!!s->rx_fifo_len);
	87	s->regs[R_STATUS] = r;
	88	}
	89
95faaa73 PC	90	static void xilinx_uartlite_reset(DeviceState *dev)
	91	{
	92	uart_update_status(XILINX_UARTLITE(dev));
	93	}
	94
010f3f5f	95	static uint64_t
a8170e5e	96	uart_read(void *opaque, hwaddr addr, unsigned int size)
ee118d95	97	{
144712ca	98	XilinxUARTLite *s = opaque;
ee118d95 EI	99	uint32_t r = 0;
	100	addr >>= 2;
	101	switch (addr)
	102	{
	103	case R_RX:
	104	r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 7];
	105	if (s->rx_fifo_len)
	106	s->rx_fifo_len--;
	107	uart_update_status(s);
	108	uart_update_irq(s);
80625b97	109	qemu_chr_accept_input(s->chr);
ee118d95 EI	110	break;
	111
	112	default:
	113	if (addr < ARRAY_SIZE(s->regs))
	114	r = s->regs[addr];
	115	DUART(qemu_log("%s addr=%x v=%x\n", __func__, addr, r));
	116	break;
	117	}
	118	return r;
	119	}
	120
	121	static void
a8170e5e	122	uart_write(void *opaque, hwaddr addr,
010f3f5f	123	uint64_t val64, unsigned int size)
ee118d95	124	{
144712ca	125	XilinxUARTLite *s = opaque;
010f3f5f	126	uint32_t value = val64;
ee118d95 EI	127	unsigned char ch = value;
	128
	129	addr >>= 2;
	130	switch (addr)
	131	{
	132	case R_STATUS:
	133	hw_error("write to UART STATUS?\n");
	134	break;
	135
	136	case R_CTRL:
	137	if (value & CONTROL_RST_RX) {
	138	s->rx_fifo_pos = 0;
	139	s->rx_fifo_len = 0;
	140	}
	141	s->regs[addr] = value;
	142	break;
	143
	144	case R_TX:
	145	if (s->chr)
2cc6e0a1	146	qemu_chr_fe_write(s->chr, &ch, 1);
ee118d95 EI	147
	148	s->regs[addr] = value;
	149
	150	/* hax. */
	151	s->regs[R_STATUS] \|= STATUS_IE;
	152	break;
	153
	154	default:
	155	DUART(printf("%s addr=%x v=%x\n", __func__, addr, value));
	156	if (addr < ARRAY_SIZE(s->regs))
	157	s->regs[addr] = value;
	158	break;
	159	}
	160	uart_update_status(s);
	161	uart_update_irq(s);
	162	}
	163
010f3f5f EI	164	static const MemoryRegionOps uart_ops = {
	165	.read = uart_read,
	166	.write = uart_write,
	167	.endianness = DEVICE_NATIVE_ENDIAN,
	168	.valid = {
	169	.min_access_size = 1,
	170	.max_access_size = 4
	171	}
ee118d95 EI	172	};
	173
	174	static void uart_rx(void opaque, const uint8_t buf, int size)
	175	{
144712ca	176	XilinxUARTLite *s = opaque;
ee118d95 EI	177
	178	/* Got a byte. */
	179	if (s->rx_fifo_len >= 8) {
	180	printf("WARNING: UART dropped char.\n");
	181	return;
	182	}
	183	s->rx_fifo[s->rx_fifo_pos] = *buf;
	184	s->rx_fifo_pos++;
	185	s->rx_fifo_pos &= 0x7;
	186	s->rx_fifo_len++;
	187
	188	uart_update_status(s);
	189	uart_update_irq(s);
	190	}
	191
	192	static int uart_can_rx(void *opaque)
	193	{
144712ca	194	XilinxUARTLite *s = opaque;
ee118d95	195
859cc10d	196	return s->rx_fifo_len < sizeof(s->rx_fifo);
ee118d95 EI	197	}
	198
	199	static void uart_event(void *opaque, int event)
	200	{
	201
	202	}
	203
aa0f607f	204	static void xilinx_uartlite_realize(DeviceState dev, Error *errp)
ee118d95	205	{
24bf6c1f	206	XilinxUARTLite *s = XILINX_UARTLITE(dev);
ee118d95	207
0beb4942	208	s->chr = qemu_char_get_next_serial();
ee118d95 EI	209	if (s->chr)
ee118d95 EI	210	qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
aa0f607f PC	211	}
	212
	213	static void xilinx_uartlite_init(Object *obj)
	214	{
	215	XilinxUARTLite *s = XILINX_UARTLITE(obj);
	216
	217	sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
	218
	219	memory_region_init_io(&s->mmio, obj, &uart_ops, s,
	220	"xlnx.xps-uartlite", R_MAX * 4);
	221	sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
ee118d95 EI	222	}
ee118d95 EI	223
999e12bb AL	224	static void xilinx_uartlite_class_init(ObjectClass klass, void data)
999e12bb AL	225	{
95faaa73	226	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	227
95faaa73	228	dc->reset = xilinx_uartlite_reset;
aa0f607f	229	dc->realize = xilinx_uartlite_realize;
999e12bb AL	230	}
999e12bb AL	231
8c43a6f0	232	static const TypeInfo xilinx_uartlite_info = {
24bf6c1f	233	.name = TYPE_XILINX_UARTLITE,
39bffca2	234	.parent = TYPE_SYS_BUS_DEVICE,
144712ca	235	.instance_size = sizeof(XilinxUARTLite),
aa0f607f	236	.instance_init = xilinx_uartlite_init,
39bffca2	237	.class_init = xilinx_uartlite_class_init,
999e12bb AL	238	};
999e12bb AL	239
83f7d43a	240	static void xilinx_uart_register_types(void)
ee118d95	241	{
39bffca2	242	type_register_static(&xilinx_uartlite_info);
ee118d95 EI	243	}
ee118d95 EI	244
83f7d43a	245	type_init(xilinx_uart_register_types)