[mirror_qemu.git] / hw / char / xilinx_uartlite.c

/*
 * QEMU model of Xilinx uartlite.
 *
 * Copyright (c) 2009 Edgar E. Iglesias.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "qemu/log.h"
#include "hw/char/xilinx_uartlite.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-properties-system.h"
#include "hw/sysbus.h"
#include "qemu/module.h"
#include "chardev/char-fe.h"
#include "qom/object.h"

#define DUART(x)

#define R_RX            0
#define R_TX            1
#define R_STATUS        2
#define R_CTRL          3
#define R_MAX           4

#define STATUS_RXVALID    0x01
#define STATUS_RXFULL     0x02
#define STATUS_TXEMPTY    0x04
#define STATUS_TXFULL     0x08
#define STATUS_IE         0x10
#define STATUS_OVERRUN    0x20
#define STATUS_FRAME      0x40
#define STATUS_PARITY     0x80

#define CONTROL_RST_TX    0x01
#define CONTROL_RST_RX    0x02
#define CONTROL_IE        0x10

struct XilinxUARTLite {
    SysBusDevice parent_obj;

    MemoryRegion mmio;
    CharBackend chr;
    qemu_irq irq;

    uint8_t rx_fifo[8];
    unsigned int rx_fifo_pos;
    unsigned int rx_fifo_len;

    uint32_t regs[R_MAX];
};

static void uart_update_irq(XilinxUARTLite *s)
{
    unsigned int irq;

    if (s->rx_fifo_len)
        s->regs[R_STATUS] |= STATUS_IE;

    irq = (s->regs[R_STATUS] & STATUS_IE) && (s->regs[R_CTRL] & CONTROL_IE);
    qemu_set_irq(s->irq, irq);
}

static void uart_update_status(XilinxUARTLite *s)
{
    uint32_t r;

    r = s->regs[R_STATUS];
    r &= ~7;
    r |= 1 << 2; /* Tx fifo is always empty. We are fast :) */
    r |= (s->rx_fifo_len == sizeof (s->rx_fifo)) << 1;
    r |= (!!s->rx_fifo_len);
    s->regs[R_STATUS] = r;
}

static void xilinx_uartlite_reset(DeviceState *dev)
{
    uart_update_status(XILINX_UARTLITE(dev));
}

static uint64_t
uart_read(void *opaque, hwaddr addr, unsigned int size)
{
    XilinxUARTLite *s = opaque;
    uint32_t r = 0;
    addr >>= 2;
    switch (addr)
    {
        case R_RX:
            r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 7];
            if (s->rx_fifo_len)
                s->rx_fifo_len--;
            uart_update_status(s);
            uart_update_irq(s);
            qemu_chr_fe_accept_input(&s->chr);
            break;

        default:
            if (addr < ARRAY_SIZE(s->regs))
                r = s->regs[addr];
            DUART(qemu_log("%s addr=%x v=%x\n", __func__, addr, r));
            break;
    }
    return r;
}

static void
uart_write(void *opaque, hwaddr addr,
           uint64_t val64, unsigned int size)
{
    XilinxUARTLite *s = opaque;
    uint32_t value = val64;
    unsigned char ch = value;

    addr >>= 2;
    switch (addr)
    {
        case R_STATUS:
            qemu_log_mask(LOG_GUEST_ERROR, "%s: write to UART STATUS\n",
                          __func__);
            break;

        case R_CTRL:
            if (value & CONTROL_RST_RX) {
                s->rx_fifo_pos = 0;
                s->rx_fifo_len = 0;
            }
            s->regs[addr] = value;
            break;

        case R_TX:
            /* XXX this blocks entire thread. Rewrite to use
             * qemu_chr_fe_write and background I/O callbacks */
            qemu_chr_fe_write_all(&s->chr, &ch, 1);
            s->regs[addr] = value;

            /* hax.  */
            s->regs[R_STATUS] |= STATUS_IE;
            break;

        default:
            DUART(printf("%s addr=%x v=%x\n", __func__, addr, value));
            if (addr < ARRAY_SIZE(s->regs))
                s->regs[addr] = value;
            break;
    }
    uart_update_status(s);
    uart_update_irq(s);
}

static const MemoryRegionOps uart_ops = {
    .read = uart_read,
    .write = uart_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 1,
        .max_access_size = 4
    }
};

static Property xilinx_uartlite_properties[] = {
    DEFINE_PROP_CHR("chardev", XilinxUARTLite, chr),
    DEFINE_PROP_END_OF_LIST(),
};

static void uart_rx(void *opaque, const uint8_t *buf, int size)
{
    XilinxUARTLite *s = opaque;

    /* Got a byte.  */
    if (s->rx_fifo_len >= 8) {
        printf("WARNING: UART dropped char.\n");
        return;
    }
    s->rx_fifo[s->rx_fifo_pos] = *buf;
    s->rx_fifo_pos++;
    s->rx_fifo_pos &= 0x7;
    s->rx_fifo_len++;

    uart_update_status(s);
    uart_update_irq(s);
}

static int uart_can_rx(void *opaque)
{
    XilinxUARTLite *s = opaque;

    return s->rx_fifo_len < sizeof(s->rx_fifo);
}

static void uart_event(void *opaque, QEMUChrEvent event)
{

}

static void xilinx_uartlite_realize(DeviceState *dev, Error **errp)
{
    XilinxUARTLite *s = XILINX_UARTLITE(dev);

    qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
                             uart_event, NULL, s, NULL, true);
}

static void xilinx_uartlite_init(Object *obj)
{
    XilinxUARTLite *s = XILINX_UARTLITE(obj);

    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);

    memory_region_init_io(&s->mmio, obj, &uart_ops, s,
                          "xlnx.xps-uartlite", R_MAX * 4);
    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
}

static void xilinx_uartlite_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->reset = xilinx_uartlite_reset;
    dc->realize = xilinx_uartlite_realize;
    device_class_set_props(dc, xilinx_uartlite_properties);
}

static const TypeInfo xilinx_uartlite_info = {
    .name          = TYPE_XILINX_UARTLITE,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(XilinxUARTLite),
    .instance_init = xilinx_uartlite_init,
    .class_init    = xilinx_uartlite_class_init,
};

static void xilinx_uart_register_types(void)
{
    type_register_static(&xilinx_uartlite_info);
}

type_init(xilinx_uart_register_types)
Commit	Line	Data
ee118d95 EI	1	/*
	2	* QEMU model of Xilinx uartlite.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
17b7f2db	25	#include "qemu/osdep.h"
492edf3e	26	#include "qemu/log.h"
3440a4a9	27	#include "hw/char/xilinx_uartlite.h"
64552b6b	28	#include "hw/irq.h"
a27bd6c7	29	#include "hw/qdev-properties.h"
ce35e229	30	#include "hw/qdev-properties-system.h"
83c9f4ca	31	#include "hw/sysbus.h"
0b8fa32f	32	#include "qemu/module.h"
4d43a603	33	#include "chardev/char-fe.h"
db1015e9	34	#include "qom/object.h"
ee118d95 EI	35
	36	#define DUART(x)
	37
	38	#define R_RX 0
	39	#define R_TX 1
	40	#define R_STATUS 2
	41	#define R_CTRL 3
	42	#define R_MAX 4
	43
	44	#define STATUS_RXVALID 0x01
	45	#define STATUS_RXFULL 0x02
	46	#define STATUS_TXEMPTY 0x04
	47	#define STATUS_TXFULL 0x08
	48	#define STATUS_IE 0x10
	49	#define STATUS_OVERRUN 0x20
	50	#define STATUS_FRAME 0x40
	51	#define STATUS_PARITY 0x80
	52
	53	#define CONTROL_RST_TX 0x01
	54	#define CONTROL_RST_RX 0x02
	55	#define CONTROL_IE 0x10
	56
db1015e9	57	struct XilinxUARTLite {
24bf6c1f AF	58	SysBusDevice parent_obj;
24bf6c1f AF	59
010f3f5f	60	MemoryRegion mmio;
becdfa00	61	CharBackend chr;
ee118d95 EI	62	qemu_irq irq;
	63
	64	uint8_t rx_fifo[8];
	65	unsigned int rx_fifo_pos;
	66	unsigned int rx_fifo_len;
	67
	68	uint32_t regs[R_MAX];
db1015e9	69	};
ee118d95	70
144712ca	71	static void uart_update_irq(XilinxUARTLite *s)
ee118d95 EI	72	{
	73	unsigned int irq;
	74
	75	if (s->rx_fifo_len)
	76	s->regs[R_STATUS] \|= STATUS_IE;
	77
	78	irq = (s->regs[R_STATUS] & STATUS_IE) && (s->regs[R_CTRL] & CONTROL_IE);
	79	qemu_set_irq(s->irq, irq);
	80	}
	81
144712ca	82	static void uart_update_status(XilinxUARTLite *s)
ee118d95 EI	83	{
	84	uint32_t r;
	85
	86	r = s->regs[R_STATUS];
	87	r &= ~7;
	88	r \|= 1 << 2; /* Tx fifo is always empty. We are fast :) */
	89	r \|= (s->rx_fifo_len == sizeof (s->rx_fifo)) << 1;
	90	r \|= (!!s->rx_fifo_len);
	91	s->regs[R_STATUS] = r;
	92	}
	93
95faaa73 PC	94	static void xilinx_uartlite_reset(DeviceState *dev)
	95	{
	96	uart_update_status(XILINX_UARTLITE(dev));
	97	}
	98
010f3f5f	99	static uint64_t
a8170e5e	100	uart_read(void *opaque, hwaddr addr, unsigned int size)
ee118d95	101	{
144712ca	102	XilinxUARTLite *s = opaque;
ee118d95 EI	103	uint32_t r = 0;
	104	addr >>= 2;
	105	switch (addr)
	106	{
	107	case R_RX:
	108	r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 7];
	109	if (s->rx_fifo_len)
	110	s->rx_fifo_len--;
	111	uart_update_status(s);
	112	uart_update_irq(s);
5345fdb4	113	qemu_chr_fe_accept_input(&s->chr);
ee118d95 EI	114	break;
	115
	116	default:
	117	if (addr < ARRAY_SIZE(s->regs))
	118	r = s->regs[addr];
	119	DUART(qemu_log("%s addr=%x v=%x\n", __func__, addr, r));
	120	break;
	121	}
	122	return r;
	123	}
	124
	125	static void
a8170e5e	126	uart_write(void *opaque, hwaddr addr,
010f3f5f	127	uint64_t val64, unsigned int size)
ee118d95	128	{
144712ca	129	XilinxUARTLite *s = opaque;
010f3f5f	130	uint32_t value = val64;
ee118d95 EI	131	unsigned char ch = value;
	132
	133	addr >>= 2;
	134	switch (addr)
	135	{
	136	case R_STATUS:
492edf3e PMD	137	qemu_log_mask(LOG_GUEST_ERROR, "%s: write to UART STATUS\n",
492edf3e PMD	138	__func__);
ee118d95 EI	139	break;
	140
	141	case R_CTRL:
	142	if (value & CONTROL_RST_RX) {
	143	s->rx_fifo_pos = 0;
	144	s->rx_fifo_len = 0;
	145	}
	146	s->regs[addr] = value;
	147	break;
	148
	149	case R_TX:
fa394ed6 MAL	150	/* XXX this blocks entire thread. Rewrite to use
	151	* qemu_chr_fe_write and background I/O callbacks */
	152	qemu_chr_fe_write_all(&s->chr, &ch, 1);
ee118d95 EI	153	s->regs[addr] = value;
	154
	155	/* hax. */
	156	s->regs[R_STATUS] \|= STATUS_IE;
	157	break;
	158
	159	default:
	160	DUART(printf("%s addr=%x v=%x\n", __func__, addr, value));
	161	if (addr < ARRAY_SIZE(s->regs))
	162	s->regs[addr] = value;
	163	break;
	164	}
	165	uart_update_status(s);
	166	uart_update_irq(s);
	167	}
	168
010f3f5f EI	169	static const MemoryRegionOps uart_ops = {
	170	.read = uart_read,
	171	.write = uart_write,
	172	.endianness = DEVICE_NATIVE_ENDIAN,
	173	.valid = {
	174	.min_access_size = 1,
	175	.max_access_size = 4
	176	}
ee118d95 EI	177	};
ee118d95 EI	178
1b6d0781 XZ	179	static Property xilinx_uartlite_properties[] = {
	180	DEFINE_PROP_CHR("chardev", XilinxUARTLite, chr),
	181	DEFINE_PROP_END_OF_LIST(),
	182	};
	183
ee118d95 EI	184	static void uart_rx(void opaque, const uint8_t buf, int size)
ee118d95 EI	185	{
144712ca	186	XilinxUARTLite *s = opaque;
ee118d95 EI	187
	188	/* Got a byte. */
	189	if (s->rx_fifo_len >= 8) {
	190	printf("WARNING: UART dropped char.\n");
	191	return;
	192	}
	193	s->rx_fifo[s->rx_fifo_pos] = *buf;
	194	s->rx_fifo_pos++;
	195	s->rx_fifo_pos &= 0x7;
	196	s->rx_fifo_len++;
	197
	198	uart_update_status(s);
	199	uart_update_irq(s);
	200	}
	201
	202	static int uart_can_rx(void *opaque)
	203	{
144712ca	204	XilinxUARTLite *s = opaque;
ee118d95	205
859cc10d	206	return s->rx_fifo_len < sizeof(s->rx_fifo);
ee118d95 EI	207	}
ee118d95 EI	208
083b266f	209	static void uart_event(void *opaque, QEMUChrEvent event)
ee118d95 EI	210	{
	211
	212	}
	213
aa0f607f	214	static void xilinx_uartlite_realize(DeviceState dev, Error *errp)
ee118d95	215	{
24bf6c1f	216	XilinxUARTLite *s = XILINX_UARTLITE(dev);
ee118d95	217
fa394ed6	218	qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
81517ba3	219	uart_event, NULL, s, NULL, true);
aa0f607f PC	220	}
	221
	222	static void xilinx_uartlite_init(Object *obj)
	223	{
	224	XilinxUARTLite *s = XILINX_UARTLITE(obj);
	225
	226	sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
	227
	228	memory_region_init_io(&s->mmio, obj, &uart_ops, s,
	229	"xlnx.xps-uartlite", R_MAX * 4);
	230	sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
ee118d95 EI	231	}
ee118d95 EI	232
999e12bb AL	233	static void xilinx_uartlite_class_init(ObjectClass klass, void data)
999e12bb AL	234	{
95faaa73	235	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	236
95faaa73	237	dc->reset = xilinx_uartlite_reset;
aa0f607f	238	dc->realize = xilinx_uartlite_realize;
4f67d30b	239	device_class_set_props(dc, xilinx_uartlite_properties);
999e12bb AL	240	}
999e12bb AL	241
8c43a6f0	242	static const TypeInfo xilinx_uartlite_info = {
24bf6c1f	243	.name = TYPE_XILINX_UARTLITE,
39bffca2	244	.parent = TYPE_SYS_BUS_DEVICE,
144712ca	245	.instance_size = sizeof(XilinxUARTLite),
aa0f607f	246	.instance_init = xilinx_uartlite_init,
39bffca2	247	.class_init = xilinx_uartlite_class_init,
999e12bb AL	248	};
999e12bb AL	249
83f7d43a	250	static void xilinx_uart_register_types(void)
ee118d95	251	{
39bffca2	252	type_register_static(&xilinx_uartlite_info);
ee118d95 EI	253	}
ee118d95 EI	254
83f7d43a	255	type_init(xilinx_uart_register_types)