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e6e5ad80 1/*
aeb3c85f 2 * QEMU Cirrus CLGD 54xx VGA Emulator.
5fafdf24 3 *
e6e5ad80 4 * Copyright (c) 2004 Fabrice Bellard
aeb3c85f 5 * Copyright (c) 2004 Makoto Suzuki (suzu)
5fafdf24 6 *
e6e5ad80
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
aeb3c85f
FB		 25/*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
87ecb68b 29#include "hw.h"
87ecb68b
PB		 30#include "pci.h"
31#include "console.h"
e6e5ad80 32#include "vga_int.h"
5245d57a 33#include "loader.h"
e6e5ad80 34
a5082316
FB		 35/*
36 * TODO:
ad81218e 37 * - destination write mask support not complete (bits 5..7)
a5082316
FB		 38 * - optimize linear mappings
39 * - optimize bitblt functions
40 */
41
e36f36e1 42//#define DEBUG_CIRRUS
a21ae81d 43//#define DEBUG_BITBLT
e36f36e1 44
e6e5ad80
FB		 45/***************************************
46 *
47 * definitions
48 *
49 ***************************************/
50
e6e5ad80
FB		 51// ID
52#define CIRRUS_ID_CLGD5422 (0x23<<2)
53#define CIRRUS_ID_CLGD5426 (0x24<<2)
54#define CIRRUS_ID_CLGD5424 (0x25<<2)
55#define CIRRUS_ID_CLGD5428 (0x26<<2)
56#define CIRRUS_ID_CLGD5430 (0x28<<2)
57#define CIRRUS_ID_CLGD5434 (0x2A<<2)
a21ae81d 58#define CIRRUS_ID_CLGD5436 (0x2B<<2)
e6e5ad80
FB		 59#define CIRRUS_ID_CLGD5446 (0x2E<<2)
60
61// sequencer 0x07
62#define CIRRUS_SR7_BPP_VGA 0x00
63#define CIRRUS_SR7_BPP_SVGA 0x01
64#define CIRRUS_SR7_BPP_MASK 0x0e
65#define CIRRUS_SR7_BPP_8 0x00
66#define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
67#define CIRRUS_SR7_BPP_24 0x04
68#define CIRRUS_SR7_BPP_16 0x06
69#define CIRRUS_SR7_BPP_32 0x08
70#define CIRRUS_SR7_ISAADDR_MASK 0xe0
71
72// sequencer 0x0f
73#define CIRRUS_MEMSIZE_512k 0x08
74#define CIRRUS_MEMSIZE_1M 0x10
75#define CIRRUS_MEMSIZE_2M 0x18
76#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
77
78// sequencer 0x12
79#define CIRRUS_CURSOR_SHOW 0x01
80#define CIRRUS_CURSOR_HIDDENPEL 0x02
81#define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
82
83// sequencer 0x17
84#define CIRRUS_BUSTYPE_VLBFAST 0x10
85#define CIRRUS_BUSTYPE_PCI 0x20
86#define CIRRUS_BUSTYPE_VLBSLOW 0x30
87#define CIRRUS_BUSTYPE_ISA 0x38
88#define CIRRUS_MMIO_ENABLE 0x04
89#define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
90#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
91
92// control 0x0b
93#define CIRRUS_BANKING_DUAL 0x01
94#define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
95
96// control 0x30
97#define CIRRUS_BLTMODE_BACKWARDS 0x01
98#define CIRRUS_BLTMODE_MEMSYSDEST 0x02
99#define CIRRUS_BLTMODE_MEMSYSSRC 0x04
100#define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
101#define CIRRUS_BLTMODE_PATTERNCOPY 0x40
102#define CIRRUS_BLTMODE_COLOREXPAND 0x80
103#define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
104#define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
105#define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
106#define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
107#define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
108
109// control 0x31
110#define CIRRUS_BLT_BUSY 0x01
111#define CIRRUS_BLT_START 0x02
112#define CIRRUS_BLT_RESET 0x04
113#define CIRRUS_BLT_FIFOUSED 0x10
a5082316 114#define CIRRUS_BLT_AUTOSTART 0x80
e6e5ad80
FB		 115
116// control 0x32
117#define CIRRUS_ROP_0 0x00
118#define CIRRUS_ROP_SRC_AND_DST 0x05
119#define CIRRUS_ROP_NOP 0x06
120#define CIRRUS_ROP_SRC_AND_NOTDST 0x09
121#define CIRRUS_ROP_NOTDST 0x0b
122#define CIRRUS_ROP_SRC 0x0d
123#define CIRRUS_ROP_1 0x0e
124#define CIRRUS_ROP_NOTSRC_AND_DST 0x50
125#define CIRRUS_ROP_SRC_XOR_DST 0x59
126#define CIRRUS_ROP_SRC_OR_DST 0x6d
127#define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
128#define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
129#define CIRRUS_ROP_SRC_OR_NOTDST 0xad
130#define CIRRUS_ROP_NOTSRC 0xd0
131#define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
132#define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
133
a5082316
FB		 134#define CIRRUS_ROP_NOP_INDEX 2
135#define CIRRUS_ROP_SRC_INDEX 5
136
a21ae81d 137// control 0x33
a5082316 138#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
4c8732d7 139#define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
a5082316 140#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
a21ae81d 141
e6e5ad80
FB		 142// memory-mapped IO
143#define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
144#define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
145#define CIRRUS_MMIO_BLTWIDTH 0x08 // word
146#define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
147#define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
148#define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
149#define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
150#define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
151#define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
152#define CIRRUS_MMIO_BLTMODE 0x18 // byte
153#define CIRRUS_MMIO_BLTROP 0x1a // byte
154#define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
155#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
156#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
157#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
158#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
159#define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
160#define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
161#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
162#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
163#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
164#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
165#define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
166#define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
167#define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
168#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
169#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
170#define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
171#define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
172
a21ae81d 173#define CIRRUS_PNPMMIO_SIZE 0x1000
e6e5ad80 174
b2eb849d
AJ		 175#define BLTUNSAFE(s) \
176 ( \
177 ( /* check dst is within bounds */ \
b2b183c2 178 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
b2eb849d 179 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
4e12cd94 180 (s)->vga.vram_size \
b2eb849d
AJ		 181 ) || \
182 ( /* check src is within bounds */ \
b2b183c2 183 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
b2eb849d 184 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
4e12cd94 185 (s)->vga.vram_size \
b2eb849d
AJ		 186 ) \
187 )
188
a5082316
FB		 189struct CirrusVGAState;
190typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
191 uint8_t * dst, const uint8_t * src,
e6e5ad80
FB		 192 int dstpitch, int srcpitch,
193 int bltwidth, int bltheight);
a5082316
FB		 194typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
195 uint8_t *dst, int dst_pitch, int width, int height);
e6e5ad80
FB		 196
197typedef struct CirrusVGAState {
4e12cd94 198 VGACommonState vga;
e6e5ad80 199
b1950430
AK		 200 MemoryRegion cirrus_linear_io;
201 MemoryRegion cirrus_linear_bitblt_io;
202 MemoryRegion cirrus_mmio_io;
203 MemoryRegion pci_bar;
204 bool linear_vram; /* vga.vram mapped over cirrus_linear_io */
205 MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */
206 MemoryRegion low_mem; /* always mapped, overridden by: */
7969d9ed 207 MemoryRegion cirrus_bank[2]; /* aliases at 0xa0000-0xb0000 */
e6e5ad80 208 uint32_t cirrus_addr_mask;
78e127ef 209 uint32_t linear_mmio_mask;
e6e5ad80
FB		 210 uint8_t cirrus_shadow_gr0;
211 uint8_t cirrus_shadow_gr1;
212 uint8_t cirrus_hidden_dac_lockindex;
213 uint8_t cirrus_hidden_dac_data;
214 uint32_t cirrus_bank_base[2];
215 uint32_t cirrus_bank_limit[2];
216 uint8_t cirrus_hidden_palette[48];
a5082316
FB		 217 uint32_t hw_cursor_x;
218 uint32_t hw_cursor_y;
e6e5ad80
FB		 219 int cirrus_blt_pixelwidth;
220 int cirrus_blt_width;
221 int cirrus_blt_height;
222 int cirrus_blt_dstpitch;
223 int cirrus_blt_srcpitch;
a5082316
FB		 224 uint32_t cirrus_blt_fgcol;
225 uint32_t cirrus_blt_bgcol;
e6e5ad80
FB		 226 uint32_t cirrus_blt_dstaddr;
227 uint32_t cirrus_blt_srcaddr;
228 uint8_t cirrus_blt_mode;
a5082316 229 uint8_t cirrus_blt_modeext;
e6e5ad80 230 cirrus_bitblt_rop_t cirrus_rop;
a5082316 231#define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
e6e5ad80
FB		 232 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
233 uint8_t *cirrus_srcptr;
234 uint8_t *cirrus_srcptr_end;
235 uint32_t cirrus_srccounter;
a5082316
FB		 236 /* hwcursor display state */
237 int last_hw_cursor_size;
238 int last_hw_cursor_x;
239 int last_hw_cursor_y;
240 int last_hw_cursor_y_start;
241 int last_hw_cursor_y_end;
78e127ef 242 int real_vram_size; /* XXX: suppress that */
4abc796d
BS		 243 int device_id;
244 int bustype;
e6e5ad80
FB		 245} CirrusVGAState;
246
247typedef struct PCICirrusVGAState {
248 PCIDevice dev;
249 CirrusVGAState cirrus_vga;
250} PCICirrusVGAState;
251
3d402831
BS		 252typedef struct ISACirrusVGAState {
253 ISADevice dev;
254 CirrusVGAState cirrus_vga;
255} ISACirrusVGAState;
256
a5082316 257static uint8_t rop_to_index[256];
3b46e624 258
e6e5ad80
FB		 259/***************************************
260 *
261 * prototypes.
262 *
263 ***************************************/
264
265
8926b517
FB		 266static void cirrus_bitblt_reset(CirrusVGAState *s);
267static void cirrus_update_memory_access(CirrusVGAState *s);
e6e5ad80
FB		 268
269/***************************************
270 *
271 * raster operations
272 *
273 ***************************************/
274
a5082316
FB		 275static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
276 uint8_t *dst,const uint8_t *src,
277 int dstpitch,int srcpitch,
278 int bltwidth,int bltheight)
279{
e6e5ad80
FB		 280}
281
a5082316
FB		 282static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
283 uint8_t *dst,
284 int dstpitch, int bltwidth,int bltheight)
e6e5ad80 285{
a5082316 286}
e6e5ad80 287
a5082316 288#define ROP_NAME 0
8c78881f 289#define ROP_FN(d, s) 0
a5082316 290#include "cirrus_vga_rop.h"
e6e5ad80 291
a5082316 292#define ROP_NAME src_and_dst
8c78881f 293#define ROP_FN(d, s) (s) & (d)
a5082316 294#include "cirrus_vga_rop.h"
e6e5ad80 295
a5082316 296#define ROP_NAME src_and_notdst
8c78881f 297#define ROP_FN(d, s) (s) & (~(d))
a5082316 298#include "cirrus_vga_rop.h"
e6e5ad80 299
a5082316 300#define ROP_NAME notdst
8c78881f 301#define ROP_FN(d, s) ~(d)
a5082316 302#include "cirrus_vga_rop.h"
e6e5ad80 303
a5082316 304#define ROP_NAME src
8c78881f 305#define ROP_FN(d, s) s
a5082316 306#include "cirrus_vga_rop.h"
e6e5ad80 307
a5082316 308#define ROP_NAME 1
8c78881f 309#define ROP_FN(d, s) ~0
a5082316
FB		 310#include "cirrus_vga_rop.h"
311
312#define ROP_NAME notsrc_and_dst
8c78881f 313#define ROP_FN(d, s) (~(s)) & (d)
a5082316
FB		 314#include "cirrus_vga_rop.h"
315
316#define ROP_NAME src_xor_dst
8c78881f 317#define ROP_FN(d, s) (s) ^ (d)
a5082316
FB		 318#include "cirrus_vga_rop.h"
319
320#define ROP_NAME src_or_dst
8c78881f 321#define ROP_FN(d, s) (s) | (d)
a5082316
FB		 322#include "cirrus_vga_rop.h"
323
324#define ROP_NAME notsrc_or_notdst
8c78881f 325#define ROP_FN(d, s) (~(s)) | (~(d))
a5082316
FB		 326#include "cirrus_vga_rop.h"
327
328#define ROP_NAME src_notxor_dst
8c78881f 329#define ROP_FN(d, s) ~((s) ^ (d))
a5082316 330#include "cirrus_vga_rop.h"
e6e5ad80 331
a5082316 332#define ROP_NAME src_or_notdst
8c78881f 333#define ROP_FN(d, s) (s) | (~(d))
a5082316
FB		 334#include "cirrus_vga_rop.h"
335
336#define ROP_NAME notsrc
8c78881f 337#define ROP_FN(d, s) (~(s))
a5082316
FB		 338#include "cirrus_vga_rop.h"
339
340#define ROP_NAME notsrc_or_dst
8c78881f 341#define ROP_FN(d, s) (~(s)) | (d)
a5082316
FB		 342#include "cirrus_vga_rop.h"
343
344#define ROP_NAME notsrc_and_notdst
8c78881f 345#define ROP_FN(d, s) (~(s)) & (~(d))
a5082316
FB		 346#include "cirrus_vga_rop.h"
347
348static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
349 cirrus_bitblt_rop_fwd_0,
350 cirrus_bitblt_rop_fwd_src_and_dst,
351 cirrus_bitblt_rop_nop,
352 cirrus_bitblt_rop_fwd_src_and_notdst,
353 cirrus_bitblt_rop_fwd_notdst,
354 cirrus_bitblt_rop_fwd_src,
355 cirrus_bitblt_rop_fwd_1,
356 cirrus_bitblt_rop_fwd_notsrc_and_dst,
357 cirrus_bitblt_rop_fwd_src_xor_dst,
358 cirrus_bitblt_rop_fwd_src_or_dst,
359 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
360 cirrus_bitblt_rop_fwd_src_notxor_dst,
361 cirrus_bitblt_rop_fwd_src_or_notdst,
362 cirrus_bitblt_rop_fwd_notsrc,
363 cirrus_bitblt_rop_fwd_notsrc_or_dst,
364 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
365};
366
367static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
368 cirrus_bitblt_rop_bkwd_0,
369 cirrus_bitblt_rop_bkwd_src_and_dst,
370 cirrus_bitblt_rop_nop,
371 cirrus_bitblt_rop_bkwd_src_and_notdst,
372 cirrus_bitblt_rop_bkwd_notdst,
373 cirrus_bitblt_rop_bkwd_src,
374 cirrus_bitblt_rop_bkwd_1,
375 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
376 cirrus_bitblt_rop_bkwd_src_xor_dst,
377 cirrus_bitblt_rop_bkwd_src_or_dst,
378 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
379 cirrus_bitblt_rop_bkwd_src_notxor_dst,
380 cirrus_bitblt_rop_bkwd_src_or_notdst,
381 cirrus_bitblt_rop_bkwd_notsrc,
382 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
383 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
384};
96cf2df8
TS		 385
386#define TRANSP_ROP(name) {\
387 name ## _8,\
388 name ## _16,\
389 }
390#define TRANSP_NOP(func) {\
391 func,\
392 func,\
393 }
394
395static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
396 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
397 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
398 TRANSP_NOP(cirrus_bitblt_rop_nop),
399 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
400 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
401 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
402 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
403 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
404 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
405 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
406 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
407 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
408 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
409 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
410 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
411 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
412};
413
414static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
415 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
416 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
417 TRANSP_NOP(cirrus_bitblt_rop_nop),
418 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
419 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
420 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
421 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
422 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
423 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
424 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
425 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
426 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
427 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
428 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
429 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
430 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
431};
432
a5082316
FB		 433#define ROP2(name) {\
434 name ## _8,\
435 name ## _16,\
436 name ## _24,\
437 name ## _32,\
438 }
439
440#define ROP_NOP2(func) {\
441 func,\
442 func,\
443 func,\
444 func,\
445 }
446
e69390ce
FB		 447static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
448 ROP2(cirrus_patternfill_0),
449 ROP2(cirrus_patternfill_src_and_dst),
450 ROP_NOP2(cirrus_bitblt_rop_nop),
451 ROP2(cirrus_patternfill_src_and_notdst),
452 ROP2(cirrus_patternfill_notdst),
453 ROP2(cirrus_patternfill_src),
454 ROP2(cirrus_patternfill_1),
455 ROP2(cirrus_patternfill_notsrc_and_dst),
456 ROP2(cirrus_patternfill_src_xor_dst),
457 ROP2(cirrus_patternfill_src_or_dst),
458 ROP2(cirrus_patternfill_notsrc_or_notdst),
459 ROP2(cirrus_patternfill_src_notxor_dst),
460 ROP2(cirrus_patternfill_src_or_notdst),
461 ROP2(cirrus_patternfill_notsrc),
462 ROP2(cirrus_patternfill_notsrc_or_dst),
463 ROP2(cirrus_patternfill_notsrc_and_notdst),
464};
465
a5082316
FB		 466static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
467 ROP2(cirrus_colorexpand_transp_0),
468 ROP2(cirrus_colorexpand_transp_src_and_dst),
469 ROP_NOP2(cirrus_bitblt_rop_nop),
470 ROP2(cirrus_colorexpand_transp_src_and_notdst),
471 ROP2(cirrus_colorexpand_transp_notdst),
472 ROP2(cirrus_colorexpand_transp_src),
473 ROP2(cirrus_colorexpand_transp_1),
474 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
475 ROP2(cirrus_colorexpand_transp_src_xor_dst),
476 ROP2(cirrus_colorexpand_transp_src_or_dst),
477 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
478 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
479 ROP2(cirrus_colorexpand_transp_src_or_notdst),
480 ROP2(cirrus_colorexpand_transp_notsrc),
481 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
482 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
483};
484
485static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
486 ROP2(cirrus_colorexpand_0),
487 ROP2(cirrus_colorexpand_src_and_dst),
488 ROP_NOP2(cirrus_bitblt_rop_nop),
489 ROP2(cirrus_colorexpand_src_and_notdst),
490 ROP2(cirrus_colorexpand_notdst),
491 ROP2(cirrus_colorexpand_src),
492 ROP2(cirrus_colorexpand_1),
493 ROP2(cirrus_colorexpand_notsrc_and_dst),
494 ROP2(cirrus_colorexpand_src_xor_dst),
495 ROP2(cirrus_colorexpand_src_or_dst),
496 ROP2(cirrus_colorexpand_notsrc_or_notdst),
497 ROP2(cirrus_colorexpand_src_notxor_dst),
498 ROP2(cirrus_colorexpand_src_or_notdst),
499 ROP2(cirrus_colorexpand_notsrc),
500 ROP2(cirrus_colorexpand_notsrc_or_dst),
501 ROP2(cirrus_colorexpand_notsrc_and_notdst),
502};
503
b30d4608
FB		 504static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
505 ROP2(cirrus_colorexpand_pattern_transp_0),
506 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
507 ROP_NOP2(cirrus_bitblt_rop_nop),
508 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
509 ROP2(cirrus_colorexpand_pattern_transp_notdst),
510 ROP2(cirrus_colorexpand_pattern_transp_src),
511 ROP2(cirrus_colorexpand_pattern_transp_1),
512 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
513 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
514 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
515 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
516 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
517 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
518 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
519 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
520 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
521};
522
523static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
524 ROP2(cirrus_colorexpand_pattern_0),
525 ROP2(cirrus_colorexpand_pattern_src_and_dst),
526 ROP_NOP2(cirrus_bitblt_rop_nop),
527 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
528 ROP2(cirrus_colorexpand_pattern_notdst),
529 ROP2(cirrus_colorexpand_pattern_src),
530 ROP2(cirrus_colorexpand_pattern_1),
531 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
532 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
533 ROP2(cirrus_colorexpand_pattern_src_or_dst),
534 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
535 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
536 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
537 ROP2(cirrus_colorexpand_pattern_notsrc),
538 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
539 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
540};
541
a5082316
FB		 542static const cirrus_fill_t cirrus_fill[16][4] = {
543 ROP2(cirrus_fill_0),
544 ROP2(cirrus_fill_src_and_dst),
545 ROP_NOP2(cirrus_bitblt_fill_nop),
546 ROP2(cirrus_fill_src_and_notdst),
547 ROP2(cirrus_fill_notdst),
548 ROP2(cirrus_fill_src),
549 ROP2(cirrus_fill_1),
550 ROP2(cirrus_fill_notsrc_and_dst),
551 ROP2(cirrus_fill_src_xor_dst),
552 ROP2(cirrus_fill_src_or_dst),
553 ROP2(cirrus_fill_notsrc_or_notdst),
554 ROP2(cirrus_fill_src_notxor_dst),
555 ROP2(cirrus_fill_src_or_notdst),
556 ROP2(cirrus_fill_notsrc),
557 ROP2(cirrus_fill_notsrc_or_dst),
558 ROP2(cirrus_fill_notsrc_and_notdst),
559};
560
561static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
e6e5ad80 562{
a5082316
FB		 563 unsigned int color;
564 switch (s->cirrus_blt_pixelwidth) {
565 case 1:
566 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
567 break;
568 case 2:
4e12cd94 569 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
a5082316
FB		 570 s->cirrus_blt_fgcol = le16_to_cpu(color);
571 break;
572 case 3:
5fafdf24 573 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
4e12cd94 574 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
a5082316
FB		 575 break;
576 default:
577 case 4:
4e12cd94
AK		 578 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
579 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
a5082316
FB		 580 s->cirrus_blt_fgcol = le32_to_cpu(color);
581 break;
e6e5ad80
FB		 582 }
583}
584
a5082316 585static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
e6e5ad80 586{
a5082316 587 unsigned int color;
e6e5ad80
FB		 588 switch (s->cirrus_blt_pixelwidth) {
589 case 1:
a5082316
FB		 590 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
591 break;
e6e5ad80 592 case 2:
4e12cd94 593 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
a5082316
FB		 594 s->cirrus_blt_bgcol = le16_to_cpu(color);
595 break;
e6e5ad80 596 case 3:
5fafdf24 597 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
4e12cd94 598 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
a5082316 599 break;
e6e5ad80 600 default:
a5082316 601 case 4:
4e12cd94
AK		 602 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
603 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
a5082316
FB		 604 s->cirrus_blt_bgcol = le32_to_cpu(color);
605 break;
e6e5ad80
FB		 606 }
607}
608
609static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
610 int off_pitch, int bytesperline,
611 int lines)
612{
613 int y;
614 int off_cur;
615 int off_cur_end;
616
617 for (y = 0; y < lines; y++) {
618 off_cur = off_begin;
b2eb849d 619 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
fd4aa979 620 memory_region_set_dirty(&s->vga.vram, off_cur, off_cur_end - off_cur);
e6e5ad80
FB		 621 off_begin += off_pitch;
622 }
623}
624
e6e5ad80
FB		 625static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
626 const uint8_t * src)
627{
e6e5ad80 628 uint8_t *dst;
e6e5ad80 629
4e12cd94 630 dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
b2eb849d
AJ		 631
632 if (BLTUNSAFE(s))
633 return 0;
634
e69390ce 635 (*s->cirrus_rop) (s, dst, src,
5fafdf24 636 s->cirrus_blt_dstpitch, 0,
e69390ce 637 s->cirrus_blt_width, s->cirrus_blt_height);
e6e5ad80 638 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
e69390ce
FB		 639 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
640 s->cirrus_blt_height);
e6e5ad80
FB		 641 return 1;
642}
643
a21ae81d
FB		 644/* fill */
645
a5082316 646static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
a21ae81d 647{
a5082316 648 cirrus_fill_t rop_func;
a21ae81d 649
b2eb849d
AJ		 650 if (BLTUNSAFE(s))
651 return 0;
a5082316 652 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
4e12cd94 653 rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
a5082316
FB		 654 s->cirrus_blt_dstpitch,
655 s->cirrus_blt_width, s->cirrus_blt_height);
a21ae81d
FB		 656 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
657 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
658 s->cirrus_blt_height);
659 cirrus_bitblt_reset(s);
660 return 1;
661}
662
e6e5ad80
FB		 663/***************************************
664 *
665 * bitblt (video-to-video)
666 *
667 ***************************************/
668
669static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
670{
671 return cirrus_bitblt_common_patterncopy(s,
4e12cd94 672 s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
b2eb849d 673 s->cirrus_addr_mask));
e6e5ad80
FB		 674}
675
24236869 676static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
e6e5ad80 677{
78935c4a
AJ		 678 int sx = 0, sy = 0;
679 int dx = 0, dy = 0;
680 int depth = 0;
24236869
FB		 681 int notify = 0;
682
92d675d1
AJ		 683 /* make sure to only copy if it's a plain copy ROP */
684 if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
685 *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {
24236869 686
92d675d1
AJ		 687 int width, height;
688
689 depth = s->vga.get_bpp(&s->vga) / 8;
690 s->vga.get_resolution(&s->vga, &width, &height);
691
692 /* extra x, y */
693 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
694 sy = (src / ABS(s->cirrus_blt_srcpitch));
695 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
696 dy = (dst / ABS(s->cirrus_blt_dstpitch));
24236869 697
92d675d1
AJ		 698 /* normalize width */
699 w /= depth;
24236869 700
92d675d1
AJ		 701 /* if we're doing a backward copy, we have to adjust
702 our x/y to be the upper left corner (instead of the lower
703 right corner) */
704 if (s->cirrus_blt_dstpitch < 0) {
705 sx -= (s->cirrus_blt_width / depth) - 1;
706 dx -= (s->cirrus_blt_width / depth) - 1;
707 sy -= s->cirrus_blt_height - 1;
708 dy -= s->cirrus_blt_height - 1;
709 }
710
711 /* are we in the visible portion of memory? */
712 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
713 (sx + w) <= width && (sy + h) <= height &&
714 (dx + w) <= width && (dy + h) <= height) {
715 notify = 1;
716 }
717 }
24236869
FB		 718
719 /* we have to flush all pending changes so that the copy
720 is generated at the appropriate moment in time */
721 if (notify)
722 vga_hw_update();
723
4e12cd94 724 (*s->cirrus_rop) (s, s->vga.vram_ptr +
b2eb849d 725 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
4e12cd94 726 s->vga.vram_ptr +
b2eb849d 727 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
e6e5ad80
FB		 728 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
729 s->cirrus_blt_width, s->cirrus_blt_height);
24236869
FB		 730
731 if (notify)
4e12cd94 732 qemu_console_copy(s->vga.ds,
38334f76
AZ		 733 sx, sy, dx, dy,
734 s->cirrus_blt_width / depth,
735 s->cirrus_blt_height);
24236869
FB		 736
737 /* we don't have to notify the display that this portion has
38334f76 738 changed since qemu_console_copy implies this */
24236869 739
31c05501
AL		 740 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
741 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
742 s->cirrus_blt_height);
24236869
FB		 743}
744
745static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
746{
65d35a09
AJ		 747 if (BLTUNSAFE(s))
748 return 0;
749
4e12cd94
AK		 750 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
751 s->cirrus_blt_srcaddr - s->vga.start_addr,
7d957bd8 752 s->cirrus_blt_width, s->cirrus_blt_height);
24236869 753
e6e5ad80
FB		 754 return 1;
755}
756
757/***************************************
758 *
759 * bitblt (cpu-to-video)
760 *
761 ***************************************/
762
e6e5ad80
FB		 763static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
764{
765 int copy_count;
a5082316 766 uint8_t *end_ptr;
3b46e624 767
e6e5ad80 768 if (s->cirrus_srccounter > 0) {
a5082316
FB		 769 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
770 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
771 the_end:
772 s->cirrus_srccounter = 0;
773 cirrus_bitblt_reset(s);
774 } else {
775 /* at least one scan line */
776 do {
4e12cd94 777 (*s->cirrus_rop)(s, s->vga.vram_ptr +
b2eb849d
AJ		 778 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
779 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
a5082316
FB		 780 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
781 s->cirrus_blt_width, 1);
782 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
783 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
784 if (s->cirrus_srccounter <= 0)
785 goto the_end;
66a0a2cb 786 /* more bytes than needed can be transferred because of
a5082316
FB		 787 word alignment, so we keep them for the next line */
788 /* XXX: keep alignment to speed up transfer */
789 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
790 copy_count = s->cirrus_srcptr_end - end_ptr;
791 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
792 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
793 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
794 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
795 }
e6e5ad80
FB		 796 }
797}
798
799/***************************************
800 *
801 * bitblt wrapper
802 *
803 ***************************************/
804
805static void cirrus_bitblt_reset(CirrusVGAState * s)
806{
f8b237af
AL		 807 int need_update;
808
4e12cd94 809 s->vga.gr[0x31] &=
e6e5ad80 810 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
f8b237af
AL		 811 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
812 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
e6e5ad80
FB		 813 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
814 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
815 s->cirrus_srccounter = 0;
f8b237af
AL		 816 if (!need_update)
817 return;
8926b517 818 cirrus_update_memory_access(s);
e6e5ad80
FB		 819}
820
821static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
822{
a5082316
FB		 823 int w;
824
e6e5ad80
FB		 825 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
826 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
827 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
828
829 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
830 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 831 s->cirrus_blt_srcpitch = 8;
e6e5ad80 832 } else {
b30d4608 833 /* XXX: check for 24 bpp */
a5082316 834 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
e6e5ad80 835 }
a5082316 836 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
e6e5ad80
FB		 837 } else {
838 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 839 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
5fafdf24 840 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
a5082316
FB		 841 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
842 else
843 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
e6e5ad80 844 } else {
c9c0eae8
FB		 845 /* always align input size to 32 bits */
846 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
e6e5ad80 847 }
a5082316 848 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
e6e5ad80 849 }
a5082316
FB		 850 s->cirrus_srcptr = s->cirrus_bltbuf;
851 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
8926b517 852 cirrus_update_memory_access(s);
e6e5ad80
FB		 853 return 1;
854}
855
856static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
857{
858 /* XXX */
a5082316 859#ifdef DEBUG_BITBLT
e6e5ad80
FB		 860 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
861#endif
862 return 0;
863}
864
865static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
866{
867 int ret;
868
869 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
870 ret = cirrus_bitblt_videotovideo_patterncopy(s);
871 } else {
872 ret = cirrus_bitblt_videotovideo_copy(s);
873 }
e6e5ad80
FB		 874 if (ret)
875 cirrus_bitblt_reset(s);
876 return ret;
877}
878
879static void cirrus_bitblt_start(CirrusVGAState * s)
880{
881 uint8_t blt_rop;
882
4e12cd94 883 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
a5082316 884
4e12cd94
AK		 885 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
886 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
887 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
888 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
e6e5ad80 889 s->cirrus_blt_dstaddr =
4e12cd94 890 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
e6e5ad80 891 s->cirrus_blt_srcaddr =
4e12cd94
AK		 892 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
893 s->cirrus_blt_mode = s->vga.gr[0x30];
894 s->cirrus_blt_modeext = s->vga.gr[0x33];
895 blt_rop = s->vga.gr[0x32];
e6e5ad80 896
a21ae81d 897#ifdef DEBUG_BITBLT
0b74ed78 898 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
5fafdf24 899 blt_rop,
a21ae81d 900 s->cirrus_blt_mode,
a5082316 901 s->cirrus_blt_modeext,
a21ae81d
FB		 902 s->cirrus_blt_width,
903 s->cirrus_blt_height,
904 s->cirrus_blt_dstpitch,
905 s->cirrus_blt_srcpitch,
906 s->cirrus_blt_dstaddr,
a5082316 907 s->cirrus_blt_srcaddr,
4e12cd94 908 s->vga.gr[0x2f]);
a21ae81d
FB		 909#endif
910
e6e5ad80
FB		 911 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
912 case CIRRUS_BLTMODE_PIXELWIDTH8:
913 s->cirrus_blt_pixelwidth = 1;
914 break;
915 case CIRRUS_BLTMODE_PIXELWIDTH16:
916 s->cirrus_blt_pixelwidth = 2;
917 break;
918 case CIRRUS_BLTMODE_PIXELWIDTH24:
919 s->cirrus_blt_pixelwidth = 3;
920 break;
921 case CIRRUS_BLTMODE_PIXELWIDTH32:
922 s->cirrus_blt_pixelwidth = 4;
923 break;
924 default:
a5082316 925#ifdef DEBUG_BITBLT
e6e5ad80
FB		 926 printf("cirrus: bitblt - pixel width is unknown\n");
927#endif
928 goto bitblt_ignore;
929 }
930 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
931
932 if ((s->
933 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
934 CIRRUS_BLTMODE_MEMSYSDEST))
935 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
a5082316 936#ifdef DEBUG_BITBLT
e6e5ad80
FB		 937 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
938#endif
939 goto bitblt_ignore;
940 }
941
a5082316 942 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
5fafdf24 943 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
a21ae81d 944 CIRRUS_BLTMODE_TRANSPARENTCOMP |
5fafdf24
TS		 945 CIRRUS_BLTMODE_PATTERNCOPY |
946 CIRRUS_BLTMODE_COLOREXPAND)) ==
a21ae81d 947 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
a5082316
FB		 948 cirrus_bitblt_fgcol(s);
949 cirrus_bitblt_solidfill(s, blt_rop);
e6e5ad80 950 } else {
5fafdf24
TS		 951 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
952 CIRRUS_BLTMODE_PATTERNCOPY)) ==
a5082316
FB		 953 CIRRUS_BLTMODE_COLOREXPAND) {
954
955 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
b30d4608 956 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
4c8732d7 957 cirrus_bitblt_bgcol(s);
b30d4608 958 else
4c8732d7 959 cirrus_bitblt_fgcol(s);
b30d4608 960 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
a5082316
FB		 961 } else {
962 cirrus_bitblt_fgcol(s);
963 cirrus_bitblt_bgcol(s);
964 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
965 }
e69390ce 966 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
b30d4608
FB		 967 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
968 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
969 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
970 cirrus_bitblt_bgcol(s);
971 else
972 cirrus_bitblt_fgcol(s);
973 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
974 } else {
975 cirrus_bitblt_fgcol(s);
976 cirrus_bitblt_bgcol(s);
977 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
978 }
979 } else {
980 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
981 }
a21ae81d 982 } else {
96cf2df8
TS		 983 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
984 if (s->cirrus_blt_pixelwidth > 2) {
985 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
986 goto bitblt_ignore;
987 }
988 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
989 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
990 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
991 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
992 } else {
993 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
994 }
995 } else {
996 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
997 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
998 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
999 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1000 } else {
1001 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1002 }
1003 }
1004 }
a21ae81d
FB		 1005 // setup bitblt engine.
1006 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1007 if (!cirrus_bitblt_cputovideo(s))
1008 goto bitblt_ignore;
1009 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1010 if (!cirrus_bitblt_videotocpu(s))
1011 goto bitblt_ignore;
1012 } else {
1013 if (!cirrus_bitblt_videotovideo(s))
1014 goto bitblt_ignore;
1015 }
e6e5ad80 1016 }
e6e5ad80
FB		 1017 return;
1018 bitblt_ignore:;
1019 cirrus_bitblt_reset(s);
1020}
1021
1022static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1023{
1024 unsigned old_value;
1025
4e12cd94
AK		 1026 old_value = s->vga.gr[0x31];
1027 s->vga.gr[0x31] = reg_value;
e6e5ad80
FB		 1028
1029 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1030 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1031 cirrus_bitblt_reset(s);
1032 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1033 ((reg_value & CIRRUS_BLT_START) != 0)) {
e6e5ad80
FB		 1034 cirrus_bitblt_start(s);
1035 }
1036}
1037
1038
1039/***************************************
1040 *
1041 * basic parameters
1042 *
1043 ***************************************/
1044
a4a2f59c 1045static void cirrus_get_offsets(VGACommonState *s1,
83acc96b
FB		 1046 uint32_t *pline_offset,
1047 uint32_t *pstart_addr,
1048 uint32_t *pline_compare)
e6e5ad80 1049{
4e12cd94 1050 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
83acc96b 1051 uint32_t start_addr, line_offset, line_compare;
e6e5ad80 1052
4e12cd94
AK		 1053 line_offset = s->vga.cr[0x13]
1054 | ((s->vga.cr[0x1b] & 0x10) << 4);
e6e5ad80
FB		 1055 line_offset <<= 3;
1056 *pline_offset = line_offset;
1057
4e12cd94
AK		 1058 start_addr = (s->vga.cr[0x0c] << 8)
1059 | s->vga.cr[0x0d]
1060 | ((s->vga.cr[0x1b] & 0x01) << 16)
1061 | ((s->vga.cr[0x1b] & 0x0c) << 15)
1062 | ((s->vga.cr[0x1d] & 0x80) << 12);
e6e5ad80 1063 *pstart_addr = start_addr;
83acc96b 1064
4e12cd94
AK		 1065 line_compare = s->vga.cr[0x18] |
1066 ((s->vga.cr[0x07] & 0x10) << 4) |
1067 ((s->vga.cr[0x09] & 0x40) << 3);
83acc96b 1068 *pline_compare = line_compare;
e6e5ad80
FB		 1069}
1070
1071static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1072{
1073 uint32_t ret = 16;
1074
1075 switch (s->cirrus_hidden_dac_data & 0xf) {
1076 case 0:
1077 ret = 15;
1078 break; /* Sierra HiColor */
1079 case 1:
1080 ret = 16;
1081 break; /* XGA HiColor */
1082 default:
1083#ifdef DEBUG_CIRRUS
1084 printf("cirrus: invalid DAC value %x in 16bpp\n",
1085 (s->cirrus_hidden_dac_data & 0xf));
1086#endif
1087 ret = 15; /* XXX */
1088 break;
1089 }
1090 return ret;
1091}
1092
a4a2f59c 1093static int cirrus_get_bpp(VGACommonState *s1)
e6e5ad80 1094{
4e12cd94 1095 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
e6e5ad80
FB		 1096 uint32_t ret = 8;
1097
4e12cd94 1098 if ((s->vga.sr[0x07] & 0x01) != 0) {
e6e5ad80 1099 /* Cirrus SVGA */
4e12cd94 1100 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
e6e5ad80
FB		 1101 case CIRRUS_SR7_BPP_8:
1102 ret = 8;
1103 break;
1104 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1105 ret = cirrus_get_bpp16_depth(s);
1106 break;
1107 case CIRRUS_SR7_BPP_24:
1108 ret = 24;
1109 break;
1110 case CIRRUS_SR7_BPP_16:
1111 ret = cirrus_get_bpp16_depth(s);
1112 break;
1113 case CIRRUS_SR7_BPP_32:
1114 ret = 32;
1115 break;
1116 default:
1117#ifdef DEBUG_CIRRUS
4e12cd94 1118 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
e6e5ad80
FB		 1119#endif
1120 ret = 8;
1121 break;
1122 }
1123 } else {
1124 /* VGA */
aeb3c85f 1125 ret = 0;
e6e5ad80
FB		 1126 }
1127
1128 return ret;
1129}
1130
a4a2f59c 1131static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
78e127ef
FB		 1132{
1133 int width, height;
3b46e624 1134
78e127ef 1135 width = (s->cr[0x01] + 1) * 8;
5fafdf24
TS		 1136 height = s->cr[0x12] |
1137 ((s->cr[0x07] & 0x02) << 7) |
78e127ef
FB		 1138 ((s->cr[0x07] & 0x40) << 3);
1139 height = (height + 1);
1140 /* interlace support */
1141 if (s->cr[0x1a] & 0x01)
1142 height = height * 2;
1143 *pwidth = width;
1144 *pheight = height;
1145}
1146
e6e5ad80
FB		 1147/***************************************
1148 *
1149 * bank memory
1150 *
1151 ***************************************/
1152
1153static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1154{
1155 unsigned offset;
1156 unsigned limit;
1157
4e12cd94
AK		 1158 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */
1159 offset = s->vga.gr[0x09 + bank_index];
e6e5ad80 1160 else /* single bank */
4e12cd94 1161 offset = s->vga.gr[0x09];
e6e5ad80 1162
4e12cd94 1163 if ((s->vga.gr[0x0b] & 0x20) != 0)
e6e5ad80
FB		 1164 offset <<= 14;
1165 else
1166 offset <<= 12;
1167
e3a4e4b6 1168 if (s->real_vram_size <= offset)
e6e5ad80
FB		 1169 limit = 0;
1170 else
e3a4e4b6 1171 limit = s->real_vram_size - offset;
e6e5ad80 1172
4e12cd94 1173 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
e6e5ad80
FB		 1174 if (limit > 0x8000) {
1175 offset += 0x8000;
1176 limit -= 0x8000;
1177 } else {
1178 limit = 0;
1179 }
1180 }
1181
1182 if (limit > 0) {
1183 s->cirrus_bank_base[bank_index] = offset;
1184 s->cirrus_bank_limit[bank_index] = limit;
1185 } else {
1186 s->cirrus_bank_base[bank_index] = 0;
1187 s->cirrus_bank_limit[bank_index] = 0;
1188 }
1189}
1190
1191/***************************************
1192 *
1193 * I/O access between 0x3c4-0x3c5
1194 *
1195 ***************************************/
1196
8a82c322 1197static int cirrus_vga_read_sr(CirrusVGAState * s)
e6e5ad80 1198{
8a82c322 1199 switch (s->vga.sr_index) {
e6e5ad80
FB		 1200 case 0x00: // Standard VGA
1201 case 0x01: // Standard VGA
1202 case 0x02: // Standard VGA
1203 case 0x03: // Standard VGA
1204 case 0x04: // Standard VGA
8a82c322 1205 return s->vga.sr[s->vga.sr_index];
e6e5ad80 1206 case 0x06: // Unlock Cirrus extensions
8a82c322 1207 return s->vga.sr[s->vga.sr_index];
e6e5ad80
FB		 1208 case 0x10:
1209 case 0x30:
1210 case 0x50:
1211 case 0x70: // Graphics Cursor X
1212 case 0x90:
1213 case 0xb0:
1214 case 0xd0:
1215 case 0xf0: // Graphics Cursor X
8a82c322 1216 return s->vga.sr[0x10];
e6e5ad80
FB		 1217 case 0x11:
1218 case 0x31:
1219 case 0x51:
1220 case 0x71: // Graphics Cursor Y
1221 case 0x91:
1222 case 0xb1:
1223 case 0xd1:
a5082316 1224 case 0xf1: // Graphics Cursor Y
8a82c322 1225 return s->vga.sr[0x11];
aeb3c85f
FB		 1226 case 0x05: // ???
1227 case 0x07: // Extended Sequencer Mode
1228 case 0x08: // EEPROM Control
1229 case 0x09: // Scratch Register 0
1230 case 0x0a: // Scratch Register 1
1231 case 0x0b: // VCLK 0
1232 case 0x0c: // VCLK 1
1233 case 0x0d: // VCLK 2
1234 case 0x0e: // VCLK 3
1235 case 0x0f: // DRAM Control
e6e5ad80
FB		 1236 case 0x12: // Graphics Cursor Attribute
1237 case 0x13: // Graphics Cursor Pattern Address
1238 case 0x14: // Scratch Register 2
1239 case 0x15: // Scratch Register 3
1240 case 0x16: // Performance Tuning Register
1241 case 0x17: // Configuration Readback and Extended Control
1242 case 0x18: // Signature Generator Control
1243 case 0x19: // Signal Generator Result
1244 case 0x1a: // Signal Generator Result
1245 case 0x1b: // VCLK 0 Denominator & Post
1246 case 0x1c: // VCLK 1 Denominator & Post
1247 case 0x1d: // VCLK 2 Denominator & Post
1248 case 0x1e: // VCLK 3 Denominator & Post
1249 case 0x1f: // BIOS Write Enable and MCLK select
1250#ifdef DEBUG_CIRRUS
8a82c322 1251 printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
e6e5ad80 1252#endif
8a82c322 1253 return s->vga.sr[s->vga.sr_index];
e6e5ad80
FB		 1254 default:
1255#ifdef DEBUG_CIRRUS
8a82c322 1256 printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
e6e5ad80 1257#endif
8a82c322 1258 return 0xff;
e6e5ad80
FB		 1259 break;
1260 }
e6e5ad80
FB		 1261}
1262
31c63201 1263static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
e6e5ad80 1264{
31c63201 1265 switch (s->vga.sr_index) {
e6e5ad80
FB		 1266 case 0x00: // Standard VGA
1267 case 0x01: // Standard VGA
1268 case 0x02: // Standard VGA
1269 case 0x03: // Standard VGA
1270 case 0x04: // Standard VGA
31c63201
JQ		 1271 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
1272 if (s->vga.sr_index == 1)
1273 s->vga.update_retrace_info(&s->vga);
1274 break;
e6e5ad80 1275 case 0x06: // Unlock Cirrus extensions
31c63201
JQ		 1276 val &= 0x17;
1277 if (val == 0x12) {
1278 s->vga.sr[s->vga.sr_index] = 0x12;
e6e5ad80 1279 } else {
31c63201 1280 s->vga.sr[s->vga.sr_index] = 0x0f;
e6e5ad80
FB		 1281 }
1282 break;
1283 case 0x10:
1284 case 0x30:
1285 case 0x50:
1286 case 0x70: // Graphics Cursor X
1287 case 0x90:
1288 case 0xb0:
1289 case 0xd0:
1290 case 0xf0: // Graphics Cursor X
31c63201
JQ		 1291 s->vga.sr[0x10] = val;
1292 s->hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1293 break;
1294 case 0x11:
1295 case 0x31:
1296 case 0x51:
1297 case 0x71: // Graphics Cursor Y
1298 case 0x91:
1299 case 0xb1:
1300 case 0xd1:
1301 case 0xf1: // Graphics Cursor Y
31c63201
JQ		 1302 s->vga.sr[0x11] = val;
1303 s->hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1304 break;
1305 case 0x07: // Extended Sequencer Mode
2bec46dc 1306 cirrus_update_memory_access(s);
e6e5ad80
FB		 1307 case 0x08: // EEPROM Control
1308 case 0x09: // Scratch Register 0
1309 case 0x0a: // Scratch Register 1
1310 case 0x0b: // VCLK 0
1311 case 0x0c: // VCLK 1
1312 case 0x0d: // VCLK 2
1313 case 0x0e: // VCLK 3
1314 case 0x0f: // DRAM Control
1315 case 0x12: // Graphics Cursor Attribute
1316 case 0x13: // Graphics Cursor Pattern Address
1317 case 0x14: // Scratch Register 2
1318 case 0x15: // Scratch Register 3
1319 case 0x16: // Performance Tuning Register
e6e5ad80
FB		 1320 case 0x18: // Signature Generator Control
1321 case 0x19: // Signature Generator Result
1322 case 0x1a: // Signature Generator Result
1323 case 0x1b: // VCLK 0 Denominator & Post
1324 case 0x1c: // VCLK 1 Denominator & Post
1325 case 0x1d: // VCLK 2 Denominator & Post
1326 case 0x1e: // VCLK 3 Denominator & Post
1327 case 0x1f: // BIOS Write Enable and MCLK select
31c63201 1328 s->vga.sr[s->vga.sr_index] = val;
e6e5ad80
FB		 1329#ifdef DEBUG_CIRRUS
1330 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
31c63201 1331 s->vga.sr_index, val);
e6e5ad80
FB		 1332#endif
1333 break;
8926b517 1334 case 0x17: // Configuration Readback and Extended Control
31c63201
JQ		 1335 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
1336 | (val & 0xc7);
8926b517
FB		 1337 cirrus_update_memory_access(s);
1338 break;
e6e5ad80
FB		 1339 default:
1340#ifdef DEBUG_CIRRUS
31c63201
JQ		 1341 printf("cirrus: outport sr_index %02x, sr_value %02x\n",
1342 s->vga.sr_index, val);
e6e5ad80
FB		 1343#endif
1344 break;
1345 }
e6e5ad80
FB		 1346}
1347
1348/***************************************
1349 *
1350 * I/O access at 0x3c6
1351 *
1352 ***************************************/
1353
957c9db5 1354static int cirrus_read_hidden_dac(CirrusVGAState * s)
e6e5ad80 1355{
a21ae81d 1356 if (++s->cirrus_hidden_dac_lockindex == 5) {
957c9db5
JQ		 1357 s->cirrus_hidden_dac_lockindex = 0;
1358 return s->cirrus_hidden_dac_data;
e6e5ad80 1359 }
957c9db5 1360 return 0xff;
e6e5ad80
FB		 1361}
1362
1363static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1364{
1365 if (s->cirrus_hidden_dac_lockindex == 4) {
1366 s->cirrus_hidden_dac_data = reg_value;
a21ae81d 1367#if defined(DEBUG_CIRRUS)
e6e5ad80
FB		 1368 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1369#endif
1370 }
1371 s->cirrus_hidden_dac_lockindex = 0;
1372}
1373
1374/***************************************
1375 *
1376 * I/O access at 0x3c9
1377 *
1378 ***************************************/
1379
5deaeee3 1380static int cirrus_vga_read_palette(CirrusVGAState * s)
e6e5ad80 1381{
5deaeee3
JQ		 1382 int val;
1383
1384 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1385 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1386 s->vga.dac_sub_index];
1387 } else {
1388 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
1389 }
4e12cd94
AK		 1390 if (++s->vga.dac_sub_index == 3) {
1391 s->vga.dac_sub_index = 0;
1392 s->vga.dac_read_index++;
e6e5ad80 1393 }
5deaeee3 1394 return val;
e6e5ad80
FB		 1395}
1396
86948bb1 1397static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value)
e6e5ad80 1398{
4e12cd94
AK		 1399 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1400 if (++s->vga.dac_sub_index == 3) {
86948bb1
JQ		 1401 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1402 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1403 s->vga.dac_cache, 3);
1404 } else {
1405 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
1406 }
a5082316 1407 /* XXX update cursor */
4e12cd94
AK		 1408 s->vga.dac_sub_index = 0;
1409 s->vga.dac_write_index++;
e6e5ad80 1410 }
e6e5ad80
FB		 1411}
1412
1413/***************************************
1414 *
1415 * I/O access between 0x3ce-0x3cf
1416 *
1417 ***************************************/
1418
f705db9d 1419static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1420{
1421 switch (reg_index) {
aeb3c85f 1422 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
f705db9d 1423 return s->cirrus_shadow_gr0;
aeb3c85f 1424 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
f705db9d 1425 return s->cirrus_shadow_gr1;
e6e5ad80
FB		 1426 case 0x02: // Standard VGA
1427 case 0x03: // Standard VGA
1428 case 0x04: // Standard VGA
1429 case 0x06: // Standard VGA
1430 case 0x07: // Standard VGA
1431 case 0x08: // Standard VGA
f705db9d 1432 return s->vga.gr[s->vga.gr_index];
e6e5ad80
FB		 1433 case 0x05: // Standard VGA, Cirrus extended mode
1434 default:
1435 break;
1436 }
1437
1438 if (reg_index < 0x3a) {
f705db9d 1439 return s->vga.gr[reg_index];
e6e5ad80
FB		 1440 } else {
1441#ifdef DEBUG_CIRRUS
1442 printf("cirrus: inport gr_index %02x\n", reg_index);
1443#endif
f705db9d 1444 return 0xff;
e6e5ad80 1445 }
e6e5ad80
FB		 1446}
1447
22286bc6
JQ		 1448static void
1449cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
e6e5ad80 1450{
a5082316
FB		 1451#if defined(DEBUG_BITBLT) && 0
1452 printf("gr%02x: %02x\n", reg_index, reg_value);
1453#endif
e6e5ad80
FB		 1454 switch (reg_index) {
1455 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
f22f5b07 1456 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
aeb3c85f 1457 s->cirrus_shadow_gr0 = reg_value;
22286bc6 1458 break;
e6e5ad80 1459 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
f22f5b07 1460 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
aeb3c85f 1461 s->cirrus_shadow_gr1 = reg_value;
22286bc6 1462 break;
e6e5ad80
FB		 1463 case 0x02: // Standard VGA
1464 case 0x03: // Standard VGA
1465 case 0x04: // Standard VGA
1466 case 0x06: // Standard VGA
1467 case 0x07: // Standard VGA
1468 case 0x08: // Standard VGA
22286bc6
JQ		 1469 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1470 break;
e6e5ad80 1471 case 0x05: // Standard VGA, Cirrus extended mode
4e12cd94 1472 s->vga.gr[reg_index] = reg_value & 0x7f;
8926b517 1473 cirrus_update_memory_access(s);
e6e5ad80
FB		 1474 break;
1475 case 0x09: // bank offset #0
1476 case 0x0A: // bank offset #1
4e12cd94 1477 s->vga.gr[reg_index] = reg_value;
8926b517
FB		 1478 cirrus_update_bank_ptr(s, 0);
1479 cirrus_update_bank_ptr(s, 1);
2bec46dc 1480 cirrus_update_memory_access(s);
8926b517 1481 break;
e6e5ad80 1482 case 0x0B:
4e12cd94 1483 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1484 cirrus_update_bank_ptr(s, 0);
1485 cirrus_update_bank_ptr(s, 1);
8926b517 1486 cirrus_update_memory_access(s);
e6e5ad80
FB		 1487 break;
1488 case 0x10: // BGCOLOR 0x0000ff00
1489 case 0x11: // FGCOLOR 0x0000ff00
1490 case 0x12: // BGCOLOR 0x00ff0000
1491 case 0x13: // FGCOLOR 0x00ff0000
1492 case 0x14: // BGCOLOR 0xff000000
1493 case 0x15: // FGCOLOR 0xff000000
1494 case 0x20: // BLT WIDTH 0x0000ff
1495 case 0x22: // BLT HEIGHT 0x0000ff
1496 case 0x24: // BLT DEST PITCH 0x0000ff
1497 case 0x26: // BLT SRC PITCH 0x0000ff
1498 case 0x28: // BLT DEST ADDR 0x0000ff
1499 case 0x29: // BLT DEST ADDR 0x00ff00
1500 case 0x2c: // BLT SRC ADDR 0x0000ff
1501 case 0x2d: // BLT SRC ADDR 0x00ff00
a5082316 1502 case 0x2f: // BLT WRITEMASK
e6e5ad80
FB		 1503 case 0x30: // BLT MODE
1504 case 0x32: // RASTER OP
a21ae81d 1505 case 0x33: // BLT MODEEXT
e6e5ad80
FB		 1506 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1507 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1508 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1509 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
4e12cd94 1510 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1511 break;
1512 case 0x21: // BLT WIDTH 0x001f00
1513 case 0x23: // BLT HEIGHT 0x001f00
1514 case 0x25: // BLT DEST PITCH 0x001f00
1515 case 0x27: // BLT SRC PITCH 0x001f00
4e12cd94 1516 s->vga.gr[reg_index] = reg_value & 0x1f;
e6e5ad80
FB		 1517 break;
1518 case 0x2a: // BLT DEST ADDR 0x3f0000
4e12cd94 1519 s->vga.gr[reg_index] = reg_value & 0x3f;
a5082316 1520 /* if auto start mode, starts bit blt now */
4e12cd94 1521 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
a5082316
FB		 1522 cirrus_bitblt_start(s);
1523 }
1524 break;
e6e5ad80 1525 case 0x2e: // BLT SRC ADDR 0x3f0000
4e12cd94 1526 s->vga.gr[reg_index] = reg_value & 0x3f;
e6e5ad80
FB		 1527 break;
1528 case 0x31: // BLT STATUS/START
1529 cirrus_write_bitblt(s, reg_value);
1530 break;
1531 default:
1532#ifdef DEBUG_CIRRUS
1533 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1534 reg_value);
1535#endif
1536 break;
1537 }
e6e5ad80
FB		 1538}
1539
1540/***************************************
1541 *
1542 * I/O access between 0x3d4-0x3d5
1543 *
1544 ***************************************/
1545
b863d514 1546static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1547{
1548 switch (reg_index) {
1549 case 0x00: // Standard VGA
1550 case 0x01: // Standard VGA
1551 case 0x02: // Standard VGA
1552 case 0x03: // Standard VGA
1553 case 0x04: // Standard VGA
1554 case 0x05: // Standard VGA
1555 case 0x06: // Standard VGA
1556 case 0x07: // Standard VGA
1557 case 0x08: // Standard VGA
1558 case 0x09: // Standard VGA
1559 case 0x0a: // Standard VGA
1560 case 0x0b: // Standard VGA
1561 case 0x0c: // Standard VGA
1562 case 0x0d: // Standard VGA
1563 case 0x0e: // Standard VGA
1564 case 0x0f: // Standard VGA
1565 case 0x10: // Standard VGA
1566 case 0x11: // Standard VGA
1567 case 0x12: // Standard VGA
1568 case 0x13: // Standard VGA
1569 case 0x14: // Standard VGA
1570 case 0x15: // Standard VGA
1571 case 0x16: // Standard VGA
1572 case 0x17: // Standard VGA
1573 case 0x18: // Standard VGA
b863d514 1574 return s->vga.cr[s->vga.cr_index];
ca896ef3 1575 case 0x24: // Attribute Controller Toggle Readback (R)
b863d514 1576 return (s->vga.ar_flip_flop << 7);
e6e5ad80
FB		 1577 case 0x19: // Interlace End
1578 case 0x1a: // Miscellaneous Control
1579 case 0x1b: // Extended Display Control
1580 case 0x1c: // Sync Adjust and Genlock
1581 case 0x1d: // Overlay Extended Control
1582 case 0x22: // Graphics Data Latches Readback (R)
e6e5ad80
FB		 1583 case 0x25: // Part Status
1584 case 0x27: // Part ID (R)
b863d514 1585 return s->vga.cr[s->vga.cr_index];
e6e5ad80 1586 case 0x26: // Attribute Controller Index Readback (R)
b863d514 1587 return s->vga.ar_index & 0x3f;
e6e5ad80
FB		 1588 break;
1589 default:
1590#ifdef DEBUG_CIRRUS
1591 printf("cirrus: inport cr_index %02x\n", reg_index);
e6e5ad80 1592#endif
b863d514 1593 return 0xff;
e6e5ad80 1594 }
e6e5ad80
FB		 1595}
1596
4ec1ce04 1597static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
e6e5ad80 1598{
4ec1ce04 1599 switch (s->vga.cr_index) {
e6e5ad80
FB		 1600 case 0x00: // Standard VGA
1601 case 0x01: // Standard VGA
1602 case 0x02: // Standard VGA
1603 case 0x03: // Standard VGA
1604 case 0x04: // Standard VGA
1605 case 0x05: // Standard VGA
1606 case 0x06: // Standard VGA
1607 case 0x07: // Standard VGA
1608 case 0x08: // Standard VGA
1609 case 0x09: // Standard VGA
1610 case 0x0a: // Standard VGA
1611 case 0x0b: // Standard VGA
1612 case 0x0c: // Standard VGA
1613 case 0x0d: // Standard VGA
1614 case 0x0e: // Standard VGA
1615 case 0x0f: // Standard VGA
1616 case 0x10: // Standard VGA
1617 case 0x11: // Standard VGA
1618 case 0x12: // Standard VGA
1619 case 0x13: // Standard VGA
1620 case 0x14: // Standard VGA
1621 case 0x15: // Standard VGA
1622 case 0x16: // Standard VGA
1623 case 0x17: // Standard VGA
1624 case 0x18: // Standard VGA
4ec1ce04
JQ		 1625 /* handle CR0-7 protection */
1626 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
1627 /* can always write bit 4 of CR7 */
1628 if (s->vga.cr_index == 7)
1629 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10);
1630 return;
1631 }
1632 s->vga.cr[s->vga.cr_index] = reg_value;
1633 switch(s->vga.cr_index) {
1634 case 0x00:
1635 case 0x04:
1636 case 0x05:
1637 case 0x06:
1638 case 0x07:
1639 case 0x11:
1640 case 0x17:
1641 s->vga.update_retrace_info(&s->vga);
1642 break;
1643 }
1644 break;
e6e5ad80
FB		 1645 case 0x19: // Interlace End
1646 case 0x1a: // Miscellaneous Control
1647 case 0x1b: // Extended Display Control
1648 case 0x1c: // Sync Adjust and Genlock
ae184e4a 1649 case 0x1d: // Overlay Extended Control
4ec1ce04 1650 s->vga.cr[s->vga.cr_index] = reg_value;
e6e5ad80
FB		 1651#ifdef DEBUG_CIRRUS
1652 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
4ec1ce04 1653 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1654#endif
1655 break;
1656 case 0x22: // Graphics Data Latches Readback (R)
1657 case 0x24: // Attribute Controller Toggle Readback (R)
1658 case 0x26: // Attribute Controller Index Readback (R)
1659 case 0x27: // Part ID (R)
1660 break;
e6e5ad80
FB		 1661 case 0x25: // Part Status
1662 default:
1663#ifdef DEBUG_CIRRUS
4ec1ce04
JQ		 1664 printf("cirrus: outport cr_index %02x, cr_value %02x\n",
1665 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1666#endif
1667 break;
1668 }
e6e5ad80
FB		 1669}
1670
1671/***************************************
1672 *
1673 * memory-mapped I/O (bitblt)
1674 *
1675 ***************************************/
1676
1677static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1678{
1679 int value = 0xff;
1680
1681 switch (address) {
1682 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
f705db9d 1683 value = cirrus_vga_read_gr(s, 0x00);
e6e5ad80
FB		 1684 break;
1685 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
f705db9d 1686 value = cirrus_vga_read_gr(s, 0x10);
e6e5ad80
FB		 1687 break;
1688 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
f705db9d 1689 value = cirrus_vga_read_gr(s, 0x12);
e6e5ad80
FB		 1690 break;
1691 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
f705db9d 1692 value = cirrus_vga_read_gr(s, 0x14);
e6e5ad80
FB		 1693 break;
1694 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
f705db9d 1695 value = cirrus_vga_read_gr(s, 0x01);
e6e5ad80
FB		 1696 break;
1697 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
f705db9d 1698 value = cirrus_vga_read_gr(s, 0x11);
e6e5ad80
FB		 1699 break;
1700 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
f705db9d 1701 value = cirrus_vga_read_gr(s, 0x13);
e6e5ad80
FB		 1702 break;
1703 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
f705db9d 1704 value = cirrus_vga_read_gr(s, 0x15);
e6e5ad80
FB		 1705 break;
1706 case (CIRRUS_MMIO_BLTWIDTH + 0):
f705db9d 1707 value = cirrus_vga_read_gr(s, 0x20);
e6e5ad80
FB		 1708 break;
1709 case (CIRRUS_MMIO_BLTWIDTH + 1):
f705db9d 1710 value = cirrus_vga_read_gr(s, 0x21);
e6e5ad80
FB		 1711 break;
1712 case (CIRRUS_MMIO_BLTHEIGHT + 0):
f705db9d 1713 value = cirrus_vga_read_gr(s, 0x22);
e6e5ad80
FB		 1714 break;
1715 case (CIRRUS_MMIO_BLTHEIGHT + 1):
f705db9d 1716 value = cirrus_vga_read_gr(s, 0x23);
e6e5ad80
FB		 1717 break;
1718 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
f705db9d 1719 value = cirrus_vga_read_gr(s, 0x24);
e6e5ad80
FB		 1720 break;
1721 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
f705db9d 1722 value = cirrus_vga_read_gr(s, 0x25);
e6e5ad80
FB		 1723 break;
1724 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
f705db9d 1725 value = cirrus_vga_read_gr(s, 0x26);
e6e5ad80
FB		 1726 break;
1727 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
f705db9d 1728 value = cirrus_vga_read_gr(s, 0x27);
e6e5ad80
FB		 1729 break;
1730 case (CIRRUS_MMIO_BLTDESTADDR + 0):
f705db9d 1731 value = cirrus_vga_read_gr(s, 0x28);
e6e5ad80
FB		 1732 break;
1733 case (CIRRUS_MMIO_BLTDESTADDR + 1):
f705db9d 1734 value = cirrus_vga_read_gr(s, 0x29);
e6e5ad80
FB		 1735 break;
1736 case (CIRRUS_MMIO_BLTDESTADDR + 2):
f705db9d 1737 value = cirrus_vga_read_gr(s, 0x2a);
e6e5ad80
FB		 1738 break;
1739 case (CIRRUS_MMIO_BLTSRCADDR + 0):
f705db9d 1740 value = cirrus_vga_read_gr(s, 0x2c);
e6e5ad80
FB		 1741 break;
1742 case (CIRRUS_MMIO_BLTSRCADDR + 1):
f705db9d 1743 value = cirrus_vga_read_gr(s, 0x2d);
e6e5ad80
FB		 1744 break;
1745 case (CIRRUS_MMIO_BLTSRCADDR + 2):
f705db9d 1746 value = cirrus_vga_read_gr(s, 0x2e);
e6e5ad80
FB		 1747 break;
1748 case CIRRUS_MMIO_BLTWRITEMASK:
f705db9d 1749 value = cirrus_vga_read_gr(s, 0x2f);
e6e5ad80
FB		 1750 break;
1751 case CIRRUS_MMIO_BLTMODE:
f705db9d 1752 value = cirrus_vga_read_gr(s, 0x30);
e6e5ad80
FB		 1753 break;
1754 case CIRRUS_MMIO_BLTROP:
f705db9d 1755 value = cirrus_vga_read_gr(s, 0x32);
e6e5ad80 1756 break;
a21ae81d 1757 case CIRRUS_MMIO_BLTMODEEXT:
f705db9d 1758 value = cirrus_vga_read_gr(s, 0x33);
a21ae81d 1759 break;
e6e5ad80 1760 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
f705db9d 1761 value = cirrus_vga_read_gr(s, 0x34);
e6e5ad80
FB		 1762 break;
1763 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
f705db9d 1764 value = cirrus_vga_read_gr(s, 0x35);
e6e5ad80
FB		 1765 break;
1766 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
f705db9d 1767 value = cirrus_vga_read_gr(s, 0x38);
e6e5ad80
FB		 1768 break;
1769 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
f705db9d 1770 value = cirrus_vga_read_gr(s, 0x39);
e6e5ad80
FB		 1771 break;
1772 case CIRRUS_MMIO_BLTSTATUS:
f705db9d 1773 value = cirrus_vga_read_gr(s, 0x31);
e6e5ad80
FB		 1774 break;
1775 default:
1776#ifdef DEBUG_CIRRUS
1777 printf("cirrus: mmio read - address 0x%04x\n", address);
1778#endif
1779 break;
1780 }
1781
1782 return (uint8_t) value;
1783}
1784
1785static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1786 uint8_t value)
1787{
1788 switch (address) {
1789 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
22286bc6 1790 cirrus_vga_write_gr(s, 0x00, value);
e6e5ad80
FB		 1791 break;
1792 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
22286bc6 1793 cirrus_vga_write_gr(s, 0x10, value);
e6e5ad80
FB		 1794 break;
1795 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
22286bc6 1796 cirrus_vga_write_gr(s, 0x12, value);
e6e5ad80
FB		 1797 break;
1798 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
22286bc6 1799 cirrus_vga_write_gr(s, 0x14, value);
e6e5ad80
FB		 1800 break;
1801 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
22286bc6 1802 cirrus_vga_write_gr(s, 0x01, value);
e6e5ad80
FB		 1803 break;
1804 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
22286bc6 1805 cirrus_vga_write_gr(s, 0x11, value);
e6e5ad80
FB		 1806 break;
1807 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
22286bc6 1808 cirrus_vga_write_gr(s, 0x13, value);
e6e5ad80
FB		 1809 break;
1810 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
22286bc6 1811 cirrus_vga_write_gr(s, 0x15, value);
e6e5ad80
FB		 1812 break;
1813 case (CIRRUS_MMIO_BLTWIDTH + 0):
22286bc6 1814 cirrus_vga_write_gr(s, 0x20, value);
e6e5ad80
FB		 1815 break;
1816 case (CIRRUS_MMIO_BLTWIDTH + 1):
22286bc6 1817 cirrus_vga_write_gr(s, 0x21, value);
e6e5ad80
FB		 1818 break;
1819 case (CIRRUS_MMIO_BLTHEIGHT + 0):
22286bc6 1820 cirrus_vga_write_gr(s, 0x22, value);
e6e5ad80
FB		 1821 break;
1822 case (CIRRUS_MMIO_BLTHEIGHT + 1):
22286bc6 1823 cirrus_vga_write_gr(s, 0x23, value);
e6e5ad80
FB		 1824 break;
1825 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
22286bc6 1826 cirrus_vga_write_gr(s, 0x24, value);
e6e5ad80
FB		 1827 break;
1828 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
22286bc6 1829 cirrus_vga_write_gr(s, 0x25, value);
e6e5ad80
FB		 1830 break;
1831 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
22286bc6 1832 cirrus_vga_write_gr(s, 0x26, value);
e6e5ad80
FB		 1833 break;
1834 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
22286bc6 1835 cirrus_vga_write_gr(s, 0x27, value);
e6e5ad80
FB		 1836 break;
1837 case (CIRRUS_MMIO_BLTDESTADDR + 0):
22286bc6 1838 cirrus_vga_write_gr(s, 0x28, value);
e6e5ad80
FB		 1839 break;
1840 case (CIRRUS_MMIO_BLTDESTADDR + 1):
22286bc6 1841 cirrus_vga_write_gr(s, 0x29, value);
e6e5ad80
FB		 1842 break;
1843 case (CIRRUS_MMIO_BLTDESTADDR + 2):
22286bc6 1844 cirrus_vga_write_gr(s, 0x2a, value);
e6e5ad80
FB		 1845 break;
1846 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1847 /* ignored */
1848 break;
1849 case (CIRRUS_MMIO_BLTSRCADDR + 0):
22286bc6 1850 cirrus_vga_write_gr(s, 0x2c, value);
e6e5ad80
FB		 1851 break;
1852 case (CIRRUS_MMIO_BLTSRCADDR + 1):
22286bc6 1853 cirrus_vga_write_gr(s, 0x2d, value);
e6e5ad80
FB		 1854 break;
1855 case (CIRRUS_MMIO_BLTSRCADDR + 2):
22286bc6 1856 cirrus_vga_write_gr(s, 0x2e, value);
e6e5ad80
FB		 1857 break;
1858 case CIRRUS_MMIO_BLTWRITEMASK:
22286bc6 1859 cirrus_vga_write_gr(s, 0x2f, value);
e6e5ad80
FB		 1860 break;
1861 case CIRRUS_MMIO_BLTMODE:
22286bc6 1862 cirrus_vga_write_gr(s, 0x30, value);
e6e5ad80
FB		 1863 break;
1864 case CIRRUS_MMIO_BLTROP:
22286bc6 1865 cirrus_vga_write_gr(s, 0x32, value);
e6e5ad80 1866 break;
a21ae81d 1867 case CIRRUS_MMIO_BLTMODEEXT:
22286bc6 1868 cirrus_vga_write_gr(s, 0x33, value);
a21ae81d 1869 break;
e6e5ad80 1870 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
22286bc6 1871 cirrus_vga_write_gr(s, 0x34, value);
e6e5ad80
FB		 1872 break;
1873 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
22286bc6 1874 cirrus_vga_write_gr(s, 0x35, value);
e6e5ad80
FB		 1875 break;
1876 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
22286bc6 1877 cirrus_vga_write_gr(s, 0x38, value);
e6e5ad80
FB		 1878 break;
1879 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
22286bc6 1880 cirrus_vga_write_gr(s, 0x39, value);
e6e5ad80
FB		 1881 break;
1882 case CIRRUS_MMIO_BLTSTATUS:
22286bc6 1883 cirrus_vga_write_gr(s, 0x31, value);
e6e5ad80
FB		 1884 break;
1885 default:
1886#ifdef DEBUG_CIRRUS
1887 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1888 address, value);
1889#endif
1890 break;
1891 }
1892}
1893
e6e5ad80
FB		 1894/***************************************
1895 *
1896 * write mode 4/5
1897 *
e6e5ad80
FB		 1898 ***************************************/
1899
1900static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1901 unsigned mode,
1902 unsigned offset,
1903 uint32_t mem_value)
1904{
1905 int x;
1906 unsigned val = mem_value;
1907 uint8_t *dst;
1908
4e12cd94 1909 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1910 for (x = 0; x < 8; x++) {
1911 if (val & 0x80) {
0b74ed78 1912 *dst = s->cirrus_shadow_gr1;
e6e5ad80 1913 } else if (mode == 5) {
0b74ed78 1914 *dst = s->cirrus_shadow_gr0;
e6e5ad80
FB		 1915 }
1916 val <<= 1;
0b74ed78 1917 dst++;
e6e5ad80 1918 }
fd4aa979 1919 memory_region_set_dirty(&s->vga.vram, offset, 8);
e6e5ad80
FB		 1920}
1921
1922static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1923 unsigned mode,
1924 unsigned offset,
1925 uint32_t mem_value)
1926{
1927 int x;
1928 unsigned val = mem_value;
1929 uint8_t *dst;
1930
4e12cd94 1931 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1932 for (x = 0; x < 8; x++) {
1933 if (val & 0x80) {
0b74ed78 1934 *dst = s->cirrus_shadow_gr1;
4e12cd94 1935 *(dst + 1) = s->vga.gr[0x11];
e6e5ad80 1936 } else if (mode == 5) {
0b74ed78 1937 *dst = s->cirrus_shadow_gr0;
4e12cd94 1938 *(dst + 1) = s->vga.gr[0x10];
e6e5ad80
FB		 1939 }
1940 val <<= 1;
0b74ed78 1941 dst += 2;
e6e5ad80 1942 }
fd4aa979 1943 memory_region_set_dirty(&s->vga.vram, offset, 16);
e6e5ad80
FB		 1944}
1945
1946/***************************************
1947 *
1948 * memory access between 0xa0000-0xbffff
1949 *
1950 ***************************************/
1951
a815b166 1952static uint64_t cirrus_vga_mem_read(void *opaque,
a8170e5e 1953 hwaddr addr,
a815b166 1954 uint32_t size)
e6e5ad80
FB		 1955{
1956 CirrusVGAState *s = opaque;
1957 unsigned bank_index;
1958 unsigned bank_offset;
1959 uint32_t val;
1960
4e12cd94 1961 if ((s->vga.sr[0x07] & 0x01) == 0) {
b2a5e761 1962 return vga_mem_readb(&s->vga, addr);
e6e5ad80
FB		 1963 }
1964
1965 if (addr < 0x10000) {
1966 /* XXX handle bitblt */
1967 /* video memory */
1968 bank_index = addr >> 15;
1969 bank_offset = addr & 0x7fff;
1970 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
1971 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 1972 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 1973 bank_offset <<= 4;
4e12cd94 1974 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 1975 bank_offset <<= 3;
1976 }
1977 bank_offset &= s->cirrus_addr_mask;
4e12cd94 1978 val = *(s->vga.vram_ptr + bank_offset);
e6e5ad80
FB		 1979 } else
1980 val = 0xff;
1981 } else if (addr >= 0x18000 && addr < 0x18100) {
1982 /* memory-mapped I/O */
1983 val = 0xff;
4e12cd94 1984 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 1985 val = cirrus_mmio_blt_read(s, addr & 0xff);
1986 }
1987 } else {
1988 val = 0xff;
1989#ifdef DEBUG_CIRRUS
0bf9e31a 1990 printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
e6e5ad80
FB		 1991#endif
1992 }
1993 return val;
1994}
1995
a815b166 1996static void cirrus_vga_mem_write(void *opaque,
a8170e5e 1997 hwaddr addr,
a815b166
AK		 1998 uint64_t mem_value,
1999 uint32_t size)
e6e5ad80
FB		 2000{
2001 CirrusVGAState *s = opaque;
2002 unsigned bank_index;
2003 unsigned bank_offset;
2004 unsigned mode;
2005
4e12cd94 2006 if ((s->vga.sr[0x07] & 0x01) == 0) {
b2a5e761 2007 vga_mem_writeb(&s->vga, addr, mem_value);
e6e5ad80
FB		 2008 return;
2009 }
2010
2011 if (addr < 0x10000) {
2012 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2013 /* bitblt */
2014 *s->cirrus_srcptr++ = (uint8_t) mem_value;
a5082316 2015 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2016 cirrus_bitblt_cputovideo_next(s);
2017 }
2018 } else {
2019 /* video memory */
2020 bank_index = addr >> 15;
2021 bank_offset = addr & 0x7fff;
2022 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2023 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 2024 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2025 bank_offset <<= 4;
4e12cd94 2026 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2027 bank_offset <<= 3;
2028 }
2029 bank_offset &= s->cirrus_addr_mask;
4e12cd94
AK		 2030 mode = s->vga.gr[0x05] & 0x7;
2031 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2032 *(s->vga.vram_ptr + bank_offset) = mem_value;
fd4aa979
BS		 2033 memory_region_set_dirty(&s->vga.vram, bank_offset,
2034 sizeof(mem_value));
e6e5ad80 2035 } else {
4e12cd94 2036 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2037 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2038 bank_offset,
2039 mem_value);
2040 } else {
2041 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2042 bank_offset,
2043 mem_value);
2044 }
2045 }
2046 }
2047 }
2048 } else if (addr >= 0x18000 && addr < 0x18100) {
2049 /* memory-mapped I/O */
4e12cd94 2050 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 2051 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2052 }
2053 } else {
2054#ifdef DEBUG_CIRRUS
08406b03 2055 printf("cirrus: mem_writeb " TARGET_FMT_plx " value %02x\n", addr,
2056 mem_value);
e6e5ad80
FB		 2057#endif
2058 }
2059}
2060
b1950430
AK		 2061static const MemoryRegionOps cirrus_vga_mem_ops = {
2062 .read = cirrus_vga_mem_read,
2063 .write = cirrus_vga_mem_write,
2064 .endianness = DEVICE_LITTLE_ENDIAN,
a815b166
AK		 2065 .impl = {
2066 .min_access_size = 1,
2067 .max_access_size = 1,
2068 },
e6e5ad80
FB		 2069};
2070
a5082316
FB		 2071/***************************************
2072 *
2073 * hardware cursor
2074 *
2075 ***************************************/
2076
2077static inline void invalidate_cursor1(CirrusVGAState *s)
2078{
2079 if (s->last_hw_cursor_size) {
4e12cd94 2080 vga_invalidate_scanlines(&s->vga,
a5082316
FB		 2081 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2082 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2083 }
2084}
2085
2086static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2087{
2088 const uint8_t *src;
2089 uint32_t content;
2090 int y, y_min, y_max;
2091
4e12cd94
AK		 2092 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2093 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2094 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2095 y_min = 64;
2096 y_max = -1;
2097 for(y = 0; y < 64; y++) {
2098 content = ((uint32_t *)src)[0] |
2099 ((uint32_t *)src)[1] |
2100 ((uint32_t *)src)[2] |
2101 ((uint32_t *)src)[3];
2102 if (content) {
2103 if (y < y_min)
2104 y_min = y;
2105 if (y > y_max)
2106 y_max = y;
2107 }
2108 src += 16;
2109 }
2110 } else {
4e12cd94 2111 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316
FB		 2112 y_min = 32;
2113 y_max = -1;
2114 for(y = 0; y < 32; y++) {
2115 content = ((uint32_t *)src)[0] |
2116 ((uint32_t *)(src + 128))[0];
2117 if (content) {
2118 if (y < y_min)
2119 y_min = y;
2120 if (y > y_max)
2121 y_max = y;
2122 }
2123 src += 4;
2124 }
2125 }
2126 if (y_min > y_max) {
2127 s->last_hw_cursor_y_start = 0;
2128 s->last_hw_cursor_y_end = 0;
2129 } else {
2130 s->last_hw_cursor_y_start = y_min;
2131 s->last_hw_cursor_y_end = y_max + 1;
2132 }
2133}
2134
2135/* NOTE: we do not currently handle the cursor bitmap change, so we
2136 update the cursor only if it moves. */
a4a2f59c 2137static void cirrus_cursor_invalidate(VGACommonState *s1)
a5082316 2138{
4e12cd94 2139 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
a5082316
FB		 2140 int size;
2141
4e12cd94 2142 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
a5082316
FB		 2143 size = 0;
2144 } else {
4e12cd94 2145 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
a5082316
FB		 2146 size = 64;
2147 else
2148 size = 32;
2149 }
2150 /* invalidate last cursor and new cursor if any change */
2151 if (s->last_hw_cursor_size != size ||
2152 s->last_hw_cursor_x != s->hw_cursor_x ||
2153 s->last_hw_cursor_y != s->hw_cursor_y) {
2154
2155 invalidate_cursor1(s);
3b46e624 2156
a5082316
FB		 2157 s->last_hw_cursor_size = size;
2158 s->last_hw_cursor_x = s->hw_cursor_x;
2159 s->last_hw_cursor_y = s->hw_cursor_y;
2160 /* compute the real cursor min and max y */
2161 cirrus_cursor_compute_yrange(s);
2162 invalidate_cursor1(s);
2163 }
2164}
2165
94d7b483
BS		 2166#define DEPTH 8
2167#include "cirrus_vga_template.h"
2168
2169#define DEPTH 16
2170#include "cirrus_vga_template.h"
2171
2172#define DEPTH 32
2173#include "cirrus_vga_template.h"
2174
a4a2f59c 2175static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
a5082316 2176{
4e12cd94 2177 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
a5082316
FB		 2178 int w, h, bpp, x1, x2, poffset;
2179 unsigned int color0, color1;
2180 const uint8_t *palette, *src;
2181 uint32_t content;
3b46e624 2182
4e12cd94 2183 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
a5082316
FB		 2184 return;
2185 /* fast test to see if the cursor intersects with the scan line */
4e12cd94 2186 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
a5082316
FB		 2187 h = 64;
2188 } else {
2189 h = 32;
2190 }
2191 if (scr_y < s->hw_cursor_y ||
2192 scr_y >= (s->hw_cursor_y + h))
2193 return;
3b46e624 2194
4e12cd94
AK		 2195 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2196 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2197 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2198 src += (scr_y - s->hw_cursor_y) * 16;
2199 poffset = 8;
2200 content = ((uint32_t *)src)[0] |
2201 ((uint32_t *)src)[1] |
2202 ((uint32_t *)src)[2] |
2203 ((uint32_t *)src)[3];
2204 } else {
4e12cd94 2205 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316
FB		 2206 src += (scr_y - s->hw_cursor_y) * 4;
2207 poffset = 128;
2208 content = ((uint32_t *)src)[0] |
2209 ((uint32_t *)(src + 128))[0];
2210 }
2211 /* if nothing to draw, no need to continue */
2212 if (!content)
2213 return;
2214 w = h;
2215
2216 x1 = s->hw_cursor_x;
4e12cd94 2217 if (x1 >= s->vga.last_scr_width)
a5082316
FB		 2218 return;
2219 x2 = s->hw_cursor_x + w;
4e12cd94
AK		 2220 if (x2 > s->vga.last_scr_width)
2221 x2 = s->vga.last_scr_width;
a5082316
FB		 2222 w = x2 - x1;
2223 palette = s->cirrus_hidden_palette;
4e12cd94
AK		 2224 color0 = s->vga.rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2225 c6_to_8(palette[0x0 * 3 + 1]),
2226 c6_to_8(palette[0x0 * 3 + 2]));
2227 color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2228 c6_to_8(palette[0xf * 3 + 1]),
2229 c6_to_8(palette[0xf * 3 + 2]));
2230 bpp = ((ds_get_bits_per_pixel(s->vga.ds) + 7) >> 3);
a5082316 2231 d1 += x1 * bpp;
4e12cd94 2232 switch(ds_get_bits_per_pixel(s->vga.ds)) {
a5082316
FB		 2233 default:
2234 break;
2235 case 8:
2236 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2237 break;
2238 case 15:
2239 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2240 break;
2241 case 16:
2242 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2243 break;
2244 case 32:
2245 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2246 break;
2247 }
2248}
2249
e6e5ad80
FB		 2250/***************************************
2251 *
2252 * LFB memory access
2253 *
2254 ***************************************/
2255
a8170e5e 2256static uint64_t cirrus_linear_read(void *opaque, hwaddr addr,
899adf81 2257 unsigned size)
e6e5ad80 2258{
e05587e8 2259 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2260 uint32_t ret;
2261
e6e5ad80
FB		 2262 addr &= s->cirrus_addr_mask;
2263
4e12cd94 2264 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2265 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2266 /* memory-mapped I/O */
2267 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2268 } else if (0) {
2269 /* XXX handle bitblt */
2270 ret = 0xff;
2271 } else {
2272 /* video memory */
4e12cd94 2273 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2274 addr <<= 4;
4e12cd94 2275 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2276 addr <<= 3;
2277 }
2278 addr &= s->cirrus_addr_mask;
4e12cd94 2279 ret = *(s->vga.vram_ptr + addr);
e6e5ad80
FB		 2280 }
2281
2282 return ret;
2283}
2284
a8170e5e 2285static void cirrus_linear_write(void *opaque, hwaddr addr,
899adf81 2286 uint64_t val, unsigned size)
e6e5ad80 2287{
e05587e8 2288 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2289 unsigned mode;
2290
2291 addr &= s->cirrus_addr_mask;
3b46e624 2292
4e12cd94 2293 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2294 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2295 /* memory-mapped I/O */
2296 cirrus_mmio_blt_write(s, addr & 0xff, val);
2297 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2298 /* bitblt */
2299 *s->cirrus_srcptr++ = (uint8_t) val;
a5082316 2300 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2301 cirrus_bitblt_cputovideo_next(s);
2302 }
2303 } else {
2304 /* video memory */
4e12cd94 2305 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2306 addr <<= 4;
4e12cd94 2307 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2308 addr <<= 3;
2309 }
2310 addr &= s->cirrus_addr_mask;
2311
4e12cd94
AK		 2312 mode = s->vga.gr[0x05] & 0x7;
2313 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2314 *(s->vga.vram_ptr + addr) = (uint8_t) val;
fd4aa979 2315 memory_region_set_dirty(&s->vga.vram, addr, 1);
e6e5ad80 2316 } else {
4e12cd94 2317 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2318 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2319 } else {
2320 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2321 }
2322 }
2323 }
2324}
2325
a5082316
FB		 2326/***************************************
2327 *
2328 * system to screen memory access
2329 *
2330 ***************************************/
2331
2332
4e56f089 2333static uint64_t cirrus_linear_bitblt_read(void *opaque,
a8170e5e 2334 hwaddr addr,
4e56f089 2335 unsigned size)
a5082316 2336{
4e56f089 2337 CirrusVGAState *s = opaque;
a5082316
FB		 2338 uint32_t ret;
2339
2340 /* XXX handle bitblt */
4e56f089 2341 (void)s;
a5082316
FB		 2342 ret = 0xff;
2343 return ret;
2344}
2345
4e56f089 2346static void cirrus_linear_bitblt_write(void *opaque,
a8170e5e 2347 hwaddr addr,
4e56f089
AK		 2348 uint64_t val,
2349 unsigned size)
a5082316 2350{
e05587e8 2351 CirrusVGAState *s = opaque;
a5082316
FB		 2352
2353 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2354 /* bitblt */
2355 *s->cirrus_srcptr++ = (uint8_t) val;
2356 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2357 cirrus_bitblt_cputovideo_next(s);
2358 }
2359 }
2360}
2361
b1950430
AK		 2362static const MemoryRegionOps cirrus_linear_bitblt_io_ops = {
2363 .read = cirrus_linear_bitblt_read,
2364 .write = cirrus_linear_bitblt_write,
2365 .endianness = DEVICE_LITTLE_ENDIAN,
4e56f089
AK		 2366 .impl = {
2367 .min_access_size = 1,
2368 .max_access_size = 1,
2369 },
a5082316
FB		 2370};
2371
b1950430
AK		 2372static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank)
2373{
7969d9ed
AK		 2374 MemoryRegion *mr = &s->cirrus_bank[bank];
2375 bool enabled = !(s->cirrus_srcptr != s->cirrus_srcptr_end)
4e12cd94
AK		 2376 && !((s->vga.sr[0x07] & 0x01) == 0)
2377 && !((s->vga.gr[0x0B] & 0x14) == 0x14)
7969d9ed
AK		 2378 && !(s->vga.gr[0x0B] & 0x02);
2379
2380 memory_region_set_enabled(mr, enabled);
2381 memory_region_set_alias_offset(mr, s->cirrus_bank_base[bank]);
b1950430 2382}
2bec46dc 2383
b1950430
AK		 2384static void map_linear_vram(CirrusVGAState *s)
2385{
4c08fd1e 2386 if (s->bustype == CIRRUS_BUSTYPE_PCI && !s->linear_vram) {
b1950430
AK		 2387 s->linear_vram = true;
2388 memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1);
2389 }
2390 map_linear_vram_bank(s, 0);
2391 map_linear_vram_bank(s, 1);
2bec46dc
AL		 2392}
2393
2394static void unmap_linear_vram(CirrusVGAState *s)
2395{
4c08fd1e 2396 if (s->bustype == CIRRUS_BUSTYPE_PCI && s->linear_vram) {
b1950430
AK		 2397 s->linear_vram = false;
2398 memory_region_del_subregion(&s->pci_bar, &s->vga.vram);
4516e45f 2399 }
7969d9ed
AK		 2400 memory_region_set_enabled(&s->cirrus_bank[0], false);
2401 memory_region_set_enabled(&s->cirrus_bank[1], false);
2bec46dc
AL		 2402}
2403
8926b517
FB		 2404/* Compute the memory access functions */
2405static void cirrus_update_memory_access(CirrusVGAState *s)
2406{
2407 unsigned mode;
2408
64c048f4 2409 memory_region_transaction_begin();
4e12cd94 2410 if ((s->vga.sr[0x17] & 0x44) == 0x44) {
8926b517
FB		 2411 goto generic_io;
2412 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2413 goto generic_io;
2414 } else {
4e12cd94 2415 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
8926b517 2416 goto generic_io;
4e12cd94 2417 } else if (s->vga.gr[0x0B] & 0x02) {
8926b517
FB		 2418 goto generic_io;
2419 }
3b46e624 2420
4e12cd94
AK		 2421 mode = s->vga.gr[0x05] & 0x7;
2422 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2bec46dc 2423 map_linear_vram(s);
8926b517
FB		 2424 } else {
2425 generic_io:
2bec46dc 2426 unmap_linear_vram(s);
8926b517
FB		 2427 }
2428 }
64c048f4 2429 memory_region_transaction_commit();
8926b517
FB		 2430}
2431
2432
e6e5ad80
FB		 2433/* I/O ports */
2434
0ceac75b 2435static uint32_t cirrus_vga_ioport_read(void *opaque, uint32_t addr)
e6e5ad80 2436{
b6343073
JQ		 2437 CirrusVGAState *c = opaque;
2438 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2439 int val, index;
2440
bd8f2f5d
JK		 2441 qemu_flush_coalesced_mmio_buffer();
2442
b6343073 2443 if (vga_ioport_invalid(s, addr)) {
e6e5ad80
FB		 2444 val = 0xff;
2445 } else {
2446 switch (addr) {
2447 case 0x3c0:
b6343073
JQ		 2448 if (s->ar_flip_flop == 0) {
2449 val = s->ar_index;
e6e5ad80
FB		 2450 } else {
2451 val = 0;
2452 }
2453 break;
2454 case 0x3c1:
b6343073 2455 index = s->ar_index & 0x1f;
e6e5ad80 2456 if (index < 21)
b6343073 2457 val = s->ar[index];
e6e5ad80
FB		 2458 else
2459 val = 0;
2460 break;
2461 case 0x3c2:
b6343073 2462 val = s->st00;
e6e5ad80
FB		 2463 break;
2464 case 0x3c4:
b6343073 2465 val = s->sr_index;
e6e5ad80
FB		 2466 break;
2467 case 0x3c5:
8a82c322
JQ		 2468 val = cirrus_vga_read_sr(c);
2469 break;
e6e5ad80 2470#ifdef DEBUG_VGA_REG
b6343073 2471 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
e6e5ad80
FB		 2472#endif
2473 break;
2474 case 0x3c6:
957c9db5 2475 val = cirrus_read_hidden_dac(c);
e6e5ad80
FB		 2476 break;
2477 case 0x3c7:
b6343073 2478 val = s->dac_state;
e6e5ad80 2479 break;
ae184e4a 2480 case 0x3c8:
b6343073
JQ		 2481 val = s->dac_write_index;
2482 c->cirrus_hidden_dac_lockindex = 0;
ae184e4a
FB		 2483 break;
2484 case 0x3c9:
5deaeee3
JQ		 2485 val = cirrus_vga_read_palette(c);
2486 break;
e6e5ad80 2487 case 0x3ca:
b6343073 2488 val = s->fcr;
e6e5ad80
FB		 2489 break;
2490 case 0x3cc:
b6343073 2491 val = s->msr;
e6e5ad80
FB		 2492 break;
2493 case 0x3ce:
b6343073 2494 val = s->gr_index;
e6e5ad80
FB		 2495 break;
2496 case 0x3cf:
f705db9d 2497 val = cirrus_vga_read_gr(c, s->gr_index);
e6e5ad80 2498#ifdef DEBUG_VGA_REG
b6343073 2499 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
e6e5ad80
FB		 2500#endif
2501 break;
2502 case 0x3b4:
2503 case 0x3d4:
b6343073 2504 val = s->cr_index;
e6e5ad80
FB		 2505 break;
2506 case 0x3b5:
2507 case 0x3d5:
b863d514 2508 val = cirrus_vga_read_cr(c, s->cr_index);
e6e5ad80 2509#ifdef DEBUG_VGA_REG
b6343073 2510 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80
FB		 2511#endif
2512 break;
2513 case 0x3ba:
2514 case 0x3da:
2515 /* just toggle to fool polling */
b6343073
JQ		 2516 val = s->st01 = s->retrace(s);
2517 s->ar_flip_flop = 0;
e6e5ad80
FB		 2518 break;
2519 default:
2520 val = 0x00;
2521 break;
2522 }
2523 }
2524#if defined(DEBUG_VGA)
2525 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2526#endif
2527 return val;
2528}
2529
0ceac75b 2530static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
e6e5ad80 2531{
b6343073
JQ		 2532 CirrusVGAState *c = opaque;
2533 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2534 int index;
2535
bd8f2f5d
JK		 2536 qemu_flush_coalesced_mmio_buffer();
2537
e6e5ad80 2538 /* check port range access depending on color/monochrome mode */
b6343073 2539 if (vga_ioport_invalid(s, addr)) {
e6e5ad80 2540 return;
25a18cbd 2541 }
e6e5ad80
FB		 2542#ifdef DEBUG_VGA
2543 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2544#endif
2545
2546 switch (addr) {
2547 case 0x3c0:
b6343073 2548 if (s->ar_flip_flop == 0) {
e6e5ad80 2549 val &= 0x3f;
b6343073 2550 s->ar_index = val;
e6e5ad80 2551 } else {
b6343073 2552 index = s->ar_index & 0x1f;
e6e5ad80
FB		 2553 switch (index) {
2554 case 0x00 ... 0x0f:
b6343073 2555 s->ar[index] = val & 0x3f;
e6e5ad80
FB		 2556 break;
2557 case 0x10:
b6343073 2558 s->ar[index] = val & ~0x10;
e6e5ad80
FB		 2559 break;
2560 case 0x11:
b6343073 2561 s->ar[index] = val;
e6e5ad80
FB		 2562 break;
2563 case 0x12:
b6343073 2564 s->ar[index] = val & ~0xc0;
e6e5ad80
FB		 2565 break;
2566 case 0x13:
b6343073 2567 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2568 break;
2569 case 0x14:
b6343073 2570 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2571 break;
2572 default:
2573 break;
2574 }
2575 }
b6343073 2576 s->ar_flip_flop ^= 1;
e6e5ad80
FB		 2577 break;
2578 case 0x3c2:
b6343073
JQ		 2579 s->msr = val & ~0x10;
2580 s->update_retrace_info(s);
e6e5ad80
FB		 2581 break;
2582 case 0x3c4:
b6343073 2583 s->sr_index = val;
e6e5ad80
FB		 2584 break;
2585 case 0x3c5:
e6e5ad80 2586#ifdef DEBUG_VGA_REG
b6343073 2587 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
e6e5ad80 2588#endif
31c63201
JQ		 2589 cirrus_vga_write_sr(c, val);
2590 break;
e6e5ad80
FB		 2591 break;
2592 case 0x3c6:
b6343073 2593 cirrus_write_hidden_dac(c, val);
e6e5ad80
FB		 2594 break;
2595 case 0x3c7:
b6343073
JQ		 2596 s->dac_read_index = val;
2597 s->dac_sub_index = 0;
2598 s->dac_state = 3;
e6e5ad80
FB		 2599 break;
2600 case 0x3c8:
b6343073
JQ		 2601 s->dac_write_index = val;
2602 s->dac_sub_index = 0;
2603 s->dac_state = 0;
e6e5ad80
FB		 2604 break;
2605 case 0x3c9:
86948bb1
JQ		 2606 cirrus_vga_write_palette(c, val);
2607 break;
e6e5ad80 2608 case 0x3ce:
b6343073 2609 s->gr_index = val;
e6e5ad80
FB		 2610 break;
2611 case 0x3cf:
e6e5ad80 2612#ifdef DEBUG_VGA_REG
b6343073 2613 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
e6e5ad80 2614#endif
22286bc6 2615 cirrus_vga_write_gr(c, s->gr_index, val);
e6e5ad80
FB		 2616 break;
2617 case 0x3b4:
2618 case 0x3d4:
b6343073 2619 s->cr_index = val;
e6e5ad80
FB		 2620 break;
2621 case 0x3b5:
2622 case 0x3d5:
e6e5ad80 2623#ifdef DEBUG_VGA_REG
b6343073 2624 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80 2625#endif
4ec1ce04 2626 cirrus_vga_write_cr(c, val);
e6e5ad80
FB		 2627 break;
2628 case 0x3ba:
2629 case 0x3da:
b6343073 2630 s->fcr = val & 0x10;
e6e5ad80
FB		 2631 break;
2632 }
2633}
2634
e36f36e1
FB		 2635/***************************************
2636 *
2637 * memory-mapped I/O access
2638 *
2639 ***************************************/
2640
a8170e5e 2641static uint64_t cirrus_mmio_read(void *opaque, hwaddr addr,
1e04d4d6 2642 unsigned size)
e36f36e1 2643{
e05587e8 2644 CirrusVGAState *s = opaque;
e36f36e1 2645
e36f36e1
FB		 2646 if (addr >= 0x100) {
2647 return cirrus_mmio_blt_read(s, addr - 0x100);
2648 } else {
0ceac75b 2649 return cirrus_vga_ioport_read(s, addr + 0x3c0);
e36f36e1
FB		 2650 }
2651}
2652
a8170e5e 2653static void cirrus_mmio_write(void *opaque, hwaddr addr,
1e04d4d6 2654 uint64_t val, unsigned size)
e36f36e1 2655{
e05587e8 2656 CirrusVGAState *s = opaque;
e36f36e1 2657
e36f36e1
FB		 2658 if (addr >= 0x100) {
2659 cirrus_mmio_blt_write(s, addr - 0x100, val);
2660 } else {
0ceac75b 2661 cirrus_vga_ioport_write(s, addr + 0x3c0, val);
e36f36e1
FB		 2662 }
2663}
2664
b1950430
AK		 2665static const MemoryRegionOps cirrus_mmio_io_ops = {
2666 .read = cirrus_mmio_read,
2667 .write = cirrus_mmio_write,
2668 .endianness = DEVICE_LITTLE_ENDIAN,
1e04d4d6
AK		 2669 .impl = {
2670 .min_access_size = 1,
2671 .max_access_size = 1,
2672 },
e36f36e1
FB		 2673};
2674
2c6ab832
FB		 2675/* load/save state */
2676
e59fb374 2677static int cirrus_post_load(void *opaque, int version_id)
2c6ab832
FB		 2678{
2679 CirrusVGAState *s = opaque;
2680
4e12cd94
AK		 2681 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
2682 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
2c6ab832 2683
2bec46dc 2684 cirrus_update_memory_access(s);
2c6ab832 2685 /* force refresh */
4e12cd94 2686 s->vga.graphic_mode = -1;
2c6ab832
FB		 2687 cirrus_update_bank_ptr(s, 0);
2688 cirrus_update_bank_ptr(s, 1);
2689 return 0;
2690}
2691
7e72abc3
JQ		 2692static const VMStateDescription vmstate_cirrus_vga = {
2693 .name = "cirrus_vga",
2694 .version_id = 2,
2695 .minimum_version_id = 1,
2696 .minimum_version_id_old = 1,
2697 .post_load = cirrus_post_load,
2698 .fields = (VMStateField []) {
2699 VMSTATE_UINT32(vga.latch, CirrusVGAState),
2700 VMSTATE_UINT8(vga.sr_index, CirrusVGAState),
2701 VMSTATE_BUFFER(vga.sr, CirrusVGAState),
2702 VMSTATE_UINT8(vga.gr_index, CirrusVGAState),
2703 VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState),
2704 VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState),
2705 VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
2706 VMSTATE_UINT8(vga.ar_index, CirrusVGAState),
2707 VMSTATE_BUFFER(vga.ar, CirrusVGAState),
2708 VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState),
2709 VMSTATE_UINT8(vga.cr_index, CirrusVGAState),
2710 VMSTATE_BUFFER(vga.cr, CirrusVGAState),
2711 VMSTATE_UINT8(vga.msr, CirrusVGAState),
2712 VMSTATE_UINT8(vga.fcr, CirrusVGAState),
2713 VMSTATE_UINT8(vga.st00, CirrusVGAState),
2714 VMSTATE_UINT8(vga.st01, CirrusVGAState),
2715 VMSTATE_UINT8(vga.dac_state, CirrusVGAState),
2716 VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState),
2717 VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState),
2718 VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState),
2719 VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState),
2720 VMSTATE_BUFFER(vga.palette, CirrusVGAState),
2721 VMSTATE_INT32(vga.bank_offset, CirrusVGAState),
2722 VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState),
2723 VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState),
2724 VMSTATE_UINT32(hw_cursor_x, CirrusVGAState),
2725 VMSTATE_UINT32(hw_cursor_y, CirrusVGAState),
2726 /* XXX: we do not save the bitblt state - we assume we do not save
2727 the state when the blitter is active */
2728 VMSTATE_END_OF_LIST()
4f335feb 2729 }
7e72abc3 2730};
4f335feb 2731
7e72abc3
JQ		 2732static const VMStateDescription vmstate_pci_cirrus_vga = {
2733 .name = "cirrus_vga",
2734 .version_id = 2,
2735 .minimum_version_id = 2,
2736 .minimum_version_id_old = 2,
7e72abc3
JQ		 2737 .fields = (VMStateField []) {
2738 VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState),
2739 VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
2740 vmstate_cirrus_vga, CirrusVGAState),
2741 VMSTATE_END_OF_LIST()
2742 }
2743};
4f335feb 2744
e6e5ad80
FB		 2745/***************************************
2746 *
2747 * initialize
2748 *
2749 ***************************************/
2750
4abc796d 2751static void cirrus_reset(void *opaque)
e6e5ad80 2752{
4abc796d 2753 CirrusVGAState *s = opaque;
e6e5ad80 2754
03a3e7ba 2755 vga_common_reset(&s->vga);
ee50c6bc 2756 unmap_linear_vram(s);
4e12cd94 2757 s->vga.sr[0x06] = 0x0f;
4abc796d 2758 if (s->device_id == CIRRUS_ID_CLGD5446) {
78e127ef 2759 /* 4MB 64 bit memory config, always PCI */
4e12cd94
AK		 2760 s->vga.sr[0x1F] = 0x2d; // MemClock
2761 s->vga.gr[0x18] = 0x0f; // fastest memory configuration
2762 s->vga.sr[0x0f] = 0x98;
2763 s->vga.sr[0x17] = 0x20;
2764 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
78e127ef 2765 } else {
4e12cd94
AK		 2766 s->vga.sr[0x1F] = 0x22; // MemClock
2767 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
2768 s->vga.sr[0x17] = s->bustype;
2769 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
78e127ef 2770 }
4e12cd94 2771 s->vga.cr[0x27] = s->device_id;
e6e5ad80
FB		 2772
2773 s->cirrus_hidden_dac_lockindex = 5;
2774 s->cirrus_hidden_dac_data = 0;
4abc796d
BS		 2775}
2776
b1950430
AK		 2777static const MemoryRegionOps cirrus_linear_io_ops = {
2778 .read = cirrus_linear_read,
2779 .write = cirrus_linear_write,
2780 .endianness = DEVICE_LITTLE_ENDIAN,
899adf81
AK		 2781 .impl = {
2782 .min_access_size = 1,
2783 .max_access_size = 1,
2784 },
b1950430
AK		 2785};
2786
be20f9e9
AK		 2787static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci,
2788 MemoryRegion *system_memory)
4abc796d
BS		 2789{
2790 int i;
2791 static int inited;
2792
2793 if (!inited) {
2794 inited = 1;
2795 for(i = 0;i < 256; i++)
2796 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
2797 rop_to_index[CIRRUS_ROP_0] = 0;
2798 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
2799 rop_to_index[CIRRUS_ROP_NOP] = 2;
2800 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
2801 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
2802 rop_to_index[CIRRUS_ROP_SRC] = 5;
2803 rop_to_index[CIRRUS_ROP_1] = 6;
2804 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
2805 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
2806 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
2807 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
2808 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
2809 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
2810 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
2811 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
2812 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
2813 s->device_id = device_id;
2814 if (is_pci)
2815 s->bustype = CIRRUS_BUSTYPE_PCI;
2816 else
2817 s->bustype = CIRRUS_BUSTYPE_ISA;
2818 }
2819
0ceac75b 2820 register_ioport_write(0x3c0, 16, 1, cirrus_vga_ioport_write, s);
4abc796d 2821
0ceac75b
JQ		 2822 register_ioport_write(0x3b4, 2, 1, cirrus_vga_ioport_write, s);
2823 register_ioport_write(0x3d4, 2, 1, cirrus_vga_ioport_write, s);
2824 register_ioport_write(0x3ba, 1, 1, cirrus_vga_ioport_write, s);
2825 register_ioport_write(0x3da, 1, 1, cirrus_vga_ioport_write, s);
4abc796d 2826
0ceac75b 2827 register_ioport_read(0x3c0, 16, 1, cirrus_vga_ioport_read, s);
4abc796d 2828
0ceac75b
JQ		 2829 register_ioport_read(0x3b4, 2, 1, cirrus_vga_ioport_read, s);
2830 register_ioport_read(0x3d4, 2, 1, cirrus_vga_ioport_read, s);
2831 register_ioport_read(0x3ba, 1, 1, cirrus_vga_ioport_read, s);
2832 register_ioport_read(0x3da, 1, 1, cirrus_vga_ioport_read, s);
4abc796d 2833
b1950430
AK		 2834 memory_region_init(&s->low_mem_container,
2835 "cirrus-lowmem-container",
2836 0x20000);
2837
2838 memory_region_init_io(&s->low_mem, &cirrus_vga_mem_ops, s,
2839 "cirrus-low-memory", 0x20000);
2840 memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
7969d9ed
AK		 2841 for (i = 0; i < 2; ++i) {
2842 static const char *names[] = { "vga.bank0", "vga.bank1" };
2843 MemoryRegion *bank = &s->cirrus_bank[i];
2844 memory_region_init_alias(bank, names[i], &s->vga.vram, 0, 0x8000);
2845 memory_region_set_enabled(bank, false);
2846 memory_region_add_subregion_overlap(&s->low_mem_container, i * 0x8000,
2847 bank, 1);
2848 }
be20f9e9 2849 memory_region_add_subregion_overlap(system_memory,
b1950430
AK		 2850 isa_mem_base + 0x000a0000,
2851 &s->low_mem_container,
2852 1);
2853 memory_region_set_coalescing(&s->low_mem);
2c6ab832 2854
fefe54e3 2855 /* I/O handler for LFB */
b1950430 2856 memory_region_init_io(&s->cirrus_linear_io, &cirrus_linear_io_ops, s,
19403a68
MT		 2857 "cirrus-linear-io", s->vga.vram_size_mb
2858 * 1024 * 1024);
bd8f2f5d 2859 memory_region_set_flush_coalesced(&s->cirrus_linear_io);
fefe54e3
AL		 2860
2861 /* I/O handler for LFB */
b1950430
AK		 2862 memory_region_init_io(&s->cirrus_linear_bitblt_io,
2863 &cirrus_linear_bitblt_io_ops,
2864 s,
2865 "cirrus-bitblt-mmio",
2866 0x400000);
bd8f2f5d 2867 memory_region_set_flush_coalesced(&s->cirrus_linear_bitblt_io);
fefe54e3
AL		 2868
2869 /* I/O handler for memory-mapped I/O */
b1950430
AK		 2870 memory_region_init_io(&s->cirrus_mmio_io, &cirrus_mmio_io_ops, s,
2871 "cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
bd8f2f5d 2872 memory_region_set_flush_coalesced(&s->cirrus_mmio_io);
fefe54e3
AL		 2873
2874 s->real_vram_size =
2875 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
2876
4e12cd94 2877 /* XXX: s->vga.vram_size must be a power of two */
fefe54e3
AL		 2878 s->cirrus_addr_mask = s->real_vram_size - 1;
2879 s->linear_mmio_mask = s->real_vram_size - 256;
2880
4e12cd94
AK		 2881 s->vga.get_bpp = cirrus_get_bpp;
2882 s->vga.get_offsets = cirrus_get_offsets;
2883 s->vga.get_resolution = cirrus_get_resolution;
2884 s->vga.cursor_invalidate = cirrus_cursor_invalidate;
2885 s->vga.cursor_draw_line = cirrus_cursor_draw_line;
fefe54e3 2886
a08d4367 2887 qemu_register_reset(cirrus_reset, s);
e6e5ad80
FB		 2888}
2889
2890/***************************************
2891 *
2892 * ISA bus support
2893 *
2894 ***************************************/
2895
3d402831 2896static int vga_initfn(ISADevice *dev)
e6e5ad80 2897{
3d402831
BS		 2898 ISACirrusVGAState *d = DO_UPCAST(ISACirrusVGAState, dev, dev);
2899 VGACommonState *s = &d->cirrus_vga.vga;
2900
4a1e244e 2901 vga_common_init(s);
3d402831
BS		 2902 cirrus_init_common(&d->cirrus_vga, CIRRUS_ID_CLGD5430, 0,
2903 isa_address_space(dev));
2904 s->ds = graphic_console_init(s->update, s->invalidate,
2905 s->screen_dump, s->text_update,
2906 s);
5245d57a 2907 rom_add_vga(VGABIOS_CIRRUS_FILENAME);
e6e5ad80 2908 /* XXX ISA-LFB support */
ad6d45fa 2909 /* FIXME not qdev yet */
3d402831
BS		 2910 return 0;
2911}
2912
19403a68
MT		 2913static Property isa_vga_cirrus_properties[] = {
2914 DEFINE_PROP_UINT32("vgamem_mb", struct ISACirrusVGAState,
2915 cirrus_vga.vga.vram_size_mb, 8),
2916 DEFINE_PROP_END_OF_LIST(),
2917};
2918
8f04ee08
AL		 2919static void isa_cirrus_vga_class_init(ObjectClass *klass, void *data)
2920{
2921 ISADeviceClass *k = ISA_DEVICE_CLASS(klass);
39bffca2 2922 DeviceClass *dc = DEVICE_CLASS(klass);
8f04ee08 2923
39bffca2
AL		 2924 dc->vmsd = &vmstate_cirrus_vga;
2925 k->init = vga_initfn;
19403a68 2926 dc->props = isa_vga_cirrus_properties;
8f04ee08
AL		 2927}
2928
39bffca2
AL		 2929static TypeInfo isa_cirrus_vga_info = {
2930 .name = "isa-cirrus-vga",
2931 .parent = TYPE_ISA_DEVICE,
2932 .instance_size = sizeof(ISACirrusVGAState),
8f04ee08 2933 .class_init = isa_cirrus_vga_class_init,
3d402831
BS		 2934};
2935
e6e5ad80
FB		 2936/***************************************
2937 *
2938 * PCI bus support
2939 *
2940 ***************************************/
2941
81a322d4 2942static int pci_cirrus_vga_initfn(PCIDevice *dev)
a414c306
GH		 2943{
2944 PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev);
2945 CirrusVGAState *s = &d->cirrus_vga;
40021f08
AL		 2946 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2947 int16_t device_id = pc->device_id;
a414c306
GH		 2948
2949 /* setup VGA */
4a1e244e 2950 vga_common_init(&s->vga);
be20f9e9 2951 cirrus_init_common(s, device_id, 1, pci_address_space(dev));
a414c306
GH		 2952 s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
2953 s->vga.screen_dump, s->vga.text_update,
2954 &s->vga);
2955
2956 /* setup PCI */
a414c306 2957
b1950430
AK		 2958 memory_region_init(&s->pci_bar, "cirrus-pci-bar0", 0x2000000);
2959
2960 /* XXX: add byte swapping apertures */
2961 memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io);
2962 memory_region_add_subregion(&s->pci_bar, 0x1000000,
2963 &s->cirrus_linear_bitblt_io);
2964
a414c306
GH		 2965 /* setup memory space */
2966 /* memory #0 LFB */
2967 /* memory #1 memory-mapped I/O */
2968 /* XXX: s->vga.vram_size must be a power of two */
e824b2cc 2969 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar);
a414c306 2970 if (device_id == CIRRUS_ID_CLGD5446) {
e824b2cc 2971 pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io);
a414c306 2972 }
81a322d4 2973 return 0;
a414c306
GH		 2974}
2975
19403a68
MT		 2976static Property pci_vga_cirrus_properties[] = {
2977 DEFINE_PROP_UINT32("vgamem_mb", struct PCICirrusVGAState,
2978 cirrus_vga.vga.vram_size_mb, 8),
2979 DEFINE_PROP_END_OF_LIST(),
2980};
2981
40021f08
AL		 2982static void cirrus_vga_class_init(ObjectClass *klass, void *data)
2983{
39bffca2 2984 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 2985 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2986
2987 k->no_hotplug = 1;
2988 k->init = pci_cirrus_vga_initfn;
2989 k->romfile = VGABIOS_CIRRUS_FILENAME;
2990 k->vendor_id = PCI_VENDOR_ID_CIRRUS;
2991 k->device_id = CIRRUS_ID_CLGD5446;
2992 k->class_id = PCI_CLASS_DISPLAY_VGA;
39bffca2
AL		 2993 dc->desc = "Cirrus CLGD 54xx VGA";
2994 dc->vmsd = &vmstate_pci_cirrus_vga;
19403a68 2995 dc->props = pci_vga_cirrus_properties;
40021f08
AL		 2996}
2997
39bffca2
AL		 2998static TypeInfo cirrus_vga_info = {
2999 .name = "cirrus-vga",
3000 .parent = TYPE_PCI_DEVICE,
3001 .instance_size = sizeof(PCICirrusVGAState),
3002 .class_init = cirrus_vga_class_init,
a414c306 3003};
e6e5ad80 3004
83f7d43a 3005static void cirrus_vga_register_types(void)
a414c306 3006{
83f7d43a 3007 type_register_static(&isa_cirrus_vga_info);
39bffca2 3008 type_register_static(&cirrus_vga_info);
e6e5ad80 3009}
83f7d43a
AF		 3010
3011type_init(cirrus_vga_register_types)
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