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Revert "eepro100: Remove unused device status entries"
[mirror_qemu.git] / hw / cirrus_vga.c
CommitLineData
e6e5ad80 1/*
aeb3c85f 2 * QEMU Cirrus CLGD 54xx VGA Emulator.
5fafdf24 3 *
e6e5ad80 4 * Copyright (c) 2004 Fabrice Bellard
aeb3c85f 5 * Copyright (c) 2004 Makoto Suzuki (suzu)
5fafdf24 6 *
e6e5ad80
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
aeb3c85f
FB		 25/*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
87ecb68b
PB		 29#include "hw.h"
30#include "pc.h"
31#include "pci.h"
32#include "console.h"
e6e5ad80 33#include "vga_int.h"
2bec46dc 34#include "kvm.h"
e6e5ad80 35
a5082316
FB		 36/*
37 * TODO:
ad81218e 38 * - destination write mask support not complete (bits 5..7)
a5082316
FB		 39 * - optimize linear mappings
40 * - optimize bitblt functions
41 */
42
e36f36e1 43//#define DEBUG_CIRRUS
a21ae81d 44//#define DEBUG_BITBLT
e36f36e1 45
e6e5ad80
FB		 46/***************************************
47 *
48 * definitions
49 *
50 ***************************************/
51
e6e5ad80
FB		 52// ID
53#define CIRRUS_ID_CLGD5422 (0x23<<2)
54#define CIRRUS_ID_CLGD5426 (0x24<<2)
55#define CIRRUS_ID_CLGD5424 (0x25<<2)
56#define CIRRUS_ID_CLGD5428 (0x26<<2)
57#define CIRRUS_ID_CLGD5430 (0x28<<2)
58#define CIRRUS_ID_CLGD5434 (0x2A<<2)
a21ae81d 59#define CIRRUS_ID_CLGD5436 (0x2B<<2)
e6e5ad80
FB		 60#define CIRRUS_ID_CLGD5446 (0x2E<<2)
61
62// sequencer 0x07
63#define CIRRUS_SR7_BPP_VGA 0x00
64#define CIRRUS_SR7_BPP_SVGA 0x01
65#define CIRRUS_SR7_BPP_MASK 0x0e
66#define CIRRUS_SR7_BPP_8 0x00
67#define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
68#define CIRRUS_SR7_BPP_24 0x04
69#define CIRRUS_SR7_BPP_16 0x06
70#define CIRRUS_SR7_BPP_32 0x08
71#define CIRRUS_SR7_ISAADDR_MASK 0xe0
72
73// sequencer 0x0f
74#define CIRRUS_MEMSIZE_512k 0x08
75#define CIRRUS_MEMSIZE_1M 0x10
76#define CIRRUS_MEMSIZE_2M 0x18
77#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
78
79// sequencer 0x12
80#define CIRRUS_CURSOR_SHOW 0x01
81#define CIRRUS_CURSOR_HIDDENPEL 0x02
82#define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
83
84// sequencer 0x17
85#define CIRRUS_BUSTYPE_VLBFAST 0x10
86#define CIRRUS_BUSTYPE_PCI 0x20
87#define CIRRUS_BUSTYPE_VLBSLOW 0x30
88#define CIRRUS_BUSTYPE_ISA 0x38
89#define CIRRUS_MMIO_ENABLE 0x04
90#define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
91#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
92
93// control 0x0b
94#define CIRRUS_BANKING_DUAL 0x01
95#define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
96
97// control 0x30
98#define CIRRUS_BLTMODE_BACKWARDS 0x01
99#define CIRRUS_BLTMODE_MEMSYSDEST 0x02
100#define CIRRUS_BLTMODE_MEMSYSSRC 0x04
101#define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
102#define CIRRUS_BLTMODE_PATTERNCOPY 0x40
103#define CIRRUS_BLTMODE_COLOREXPAND 0x80
104#define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
105#define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
106#define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
107#define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
108#define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
109
110// control 0x31
111#define CIRRUS_BLT_BUSY 0x01
112#define CIRRUS_BLT_START 0x02
113#define CIRRUS_BLT_RESET 0x04
114#define CIRRUS_BLT_FIFOUSED 0x10
a5082316 115#define CIRRUS_BLT_AUTOSTART 0x80
e6e5ad80
FB		 116
117// control 0x32
118#define CIRRUS_ROP_0 0x00
119#define CIRRUS_ROP_SRC_AND_DST 0x05
120#define CIRRUS_ROP_NOP 0x06
121#define CIRRUS_ROP_SRC_AND_NOTDST 0x09
122#define CIRRUS_ROP_NOTDST 0x0b
123#define CIRRUS_ROP_SRC 0x0d
124#define CIRRUS_ROP_1 0x0e
125#define CIRRUS_ROP_NOTSRC_AND_DST 0x50
126#define CIRRUS_ROP_SRC_XOR_DST 0x59
127#define CIRRUS_ROP_SRC_OR_DST 0x6d
128#define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
129#define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
130#define CIRRUS_ROP_SRC_OR_NOTDST 0xad
131#define CIRRUS_ROP_NOTSRC 0xd0
132#define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
133#define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
134
a5082316
FB		 135#define CIRRUS_ROP_NOP_INDEX 2
136#define CIRRUS_ROP_SRC_INDEX 5
137
a21ae81d 138// control 0x33
a5082316 139#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
4c8732d7 140#define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
a5082316 141#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
a21ae81d 142
e6e5ad80
FB		 143// memory-mapped IO
144#define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
145#define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
146#define CIRRUS_MMIO_BLTWIDTH 0x08 // word
147#define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
148#define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
149#define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
150#define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
151#define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
152#define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
153#define CIRRUS_MMIO_BLTMODE 0x18 // byte
154#define CIRRUS_MMIO_BLTROP 0x1a // byte
155#define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
156#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
157#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
158#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
159#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
160#define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
161#define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
162#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
163#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
164#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
165#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
166#define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
167#define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
168#define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
169#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
170#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
171#define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
172#define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
173
e6e5ad80
FB		 174// PCI 0x04: command(word), 0x06(word): status
175#define PCI_COMMAND_IOACCESS 0x0001
176#define PCI_COMMAND_MEMACCESS 0x0002
177#define PCI_COMMAND_BUSMASTER 0x0004
178#define PCI_COMMAND_SPECIALCYCLE 0x0008
179#define PCI_COMMAND_MEMWRITEINVALID 0x0010
180#define PCI_COMMAND_PALETTESNOOPING 0x0020
181#define PCI_COMMAND_PARITYDETECTION 0x0040
182#define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
183#define PCI_COMMAND_SERR 0x0100
184#define PCI_COMMAND_BACKTOBACKTRANS 0x0200
185// PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
186#define PCI_CLASS_BASE_DISPLAY 0x03
187// PCI 0x08, 0x00ff0000
188#define PCI_CLASS_SUB_VGA 0x00
189// PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
e6e5ad80
FB		 190// 0x10-0x3f (headertype 00h)
191// PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
192// 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
193#define PCI_MAP_MEM 0x0
194#define PCI_MAP_IO 0x1
195#define PCI_MAP_MEM_ADDR_MASK (~0xf)
196#define PCI_MAP_IO_ADDR_MASK (~0x3)
197#define PCI_MAP_MEMFLAGS_32BIT 0x0
198#define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
199#define PCI_MAP_MEMFLAGS_64BIT 0x4
200#define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
201// PCI 0x28: cardbus CIS pointer
202// PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
203// PCI 0x30: expansion ROM base address
204#define PCI_ROMBIOS_ENABLED 0x1
205// PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
206// PCI 0x38: reserved
207// PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
208
a21ae81d 209#define CIRRUS_PNPMMIO_SIZE 0x1000
e6e5ad80 210
b2b183c2
AL		 211#define ABS(a) ((signed)(a) > 0 ? a : -a)
212
b2eb849d
AJ		 213#define BLTUNSAFE(s) \
214 ( \
215 ( /* check dst is within bounds */ \
b2b183c2 216 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
b2eb849d 217 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
4e12cd94 218 (s)->vga.vram_size \
b2eb849d
AJ		 219 ) || \
220 ( /* check src is within bounds */ \
b2b183c2 221 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
b2eb849d 222 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
4e12cd94 223 (s)->vga.vram_size \
b2eb849d
AJ		 224 ) \
225 )
226
a5082316
FB		 227struct CirrusVGAState;
228typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
229 uint8_t * dst, const uint8_t * src,
e6e5ad80
FB		 230 int dstpitch, int srcpitch,
231 int bltwidth, int bltheight);
a5082316
FB		 232typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
233 uint8_t *dst, int dst_pitch, int width, int height);
e6e5ad80
FB		 234
235typedef struct CirrusVGAState {
4e12cd94 236 VGACommonState vga;
e6e5ad80
FB		 237
238 int cirrus_linear_io_addr;
a5082316 239 int cirrus_linear_bitblt_io_addr;
e6e5ad80
FB		 240 int cirrus_mmio_io_addr;
241 uint32_t cirrus_addr_mask;
78e127ef 242 uint32_t linear_mmio_mask;
e6e5ad80
FB		 243 uint8_t cirrus_shadow_gr0;
244 uint8_t cirrus_shadow_gr1;
245 uint8_t cirrus_hidden_dac_lockindex;
246 uint8_t cirrus_hidden_dac_data;
247 uint32_t cirrus_bank_base[2];
248 uint32_t cirrus_bank_limit[2];
249 uint8_t cirrus_hidden_palette[48];
a5082316
FB		 250 uint32_t hw_cursor_x;
251 uint32_t hw_cursor_y;
e6e5ad80
FB		 252 int cirrus_blt_pixelwidth;
253 int cirrus_blt_width;
254 int cirrus_blt_height;
255 int cirrus_blt_dstpitch;
256 int cirrus_blt_srcpitch;
a5082316
FB		 257 uint32_t cirrus_blt_fgcol;
258 uint32_t cirrus_blt_bgcol;
e6e5ad80
FB		 259 uint32_t cirrus_blt_dstaddr;
260 uint32_t cirrus_blt_srcaddr;
261 uint8_t cirrus_blt_mode;
a5082316 262 uint8_t cirrus_blt_modeext;
e6e5ad80 263 cirrus_bitblt_rop_t cirrus_rop;
a5082316 264#define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
e6e5ad80
FB		 265 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
266 uint8_t *cirrus_srcptr;
267 uint8_t *cirrus_srcptr_end;
268 uint32_t cirrus_srccounter;
a5082316
FB		 269 /* hwcursor display state */
270 int last_hw_cursor_size;
271 int last_hw_cursor_x;
272 int last_hw_cursor_y;
273 int last_hw_cursor_y_start;
274 int last_hw_cursor_y_end;
78e127ef 275 int real_vram_size; /* XXX: suppress that */
4abc796d
BS		 276 int device_id;
277 int bustype;
e6e5ad80
FB		 278} CirrusVGAState;
279
280typedef struct PCICirrusVGAState {
281 PCIDevice dev;
282 CirrusVGAState cirrus_vga;
283} PCICirrusVGAState;
284
a5082316 285static uint8_t rop_to_index[256];
3b46e624 286
e6e5ad80
FB		 287/***************************************
288 *
289 * prototypes.
290 *
291 ***************************************/
292
293
8926b517
FB		 294static void cirrus_bitblt_reset(CirrusVGAState *s);
295static void cirrus_update_memory_access(CirrusVGAState *s);
e6e5ad80
FB		 296
297/***************************************
298 *
299 * raster operations
300 *
301 ***************************************/
302
a5082316
FB		 303static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
304 uint8_t *dst,const uint8_t *src,
305 int dstpitch,int srcpitch,
306 int bltwidth,int bltheight)
307{
e6e5ad80
FB		 308}
309
a5082316
FB		 310static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
311 uint8_t *dst,
312 int dstpitch, int bltwidth,int bltheight)
e6e5ad80 313{
a5082316 314}
e6e5ad80 315
a5082316
FB		 316#define ROP_NAME 0
317#define ROP_OP(d, s) d = 0
318#include "cirrus_vga_rop.h"
e6e5ad80 319
a5082316
FB		 320#define ROP_NAME src_and_dst
321#define ROP_OP(d, s) d = (s) & (d)
322#include "cirrus_vga_rop.h"
e6e5ad80 323
a5082316
FB		 324#define ROP_NAME src_and_notdst
325#define ROP_OP(d, s) d = (s) & (~(d))
326#include "cirrus_vga_rop.h"
e6e5ad80 327
a5082316
FB		 328#define ROP_NAME notdst
329#define ROP_OP(d, s) d = ~(d)
330#include "cirrus_vga_rop.h"
e6e5ad80 331
a5082316
FB		 332#define ROP_NAME src
333#define ROP_OP(d, s) d = s
334#include "cirrus_vga_rop.h"
e6e5ad80 335
a5082316 336#define ROP_NAME 1
4c8732d7 337#define ROP_OP(d, s) d = ~0
a5082316
FB		 338#include "cirrus_vga_rop.h"
339
340#define ROP_NAME notsrc_and_dst
341#define ROP_OP(d, s) d = (~(s)) & (d)
342#include "cirrus_vga_rop.h"
343
344#define ROP_NAME src_xor_dst
345#define ROP_OP(d, s) d = (s) ^ (d)
346#include "cirrus_vga_rop.h"
347
348#define ROP_NAME src_or_dst
349#define ROP_OP(d, s) d = (s) | (d)
350#include "cirrus_vga_rop.h"
351
352#define ROP_NAME notsrc_or_notdst
353#define ROP_OP(d, s) d = (~(s)) | (~(d))
354#include "cirrus_vga_rop.h"
355
356#define ROP_NAME src_notxor_dst
357#define ROP_OP(d, s) d = ~((s) ^ (d))
358#include "cirrus_vga_rop.h"
e6e5ad80 359
a5082316
FB		 360#define ROP_NAME src_or_notdst
361#define ROP_OP(d, s) d = (s) | (~(d))
362#include "cirrus_vga_rop.h"
363
364#define ROP_NAME notsrc
365#define ROP_OP(d, s) d = (~(s))
366#include "cirrus_vga_rop.h"
367
368#define ROP_NAME notsrc_or_dst
369#define ROP_OP(d, s) d = (~(s)) | (d)
370#include "cirrus_vga_rop.h"
371
372#define ROP_NAME notsrc_and_notdst
373#define ROP_OP(d, s) d = (~(s)) & (~(d))
374#include "cirrus_vga_rop.h"
375
376static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
377 cirrus_bitblt_rop_fwd_0,
378 cirrus_bitblt_rop_fwd_src_and_dst,
379 cirrus_bitblt_rop_nop,
380 cirrus_bitblt_rop_fwd_src_and_notdst,
381 cirrus_bitblt_rop_fwd_notdst,
382 cirrus_bitblt_rop_fwd_src,
383 cirrus_bitblt_rop_fwd_1,
384 cirrus_bitblt_rop_fwd_notsrc_and_dst,
385 cirrus_bitblt_rop_fwd_src_xor_dst,
386 cirrus_bitblt_rop_fwd_src_or_dst,
387 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
388 cirrus_bitblt_rop_fwd_src_notxor_dst,
389 cirrus_bitblt_rop_fwd_src_or_notdst,
390 cirrus_bitblt_rop_fwd_notsrc,
391 cirrus_bitblt_rop_fwd_notsrc_or_dst,
392 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
393};
394
395static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
396 cirrus_bitblt_rop_bkwd_0,
397 cirrus_bitblt_rop_bkwd_src_and_dst,
398 cirrus_bitblt_rop_nop,
399 cirrus_bitblt_rop_bkwd_src_and_notdst,
400 cirrus_bitblt_rop_bkwd_notdst,
401 cirrus_bitblt_rop_bkwd_src,
402 cirrus_bitblt_rop_bkwd_1,
403 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
404 cirrus_bitblt_rop_bkwd_src_xor_dst,
405 cirrus_bitblt_rop_bkwd_src_or_dst,
406 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
407 cirrus_bitblt_rop_bkwd_src_notxor_dst,
408 cirrus_bitblt_rop_bkwd_src_or_notdst,
409 cirrus_bitblt_rop_bkwd_notsrc,
410 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
411 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
412};
96cf2df8
TS		 413
414#define TRANSP_ROP(name) {\
415 name ## _8,\
416 name ## _16,\
417 }
418#define TRANSP_NOP(func) {\
419 func,\
420 func,\
421 }
422
423static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
424 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
425 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
426 TRANSP_NOP(cirrus_bitblt_rop_nop),
427 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
428 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
429 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
430 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
431 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
432 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
433 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
434 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
435 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
436 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
437 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
438 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
439 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
440};
441
442static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
443 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
444 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
445 TRANSP_NOP(cirrus_bitblt_rop_nop),
446 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
447 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
448 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
449 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
450 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
451 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
452 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
453 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
454 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
455 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
456 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
457 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
458 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
459};
460
a5082316
FB		 461#define ROP2(name) {\
462 name ## _8,\
463 name ## _16,\
464 name ## _24,\
465 name ## _32,\
466 }
467
468#define ROP_NOP2(func) {\
469 func,\
470 func,\
471 func,\
472 func,\
473 }
474
e69390ce
FB		 475static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
476 ROP2(cirrus_patternfill_0),
477 ROP2(cirrus_patternfill_src_and_dst),
478 ROP_NOP2(cirrus_bitblt_rop_nop),
479 ROP2(cirrus_patternfill_src_and_notdst),
480 ROP2(cirrus_patternfill_notdst),
481 ROP2(cirrus_patternfill_src),
482 ROP2(cirrus_patternfill_1),
483 ROP2(cirrus_patternfill_notsrc_and_dst),
484 ROP2(cirrus_patternfill_src_xor_dst),
485 ROP2(cirrus_patternfill_src_or_dst),
486 ROP2(cirrus_patternfill_notsrc_or_notdst),
487 ROP2(cirrus_patternfill_src_notxor_dst),
488 ROP2(cirrus_patternfill_src_or_notdst),
489 ROP2(cirrus_patternfill_notsrc),
490 ROP2(cirrus_patternfill_notsrc_or_dst),
491 ROP2(cirrus_patternfill_notsrc_and_notdst),
492};
493
a5082316
FB		 494static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
495 ROP2(cirrus_colorexpand_transp_0),
496 ROP2(cirrus_colorexpand_transp_src_and_dst),
497 ROP_NOP2(cirrus_bitblt_rop_nop),
498 ROP2(cirrus_colorexpand_transp_src_and_notdst),
499 ROP2(cirrus_colorexpand_transp_notdst),
500 ROP2(cirrus_colorexpand_transp_src),
501 ROP2(cirrus_colorexpand_transp_1),
502 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
503 ROP2(cirrus_colorexpand_transp_src_xor_dst),
504 ROP2(cirrus_colorexpand_transp_src_or_dst),
505 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
506 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
507 ROP2(cirrus_colorexpand_transp_src_or_notdst),
508 ROP2(cirrus_colorexpand_transp_notsrc),
509 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
510 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
511};
512
513static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
514 ROP2(cirrus_colorexpand_0),
515 ROP2(cirrus_colorexpand_src_and_dst),
516 ROP_NOP2(cirrus_bitblt_rop_nop),
517 ROP2(cirrus_colorexpand_src_and_notdst),
518 ROP2(cirrus_colorexpand_notdst),
519 ROP2(cirrus_colorexpand_src),
520 ROP2(cirrus_colorexpand_1),
521 ROP2(cirrus_colorexpand_notsrc_and_dst),
522 ROP2(cirrus_colorexpand_src_xor_dst),
523 ROP2(cirrus_colorexpand_src_or_dst),
524 ROP2(cirrus_colorexpand_notsrc_or_notdst),
525 ROP2(cirrus_colorexpand_src_notxor_dst),
526 ROP2(cirrus_colorexpand_src_or_notdst),
527 ROP2(cirrus_colorexpand_notsrc),
528 ROP2(cirrus_colorexpand_notsrc_or_dst),
529 ROP2(cirrus_colorexpand_notsrc_and_notdst),
530};
531
b30d4608
FB		 532static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
533 ROP2(cirrus_colorexpand_pattern_transp_0),
534 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
535 ROP_NOP2(cirrus_bitblt_rop_nop),
536 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
537 ROP2(cirrus_colorexpand_pattern_transp_notdst),
538 ROP2(cirrus_colorexpand_pattern_transp_src),
539 ROP2(cirrus_colorexpand_pattern_transp_1),
540 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
541 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
542 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
543 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
544 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
545 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
546 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
547 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
548 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
549};
550
551static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
552 ROP2(cirrus_colorexpand_pattern_0),
553 ROP2(cirrus_colorexpand_pattern_src_and_dst),
554 ROP_NOP2(cirrus_bitblt_rop_nop),
555 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
556 ROP2(cirrus_colorexpand_pattern_notdst),
557 ROP2(cirrus_colorexpand_pattern_src),
558 ROP2(cirrus_colorexpand_pattern_1),
559 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
560 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
561 ROP2(cirrus_colorexpand_pattern_src_or_dst),
562 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
563 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
564 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
565 ROP2(cirrus_colorexpand_pattern_notsrc),
566 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
567 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
568};
569
a5082316
FB		 570static const cirrus_fill_t cirrus_fill[16][4] = {
571 ROP2(cirrus_fill_0),
572 ROP2(cirrus_fill_src_and_dst),
573 ROP_NOP2(cirrus_bitblt_fill_nop),
574 ROP2(cirrus_fill_src_and_notdst),
575 ROP2(cirrus_fill_notdst),
576 ROP2(cirrus_fill_src),
577 ROP2(cirrus_fill_1),
578 ROP2(cirrus_fill_notsrc_and_dst),
579 ROP2(cirrus_fill_src_xor_dst),
580 ROP2(cirrus_fill_src_or_dst),
581 ROP2(cirrus_fill_notsrc_or_notdst),
582 ROP2(cirrus_fill_src_notxor_dst),
583 ROP2(cirrus_fill_src_or_notdst),
584 ROP2(cirrus_fill_notsrc),
585 ROP2(cirrus_fill_notsrc_or_dst),
586 ROP2(cirrus_fill_notsrc_and_notdst),
587};
588
589static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
e6e5ad80 590{
a5082316
FB		 591 unsigned int color;
592 switch (s->cirrus_blt_pixelwidth) {
593 case 1:
594 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
595 break;
596 case 2:
4e12cd94 597 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
a5082316
FB		 598 s->cirrus_blt_fgcol = le16_to_cpu(color);
599 break;
600 case 3:
5fafdf24 601 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
4e12cd94 602 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
a5082316
FB		 603 break;
604 default:
605 case 4:
4e12cd94
AK		 606 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
607 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
a5082316
FB		 608 s->cirrus_blt_fgcol = le32_to_cpu(color);
609 break;
e6e5ad80
FB		 610 }
611}
612
a5082316 613static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
e6e5ad80 614{
a5082316 615 unsigned int color;
e6e5ad80
FB		 616 switch (s->cirrus_blt_pixelwidth) {
617 case 1:
a5082316
FB		 618 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
619 break;
e6e5ad80 620 case 2:
4e12cd94 621 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
a5082316
FB		 622 s->cirrus_blt_bgcol = le16_to_cpu(color);
623 break;
e6e5ad80 624 case 3:
5fafdf24 625 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
4e12cd94 626 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
a5082316 627 break;
e6e5ad80 628 default:
a5082316 629 case 4:
4e12cd94
AK		 630 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
631 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
a5082316
FB		 632 s->cirrus_blt_bgcol = le32_to_cpu(color);
633 break;
e6e5ad80
FB		 634 }
635}
636
637static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
638 int off_pitch, int bytesperline,
639 int lines)
640{
641 int y;
642 int off_cur;
643 int off_cur_end;
644
645 for (y = 0; y < lines; y++) {
646 off_cur = off_begin;
b2eb849d 647 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
e6e5ad80
FB		 648 off_cur &= TARGET_PAGE_MASK;
649 while (off_cur < off_cur_end) {
4e12cd94 650 cpu_physical_memory_set_dirty(s->vga.vram_offset + off_cur);
e6e5ad80
FB		 651 off_cur += TARGET_PAGE_SIZE;
652 }
653 off_begin += off_pitch;
654 }
655}
656
e6e5ad80
FB		 657static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
658 const uint8_t * src)
659{
e6e5ad80 660 uint8_t *dst;
e6e5ad80 661
4e12cd94 662 dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
b2eb849d
AJ		 663
664 if (BLTUNSAFE(s))
665 return 0;
666
e69390ce 667 (*s->cirrus_rop) (s, dst, src,
5fafdf24 668 s->cirrus_blt_dstpitch, 0,
e69390ce 669 s->cirrus_blt_width, s->cirrus_blt_height);
e6e5ad80 670 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
e69390ce
FB		 671 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
672 s->cirrus_blt_height);
e6e5ad80
FB		 673 return 1;
674}
675
a21ae81d
FB		 676/* fill */
677
a5082316 678static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
a21ae81d 679{
a5082316 680 cirrus_fill_t rop_func;
a21ae81d 681
b2eb849d
AJ		 682 if (BLTUNSAFE(s))
683 return 0;
a5082316 684 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
4e12cd94 685 rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
a5082316
FB		 686 s->cirrus_blt_dstpitch,
687 s->cirrus_blt_width, s->cirrus_blt_height);
a21ae81d
FB		 688 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
689 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
690 s->cirrus_blt_height);
691 cirrus_bitblt_reset(s);
692 return 1;
693}
694
e6e5ad80
FB		 695/***************************************
696 *
697 * bitblt (video-to-video)
698 *
699 ***************************************/
700
701static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
702{
703 return cirrus_bitblt_common_patterncopy(s,
4e12cd94 704 s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
b2eb849d 705 s->cirrus_addr_mask));
e6e5ad80
FB		 706}
707
24236869 708static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
e6e5ad80 709{
24236869
FB		 710 int sx, sy;
711 int dx, dy;
712 int width, height;
713 int depth;
714 int notify = 0;
715
4e12cd94
AK		 716 depth = s->vga.get_bpp(&s->vga) / 8;
717 s->vga.get_resolution(&s->vga, &width, &height);
24236869
FB		 718
719 /* extra x, y */
d85d0d38
AL		 720 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
721 sy = (src / ABS(s->cirrus_blt_srcpitch));
722 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
723 dy = (dst / ABS(s->cirrus_blt_dstpitch));
24236869
FB		 724
725 /* normalize width */
726 w /= depth;
727
728 /* if we're doing a backward copy, we have to adjust
729 our x/y to be the upper left corner (instead of the lower
730 right corner) */
731 if (s->cirrus_blt_dstpitch < 0) {
732 sx -= (s->cirrus_blt_width / depth) - 1;
733 dx -= (s->cirrus_blt_width / depth) - 1;
734 sy -= s->cirrus_blt_height - 1;
735 dy -= s->cirrus_blt_height - 1;
736 }
737
738 /* are we in the visible portion of memory? */
739 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
740 (sx + w) <= width && (sy + h) <= height &&
741 (dx + w) <= width && (dy + h) <= height) {
742 notify = 1;
743 }
744
745 /* make to sure only copy if it's a plain copy ROP */
746 if (*s->cirrus_rop != cirrus_bitblt_rop_fwd_src &&
747 *s->cirrus_rop != cirrus_bitblt_rop_bkwd_src)
748 notify = 0;
749
750 /* we have to flush all pending changes so that the copy
751 is generated at the appropriate moment in time */
752 if (notify)
753 vga_hw_update();
754
4e12cd94 755 (*s->cirrus_rop) (s, s->vga.vram_ptr +
b2eb849d 756 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
4e12cd94 757 s->vga.vram_ptr +
b2eb849d 758 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
e6e5ad80
FB		 759 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
760 s->cirrus_blt_width, s->cirrus_blt_height);
24236869
FB		 761
762 if (notify)
4e12cd94 763 qemu_console_copy(s->vga.ds,
38334f76
AZ		 764 sx, sy, dx, dy,
765 s->cirrus_blt_width / depth,
766 s->cirrus_blt_height);
24236869
FB		 767
768 /* we don't have to notify the display that this portion has
38334f76 769 changed since qemu_console_copy implies this */
24236869 770
31c05501
AL		 771 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
772 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
773 s->cirrus_blt_height);
24236869
FB		 774}
775
776static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
777{
65d35a09
AJ		 778 if (BLTUNSAFE(s))
779 return 0;
780
4e12cd94
AK		 781 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
782 s->cirrus_blt_srcaddr - s->vga.start_addr,
7d957bd8 783 s->cirrus_blt_width, s->cirrus_blt_height);
24236869 784
e6e5ad80
FB		 785 return 1;
786}
787
788/***************************************
789 *
790 * bitblt (cpu-to-video)
791 *
792 ***************************************/
793
e6e5ad80
FB		 794static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
795{
796 int copy_count;
a5082316 797 uint8_t *end_ptr;
3b46e624 798
e6e5ad80 799 if (s->cirrus_srccounter > 0) {
a5082316
FB		 800 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
801 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
802 the_end:
803 s->cirrus_srccounter = 0;
804 cirrus_bitblt_reset(s);
805 } else {
806 /* at least one scan line */
807 do {
4e12cd94 808 (*s->cirrus_rop)(s, s->vga.vram_ptr +
b2eb849d
AJ		 809 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
810 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
a5082316
FB		 811 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
812 s->cirrus_blt_width, 1);
813 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
814 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
815 if (s->cirrus_srccounter <= 0)
816 goto the_end;
817 /* more bytes than needed can be transfered because of
818 word alignment, so we keep them for the next line */
819 /* XXX: keep alignment to speed up transfer */
820 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
821 copy_count = s->cirrus_srcptr_end - end_ptr;
822 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
823 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
824 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
825 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
826 }
e6e5ad80
FB		 827 }
828}
829
830/***************************************
831 *
832 * bitblt wrapper
833 *
834 ***************************************/
835
836static void cirrus_bitblt_reset(CirrusVGAState * s)
837{
f8b237af
AL		 838 int need_update;
839
4e12cd94 840 s->vga.gr[0x31] &=
e6e5ad80 841 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
f8b237af
AL		 842 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
843 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
e6e5ad80
FB		 844 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
845 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
846 s->cirrus_srccounter = 0;
f8b237af
AL		 847 if (!need_update)
848 return;
8926b517 849 cirrus_update_memory_access(s);
e6e5ad80
FB		 850}
851
852static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
853{
a5082316
FB		 854 int w;
855
e6e5ad80
FB		 856 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
857 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
858 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
859
860 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
861 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 862 s->cirrus_blt_srcpitch = 8;
e6e5ad80 863 } else {
b30d4608 864 /* XXX: check for 24 bpp */
a5082316 865 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
e6e5ad80 866 }
a5082316 867 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
e6e5ad80
FB		 868 } else {
869 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 870 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
5fafdf24 871 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
a5082316
FB		 872 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
873 else
874 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
e6e5ad80 875 } else {
c9c0eae8
FB		 876 /* always align input size to 32 bits */
877 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
e6e5ad80 878 }
a5082316 879 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
e6e5ad80 880 }
a5082316
FB		 881 s->cirrus_srcptr = s->cirrus_bltbuf;
882 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
8926b517 883 cirrus_update_memory_access(s);
e6e5ad80
FB		 884 return 1;
885}
886
887static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
888{
889 /* XXX */
a5082316 890#ifdef DEBUG_BITBLT
e6e5ad80
FB		 891 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
892#endif
893 return 0;
894}
895
896static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
897{
898 int ret;
899
900 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
901 ret = cirrus_bitblt_videotovideo_patterncopy(s);
902 } else {
903 ret = cirrus_bitblt_videotovideo_copy(s);
904 }
e6e5ad80
FB		 905 if (ret)
906 cirrus_bitblt_reset(s);
907 return ret;
908}
909
910static void cirrus_bitblt_start(CirrusVGAState * s)
911{
912 uint8_t blt_rop;
913
4e12cd94 914 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
a5082316 915
4e12cd94
AK		 916 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
917 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
918 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
919 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
e6e5ad80 920 s->cirrus_blt_dstaddr =
4e12cd94 921 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
e6e5ad80 922 s->cirrus_blt_srcaddr =
4e12cd94
AK		 923 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
924 s->cirrus_blt_mode = s->vga.gr[0x30];
925 s->cirrus_blt_modeext = s->vga.gr[0x33];
926 blt_rop = s->vga.gr[0x32];
e6e5ad80 927
a21ae81d 928#ifdef DEBUG_BITBLT
0b74ed78 929 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
5fafdf24 930 blt_rop,
a21ae81d 931 s->cirrus_blt_mode,
a5082316 932 s->cirrus_blt_modeext,
a21ae81d
FB		 933 s->cirrus_blt_width,
934 s->cirrus_blt_height,
935 s->cirrus_blt_dstpitch,
936 s->cirrus_blt_srcpitch,
937 s->cirrus_blt_dstaddr,
a5082316 938 s->cirrus_blt_srcaddr,
4e12cd94 939 s->vga.gr[0x2f]);
a21ae81d
FB		 940#endif
941
e6e5ad80
FB		 942 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
943 case CIRRUS_BLTMODE_PIXELWIDTH8:
944 s->cirrus_blt_pixelwidth = 1;
945 break;
946 case CIRRUS_BLTMODE_PIXELWIDTH16:
947 s->cirrus_blt_pixelwidth = 2;
948 break;
949 case CIRRUS_BLTMODE_PIXELWIDTH24:
950 s->cirrus_blt_pixelwidth = 3;
951 break;
952 case CIRRUS_BLTMODE_PIXELWIDTH32:
953 s->cirrus_blt_pixelwidth = 4;
954 break;
955 default:
a5082316 956#ifdef DEBUG_BITBLT
e6e5ad80
FB		 957 printf("cirrus: bitblt - pixel width is unknown\n");
958#endif
959 goto bitblt_ignore;
960 }
961 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
962
963 if ((s->
964 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
965 CIRRUS_BLTMODE_MEMSYSDEST))
966 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
a5082316 967#ifdef DEBUG_BITBLT
e6e5ad80
FB		 968 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
969#endif
970 goto bitblt_ignore;
971 }
972
a5082316 973 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
5fafdf24 974 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
a21ae81d 975 CIRRUS_BLTMODE_TRANSPARENTCOMP |
5fafdf24
TS		 976 CIRRUS_BLTMODE_PATTERNCOPY |
977 CIRRUS_BLTMODE_COLOREXPAND)) ==
a21ae81d 978 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
a5082316
FB		 979 cirrus_bitblt_fgcol(s);
980 cirrus_bitblt_solidfill(s, blt_rop);
e6e5ad80 981 } else {
5fafdf24
TS		 982 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
983 CIRRUS_BLTMODE_PATTERNCOPY)) ==
a5082316
FB		 984 CIRRUS_BLTMODE_COLOREXPAND) {
985
986 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
b30d4608 987 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
4c8732d7 988 cirrus_bitblt_bgcol(s);
b30d4608 989 else
4c8732d7 990 cirrus_bitblt_fgcol(s);
b30d4608 991 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
a5082316
FB		 992 } else {
993 cirrus_bitblt_fgcol(s);
994 cirrus_bitblt_bgcol(s);
995 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
996 }
e69390ce 997 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
b30d4608
FB		 998 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
999 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1000 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1001 cirrus_bitblt_bgcol(s);
1002 else
1003 cirrus_bitblt_fgcol(s);
1004 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1005 } else {
1006 cirrus_bitblt_fgcol(s);
1007 cirrus_bitblt_bgcol(s);
1008 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1009 }
1010 } else {
1011 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1012 }
a21ae81d 1013 } else {
96cf2df8
TS		 1014 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1015 if (s->cirrus_blt_pixelwidth > 2) {
1016 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1017 goto bitblt_ignore;
1018 }
1019 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1020 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1021 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1022 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1023 } else {
1024 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1025 }
1026 } else {
1027 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1028 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1029 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1030 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1031 } else {
1032 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1033 }
1034 }
1035 }
a21ae81d
FB		 1036 // setup bitblt engine.
1037 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1038 if (!cirrus_bitblt_cputovideo(s))
1039 goto bitblt_ignore;
1040 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1041 if (!cirrus_bitblt_videotocpu(s))
1042 goto bitblt_ignore;
1043 } else {
1044 if (!cirrus_bitblt_videotovideo(s))
1045 goto bitblt_ignore;
1046 }
e6e5ad80 1047 }
e6e5ad80
FB		 1048 return;
1049 bitblt_ignore:;
1050 cirrus_bitblt_reset(s);
1051}
1052
1053static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1054{
1055 unsigned old_value;
1056
4e12cd94
AK		 1057 old_value = s->vga.gr[0x31];
1058 s->vga.gr[0x31] = reg_value;
e6e5ad80
FB		 1059
1060 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1061 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1062 cirrus_bitblt_reset(s);
1063 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1064 ((reg_value & CIRRUS_BLT_START) != 0)) {
e6e5ad80
FB		 1065 cirrus_bitblt_start(s);
1066 }
1067}
1068
1069
1070/***************************************
1071 *
1072 * basic parameters
1073 *
1074 ***************************************/
1075
a4a2f59c 1076static void cirrus_get_offsets(VGACommonState *s1,
83acc96b
FB		 1077 uint32_t *pline_offset,
1078 uint32_t *pstart_addr,
1079 uint32_t *pline_compare)
e6e5ad80 1080{
4e12cd94 1081 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
83acc96b 1082 uint32_t start_addr, line_offset, line_compare;
e6e5ad80 1083
4e12cd94
AK		 1084 line_offset = s->vga.cr[0x13]
1085 | ((s->vga.cr[0x1b] & 0x10) << 4);
e6e5ad80
FB		 1086 line_offset <<= 3;
1087 *pline_offset = line_offset;
1088
4e12cd94
AK		 1089 start_addr = (s->vga.cr[0x0c] << 8)
1090 | s->vga.cr[0x0d]
1091 | ((s->vga.cr[0x1b] & 0x01) << 16)
1092 | ((s->vga.cr[0x1b] & 0x0c) << 15)
1093 | ((s->vga.cr[0x1d] & 0x80) << 12);
e6e5ad80 1094 *pstart_addr = start_addr;
83acc96b 1095
4e12cd94
AK		 1096 line_compare = s->vga.cr[0x18] |
1097 ((s->vga.cr[0x07] & 0x10) << 4) |
1098 ((s->vga.cr[0x09] & 0x40) << 3);
83acc96b 1099 *pline_compare = line_compare;
e6e5ad80
FB		 1100}
1101
1102static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1103{
1104 uint32_t ret = 16;
1105
1106 switch (s->cirrus_hidden_dac_data & 0xf) {
1107 case 0:
1108 ret = 15;
1109 break; /* Sierra HiColor */
1110 case 1:
1111 ret = 16;
1112 break; /* XGA HiColor */
1113 default:
1114#ifdef DEBUG_CIRRUS
1115 printf("cirrus: invalid DAC value %x in 16bpp\n",
1116 (s->cirrus_hidden_dac_data & 0xf));
1117#endif
1118 ret = 15; /* XXX */
1119 break;
1120 }
1121 return ret;
1122}
1123
a4a2f59c 1124static int cirrus_get_bpp(VGACommonState *s1)
e6e5ad80 1125{
4e12cd94 1126 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
e6e5ad80
FB		 1127 uint32_t ret = 8;
1128
4e12cd94 1129 if ((s->vga.sr[0x07] & 0x01) != 0) {
e6e5ad80 1130 /* Cirrus SVGA */
4e12cd94 1131 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
e6e5ad80
FB		 1132 case CIRRUS_SR7_BPP_8:
1133 ret = 8;
1134 break;
1135 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1136 ret = cirrus_get_bpp16_depth(s);
1137 break;
1138 case CIRRUS_SR7_BPP_24:
1139 ret = 24;
1140 break;
1141 case CIRRUS_SR7_BPP_16:
1142 ret = cirrus_get_bpp16_depth(s);
1143 break;
1144 case CIRRUS_SR7_BPP_32:
1145 ret = 32;
1146 break;
1147 default:
1148#ifdef DEBUG_CIRRUS
4e12cd94 1149 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
e6e5ad80
FB		 1150#endif
1151 ret = 8;
1152 break;
1153 }
1154 } else {
1155 /* VGA */
aeb3c85f 1156 ret = 0;
e6e5ad80
FB		 1157 }
1158
1159 return ret;
1160}
1161
a4a2f59c 1162static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
78e127ef
FB		 1163{
1164 int width, height;
3b46e624 1165
78e127ef 1166 width = (s->cr[0x01] + 1) * 8;
5fafdf24
TS		 1167 height = s->cr[0x12] |
1168 ((s->cr[0x07] & 0x02) << 7) |
78e127ef
FB		 1169 ((s->cr[0x07] & 0x40) << 3);
1170 height = (height + 1);
1171 /* interlace support */
1172 if (s->cr[0x1a] & 0x01)
1173 height = height * 2;
1174 *pwidth = width;
1175 *pheight = height;
1176}
1177
e6e5ad80
FB		 1178/***************************************
1179 *
1180 * bank memory
1181 *
1182 ***************************************/
1183
1184static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1185{
1186 unsigned offset;
1187 unsigned limit;
1188
4e12cd94
AK		 1189 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */
1190 offset = s->vga.gr[0x09 + bank_index];
e6e5ad80 1191 else /* single bank */
4e12cd94 1192 offset = s->vga.gr[0x09];
e6e5ad80 1193
4e12cd94 1194 if ((s->vga.gr[0x0b] & 0x20) != 0)
e6e5ad80
FB		 1195 offset <<= 14;
1196 else
1197 offset <<= 12;
1198
e3a4e4b6 1199 if (s->real_vram_size <= offset)
e6e5ad80
FB		 1200 limit = 0;
1201 else
e3a4e4b6 1202 limit = s->real_vram_size - offset;
e6e5ad80 1203
4e12cd94 1204 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
e6e5ad80
FB		 1205 if (limit > 0x8000) {
1206 offset += 0x8000;
1207 limit -= 0x8000;
1208 } else {
1209 limit = 0;
1210 }
1211 }
1212
1213 if (limit > 0) {
2bec46dc
AL		 1214 /* Thinking about changing bank base? First, drop the dirty bitmap information
1215 * on the current location, otherwise we lose this pointer forever */
4e12cd94 1216 if (s->vga.lfb_vram_mapped) {
c227f099 1217 target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
2bec46dc
AL		 1218 cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
1219 }
e6e5ad80
FB		 1220 s->cirrus_bank_base[bank_index] = offset;
1221 s->cirrus_bank_limit[bank_index] = limit;
1222 } else {
1223 s->cirrus_bank_base[bank_index] = 0;
1224 s->cirrus_bank_limit[bank_index] = 0;
1225 }
1226}
1227
1228/***************************************
1229 *
1230 * I/O access between 0x3c4-0x3c5
1231 *
1232 ***************************************/
1233
8a82c322 1234static int cirrus_vga_read_sr(CirrusVGAState * s)
e6e5ad80 1235{
8a82c322 1236 switch (s->vga.sr_index) {
e6e5ad80
FB		 1237 case 0x00: // Standard VGA
1238 case 0x01: // Standard VGA
1239 case 0x02: // Standard VGA
1240 case 0x03: // Standard VGA
1241 case 0x04: // Standard VGA
8a82c322 1242 return s->vga.sr[s->vga.sr_index];
e6e5ad80 1243 case 0x06: // Unlock Cirrus extensions
8a82c322 1244 return s->vga.sr[s->vga.sr_index];
e6e5ad80
FB		 1245 case 0x10:
1246 case 0x30:
1247 case 0x50:
1248 case 0x70: // Graphics Cursor X
1249 case 0x90:
1250 case 0xb0:
1251 case 0xd0:
1252 case 0xf0: // Graphics Cursor X
8a82c322 1253 return s->vga.sr[0x10];
e6e5ad80
FB		 1254 case 0x11:
1255 case 0x31:
1256 case 0x51:
1257 case 0x71: // Graphics Cursor Y
1258 case 0x91:
1259 case 0xb1:
1260 case 0xd1:
a5082316 1261 case 0xf1: // Graphics Cursor Y
8a82c322 1262 return s->vga.sr[0x11];
aeb3c85f
FB		 1263 case 0x05: // ???
1264 case 0x07: // Extended Sequencer Mode
1265 case 0x08: // EEPROM Control
1266 case 0x09: // Scratch Register 0
1267 case 0x0a: // Scratch Register 1
1268 case 0x0b: // VCLK 0
1269 case 0x0c: // VCLK 1
1270 case 0x0d: // VCLK 2
1271 case 0x0e: // VCLK 3
1272 case 0x0f: // DRAM Control
e6e5ad80
FB		 1273 case 0x12: // Graphics Cursor Attribute
1274 case 0x13: // Graphics Cursor Pattern Address
1275 case 0x14: // Scratch Register 2
1276 case 0x15: // Scratch Register 3
1277 case 0x16: // Performance Tuning Register
1278 case 0x17: // Configuration Readback and Extended Control
1279 case 0x18: // Signature Generator Control
1280 case 0x19: // Signal Generator Result
1281 case 0x1a: // Signal Generator Result
1282 case 0x1b: // VCLK 0 Denominator & Post
1283 case 0x1c: // VCLK 1 Denominator & Post
1284 case 0x1d: // VCLK 2 Denominator & Post
1285 case 0x1e: // VCLK 3 Denominator & Post
1286 case 0x1f: // BIOS Write Enable and MCLK select
1287#ifdef DEBUG_CIRRUS
8a82c322 1288 printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
e6e5ad80 1289#endif
8a82c322 1290 return s->vga.sr[s->vga.sr_index];
e6e5ad80
FB		 1291 default:
1292#ifdef DEBUG_CIRRUS
8a82c322 1293 printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
e6e5ad80 1294#endif
8a82c322 1295 return 0xff;
e6e5ad80
FB		 1296 break;
1297 }
e6e5ad80
FB		 1298}
1299
31c63201 1300static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
e6e5ad80 1301{
31c63201 1302 switch (s->vga.sr_index) {
e6e5ad80
FB		 1303 case 0x00: // Standard VGA
1304 case 0x01: // Standard VGA
1305 case 0x02: // Standard VGA
1306 case 0x03: // Standard VGA
1307 case 0x04: // Standard VGA
31c63201
JQ		 1308 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
1309 if (s->vga.sr_index == 1)
1310 s->vga.update_retrace_info(&s->vga);
1311 break;
e6e5ad80 1312 case 0x06: // Unlock Cirrus extensions
31c63201
JQ		 1313 val &= 0x17;
1314 if (val == 0x12) {
1315 s->vga.sr[s->vga.sr_index] = 0x12;
e6e5ad80 1316 } else {
31c63201 1317 s->vga.sr[s->vga.sr_index] = 0x0f;
e6e5ad80
FB		 1318 }
1319 break;
1320 case 0x10:
1321 case 0x30:
1322 case 0x50:
1323 case 0x70: // Graphics Cursor X
1324 case 0x90:
1325 case 0xb0:
1326 case 0xd0:
1327 case 0xf0: // Graphics Cursor X
31c63201
JQ		 1328 s->vga.sr[0x10] = val;
1329 s->hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1330 break;
1331 case 0x11:
1332 case 0x31:
1333 case 0x51:
1334 case 0x71: // Graphics Cursor Y
1335 case 0x91:
1336 case 0xb1:
1337 case 0xd1:
1338 case 0xf1: // Graphics Cursor Y
31c63201
JQ		 1339 s->vga.sr[0x11] = val;
1340 s->hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1341 break;
1342 case 0x07: // Extended Sequencer Mode
2bec46dc 1343 cirrus_update_memory_access(s);
e6e5ad80
FB		 1344 case 0x08: // EEPROM Control
1345 case 0x09: // Scratch Register 0
1346 case 0x0a: // Scratch Register 1
1347 case 0x0b: // VCLK 0
1348 case 0x0c: // VCLK 1
1349 case 0x0d: // VCLK 2
1350 case 0x0e: // VCLK 3
1351 case 0x0f: // DRAM Control
1352 case 0x12: // Graphics Cursor Attribute
1353 case 0x13: // Graphics Cursor Pattern Address
1354 case 0x14: // Scratch Register 2
1355 case 0x15: // Scratch Register 3
1356 case 0x16: // Performance Tuning Register
e6e5ad80
FB		 1357 case 0x18: // Signature Generator Control
1358 case 0x19: // Signature Generator Result
1359 case 0x1a: // Signature Generator Result
1360 case 0x1b: // VCLK 0 Denominator & Post
1361 case 0x1c: // VCLK 1 Denominator & Post
1362 case 0x1d: // VCLK 2 Denominator & Post
1363 case 0x1e: // VCLK 3 Denominator & Post
1364 case 0x1f: // BIOS Write Enable and MCLK select
31c63201 1365 s->vga.sr[s->vga.sr_index] = val;
e6e5ad80
FB		 1366#ifdef DEBUG_CIRRUS
1367 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
31c63201 1368 s->vga.sr_index, val);
e6e5ad80
FB		 1369#endif
1370 break;
8926b517 1371 case 0x17: // Configuration Readback and Extended Control
31c63201
JQ		 1372 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
1373 | (val & 0xc7);
8926b517
FB		 1374 cirrus_update_memory_access(s);
1375 break;
e6e5ad80
FB		 1376 default:
1377#ifdef DEBUG_CIRRUS
31c63201
JQ		 1378 printf("cirrus: outport sr_index %02x, sr_value %02x\n",
1379 s->vga.sr_index, val);
e6e5ad80
FB		 1380#endif
1381 break;
1382 }
e6e5ad80
FB		 1383}
1384
1385/***************************************
1386 *
1387 * I/O access at 0x3c6
1388 *
1389 ***************************************/
1390
957c9db5 1391static int cirrus_read_hidden_dac(CirrusVGAState * s)
e6e5ad80 1392{
a21ae81d 1393 if (++s->cirrus_hidden_dac_lockindex == 5) {
957c9db5
JQ		 1394 s->cirrus_hidden_dac_lockindex = 0;
1395 return s->cirrus_hidden_dac_data;
e6e5ad80 1396 }
957c9db5 1397 return 0xff;
e6e5ad80
FB		 1398}
1399
1400static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1401{
1402 if (s->cirrus_hidden_dac_lockindex == 4) {
1403 s->cirrus_hidden_dac_data = reg_value;
a21ae81d 1404#if defined(DEBUG_CIRRUS)
e6e5ad80
FB		 1405 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1406#endif
1407 }
1408 s->cirrus_hidden_dac_lockindex = 0;
1409}
1410
1411/***************************************
1412 *
1413 * I/O access at 0x3c9
1414 *
1415 ***************************************/
1416
5deaeee3 1417static int cirrus_vga_read_palette(CirrusVGAState * s)
e6e5ad80 1418{
5deaeee3
JQ		 1419 int val;
1420
1421 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1422 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1423 s->vga.dac_sub_index];
1424 } else {
1425 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
1426 }
4e12cd94
AK		 1427 if (++s->vga.dac_sub_index == 3) {
1428 s->vga.dac_sub_index = 0;
1429 s->vga.dac_read_index++;
e6e5ad80 1430 }
5deaeee3 1431 return val;
e6e5ad80
FB		 1432}
1433
86948bb1 1434static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value)
e6e5ad80 1435{
4e12cd94
AK		 1436 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1437 if (++s->vga.dac_sub_index == 3) {
86948bb1
JQ		 1438 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1439 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1440 s->vga.dac_cache, 3);
1441 } else {
1442 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
1443 }
a5082316 1444 /* XXX update cursor */
4e12cd94
AK		 1445 s->vga.dac_sub_index = 0;
1446 s->vga.dac_write_index++;
e6e5ad80 1447 }
e6e5ad80
FB		 1448}
1449
1450/***************************************
1451 *
1452 * I/O access between 0x3ce-0x3cf
1453 *
1454 ***************************************/
1455
f705db9d 1456static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1457{
1458 switch (reg_index) {
aeb3c85f 1459 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
f705db9d 1460 return s->cirrus_shadow_gr0;
aeb3c85f 1461 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
f705db9d 1462 return s->cirrus_shadow_gr1;
e6e5ad80
FB		 1463 case 0x02: // Standard VGA
1464 case 0x03: // Standard VGA
1465 case 0x04: // Standard VGA
1466 case 0x06: // Standard VGA
1467 case 0x07: // Standard VGA
1468 case 0x08: // Standard VGA
f705db9d 1469 return s->vga.gr[s->vga.gr_index];
e6e5ad80
FB		 1470 case 0x05: // Standard VGA, Cirrus extended mode
1471 default:
1472 break;
1473 }
1474
1475 if (reg_index < 0x3a) {
f705db9d 1476 return s->vga.gr[reg_index];
e6e5ad80
FB		 1477 } else {
1478#ifdef DEBUG_CIRRUS
1479 printf("cirrus: inport gr_index %02x\n", reg_index);
1480#endif
f705db9d 1481 return 0xff;
e6e5ad80 1482 }
e6e5ad80
FB		 1483}
1484
22286bc6
JQ		 1485static void
1486cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
e6e5ad80 1487{
a5082316
FB		 1488#if defined(DEBUG_BITBLT) && 0
1489 printf("gr%02x: %02x\n", reg_index, reg_value);
1490#endif
e6e5ad80
FB		 1491 switch (reg_index) {
1492 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
aeb3c85f 1493 s->cirrus_shadow_gr0 = reg_value;
22286bc6 1494 break;
e6e5ad80 1495 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
aeb3c85f 1496 s->cirrus_shadow_gr1 = reg_value;
22286bc6 1497 break;
e6e5ad80
FB		 1498 case 0x02: // Standard VGA
1499 case 0x03: // Standard VGA
1500 case 0x04: // Standard VGA
1501 case 0x06: // Standard VGA
1502 case 0x07: // Standard VGA
1503 case 0x08: // Standard VGA
22286bc6
JQ		 1504 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1505 break;
e6e5ad80 1506 case 0x05: // Standard VGA, Cirrus extended mode
4e12cd94 1507 s->vga.gr[reg_index] = reg_value & 0x7f;
8926b517 1508 cirrus_update_memory_access(s);
e6e5ad80
FB		 1509 break;
1510 case 0x09: // bank offset #0
1511 case 0x0A: // bank offset #1
4e12cd94 1512 s->vga.gr[reg_index] = reg_value;
8926b517
FB		 1513 cirrus_update_bank_ptr(s, 0);
1514 cirrus_update_bank_ptr(s, 1);
2bec46dc 1515 cirrus_update_memory_access(s);
8926b517 1516 break;
e6e5ad80 1517 case 0x0B:
4e12cd94 1518 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1519 cirrus_update_bank_ptr(s, 0);
1520 cirrus_update_bank_ptr(s, 1);
8926b517 1521 cirrus_update_memory_access(s);
e6e5ad80
FB		 1522 break;
1523 case 0x10: // BGCOLOR 0x0000ff00
1524 case 0x11: // FGCOLOR 0x0000ff00
1525 case 0x12: // BGCOLOR 0x00ff0000
1526 case 0x13: // FGCOLOR 0x00ff0000
1527 case 0x14: // BGCOLOR 0xff000000
1528 case 0x15: // FGCOLOR 0xff000000
1529 case 0x20: // BLT WIDTH 0x0000ff
1530 case 0x22: // BLT HEIGHT 0x0000ff
1531 case 0x24: // BLT DEST PITCH 0x0000ff
1532 case 0x26: // BLT SRC PITCH 0x0000ff
1533 case 0x28: // BLT DEST ADDR 0x0000ff
1534 case 0x29: // BLT DEST ADDR 0x00ff00
1535 case 0x2c: // BLT SRC ADDR 0x0000ff
1536 case 0x2d: // BLT SRC ADDR 0x00ff00
a5082316 1537 case 0x2f: // BLT WRITEMASK
e6e5ad80
FB		 1538 case 0x30: // BLT MODE
1539 case 0x32: // RASTER OP
a21ae81d 1540 case 0x33: // BLT MODEEXT
e6e5ad80
FB		 1541 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1542 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1543 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1544 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
4e12cd94 1545 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1546 break;
1547 case 0x21: // BLT WIDTH 0x001f00
1548 case 0x23: // BLT HEIGHT 0x001f00
1549 case 0x25: // BLT DEST PITCH 0x001f00
1550 case 0x27: // BLT SRC PITCH 0x001f00
4e12cd94 1551 s->vga.gr[reg_index] = reg_value & 0x1f;
e6e5ad80
FB		 1552 break;
1553 case 0x2a: // BLT DEST ADDR 0x3f0000
4e12cd94 1554 s->vga.gr[reg_index] = reg_value & 0x3f;
a5082316 1555 /* if auto start mode, starts bit blt now */
4e12cd94 1556 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
a5082316
FB		 1557 cirrus_bitblt_start(s);
1558 }
1559 break;
e6e5ad80 1560 case 0x2e: // BLT SRC ADDR 0x3f0000
4e12cd94 1561 s->vga.gr[reg_index] = reg_value & 0x3f;
e6e5ad80
FB		 1562 break;
1563 case 0x31: // BLT STATUS/START
1564 cirrus_write_bitblt(s, reg_value);
1565 break;
1566 default:
1567#ifdef DEBUG_CIRRUS
1568 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1569 reg_value);
1570#endif
1571 break;
1572 }
e6e5ad80
FB		 1573}
1574
1575/***************************************
1576 *
1577 * I/O access between 0x3d4-0x3d5
1578 *
1579 ***************************************/
1580
b863d514 1581static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1582{
1583 switch (reg_index) {
1584 case 0x00: // Standard VGA
1585 case 0x01: // Standard VGA
1586 case 0x02: // Standard VGA
1587 case 0x03: // Standard VGA
1588 case 0x04: // Standard VGA
1589 case 0x05: // Standard VGA
1590 case 0x06: // Standard VGA
1591 case 0x07: // Standard VGA
1592 case 0x08: // Standard VGA
1593 case 0x09: // Standard VGA
1594 case 0x0a: // Standard VGA
1595 case 0x0b: // Standard VGA
1596 case 0x0c: // Standard VGA
1597 case 0x0d: // Standard VGA
1598 case 0x0e: // Standard VGA
1599 case 0x0f: // Standard VGA
1600 case 0x10: // Standard VGA
1601 case 0x11: // Standard VGA
1602 case 0x12: // Standard VGA
1603 case 0x13: // Standard VGA
1604 case 0x14: // Standard VGA
1605 case 0x15: // Standard VGA
1606 case 0x16: // Standard VGA
1607 case 0x17: // Standard VGA
1608 case 0x18: // Standard VGA
b863d514 1609 return s->vga.cr[s->vga.cr_index];
ca896ef3 1610 case 0x24: // Attribute Controller Toggle Readback (R)
b863d514 1611 return (s->vga.ar_flip_flop << 7);
e6e5ad80
FB		 1612 case 0x19: // Interlace End
1613 case 0x1a: // Miscellaneous Control
1614 case 0x1b: // Extended Display Control
1615 case 0x1c: // Sync Adjust and Genlock
1616 case 0x1d: // Overlay Extended Control
1617 case 0x22: // Graphics Data Latches Readback (R)
e6e5ad80
FB		 1618 case 0x25: // Part Status
1619 case 0x27: // Part ID (R)
b863d514 1620 return s->vga.cr[s->vga.cr_index];
e6e5ad80 1621 case 0x26: // Attribute Controller Index Readback (R)
b863d514 1622 return s->vga.ar_index & 0x3f;
e6e5ad80
FB		 1623 break;
1624 default:
1625#ifdef DEBUG_CIRRUS
1626 printf("cirrus: inport cr_index %02x\n", reg_index);
e6e5ad80 1627#endif
b863d514 1628 return 0xff;
e6e5ad80 1629 }
e6e5ad80
FB		 1630}
1631
4ec1ce04 1632static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
e6e5ad80 1633{
4ec1ce04 1634 switch (s->vga.cr_index) {
e6e5ad80
FB		 1635 case 0x00: // Standard VGA
1636 case 0x01: // Standard VGA
1637 case 0x02: // Standard VGA
1638 case 0x03: // Standard VGA
1639 case 0x04: // Standard VGA
1640 case 0x05: // Standard VGA
1641 case 0x06: // Standard VGA
1642 case 0x07: // Standard VGA
1643 case 0x08: // Standard VGA
1644 case 0x09: // Standard VGA
1645 case 0x0a: // Standard VGA
1646 case 0x0b: // Standard VGA
1647 case 0x0c: // Standard VGA
1648 case 0x0d: // Standard VGA
1649 case 0x0e: // Standard VGA
1650 case 0x0f: // Standard VGA
1651 case 0x10: // Standard VGA
1652 case 0x11: // Standard VGA
1653 case 0x12: // Standard VGA
1654 case 0x13: // Standard VGA
1655 case 0x14: // Standard VGA
1656 case 0x15: // Standard VGA
1657 case 0x16: // Standard VGA
1658 case 0x17: // Standard VGA
1659 case 0x18: // Standard VGA
4ec1ce04
JQ		 1660 /* handle CR0-7 protection */
1661 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
1662 /* can always write bit 4 of CR7 */
1663 if (s->vga.cr_index == 7)
1664 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10);
1665 return;
1666 }
1667 s->vga.cr[s->vga.cr_index] = reg_value;
1668 switch(s->vga.cr_index) {
1669 case 0x00:
1670 case 0x04:
1671 case 0x05:
1672 case 0x06:
1673 case 0x07:
1674 case 0x11:
1675 case 0x17:
1676 s->vga.update_retrace_info(&s->vga);
1677 break;
1678 }
1679 break;
e6e5ad80
FB		 1680 case 0x19: // Interlace End
1681 case 0x1a: // Miscellaneous Control
1682 case 0x1b: // Extended Display Control
1683 case 0x1c: // Sync Adjust and Genlock
ae184e4a 1684 case 0x1d: // Overlay Extended Control
4ec1ce04 1685 s->vga.cr[s->vga.cr_index] = reg_value;
e6e5ad80
FB		 1686#ifdef DEBUG_CIRRUS
1687 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
4ec1ce04 1688 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1689#endif
1690 break;
1691 case 0x22: // Graphics Data Latches Readback (R)
1692 case 0x24: // Attribute Controller Toggle Readback (R)
1693 case 0x26: // Attribute Controller Index Readback (R)
1694 case 0x27: // Part ID (R)
1695 break;
e6e5ad80
FB		 1696 case 0x25: // Part Status
1697 default:
1698#ifdef DEBUG_CIRRUS
4ec1ce04
JQ		 1699 printf("cirrus: outport cr_index %02x, cr_value %02x\n",
1700 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1701#endif
1702 break;
1703 }
e6e5ad80
FB		 1704}
1705
1706/***************************************
1707 *
1708 * memory-mapped I/O (bitblt)
1709 *
1710 ***************************************/
1711
1712static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1713{
1714 int value = 0xff;
1715
1716 switch (address) {
1717 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
f705db9d 1718 value = cirrus_vga_read_gr(s, 0x00);
e6e5ad80
FB		 1719 break;
1720 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
f705db9d 1721 value = cirrus_vga_read_gr(s, 0x10);
e6e5ad80
FB		 1722 break;
1723 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
f705db9d 1724 value = cirrus_vga_read_gr(s, 0x12);
e6e5ad80
FB		 1725 break;
1726 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
f705db9d 1727 value = cirrus_vga_read_gr(s, 0x14);
e6e5ad80
FB		 1728 break;
1729 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
f705db9d 1730 value = cirrus_vga_read_gr(s, 0x01);
e6e5ad80
FB		 1731 break;
1732 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
f705db9d 1733 value = cirrus_vga_read_gr(s, 0x11);
e6e5ad80
FB		 1734 break;
1735 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
f705db9d 1736 value = cirrus_vga_read_gr(s, 0x13);
e6e5ad80
FB		 1737 break;
1738 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
f705db9d 1739 value = cirrus_vga_read_gr(s, 0x15);
e6e5ad80
FB		 1740 break;
1741 case (CIRRUS_MMIO_BLTWIDTH + 0):
f705db9d 1742 value = cirrus_vga_read_gr(s, 0x20);
e6e5ad80
FB		 1743 break;
1744 case (CIRRUS_MMIO_BLTWIDTH + 1):
f705db9d 1745 value = cirrus_vga_read_gr(s, 0x21);
e6e5ad80
FB		 1746 break;
1747 case (CIRRUS_MMIO_BLTHEIGHT + 0):
f705db9d 1748 value = cirrus_vga_read_gr(s, 0x22);
e6e5ad80
FB		 1749 break;
1750 case (CIRRUS_MMIO_BLTHEIGHT + 1):
f705db9d 1751 value = cirrus_vga_read_gr(s, 0x23);
e6e5ad80
FB		 1752 break;
1753 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
f705db9d 1754 value = cirrus_vga_read_gr(s, 0x24);
e6e5ad80
FB		 1755 break;
1756 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
f705db9d 1757 value = cirrus_vga_read_gr(s, 0x25);
e6e5ad80
FB		 1758 break;
1759 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
f705db9d 1760 value = cirrus_vga_read_gr(s, 0x26);
e6e5ad80
FB		 1761 break;
1762 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
f705db9d 1763 value = cirrus_vga_read_gr(s, 0x27);
e6e5ad80
FB		 1764 break;
1765 case (CIRRUS_MMIO_BLTDESTADDR + 0):
f705db9d 1766 value = cirrus_vga_read_gr(s, 0x28);
e6e5ad80
FB		 1767 break;
1768 case (CIRRUS_MMIO_BLTDESTADDR + 1):
f705db9d 1769 value = cirrus_vga_read_gr(s, 0x29);
e6e5ad80
FB		 1770 break;
1771 case (CIRRUS_MMIO_BLTDESTADDR + 2):
f705db9d 1772 value = cirrus_vga_read_gr(s, 0x2a);
e6e5ad80
FB		 1773 break;
1774 case (CIRRUS_MMIO_BLTSRCADDR + 0):
f705db9d 1775 value = cirrus_vga_read_gr(s, 0x2c);
e6e5ad80
FB		 1776 break;
1777 case (CIRRUS_MMIO_BLTSRCADDR + 1):
f705db9d 1778 value = cirrus_vga_read_gr(s, 0x2d);
e6e5ad80
FB		 1779 break;
1780 case (CIRRUS_MMIO_BLTSRCADDR + 2):
f705db9d 1781 value = cirrus_vga_read_gr(s, 0x2e);
e6e5ad80
FB		 1782 break;
1783 case CIRRUS_MMIO_BLTWRITEMASK:
f705db9d 1784 value = cirrus_vga_read_gr(s, 0x2f);
e6e5ad80
FB		 1785 break;
1786 case CIRRUS_MMIO_BLTMODE:
f705db9d 1787 value = cirrus_vga_read_gr(s, 0x30);
e6e5ad80
FB		 1788 break;
1789 case CIRRUS_MMIO_BLTROP:
f705db9d 1790 value = cirrus_vga_read_gr(s, 0x32);
e6e5ad80 1791 break;
a21ae81d 1792 case CIRRUS_MMIO_BLTMODEEXT:
f705db9d 1793 value = cirrus_vga_read_gr(s, 0x33);
a21ae81d 1794 break;
e6e5ad80 1795 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
f705db9d 1796 value = cirrus_vga_read_gr(s, 0x34);
e6e5ad80
FB		 1797 break;
1798 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
f705db9d 1799 value = cirrus_vga_read_gr(s, 0x35);
e6e5ad80
FB		 1800 break;
1801 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
f705db9d 1802 value = cirrus_vga_read_gr(s, 0x38);
e6e5ad80
FB		 1803 break;
1804 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
f705db9d 1805 value = cirrus_vga_read_gr(s, 0x39);
e6e5ad80
FB		 1806 break;
1807 case CIRRUS_MMIO_BLTSTATUS:
f705db9d 1808 value = cirrus_vga_read_gr(s, 0x31);
e6e5ad80
FB		 1809 break;
1810 default:
1811#ifdef DEBUG_CIRRUS
1812 printf("cirrus: mmio read - address 0x%04x\n", address);
1813#endif
1814 break;
1815 }
1816
1817 return (uint8_t) value;
1818}
1819
1820static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1821 uint8_t value)
1822{
1823 switch (address) {
1824 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
22286bc6 1825 cirrus_vga_write_gr(s, 0x00, value);
e6e5ad80
FB		 1826 break;
1827 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
22286bc6 1828 cirrus_vga_write_gr(s, 0x10, value);
e6e5ad80
FB		 1829 break;
1830 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
22286bc6 1831 cirrus_vga_write_gr(s, 0x12, value);
e6e5ad80
FB		 1832 break;
1833 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
22286bc6 1834 cirrus_vga_write_gr(s, 0x14, value);
e6e5ad80
FB		 1835 break;
1836 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
22286bc6 1837 cirrus_vga_write_gr(s, 0x01, value);
e6e5ad80
FB		 1838 break;
1839 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
22286bc6 1840 cirrus_vga_write_gr(s, 0x11, value);
e6e5ad80
FB		 1841 break;
1842 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
22286bc6 1843 cirrus_vga_write_gr(s, 0x13, value);
e6e5ad80
FB		 1844 break;
1845 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
22286bc6 1846 cirrus_vga_write_gr(s, 0x15, value);
e6e5ad80
FB		 1847 break;
1848 case (CIRRUS_MMIO_BLTWIDTH + 0):
22286bc6 1849 cirrus_vga_write_gr(s, 0x20, value);
e6e5ad80
FB		 1850 break;
1851 case (CIRRUS_MMIO_BLTWIDTH + 1):
22286bc6 1852 cirrus_vga_write_gr(s, 0x21, value);
e6e5ad80
FB		 1853 break;
1854 case (CIRRUS_MMIO_BLTHEIGHT + 0):
22286bc6 1855 cirrus_vga_write_gr(s, 0x22, value);
e6e5ad80
FB		 1856 break;
1857 case (CIRRUS_MMIO_BLTHEIGHT + 1):
22286bc6 1858 cirrus_vga_write_gr(s, 0x23, value);
e6e5ad80
FB		 1859 break;
1860 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
22286bc6 1861 cirrus_vga_write_gr(s, 0x24, value);
e6e5ad80
FB		 1862 break;
1863 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
22286bc6 1864 cirrus_vga_write_gr(s, 0x25, value);
e6e5ad80
FB		 1865 break;
1866 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
22286bc6 1867 cirrus_vga_write_gr(s, 0x26, value);
e6e5ad80
FB		 1868 break;
1869 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
22286bc6 1870 cirrus_vga_write_gr(s, 0x27, value);
e6e5ad80
FB		 1871 break;
1872 case (CIRRUS_MMIO_BLTDESTADDR + 0):
22286bc6 1873 cirrus_vga_write_gr(s, 0x28, value);
e6e5ad80
FB		 1874 break;
1875 case (CIRRUS_MMIO_BLTDESTADDR + 1):
22286bc6 1876 cirrus_vga_write_gr(s, 0x29, value);
e6e5ad80
FB		 1877 break;
1878 case (CIRRUS_MMIO_BLTDESTADDR + 2):
22286bc6 1879 cirrus_vga_write_gr(s, 0x2a, value);
e6e5ad80
FB		 1880 break;
1881 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1882 /* ignored */
1883 break;
1884 case (CIRRUS_MMIO_BLTSRCADDR + 0):
22286bc6 1885 cirrus_vga_write_gr(s, 0x2c, value);
e6e5ad80
FB		 1886 break;
1887 case (CIRRUS_MMIO_BLTSRCADDR + 1):
22286bc6 1888 cirrus_vga_write_gr(s, 0x2d, value);
e6e5ad80
FB		 1889 break;
1890 case (CIRRUS_MMIO_BLTSRCADDR + 2):
22286bc6 1891 cirrus_vga_write_gr(s, 0x2e, value);
e6e5ad80
FB		 1892 break;
1893 case CIRRUS_MMIO_BLTWRITEMASK:
22286bc6 1894 cirrus_vga_write_gr(s, 0x2f, value);
e6e5ad80
FB		 1895 break;
1896 case CIRRUS_MMIO_BLTMODE:
22286bc6 1897 cirrus_vga_write_gr(s, 0x30, value);
e6e5ad80
FB		 1898 break;
1899 case CIRRUS_MMIO_BLTROP:
22286bc6 1900 cirrus_vga_write_gr(s, 0x32, value);
e6e5ad80 1901 break;
a21ae81d 1902 case CIRRUS_MMIO_BLTMODEEXT:
22286bc6 1903 cirrus_vga_write_gr(s, 0x33, value);
a21ae81d 1904 break;
e6e5ad80 1905 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
22286bc6 1906 cirrus_vga_write_gr(s, 0x34, value);
e6e5ad80
FB		 1907 break;
1908 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
22286bc6 1909 cirrus_vga_write_gr(s, 0x35, value);
e6e5ad80
FB		 1910 break;
1911 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
22286bc6 1912 cirrus_vga_write_gr(s, 0x38, value);
e6e5ad80
FB		 1913 break;
1914 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
22286bc6 1915 cirrus_vga_write_gr(s, 0x39, value);
e6e5ad80
FB		 1916 break;
1917 case CIRRUS_MMIO_BLTSTATUS:
22286bc6 1918 cirrus_vga_write_gr(s, 0x31, value);
e6e5ad80
FB		 1919 break;
1920 default:
1921#ifdef DEBUG_CIRRUS
1922 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1923 address, value);
1924#endif
1925 break;
1926 }
1927}
1928
e6e5ad80
FB		 1929/***************************************
1930 *
1931 * write mode 4/5
1932 *
1933 * assume TARGET_PAGE_SIZE >= 16
1934 *
1935 ***************************************/
1936
1937static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1938 unsigned mode,
1939 unsigned offset,
1940 uint32_t mem_value)
1941{
1942 int x;
1943 unsigned val = mem_value;
1944 uint8_t *dst;
1945
4e12cd94 1946 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1947 for (x = 0; x < 8; x++) {
1948 if (val & 0x80) {
0b74ed78 1949 *dst = s->cirrus_shadow_gr1;
e6e5ad80 1950 } else if (mode == 5) {
0b74ed78 1951 *dst = s->cirrus_shadow_gr0;
e6e5ad80
FB		 1952 }
1953 val <<= 1;
0b74ed78 1954 dst++;
e6e5ad80 1955 }
4e12cd94
AK		 1956 cpu_physical_memory_set_dirty(s->vga.vram_offset + offset);
1957 cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 7);
e6e5ad80
FB		 1958}
1959
1960static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1961 unsigned mode,
1962 unsigned offset,
1963 uint32_t mem_value)
1964{
1965 int x;
1966 unsigned val = mem_value;
1967 uint8_t *dst;
1968
4e12cd94 1969 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1970 for (x = 0; x < 8; x++) {
1971 if (val & 0x80) {
0b74ed78 1972 *dst = s->cirrus_shadow_gr1;
4e12cd94 1973 *(dst + 1) = s->vga.gr[0x11];
e6e5ad80 1974 } else if (mode == 5) {
0b74ed78 1975 *dst = s->cirrus_shadow_gr0;
4e12cd94 1976 *(dst + 1) = s->vga.gr[0x10];
e6e5ad80
FB		 1977 }
1978 val <<= 1;
0b74ed78 1979 dst += 2;
e6e5ad80 1980 }
4e12cd94
AK		 1981 cpu_physical_memory_set_dirty(s->vga.vram_offset + offset);
1982 cpu_physical_memory_set_dirty(s->vga.vram_offset + offset + 15);
e6e5ad80
FB		 1983}
1984
1985/***************************************
1986 *
1987 * memory access between 0xa0000-0xbffff
1988 *
1989 ***************************************/
1990
c227f099 1991static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
e6e5ad80
FB		 1992{
1993 CirrusVGAState *s = opaque;
1994 unsigned bank_index;
1995 unsigned bank_offset;
1996 uint32_t val;
1997
4e12cd94 1998 if ((s->vga.sr[0x07] & 0x01) == 0) {
e6e5ad80
FB		 1999 return vga_mem_readb(s, addr);
2000 }
2001
aeb3c85f
FB		 2002 addr &= 0x1ffff;
2003
e6e5ad80
FB		 2004 if (addr < 0x10000) {
2005 /* XXX handle bitblt */
2006 /* video memory */
2007 bank_index = addr >> 15;
2008 bank_offset = addr & 0x7fff;
2009 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2010 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 2011 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2012 bank_offset <<= 4;
4e12cd94 2013 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2014 bank_offset <<= 3;
2015 }
2016 bank_offset &= s->cirrus_addr_mask;
4e12cd94 2017 val = *(s->vga.vram_ptr + bank_offset);
e6e5ad80
FB		 2018 } else
2019 val = 0xff;
2020 } else if (addr >= 0x18000 && addr < 0x18100) {
2021 /* memory-mapped I/O */
2022 val = 0xff;
4e12cd94 2023 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 2024 val = cirrus_mmio_blt_read(s, addr & 0xff);
2025 }
2026 } else {
2027 val = 0xff;
2028#ifdef DEBUG_CIRRUS
0bf9e31a 2029 printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
e6e5ad80
FB		 2030#endif
2031 }
2032 return val;
2033}
2034
c227f099 2035static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
e6e5ad80
FB		 2036{
2037 uint32_t v;
2038#ifdef TARGET_WORDS_BIGENDIAN
2039 v = cirrus_vga_mem_readb(opaque, addr) << 8;
2040 v |= cirrus_vga_mem_readb(opaque, addr + 1);
2041#else
2042 v = cirrus_vga_mem_readb(opaque, addr);
2043 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2044#endif
2045 return v;
2046}
2047
c227f099 2048static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
e6e5ad80
FB		 2049{
2050 uint32_t v;
2051#ifdef TARGET_WORDS_BIGENDIAN
2052 v = cirrus_vga_mem_readb(opaque, addr) << 24;
2053 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
2054 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
2055 v |= cirrus_vga_mem_readb(opaque, addr + 3);
2056#else
2057 v = cirrus_vga_mem_readb(opaque, addr);
2058 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2059 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
2060 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
2061#endif
2062 return v;
2063}
2064
c227f099 2065static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
e6e5ad80
FB		 2066 uint32_t mem_value)
2067{
2068 CirrusVGAState *s = opaque;
2069 unsigned bank_index;
2070 unsigned bank_offset;
2071 unsigned mode;
2072
4e12cd94 2073 if ((s->vga.sr[0x07] & 0x01) == 0) {
e6e5ad80
FB		 2074 vga_mem_writeb(s, addr, mem_value);
2075 return;
2076 }
2077
aeb3c85f
FB		 2078 addr &= 0x1ffff;
2079
e6e5ad80
FB		 2080 if (addr < 0x10000) {
2081 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2082 /* bitblt */
2083 *s->cirrus_srcptr++ = (uint8_t) mem_value;
a5082316 2084 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2085 cirrus_bitblt_cputovideo_next(s);
2086 }
2087 } else {
2088 /* video memory */
2089 bank_index = addr >> 15;
2090 bank_offset = addr & 0x7fff;
2091 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2092 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 2093 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2094 bank_offset <<= 4;
4e12cd94 2095 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2096 bank_offset <<= 3;
2097 }
2098 bank_offset &= s->cirrus_addr_mask;
4e12cd94
AK		 2099 mode = s->vga.gr[0x05] & 0x7;
2100 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2101 *(s->vga.vram_ptr + bank_offset) = mem_value;
2102 cpu_physical_memory_set_dirty(s->vga.vram_offset +
e6e5ad80
FB		 2103 bank_offset);
2104 } else {
4e12cd94 2105 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2106 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2107 bank_offset,
2108 mem_value);
2109 } else {
2110 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2111 bank_offset,
2112 mem_value);
2113 }
2114 }
2115 }
2116 }
2117 } else if (addr >= 0x18000 && addr < 0x18100) {
2118 /* memory-mapped I/O */
4e12cd94 2119 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 2120 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2121 }
2122 } else {
2123#ifdef DEBUG_CIRRUS
0bf9e31a
BS		 2124 printf("cirrus: mem_writeb " TARGET_FMT_plx " value %02x\n", addr,
2125 mem_value);
e6e5ad80
FB		 2126#endif
2127 }
2128}
2129
c227f099 2130static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
e6e5ad80
FB		 2131{
2132#ifdef TARGET_WORDS_BIGENDIAN
2133 cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
2134 cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
2135#else
2136 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2137 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2138#endif
2139}
2140
c227f099 2141static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
e6e5ad80
FB		 2142{
2143#ifdef TARGET_WORDS_BIGENDIAN
2144 cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
2145 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2146 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2147 cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
2148#else
2149 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2150 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2151 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2152 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2153#endif
2154}
2155
d60efc6b 2156static CPUReadMemoryFunc * const cirrus_vga_mem_read[3] = {
e6e5ad80
FB		 2157 cirrus_vga_mem_readb,
2158 cirrus_vga_mem_readw,
2159 cirrus_vga_mem_readl,
2160};
2161
d60efc6b 2162static CPUWriteMemoryFunc * const cirrus_vga_mem_write[3] = {
e6e5ad80
FB		 2163 cirrus_vga_mem_writeb,
2164 cirrus_vga_mem_writew,
2165 cirrus_vga_mem_writel,
2166};
2167
a5082316
FB		 2168/***************************************
2169 *
2170 * hardware cursor
2171 *
2172 ***************************************/
2173
2174static inline void invalidate_cursor1(CirrusVGAState *s)
2175{
2176 if (s->last_hw_cursor_size) {
4e12cd94 2177 vga_invalidate_scanlines(&s->vga,
a5082316
FB		 2178 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2179 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2180 }
2181}
2182
2183static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2184{
2185 const uint8_t *src;
2186 uint32_t content;
2187 int y, y_min, y_max;
2188
4e12cd94
AK		 2189 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2190 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2191 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2192 y_min = 64;
2193 y_max = -1;
2194 for(y = 0; y < 64; y++) {
2195 content = ((uint32_t *)src)[0] |
2196 ((uint32_t *)src)[1] |
2197 ((uint32_t *)src)[2] |
2198 ((uint32_t *)src)[3];
2199 if (content) {
2200 if (y < y_min)
2201 y_min = y;
2202 if (y > y_max)
2203 y_max = y;
2204 }
2205 src += 16;
2206 }
2207 } else {
4e12cd94 2208 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316
FB		 2209 y_min = 32;
2210 y_max = -1;
2211 for(y = 0; y < 32; y++) {
2212 content = ((uint32_t *)src)[0] |
2213 ((uint32_t *)(src + 128))[0];
2214 if (content) {
2215 if (y < y_min)
2216 y_min = y;
2217 if (y > y_max)
2218 y_max = y;
2219 }
2220 src += 4;
2221 }
2222 }
2223 if (y_min > y_max) {
2224 s->last_hw_cursor_y_start = 0;
2225 s->last_hw_cursor_y_end = 0;
2226 } else {
2227 s->last_hw_cursor_y_start = y_min;
2228 s->last_hw_cursor_y_end = y_max + 1;
2229 }
2230}
2231
2232/* NOTE: we do not currently handle the cursor bitmap change, so we
2233 update the cursor only if it moves. */
a4a2f59c 2234static void cirrus_cursor_invalidate(VGACommonState *s1)
a5082316 2235{
4e12cd94 2236 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
a5082316
FB		 2237 int size;
2238
4e12cd94 2239 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
a5082316
FB		 2240 size = 0;
2241 } else {
4e12cd94 2242 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
a5082316
FB		 2243 size = 64;
2244 else
2245 size = 32;
2246 }
2247 /* invalidate last cursor and new cursor if any change */
2248 if (s->last_hw_cursor_size != size ||
2249 s->last_hw_cursor_x != s->hw_cursor_x ||
2250 s->last_hw_cursor_y != s->hw_cursor_y) {
2251
2252 invalidate_cursor1(s);
3b46e624 2253
a5082316
FB		 2254 s->last_hw_cursor_size = size;
2255 s->last_hw_cursor_x = s->hw_cursor_x;
2256 s->last_hw_cursor_y = s->hw_cursor_y;
2257 /* compute the real cursor min and max y */
2258 cirrus_cursor_compute_yrange(s);
2259 invalidate_cursor1(s);
2260 }
2261}
2262
a4a2f59c 2263static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
a5082316 2264{
4e12cd94 2265 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
a5082316
FB		 2266 int w, h, bpp, x1, x2, poffset;
2267 unsigned int color0, color1;
2268 const uint8_t *palette, *src;
2269 uint32_t content;
3b46e624 2270
4e12cd94 2271 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
a5082316
FB		 2272 return;
2273 /* fast test to see if the cursor intersects with the scan line */
4e12cd94 2274 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
a5082316
FB		 2275 h = 64;
2276 } else {
2277 h = 32;
2278 }
2279 if (scr_y < s->hw_cursor_y ||
2280 scr_y >= (s->hw_cursor_y + h))
2281 return;
3b46e624 2282
4e12cd94
AK		 2283 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2284 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2285 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2286 src += (scr_y - s->hw_cursor_y) * 16;
2287 poffset = 8;
2288 content = ((uint32_t *)src)[0] |
2289 ((uint32_t *)src)[1] |
2290 ((uint32_t *)src)[2] |
2291 ((uint32_t *)src)[3];
2292 } else {
4e12cd94 2293 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316
FB		 2294 src += (scr_y - s->hw_cursor_y) * 4;
2295 poffset = 128;
2296 content = ((uint32_t *)src)[0] |
2297 ((uint32_t *)(src + 128))[0];
2298 }
2299 /* if nothing to draw, no need to continue */
2300 if (!content)
2301 return;
2302 w = h;
2303
2304 x1 = s->hw_cursor_x;
4e12cd94 2305 if (x1 >= s->vga.last_scr_width)
a5082316
FB		 2306 return;
2307 x2 = s->hw_cursor_x + w;
4e12cd94
AK		 2308 if (x2 > s->vga.last_scr_width)
2309 x2 = s->vga.last_scr_width;
a5082316
FB		 2310 w = x2 - x1;
2311 palette = s->cirrus_hidden_palette;
4e12cd94
AK		 2312 color0 = s->vga.rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2313 c6_to_8(palette[0x0 * 3 + 1]),
2314 c6_to_8(palette[0x0 * 3 + 2]));
2315 color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2316 c6_to_8(palette[0xf * 3 + 1]),
2317 c6_to_8(palette[0xf * 3 + 2]));
2318 bpp = ((ds_get_bits_per_pixel(s->vga.ds) + 7) >> 3);
a5082316 2319 d1 += x1 * bpp;
4e12cd94 2320 switch(ds_get_bits_per_pixel(s->vga.ds)) {
a5082316
FB		 2321 default:
2322 break;
2323 case 8:
2324 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2325 break;
2326 case 15:
2327 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2328 break;
2329 case 16:
2330 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2331 break;
2332 case 32:
2333 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2334 break;
2335 }
2336}
2337
e6e5ad80
FB		 2338/***************************************
2339 *
2340 * LFB memory access
2341 *
2342 ***************************************/
2343
c227f099 2344static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
e6e5ad80 2345{
e05587e8 2346 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2347 uint32_t ret;
2348
e6e5ad80
FB		 2349 addr &= s->cirrus_addr_mask;
2350
4e12cd94 2351 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2352 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2353 /* memory-mapped I/O */
2354 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2355 } else if (0) {
2356 /* XXX handle bitblt */
2357 ret = 0xff;
2358 } else {
2359 /* video memory */
4e12cd94 2360 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2361 addr <<= 4;
4e12cd94 2362 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2363 addr <<= 3;
2364 }
2365 addr &= s->cirrus_addr_mask;
4e12cd94 2366 ret = *(s->vga.vram_ptr + addr);
e6e5ad80
FB		 2367 }
2368
2369 return ret;
2370}
2371
c227f099 2372static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
e6e5ad80
FB		 2373{
2374 uint32_t v;
2375#ifdef TARGET_WORDS_BIGENDIAN
2376 v = cirrus_linear_readb(opaque, addr) << 8;
2377 v |= cirrus_linear_readb(opaque, addr + 1);
2378#else
2379 v = cirrus_linear_readb(opaque, addr);
2380 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2381#endif
2382 return v;
2383}
2384
c227f099 2385static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
e6e5ad80
FB		 2386{
2387 uint32_t v;
2388#ifdef TARGET_WORDS_BIGENDIAN
2389 v = cirrus_linear_readb(opaque, addr) << 24;
2390 v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2391 v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2392 v |= cirrus_linear_readb(opaque, addr + 3);
2393#else
2394 v = cirrus_linear_readb(opaque, addr);
2395 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2396 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2397 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2398#endif
2399 return v;
2400}
2401
c227f099 2402static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
e6e5ad80
FB		 2403 uint32_t val)
2404{
e05587e8 2405 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2406 unsigned mode;
2407
2408 addr &= s->cirrus_addr_mask;
3b46e624 2409
4e12cd94 2410 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2411 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2412 /* memory-mapped I/O */
2413 cirrus_mmio_blt_write(s, addr & 0xff, val);
2414 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2415 /* bitblt */
2416 *s->cirrus_srcptr++ = (uint8_t) val;
a5082316 2417 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2418 cirrus_bitblt_cputovideo_next(s);
2419 }
2420 } else {
2421 /* video memory */
4e12cd94 2422 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2423 addr <<= 4;
4e12cd94 2424 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2425 addr <<= 3;
2426 }
2427 addr &= s->cirrus_addr_mask;
2428
4e12cd94
AK		 2429 mode = s->vga.gr[0x05] & 0x7;
2430 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2431 *(s->vga.vram_ptr + addr) = (uint8_t) val;
2432 cpu_physical_memory_set_dirty(s->vga.vram_offset + addr);
e6e5ad80 2433 } else {
4e12cd94 2434 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2435 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2436 } else {
2437 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2438 }
2439 }
2440 }
2441}
2442
c227f099 2443static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
e6e5ad80
FB		 2444 uint32_t val)
2445{
2446#ifdef TARGET_WORDS_BIGENDIAN
2447 cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2448 cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2449#else
2450 cirrus_linear_writeb(opaque, addr, val & 0xff);
2451 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2452#endif
2453}
2454
c227f099 2455static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
e6e5ad80
FB		 2456 uint32_t val)
2457{
2458#ifdef TARGET_WORDS_BIGENDIAN
2459 cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2460 cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2461 cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2462 cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2463#else
2464 cirrus_linear_writeb(opaque, addr, val & 0xff);
2465 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2466 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2467 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2468#endif
2469}
2470
2471
d60efc6b 2472static CPUReadMemoryFunc * const cirrus_linear_read[3] = {
e6e5ad80
FB		 2473 cirrus_linear_readb,
2474 cirrus_linear_readw,
2475 cirrus_linear_readl,
2476};
2477
d60efc6b 2478static CPUWriteMemoryFunc * const cirrus_linear_write[3] = {
e6e5ad80
FB		 2479 cirrus_linear_writeb,
2480 cirrus_linear_writew,
2481 cirrus_linear_writel,
2482};
2483
a5082316
FB		 2484/***************************************
2485 *
2486 * system to screen memory access
2487 *
2488 ***************************************/
2489
2490
c227f099 2491static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
a5082316
FB		 2492{
2493 uint32_t ret;
2494
2495 /* XXX handle bitblt */
2496 ret = 0xff;
2497 return ret;
2498}
2499
c227f099 2500static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
a5082316
FB		 2501{
2502 uint32_t v;
2503#ifdef TARGET_WORDS_BIGENDIAN
2504 v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2505 v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2506#else
2507 v = cirrus_linear_bitblt_readb(opaque, addr);
2508 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2509#endif
2510 return v;
2511}
2512
c227f099 2513static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
a5082316
FB		 2514{
2515 uint32_t v;
2516#ifdef TARGET_WORDS_BIGENDIAN
2517 v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2518 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2519 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2520 v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2521#else
2522 v = cirrus_linear_bitblt_readb(opaque, addr);
2523 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2524 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2525 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2526#endif
2527 return v;
2528}
2529
c227f099 2530static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
a5082316
FB		 2531 uint32_t val)
2532{
e05587e8 2533 CirrusVGAState *s = opaque;
a5082316
FB		 2534
2535 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2536 /* bitblt */
2537 *s->cirrus_srcptr++ = (uint8_t) val;
2538 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2539 cirrus_bitblt_cputovideo_next(s);
2540 }
2541 }
2542}
2543
c227f099 2544static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
a5082316
FB		 2545 uint32_t val)
2546{
2547#ifdef TARGET_WORDS_BIGENDIAN
2548 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2549 cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2550#else
2551 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2552 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2553#endif
2554}
2555
c227f099 2556static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
a5082316
FB		 2557 uint32_t val)
2558{
2559#ifdef TARGET_WORDS_BIGENDIAN
2560 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2561 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2562 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2563 cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2564#else
2565 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2566 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2567 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2568 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2569#endif
2570}
2571
2572
d60efc6b 2573static CPUReadMemoryFunc * const cirrus_linear_bitblt_read[3] = {
a5082316
FB		 2574 cirrus_linear_bitblt_readb,
2575 cirrus_linear_bitblt_readw,
2576 cirrus_linear_bitblt_readl,
2577};
2578
d60efc6b 2579static CPUWriteMemoryFunc * const cirrus_linear_bitblt_write[3] = {
a5082316
FB		 2580 cirrus_linear_bitblt_writeb,
2581 cirrus_linear_bitblt_writew,
2582 cirrus_linear_bitblt_writel,
2583};
2584
2bec46dc
AL		 2585static void map_linear_vram(CirrusVGAState *s)
2586{
4e12cd94
AK		 2587 if (!s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end) {
2588 s->vga.map_addr = s->vga.lfb_addr;
2589 s->vga.map_end = s->vga.lfb_end;
2590 cpu_register_physical_memory(s->vga.map_addr, s->vga.map_end - s->vga.map_addr, s->vga.vram_offset);
2bec46dc
AL		 2591 }
2592
4e12cd94 2593 if (!s->vga.map_addr)
2bec46dc
AL		 2594 return;
2595
4e12cd94 2596 s->vga.lfb_vram_mapped = 0;
2bec46dc
AL		 2597
2598 if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
4e12cd94
AK		 2599 && !((s->vga.sr[0x07] & 0x01) == 0)
2600 && !((s->vga.gr[0x0B] & 0x14) == 0x14)
2601 && !(s->vga.gr[0x0B] & 0x02)) {
2bec46dc
AL		 2602
2603 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
4e12cd94 2604 (s->vga.vram_offset + s->cirrus_bank_base[0]) | IO_MEM_RAM);
2bec46dc 2605 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
4e12cd94 2606 (s->vga.vram_offset + s->cirrus_bank_base[1]) | IO_MEM_RAM);
2bec46dc 2607
4e12cd94 2608 s->vga.lfb_vram_mapped = 1;
2bec46dc
AL		 2609 }
2610 else {
7cff316e 2611 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
4e12cd94 2612 s->vga.vga_io_memory);
2bec46dc
AL		 2613 }
2614
4e12cd94 2615 vga_dirty_log_start(&s->vga);
2bec46dc
AL		 2616}
2617
2618static void unmap_linear_vram(CirrusVGAState *s)
2619{
4e12cd94
AK		 2620 if (s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end)
2621 s->vga.map_addr = s->vga.map_end = 0;
2bec46dc
AL		 2622
2623 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
4e12cd94 2624 s->vga.vga_io_memory);
2bec46dc
AL		 2625}
2626
8926b517
FB		 2627/* Compute the memory access functions */
2628static void cirrus_update_memory_access(CirrusVGAState *s)
2629{
2630 unsigned mode;
2631
4e12cd94 2632 if ((s->vga.sr[0x17] & 0x44) == 0x44) {
8926b517
FB		 2633 goto generic_io;
2634 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2635 goto generic_io;
2636 } else {
4e12cd94 2637 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
8926b517 2638 goto generic_io;
4e12cd94 2639 } else if (s->vga.gr[0x0B] & 0x02) {
8926b517
FB		 2640 goto generic_io;
2641 }
3b46e624 2642
4e12cd94
AK		 2643 mode = s->vga.gr[0x05] & 0x7;
2644 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2bec46dc 2645 map_linear_vram(s);
8926b517
FB		 2646 } else {
2647 generic_io:
2bec46dc 2648 unmap_linear_vram(s);
8926b517
FB		 2649 }
2650 }
2651}
2652
2653
e6e5ad80
FB		 2654/* I/O ports */
2655
0ceac75b 2656static uint32_t cirrus_vga_ioport_read(void *opaque, uint32_t addr)
e6e5ad80 2657{
b6343073
JQ		 2658 CirrusVGAState *c = opaque;
2659 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2660 int val, index;
2661
b6343073 2662 if (vga_ioport_invalid(s, addr)) {
e6e5ad80
FB		 2663 val = 0xff;
2664 } else {
2665 switch (addr) {
2666 case 0x3c0:
b6343073
JQ		 2667 if (s->ar_flip_flop == 0) {
2668 val = s->ar_index;
e6e5ad80
FB		 2669 } else {
2670 val = 0;
2671 }
2672 break;
2673 case 0x3c1:
b6343073 2674 index = s->ar_index & 0x1f;
e6e5ad80 2675 if (index < 21)
b6343073 2676 val = s->ar[index];
e6e5ad80
FB		 2677 else
2678 val = 0;
2679 break;
2680 case 0x3c2:
b6343073 2681 val = s->st00;
e6e5ad80
FB		 2682 break;
2683 case 0x3c4:
b6343073 2684 val = s->sr_index;
e6e5ad80
FB		 2685 break;
2686 case 0x3c5:
8a82c322
JQ		 2687 val = cirrus_vga_read_sr(c);
2688 break;
e6e5ad80 2689#ifdef DEBUG_VGA_REG
b6343073 2690 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
e6e5ad80
FB		 2691#endif
2692 break;
2693 case 0x3c6:
957c9db5 2694 val = cirrus_read_hidden_dac(c);
e6e5ad80
FB		 2695 break;
2696 case 0x3c7:
b6343073 2697 val = s->dac_state;
e6e5ad80 2698 break;
ae184e4a 2699 case 0x3c8:
b6343073
JQ		 2700 val = s->dac_write_index;
2701 c->cirrus_hidden_dac_lockindex = 0;
ae184e4a
FB		 2702 break;
2703 case 0x3c9:
5deaeee3
JQ		 2704 val = cirrus_vga_read_palette(c);
2705 break;
e6e5ad80 2706 case 0x3ca:
b6343073 2707 val = s->fcr;
e6e5ad80
FB		 2708 break;
2709 case 0x3cc:
b6343073 2710 val = s->msr;
e6e5ad80
FB		 2711 break;
2712 case 0x3ce:
b6343073 2713 val = s->gr_index;
e6e5ad80
FB		 2714 break;
2715 case 0x3cf:
f705db9d 2716 val = cirrus_vga_read_gr(c, s->gr_index);
e6e5ad80 2717#ifdef DEBUG_VGA_REG
b6343073 2718 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
e6e5ad80
FB		 2719#endif
2720 break;
2721 case 0x3b4:
2722 case 0x3d4:
b6343073 2723 val = s->cr_index;
e6e5ad80
FB		 2724 break;
2725 case 0x3b5:
2726 case 0x3d5:
b863d514 2727 val = cirrus_vga_read_cr(c, s->cr_index);
e6e5ad80 2728#ifdef DEBUG_VGA_REG
b6343073 2729 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80
FB		 2730#endif
2731 break;
2732 case 0x3ba:
2733 case 0x3da:
2734 /* just toggle to fool polling */
b6343073
JQ		 2735 val = s->st01 = s->retrace(s);
2736 s->ar_flip_flop = 0;
e6e5ad80
FB		 2737 break;
2738 default:
2739 val = 0x00;
2740 break;
2741 }
2742 }
2743#if defined(DEBUG_VGA)
2744 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2745#endif
2746 return val;
2747}
2748
0ceac75b 2749static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
e6e5ad80 2750{
b6343073
JQ		 2751 CirrusVGAState *c = opaque;
2752 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2753 int index;
2754
2755 /* check port range access depending on color/monochrome mode */
b6343073 2756 if (vga_ioport_invalid(s, addr)) {
e6e5ad80 2757 return;
25a18cbd 2758 }
e6e5ad80
FB		 2759#ifdef DEBUG_VGA
2760 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2761#endif
2762
2763 switch (addr) {
2764 case 0x3c0:
b6343073 2765 if (s->ar_flip_flop == 0) {
e6e5ad80 2766 val &= 0x3f;
b6343073 2767 s->ar_index = val;
e6e5ad80 2768 } else {
b6343073 2769 index = s->ar_index & 0x1f;
e6e5ad80
FB		 2770 switch (index) {
2771 case 0x00 ... 0x0f:
b6343073 2772 s->ar[index] = val & 0x3f;
e6e5ad80
FB		 2773 break;
2774 case 0x10:
b6343073 2775 s->ar[index] = val & ~0x10;
e6e5ad80
FB		 2776 break;
2777 case 0x11:
b6343073 2778 s->ar[index] = val;
e6e5ad80
FB		 2779 break;
2780 case 0x12:
b6343073 2781 s->ar[index] = val & ~0xc0;
e6e5ad80
FB		 2782 break;
2783 case 0x13:
b6343073 2784 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2785 break;
2786 case 0x14:
b6343073 2787 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2788 break;
2789 default:
2790 break;
2791 }
2792 }
b6343073 2793 s->ar_flip_flop ^= 1;
e6e5ad80
FB		 2794 break;
2795 case 0x3c2:
b6343073
JQ		 2796 s->msr = val & ~0x10;
2797 s->update_retrace_info(s);
e6e5ad80
FB		 2798 break;
2799 case 0x3c4:
b6343073 2800 s->sr_index = val;
e6e5ad80
FB		 2801 break;
2802 case 0x3c5:
e6e5ad80 2803#ifdef DEBUG_VGA_REG
b6343073 2804 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
e6e5ad80 2805#endif
31c63201
JQ		 2806 cirrus_vga_write_sr(c, val);
2807 break;
e6e5ad80
FB		 2808 break;
2809 case 0x3c6:
b6343073 2810 cirrus_write_hidden_dac(c, val);
e6e5ad80
FB		 2811 break;
2812 case 0x3c7:
b6343073
JQ		 2813 s->dac_read_index = val;
2814 s->dac_sub_index = 0;
2815 s->dac_state = 3;
e6e5ad80
FB		 2816 break;
2817 case 0x3c8:
b6343073
JQ		 2818 s->dac_write_index = val;
2819 s->dac_sub_index = 0;
2820 s->dac_state = 0;
e6e5ad80
FB		 2821 break;
2822 case 0x3c9:
86948bb1
JQ		 2823 cirrus_vga_write_palette(c, val);
2824 break;
e6e5ad80 2825 case 0x3ce:
b6343073 2826 s->gr_index = val;
e6e5ad80
FB		 2827 break;
2828 case 0x3cf:
e6e5ad80 2829#ifdef DEBUG_VGA_REG
b6343073 2830 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
e6e5ad80 2831#endif
22286bc6 2832 cirrus_vga_write_gr(c, s->gr_index, val);
e6e5ad80
FB		 2833 break;
2834 case 0x3b4:
2835 case 0x3d4:
b6343073 2836 s->cr_index = val;
e6e5ad80
FB		 2837 break;
2838 case 0x3b5:
2839 case 0x3d5:
e6e5ad80 2840#ifdef DEBUG_VGA_REG
b6343073 2841 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80 2842#endif
4ec1ce04 2843 cirrus_vga_write_cr(c, val);
e6e5ad80
FB		 2844 break;
2845 case 0x3ba:
2846 case 0x3da:
b6343073 2847 s->fcr = val & 0x10;
e6e5ad80
FB		 2848 break;
2849 }
2850}
2851
e36f36e1
FB		 2852/***************************************
2853 *
2854 * memory-mapped I/O access
2855 *
2856 ***************************************/
2857
c227f099 2858static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
e36f36e1 2859{
e05587e8 2860 CirrusVGAState *s = opaque;
e36f36e1
FB		 2861
2862 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2863
2864 if (addr >= 0x100) {
2865 return cirrus_mmio_blt_read(s, addr - 0x100);
2866 } else {
0ceac75b 2867 return cirrus_vga_ioport_read(s, addr + 0x3c0);
e36f36e1
FB		 2868 }
2869}
2870
c227f099 2871static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
e36f36e1
FB		 2872{
2873 uint32_t v;
2874#ifdef TARGET_WORDS_BIGENDIAN
2875 v = cirrus_mmio_readb(opaque, addr) << 8;
2876 v |= cirrus_mmio_readb(opaque, addr + 1);
2877#else
2878 v = cirrus_mmio_readb(opaque, addr);
2879 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2880#endif
2881 return v;
2882}
2883
c227f099 2884static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
e36f36e1
FB		 2885{
2886 uint32_t v;
2887#ifdef TARGET_WORDS_BIGENDIAN
2888 v = cirrus_mmio_readb(opaque, addr) << 24;
2889 v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
2890 v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
2891 v |= cirrus_mmio_readb(opaque, addr + 3);
2892#else
2893 v = cirrus_mmio_readb(opaque, addr);
2894 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2895 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
2896 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
2897#endif
2898 return v;
2899}
2900
c227f099 2901static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
e36f36e1
FB		 2902 uint32_t val)
2903{
e05587e8 2904 CirrusVGAState *s = opaque;
e36f36e1
FB		 2905
2906 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2907
2908 if (addr >= 0x100) {
2909 cirrus_mmio_blt_write(s, addr - 0x100, val);
2910 } else {
0ceac75b 2911 cirrus_vga_ioport_write(s, addr + 0x3c0, val);
e36f36e1
FB		 2912 }
2913}
2914
c227f099 2915static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
e36f36e1
FB		 2916 uint32_t val)
2917{
2918#ifdef TARGET_WORDS_BIGENDIAN
2919 cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
2920 cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
2921#else
2922 cirrus_mmio_writeb(opaque, addr, val & 0xff);
2923 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2924#endif
2925}
2926
c227f099 2927static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
e36f36e1
FB		 2928 uint32_t val)
2929{
2930#ifdef TARGET_WORDS_BIGENDIAN
2931 cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
2932 cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2933 cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2934 cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
2935#else
2936 cirrus_mmio_writeb(opaque, addr, val & 0xff);
2937 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2938 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2939 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2940#endif
2941}
2942
2943
d60efc6b 2944static CPUReadMemoryFunc * const cirrus_mmio_read[3] = {
e36f36e1
FB		 2945 cirrus_mmio_readb,
2946 cirrus_mmio_readw,
2947 cirrus_mmio_readl,
2948};
2949
d60efc6b 2950static CPUWriteMemoryFunc * const cirrus_mmio_write[3] = {
e36f36e1
FB		 2951 cirrus_mmio_writeb,
2952 cirrus_mmio_writew,
2953 cirrus_mmio_writel,
2954};
2955
2c6ab832
FB		 2956/* load/save state */
2957
7e72abc3 2958static int cirrus_post_load(void *opaque)
2c6ab832
FB		 2959{
2960 CirrusVGAState *s = opaque;
2961
4e12cd94
AK		 2962 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
2963 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
2c6ab832 2964
2bec46dc 2965 cirrus_update_memory_access(s);
2c6ab832 2966 /* force refresh */
4e12cd94 2967 s->vga.graphic_mode = -1;
2c6ab832
FB		 2968 cirrus_update_bank_ptr(s, 0);
2969 cirrus_update_bank_ptr(s, 1);
2970 return 0;
2971}
2972
7e72abc3
JQ		 2973static const VMStateDescription vmstate_cirrus_vga = {
2974 .name = "cirrus_vga",
2975 .version_id = 2,
2976 .minimum_version_id = 1,
2977 .minimum_version_id_old = 1,
2978 .post_load = cirrus_post_load,
2979 .fields = (VMStateField []) {
2980 VMSTATE_UINT32(vga.latch, CirrusVGAState),
2981 VMSTATE_UINT8(vga.sr_index, CirrusVGAState),
2982 VMSTATE_BUFFER(vga.sr, CirrusVGAState),
2983 VMSTATE_UINT8(vga.gr_index, CirrusVGAState),
2984 VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState),
2985 VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState),
2986 VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
2987 VMSTATE_UINT8(vga.ar_index, CirrusVGAState),
2988 VMSTATE_BUFFER(vga.ar, CirrusVGAState),
2989 VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState),
2990 VMSTATE_UINT8(vga.cr_index, CirrusVGAState),
2991 VMSTATE_BUFFER(vga.cr, CirrusVGAState),
2992 VMSTATE_UINT8(vga.msr, CirrusVGAState),
2993 VMSTATE_UINT8(vga.fcr, CirrusVGAState),
2994 VMSTATE_UINT8(vga.st00, CirrusVGAState),
2995 VMSTATE_UINT8(vga.st01, CirrusVGAState),
2996 VMSTATE_UINT8(vga.dac_state, CirrusVGAState),
2997 VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState),
2998 VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState),
2999 VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState),
3000 VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState),
3001 VMSTATE_BUFFER(vga.palette, CirrusVGAState),
3002 VMSTATE_INT32(vga.bank_offset, CirrusVGAState),
3003 VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState),
3004 VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState),
3005 VMSTATE_UINT32(hw_cursor_x, CirrusVGAState),
3006 VMSTATE_UINT32(hw_cursor_y, CirrusVGAState),
3007 /* XXX: we do not save the bitblt state - we assume we do not save
3008 the state when the blitter is active */
3009 VMSTATE_END_OF_LIST()
4f335feb 3010 }
7e72abc3 3011};
4f335feb 3012
7e72abc3
JQ		 3013static const VMStateDescription vmstate_pci_cirrus_vga = {
3014 .name = "cirrus_vga",
3015 .version_id = 2,
3016 .minimum_version_id = 2,
3017 .minimum_version_id_old = 2,
3018 .post_load = cirrus_post_load,
3019 .fields = (VMStateField []) {
3020 VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState),
3021 VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
3022 vmstate_cirrus_vga, CirrusVGAState),
3023 VMSTATE_END_OF_LIST()
3024 }
3025};
4f335feb 3026
e6e5ad80
FB		 3027/***************************************
3028 *
3029 * initialize
3030 *
3031 ***************************************/
3032
4abc796d 3033static void cirrus_reset(void *opaque)
e6e5ad80 3034{
4abc796d 3035 CirrusVGAState *s = opaque;
e6e5ad80 3036
03a3e7ba 3037 vga_common_reset(&s->vga);
ee50c6bc 3038 unmap_linear_vram(s);
4e12cd94 3039 s->vga.sr[0x06] = 0x0f;
4abc796d 3040 if (s->device_id == CIRRUS_ID_CLGD5446) {
78e127ef 3041 /* 4MB 64 bit memory config, always PCI */
4e12cd94
AK		 3042 s->vga.sr[0x1F] = 0x2d; // MemClock
3043 s->vga.gr[0x18] = 0x0f; // fastest memory configuration
3044 s->vga.sr[0x0f] = 0x98;
3045 s->vga.sr[0x17] = 0x20;
3046 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
78e127ef 3047 } else {
4e12cd94
AK		 3048 s->vga.sr[0x1F] = 0x22; // MemClock
3049 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
3050 s->vga.sr[0x17] = s->bustype;
3051 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
78e127ef 3052 }
4e12cd94 3053 s->vga.cr[0x27] = s->device_id;
e6e5ad80 3054
78e127ef
FB		 3055 /* Win2K seems to assume that the pattern buffer is at 0xff
3056 initially ! */
4e12cd94 3057 memset(s->vga.vram_ptr, 0xff, s->real_vram_size);
78e127ef 3058
e6e5ad80
FB		 3059 s->cirrus_hidden_dac_lockindex = 5;
3060 s->cirrus_hidden_dac_data = 0;
4abc796d
BS		 3061}
3062
3063static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3064{
3065 int i;
3066 static int inited;
3067
3068 if (!inited) {
3069 inited = 1;
3070 for(i = 0;i < 256; i++)
3071 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
3072 rop_to_index[CIRRUS_ROP_0] = 0;
3073 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
3074 rop_to_index[CIRRUS_ROP_NOP] = 2;
3075 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
3076 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
3077 rop_to_index[CIRRUS_ROP_SRC] = 5;
3078 rop_to_index[CIRRUS_ROP_1] = 6;
3079 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
3080 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
3081 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
3082 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
3083 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
3084 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
3085 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
3086 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
3087 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
3088 s->device_id = device_id;
3089 if (is_pci)
3090 s->bustype = CIRRUS_BUSTYPE_PCI;
3091 else
3092 s->bustype = CIRRUS_BUSTYPE_ISA;
3093 }
3094
0ceac75b 3095 register_ioport_write(0x3c0, 16, 1, cirrus_vga_ioport_write, s);
4abc796d 3096
0ceac75b
JQ		 3097 register_ioport_write(0x3b4, 2, 1, cirrus_vga_ioport_write, s);
3098 register_ioport_write(0x3d4, 2, 1, cirrus_vga_ioport_write, s);
3099 register_ioport_write(0x3ba, 1, 1, cirrus_vga_ioport_write, s);
3100 register_ioport_write(0x3da, 1, 1, cirrus_vga_ioport_write, s);
4abc796d 3101
0ceac75b 3102 register_ioport_read(0x3c0, 16, 1, cirrus_vga_ioport_read, s);
4abc796d 3103
0ceac75b
JQ		 3104 register_ioport_read(0x3b4, 2, 1, cirrus_vga_ioport_read, s);
3105 register_ioport_read(0x3d4, 2, 1, cirrus_vga_ioport_read, s);
3106 register_ioport_read(0x3ba, 1, 1, cirrus_vga_ioport_read, s);
3107 register_ioport_read(0x3da, 1, 1, cirrus_vga_ioport_read, s);
4abc796d 3108
1eed09cb 3109 s->vga.vga_io_memory = cpu_register_io_memory(cirrus_vga_mem_read,
4e12cd94 3110 cirrus_vga_mem_write, s);
4abc796d 3111 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
4e12cd94 3112 s->vga.vga_io_memory);
4abc796d 3113 qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
2c6ab832 3114
fefe54e3
AL		 3115 /* I/O handler for LFB */
3116 s->cirrus_linear_io_addr =
1eed09cb 3117 cpu_register_io_memory(cirrus_linear_read, cirrus_linear_write, s);
fefe54e3
AL		 3118
3119 /* I/O handler for LFB */
3120 s->cirrus_linear_bitblt_io_addr =
1eed09cb 3121 cpu_register_io_memory(cirrus_linear_bitblt_read,
fefe54e3
AL		 3122 cirrus_linear_bitblt_write, s);
3123
3124 /* I/O handler for memory-mapped I/O */
3125 s->cirrus_mmio_io_addr =
1eed09cb 3126 cpu_register_io_memory(cirrus_mmio_read, cirrus_mmio_write, s);
fefe54e3
AL		 3127
3128 s->real_vram_size =
3129 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
3130
4e12cd94 3131 /* XXX: s->vga.vram_size must be a power of two */
fefe54e3
AL		 3132 s->cirrus_addr_mask = s->real_vram_size - 1;
3133 s->linear_mmio_mask = s->real_vram_size - 256;
3134
4e12cd94
AK		 3135 s->vga.get_bpp = cirrus_get_bpp;
3136 s->vga.get_offsets = cirrus_get_offsets;
3137 s->vga.get_resolution = cirrus_get_resolution;
3138 s->vga.cursor_invalidate = cirrus_cursor_invalidate;
3139 s->vga.cursor_draw_line = cirrus_cursor_draw_line;
fefe54e3 3140
a08d4367 3141 qemu_register_reset(cirrus_reset, s);
4abc796d 3142 cirrus_reset(s);
e6e5ad80
FB		 3143}
3144
3145/***************************************
3146 *
3147 * ISA bus support
3148 *
3149 ***************************************/
3150
fbe1b595 3151void isa_cirrus_vga_init(void)
e6e5ad80
FB		 3152{
3153 CirrusVGAState *s;
3154
3155 s = qemu_mallocz(sizeof(CirrusVGAState));
3b46e624 3156
fbe1b595 3157 vga_common_init(&s->vga, VGA_RAM_SIZE);
78e127ef 3158 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
4e12cd94
AK		 3159 s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
3160 s->vga.screen_dump, s->vga.text_update,
3161 &s->vga);
7e72abc3 3162 vmstate_register(0, &vmstate_cirrus_vga, s);
e6e5ad80
FB		 3163 /* XXX ISA-LFB support */
3164}
3165
3166/***************************************
3167 *
3168 * PCI bus support
3169 *
3170 ***************************************/
3171
3172static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3173 uint32_t addr, uint32_t size, int type)
3174{
f3566bf9 3175 CirrusVGAState *s = &DO_UPCAST(PCICirrusVGAState, dev, d)->cirrus_vga;
e6e5ad80 3176
a5082316 3177 /* XXX: add byte swapping apertures */
4e12cd94 3178 cpu_register_physical_memory(addr, s->vga.vram_size,
e6e5ad80 3179 s->cirrus_linear_io_addr);
a5082316
FB		 3180 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3181 s->cirrus_linear_bitblt_io_addr);
2bec46dc 3182
4e12cd94
AK		 3183 s->vga.map_addr = s->vga.map_end = 0;
3184 s->vga.lfb_addr = addr & TARGET_PAGE_MASK;
3185 s->vga.lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
2bec46dc 3186 /* account for overflow */
4e12cd94
AK		 3187 if (s->vga.lfb_end < addr + VGA_RAM_SIZE)
3188 s->vga.lfb_end = addr + VGA_RAM_SIZE;
ba7349cd 3189
4e12cd94 3190 vga_dirty_log_start(&s->vga);
e6e5ad80
FB		 3191}
3192
3193static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3194 uint32_t addr, uint32_t size, int type)
3195{
f3566bf9 3196 CirrusVGAState *s = &DO_UPCAST(PCICirrusVGAState, dev, d)->cirrus_vga;
e6e5ad80
FB		 3197
3198 cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3199 s->cirrus_mmio_io_addr);
3200}
3201
ba7349cd
AL		 3202static void pci_cirrus_write_config(PCIDevice *d,
3203 uint32_t address, uint32_t val, int len)
3204{
f3566bf9 3205 PCICirrusVGAState *pvs = DO_UPCAST(PCICirrusVGAState, dev, d);
ba7349cd
AL		 3206 CirrusVGAState *s = &pvs->cirrus_vga;
3207
ba7349cd 3208 pci_default_write_config(d, address, val, len);
f3566bf9 3209 if (s->vga.map_addr && d->io_regions[0].addr == -1)
4e12cd94 3210 s->vga.map_addr = 0;
ba7349cd 3211 cirrus_update_memory_access(s);
ba7349cd
AL		 3212}
3213
81a322d4 3214static int pci_cirrus_vga_initfn(PCIDevice *dev)
a414c306
GH		 3215{
3216 PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev);
3217 CirrusVGAState *s = &d->cirrus_vga;
3218 uint8_t *pci_conf = d->dev.config;
3219 int device_id = CIRRUS_ID_CLGD5446;
3220
3221 /* setup VGA */
3222 vga_common_init(&s->vga, VGA_RAM_SIZE);
3223 cirrus_init_common(s, device_id, 1);
a414c306
GH		 3224 s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
3225 s->vga.screen_dump, s->vga.text_update,
3226 &s->vga);
3227
3228 /* setup PCI */
3229 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CIRRUS);
3230 pci_config_set_device_id(pci_conf, device_id);
3231 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3232 pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
3233 pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
3234
3235 /* setup memory space */
3236 /* memory #0 LFB */
3237 /* memory #1 memory-mapped I/O */
3238 /* XXX: s->vga.vram_size must be a power of two */
3239 pci_register_bar((PCIDevice *)d, 0, 0x2000000,
3240 PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
3241 if (device_id == CIRRUS_ID_CLGD5446) {
3242 pci_register_bar((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
3243 PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
3244 }
7e72abc3 3245 vmstate_register(0, &vmstate_pci_cirrus_vga, d);
a414c306 3246 /* XXX: ROM BIOS */
81a322d4 3247 return 0;
a414c306
GH		 3248}
3249
fbe1b595 3250void pci_cirrus_vga_init(PCIBus *bus)
e6e5ad80 3251{
a414c306
GH		 3252 pci_create_simple(bus, -1, "Cirrus VGA");
3253}
d34cab9f 3254
a414c306
GH		 3255static PCIDeviceInfo cirrus_vga_info = {
3256 .qdev.name = "Cirrus VGA",
3257 .qdev.size = sizeof(PCICirrusVGAState),
3258 .init = pci_cirrus_vga_initfn,
3259 .config_write = pci_cirrus_write_config,
3260};
e6e5ad80 3261
a414c306
GH		 3262static void cirrus_vga_register(void)
3263{
3264 pci_qdev_register(&cirrus_vga_info);
e6e5ad80 3265}
a414c306 3266device_init(cirrus_vga_register);
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