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pci: fold BAR mapping function into its caller
[mirror_qemu.git] / hw / cirrus_vga.c
CommitLineData
e6e5ad80 1/*
aeb3c85f 2 * QEMU Cirrus CLGD 54xx VGA Emulator.
5fafdf24 3 *
e6e5ad80 4 * Copyright (c) 2004 Fabrice Bellard
aeb3c85f 5 * Copyright (c) 2004 Makoto Suzuki (suzu)
5fafdf24 6 *
e6e5ad80
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
aeb3c85f
FB		 25/*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
87ecb68b
PB		 29#include "hw.h"
30#include "pc.h"
31#include "pci.h"
32#include "console.h"
e6e5ad80 33#include "vga_int.h"
5245d57a 34#include "loader.h"
b1950430 35#include "exec-memory.h"
e6e5ad80 36
a5082316
FB		 37/*
38 * TODO:
ad81218e 39 * - destination write mask support not complete (bits 5..7)
a5082316
FB		 40 * - optimize linear mappings
41 * - optimize bitblt functions
42 */
43
e36f36e1 44//#define DEBUG_CIRRUS
a21ae81d 45//#define DEBUG_BITBLT
e36f36e1 46
e6e5ad80
FB		 47/***************************************
48 *
49 * definitions
50 *
51 ***************************************/
52
e6e5ad80
FB		 53// ID
54#define CIRRUS_ID_CLGD5422 (0x23<<2)
55#define CIRRUS_ID_CLGD5426 (0x24<<2)
56#define CIRRUS_ID_CLGD5424 (0x25<<2)
57#define CIRRUS_ID_CLGD5428 (0x26<<2)
58#define CIRRUS_ID_CLGD5430 (0x28<<2)
59#define CIRRUS_ID_CLGD5434 (0x2A<<2)
a21ae81d 60#define CIRRUS_ID_CLGD5436 (0x2B<<2)
e6e5ad80
FB		 61#define CIRRUS_ID_CLGD5446 (0x2E<<2)
62
63// sequencer 0x07
64#define CIRRUS_SR7_BPP_VGA 0x00
65#define CIRRUS_SR7_BPP_SVGA 0x01
66#define CIRRUS_SR7_BPP_MASK 0x0e
67#define CIRRUS_SR7_BPP_8 0x00
68#define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
69#define CIRRUS_SR7_BPP_24 0x04
70#define CIRRUS_SR7_BPP_16 0x06
71#define CIRRUS_SR7_BPP_32 0x08
72#define CIRRUS_SR7_ISAADDR_MASK 0xe0
73
74// sequencer 0x0f
75#define CIRRUS_MEMSIZE_512k 0x08
76#define CIRRUS_MEMSIZE_1M 0x10
77#define CIRRUS_MEMSIZE_2M 0x18
78#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
79
80// sequencer 0x12
81#define CIRRUS_CURSOR_SHOW 0x01
82#define CIRRUS_CURSOR_HIDDENPEL 0x02
83#define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
84
85// sequencer 0x17
86#define CIRRUS_BUSTYPE_VLBFAST 0x10
87#define CIRRUS_BUSTYPE_PCI 0x20
88#define CIRRUS_BUSTYPE_VLBSLOW 0x30
89#define CIRRUS_BUSTYPE_ISA 0x38
90#define CIRRUS_MMIO_ENABLE 0x04
91#define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
92#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
93
94// control 0x0b
95#define CIRRUS_BANKING_DUAL 0x01
96#define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
97
98// control 0x30
99#define CIRRUS_BLTMODE_BACKWARDS 0x01
100#define CIRRUS_BLTMODE_MEMSYSDEST 0x02
101#define CIRRUS_BLTMODE_MEMSYSSRC 0x04
102#define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
103#define CIRRUS_BLTMODE_PATTERNCOPY 0x40
104#define CIRRUS_BLTMODE_COLOREXPAND 0x80
105#define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
106#define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
107#define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
108#define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
109#define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
110
111// control 0x31
112#define CIRRUS_BLT_BUSY 0x01
113#define CIRRUS_BLT_START 0x02
114#define CIRRUS_BLT_RESET 0x04
115#define CIRRUS_BLT_FIFOUSED 0x10
a5082316 116#define CIRRUS_BLT_AUTOSTART 0x80
e6e5ad80
FB		 117
118// control 0x32
119#define CIRRUS_ROP_0 0x00
120#define CIRRUS_ROP_SRC_AND_DST 0x05
121#define CIRRUS_ROP_NOP 0x06
122#define CIRRUS_ROP_SRC_AND_NOTDST 0x09
123#define CIRRUS_ROP_NOTDST 0x0b
124#define CIRRUS_ROP_SRC 0x0d
125#define CIRRUS_ROP_1 0x0e
126#define CIRRUS_ROP_NOTSRC_AND_DST 0x50
127#define CIRRUS_ROP_SRC_XOR_DST 0x59
128#define CIRRUS_ROP_SRC_OR_DST 0x6d
129#define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
130#define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
131#define CIRRUS_ROP_SRC_OR_NOTDST 0xad
132#define CIRRUS_ROP_NOTSRC 0xd0
133#define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
134#define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
135
a5082316
FB		 136#define CIRRUS_ROP_NOP_INDEX 2
137#define CIRRUS_ROP_SRC_INDEX 5
138
a21ae81d 139// control 0x33
a5082316 140#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
4c8732d7 141#define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
a5082316 142#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
a21ae81d 143
e6e5ad80
FB		 144// memory-mapped IO
145#define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
146#define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
147#define CIRRUS_MMIO_BLTWIDTH 0x08 // word
148#define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
149#define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
150#define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
151#define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
152#define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
153#define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
154#define CIRRUS_MMIO_BLTMODE 0x18 // byte
155#define CIRRUS_MMIO_BLTROP 0x1a // byte
156#define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
157#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
158#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
159#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
160#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
161#define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
162#define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
163#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
164#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
165#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
166#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
167#define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
168#define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
169#define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
170#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
171#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
172#define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
173#define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
174
a21ae81d 175#define CIRRUS_PNPMMIO_SIZE 0x1000
e6e5ad80 176
b2b183c2
AL		 177#define ABS(a) ((signed)(a) > 0 ? a : -a)
178
b2eb849d
AJ		 179#define BLTUNSAFE(s) \
180 ( \
181 ( /* check dst is within bounds */ \
b2b183c2 182 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
b2eb849d 183 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
4e12cd94 184 (s)->vga.vram_size \
b2eb849d
AJ		 185 ) || \
186 ( /* check src is within bounds */ \
b2b183c2 187 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
b2eb849d 188 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
4e12cd94 189 (s)->vga.vram_size \
b2eb849d
AJ		 190 ) \
191 )
192
a5082316
FB		 193struct CirrusVGAState;
194typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
195 uint8_t * dst, const uint8_t * src,
e6e5ad80
FB		 196 int dstpitch, int srcpitch,
197 int bltwidth, int bltheight);
a5082316
FB		 198typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
199 uint8_t *dst, int dst_pitch, int width, int height);
e6e5ad80
FB		 200
201typedef struct CirrusVGAState {
4e12cd94 202 VGACommonState vga;
e6e5ad80 203
b1950430
AK		 204 MemoryRegion cirrus_linear_io;
205 MemoryRegion cirrus_linear_bitblt_io;
206 MemoryRegion cirrus_mmio_io;
207 MemoryRegion pci_bar;
208 bool linear_vram; /* vga.vram mapped over cirrus_linear_io */
209 MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */
210 MemoryRegion low_mem; /* always mapped, overridden by: */
211 MemoryRegion *cirrus_bank[2]; /* aliases at 0xa0000-0xb0000 */
e6e5ad80 212 uint32_t cirrus_addr_mask;
78e127ef 213 uint32_t linear_mmio_mask;
e6e5ad80
FB		 214 uint8_t cirrus_shadow_gr0;
215 uint8_t cirrus_shadow_gr1;
216 uint8_t cirrus_hidden_dac_lockindex;
217 uint8_t cirrus_hidden_dac_data;
218 uint32_t cirrus_bank_base[2];
219 uint32_t cirrus_bank_limit[2];
220 uint8_t cirrus_hidden_palette[48];
a5082316
FB		 221 uint32_t hw_cursor_x;
222 uint32_t hw_cursor_y;
e6e5ad80
FB		 223 int cirrus_blt_pixelwidth;
224 int cirrus_blt_width;
225 int cirrus_blt_height;
226 int cirrus_blt_dstpitch;
227 int cirrus_blt_srcpitch;
a5082316
FB		 228 uint32_t cirrus_blt_fgcol;
229 uint32_t cirrus_blt_bgcol;
e6e5ad80
FB		 230 uint32_t cirrus_blt_dstaddr;
231 uint32_t cirrus_blt_srcaddr;
232 uint8_t cirrus_blt_mode;
a5082316 233 uint8_t cirrus_blt_modeext;
e6e5ad80 234 cirrus_bitblt_rop_t cirrus_rop;
a5082316 235#define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
e6e5ad80
FB		 236 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
237 uint8_t *cirrus_srcptr;
238 uint8_t *cirrus_srcptr_end;
239 uint32_t cirrus_srccounter;
a5082316
FB		 240 /* hwcursor display state */
241 int last_hw_cursor_size;
242 int last_hw_cursor_x;
243 int last_hw_cursor_y;
244 int last_hw_cursor_y_start;
245 int last_hw_cursor_y_end;
78e127ef 246 int real_vram_size; /* XXX: suppress that */
4abc796d
BS		 247 int device_id;
248 int bustype;
e6e5ad80
FB		 249} CirrusVGAState;
250
251typedef struct PCICirrusVGAState {
252 PCIDevice dev;
253 CirrusVGAState cirrus_vga;
254} PCICirrusVGAState;
255
a5082316 256static uint8_t rop_to_index[256];
3b46e624 257
e6e5ad80
FB		 258/***************************************
259 *
260 * prototypes.
261 *
262 ***************************************/
263
264
8926b517
FB		 265static void cirrus_bitblt_reset(CirrusVGAState *s);
266static void cirrus_update_memory_access(CirrusVGAState *s);
e6e5ad80
FB		 267
268/***************************************
269 *
270 * raster operations
271 *
272 ***************************************/
273
a5082316
FB		 274static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
275 uint8_t *dst,const uint8_t *src,
276 int dstpitch,int srcpitch,
277 int bltwidth,int bltheight)
278{
e6e5ad80
FB		 279}
280
a5082316
FB		 281static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
282 uint8_t *dst,
283 int dstpitch, int bltwidth,int bltheight)
e6e5ad80 284{
a5082316 285}
e6e5ad80 286
a5082316 287#define ROP_NAME 0
8c78881f 288#define ROP_FN(d, s) 0
a5082316 289#include "cirrus_vga_rop.h"
e6e5ad80 290
a5082316 291#define ROP_NAME src_and_dst
8c78881f 292#define ROP_FN(d, s) (s) & (d)
a5082316 293#include "cirrus_vga_rop.h"
e6e5ad80 294
a5082316 295#define ROP_NAME src_and_notdst
8c78881f 296#define ROP_FN(d, s) (s) & (~(d))
a5082316 297#include "cirrus_vga_rop.h"
e6e5ad80 298
a5082316 299#define ROP_NAME notdst
8c78881f 300#define ROP_FN(d, s) ~(d)
a5082316 301#include "cirrus_vga_rop.h"
e6e5ad80 302
a5082316 303#define ROP_NAME src
8c78881f 304#define ROP_FN(d, s) s
a5082316 305#include "cirrus_vga_rop.h"
e6e5ad80 306
a5082316 307#define ROP_NAME 1
8c78881f 308#define ROP_FN(d, s) ~0
a5082316
FB		 309#include "cirrus_vga_rop.h"
310
311#define ROP_NAME notsrc_and_dst
8c78881f 312#define ROP_FN(d, s) (~(s)) & (d)
a5082316
FB		 313#include "cirrus_vga_rop.h"
314
315#define ROP_NAME src_xor_dst
8c78881f 316#define ROP_FN(d, s) (s) ^ (d)
a5082316
FB		 317#include "cirrus_vga_rop.h"
318
319#define ROP_NAME src_or_dst
8c78881f 320#define ROP_FN(d, s) (s) | (d)
a5082316
FB		 321#include "cirrus_vga_rop.h"
322
323#define ROP_NAME notsrc_or_notdst
8c78881f 324#define ROP_FN(d, s) (~(s)) | (~(d))
a5082316
FB		 325#include "cirrus_vga_rop.h"
326
327#define ROP_NAME src_notxor_dst
8c78881f 328#define ROP_FN(d, s) ~((s) ^ (d))
a5082316 329#include "cirrus_vga_rop.h"
e6e5ad80 330
a5082316 331#define ROP_NAME src_or_notdst
8c78881f 332#define ROP_FN(d, s) (s) | (~(d))
a5082316
FB		 333#include "cirrus_vga_rop.h"
334
335#define ROP_NAME notsrc
8c78881f 336#define ROP_FN(d, s) (~(s))
a5082316
FB		 337#include "cirrus_vga_rop.h"
338
339#define ROP_NAME notsrc_or_dst
8c78881f 340#define ROP_FN(d, s) (~(s)) | (d)
a5082316
FB		 341#include "cirrus_vga_rop.h"
342
343#define ROP_NAME notsrc_and_notdst
8c78881f 344#define ROP_FN(d, s) (~(s)) & (~(d))
a5082316
FB		 345#include "cirrus_vga_rop.h"
346
347static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
348 cirrus_bitblt_rop_fwd_0,
349 cirrus_bitblt_rop_fwd_src_and_dst,
350 cirrus_bitblt_rop_nop,
351 cirrus_bitblt_rop_fwd_src_and_notdst,
352 cirrus_bitblt_rop_fwd_notdst,
353 cirrus_bitblt_rop_fwd_src,
354 cirrus_bitblt_rop_fwd_1,
355 cirrus_bitblt_rop_fwd_notsrc_and_dst,
356 cirrus_bitblt_rop_fwd_src_xor_dst,
357 cirrus_bitblt_rop_fwd_src_or_dst,
358 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
359 cirrus_bitblt_rop_fwd_src_notxor_dst,
360 cirrus_bitblt_rop_fwd_src_or_notdst,
361 cirrus_bitblt_rop_fwd_notsrc,
362 cirrus_bitblt_rop_fwd_notsrc_or_dst,
363 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
364};
365
366static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
367 cirrus_bitblt_rop_bkwd_0,
368 cirrus_bitblt_rop_bkwd_src_and_dst,
369 cirrus_bitblt_rop_nop,
370 cirrus_bitblt_rop_bkwd_src_and_notdst,
371 cirrus_bitblt_rop_bkwd_notdst,
372 cirrus_bitblt_rop_bkwd_src,
373 cirrus_bitblt_rop_bkwd_1,
374 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
375 cirrus_bitblt_rop_bkwd_src_xor_dst,
376 cirrus_bitblt_rop_bkwd_src_or_dst,
377 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
378 cirrus_bitblt_rop_bkwd_src_notxor_dst,
379 cirrus_bitblt_rop_bkwd_src_or_notdst,
380 cirrus_bitblt_rop_bkwd_notsrc,
381 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
382 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
383};
96cf2df8
TS		 384
385#define TRANSP_ROP(name) {\
386 name ## _8,\
387 name ## _16,\
388 }
389#define TRANSP_NOP(func) {\
390 func,\
391 func,\
392 }
393
394static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
395 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
396 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
397 TRANSP_NOP(cirrus_bitblt_rop_nop),
398 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
399 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
400 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
401 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
402 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
403 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
404 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
405 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
406 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
407 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
408 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
409 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
410 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
411};
412
413static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
414 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
415 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
416 TRANSP_NOP(cirrus_bitblt_rop_nop),
417 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
418 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
419 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
420 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
421 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
422 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
423 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
424 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
425 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
426 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
427 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
428 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
429 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
430};
431
a5082316
FB		 432#define ROP2(name) {\
433 name ## _8,\
434 name ## _16,\
435 name ## _24,\
436 name ## _32,\
437 }
438
439#define ROP_NOP2(func) {\
440 func,\
441 func,\
442 func,\
443 func,\
444 }
445
e69390ce
FB		 446static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
447 ROP2(cirrus_patternfill_0),
448 ROP2(cirrus_patternfill_src_and_dst),
449 ROP_NOP2(cirrus_bitblt_rop_nop),
450 ROP2(cirrus_patternfill_src_and_notdst),
451 ROP2(cirrus_patternfill_notdst),
452 ROP2(cirrus_patternfill_src),
453 ROP2(cirrus_patternfill_1),
454 ROP2(cirrus_patternfill_notsrc_and_dst),
455 ROP2(cirrus_patternfill_src_xor_dst),
456 ROP2(cirrus_patternfill_src_or_dst),
457 ROP2(cirrus_patternfill_notsrc_or_notdst),
458 ROP2(cirrus_patternfill_src_notxor_dst),
459 ROP2(cirrus_patternfill_src_or_notdst),
460 ROP2(cirrus_patternfill_notsrc),
461 ROP2(cirrus_patternfill_notsrc_or_dst),
462 ROP2(cirrus_patternfill_notsrc_and_notdst),
463};
464
a5082316
FB		 465static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
466 ROP2(cirrus_colorexpand_transp_0),
467 ROP2(cirrus_colorexpand_transp_src_and_dst),
468 ROP_NOP2(cirrus_bitblt_rop_nop),
469 ROP2(cirrus_colorexpand_transp_src_and_notdst),
470 ROP2(cirrus_colorexpand_transp_notdst),
471 ROP2(cirrus_colorexpand_transp_src),
472 ROP2(cirrus_colorexpand_transp_1),
473 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
474 ROP2(cirrus_colorexpand_transp_src_xor_dst),
475 ROP2(cirrus_colorexpand_transp_src_or_dst),
476 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
477 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
478 ROP2(cirrus_colorexpand_transp_src_or_notdst),
479 ROP2(cirrus_colorexpand_transp_notsrc),
480 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
481 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
482};
483
484static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
485 ROP2(cirrus_colorexpand_0),
486 ROP2(cirrus_colorexpand_src_and_dst),
487 ROP_NOP2(cirrus_bitblt_rop_nop),
488 ROP2(cirrus_colorexpand_src_and_notdst),
489 ROP2(cirrus_colorexpand_notdst),
490 ROP2(cirrus_colorexpand_src),
491 ROP2(cirrus_colorexpand_1),
492 ROP2(cirrus_colorexpand_notsrc_and_dst),
493 ROP2(cirrus_colorexpand_src_xor_dst),
494 ROP2(cirrus_colorexpand_src_or_dst),
495 ROP2(cirrus_colorexpand_notsrc_or_notdst),
496 ROP2(cirrus_colorexpand_src_notxor_dst),
497 ROP2(cirrus_colorexpand_src_or_notdst),
498 ROP2(cirrus_colorexpand_notsrc),
499 ROP2(cirrus_colorexpand_notsrc_or_dst),
500 ROP2(cirrus_colorexpand_notsrc_and_notdst),
501};
502
b30d4608
FB		 503static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
504 ROP2(cirrus_colorexpand_pattern_transp_0),
505 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
506 ROP_NOP2(cirrus_bitblt_rop_nop),
507 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
508 ROP2(cirrus_colorexpand_pattern_transp_notdst),
509 ROP2(cirrus_colorexpand_pattern_transp_src),
510 ROP2(cirrus_colorexpand_pattern_transp_1),
511 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
512 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
513 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
514 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
515 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
516 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
517 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
518 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
519 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
520};
521
522static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
523 ROP2(cirrus_colorexpand_pattern_0),
524 ROP2(cirrus_colorexpand_pattern_src_and_dst),
525 ROP_NOP2(cirrus_bitblt_rop_nop),
526 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
527 ROP2(cirrus_colorexpand_pattern_notdst),
528 ROP2(cirrus_colorexpand_pattern_src),
529 ROP2(cirrus_colorexpand_pattern_1),
530 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
531 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
532 ROP2(cirrus_colorexpand_pattern_src_or_dst),
533 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
534 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
535 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
536 ROP2(cirrus_colorexpand_pattern_notsrc),
537 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
538 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
539};
540
a5082316
FB		 541static const cirrus_fill_t cirrus_fill[16][4] = {
542 ROP2(cirrus_fill_0),
543 ROP2(cirrus_fill_src_and_dst),
544 ROP_NOP2(cirrus_bitblt_fill_nop),
545 ROP2(cirrus_fill_src_and_notdst),
546 ROP2(cirrus_fill_notdst),
547 ROP2(cirrus_fill_src),
548 ROP2(cirrus_fill_1),
549 ROP2(cirrus_fill_notsrc_and_dst),
550 ROP2(cirrus_fill_src_xor_dst),
551 ROP2(cirrus_fill_src_or_dst),
552 ROP2(cirrus_fill_notsrc_or_notdst),
553 ROP2(cirrus_fill_src_notxor_dst),
554 ROP2(cirrus_fill_src_or_notdst),
555 ROP2(cirrus_fill_notsrc),
556 ROP2(cirrus_fill_notsrc_or_dst),
557 ROP2(cirrus_fill_notsrc_and_notdst),
558};
559
560static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
e6e5ad80 561{
a5082316
FB		 562 unsigned int color;
563 switch (s->cirrus_blt_pixelwidth) {
564 case 1:
565 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
566 break;
567 case 2:
4e12cd94 568 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
a5082316
FB		 569 s->cirrus_blt_fgcol = le16_to_cpu(color);
570 break;
571 case 3:
5fafdf24 572 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
4e12cd94 573 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
a5082316
FB		 574 break;
575 default:
576 case 4:
4e12cd94
AK		 577 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
578 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
a5082316
FB		 579 s->cirrus_blt_fgcol = le32_to_cpu(color);
580 break;
e6e5ad80
FB		 581 }
582}
583
a5082316 584static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
e6e5ad80 585{
a5082316 586 unsigned int color;
e6e5ad80
FB		 587 switch (s->cirrus_blt_pixelwidth) {
588 case 1:
a5082316
FB		 589 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
590 break;
e6e5ad80 591 case 2:
4e12cd94 592 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
a5082316
FB		 593 s->cirrus_blt_bgcol = le16_to_cpu(color);
594 break;
e6e5ad80 595 case 3:
5fafdf24 596 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
4e12cd94 597 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
a5082316 598 break;
e6e5ad80 599 default:
a5082316 600 case 4:
4e12cd94
AK		 601 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
602 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
a5082316
FB		 603 s->cirrus_blt_bgcol = le32_to_cpu(color);
604 break;
e6e5ad80
FB		 605 }
606}
607
608static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
609 int off_pitch, int bytesperline,
610 int lines)
611{
612 int y;
613 int off_cur;
614 int off_cur_end;
615
616 for (y = 0; y < lines; y++) {
617 off_cur = off_begin;
b2eb849d 618 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
e6e5ad80
FB		 619 off_cur &= TARGET_PAGE_MASK;
620 while (off_cur < off_cur_end) {
b1950430 621 memory_region_set_dirty(&s->vga.vram, off_cur);
e6e5ad80
FB		 622 off_cur += TARGET_PAGE_SIZE;
623 }
624 off_begin += off_pitch;
625 }
626}
627
e6e5ad80
FB		 628static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
629 const uint8_t * src)
630{
e6e5ad80 631 uint8_t *dst;
e6e5ad80 632
4e12cd94 633 dst = s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
b2eb849d
AJ		 634
635 if (BLTUNSAFE(s))
636 return 0;
637
e69390ce 638 (*s->cirrus_rop) (s, dst, src,
5fafdf24 639 s->cirrus_blt_dstpitch, 0,
e69390ce 640 s->cirrus_blt_width, s->cirrus_blt_height);
e6e5ad80 641 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
e69390ce
FB		 642 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
643 s->cirrus_blt_height);
e6e5ad80
FB		 644 return 1;
645}
646
a21ae81d
FB		 647/* fill */
648
a5082316 649static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
a21ae81d 650{
a5082316 651 cirrus_fill_t rop_func;
a21ae81d 652
b2eb849d
AJ		 653 if (BLTUNSAFE(s))
654 return 0;
a5082316 655 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
4e12cd94 656 rop_func(s, s->vga.vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
a5082316
FB		 657 s->cirrus_blt_dstpitch,
658 s->cirrus_blt_width, s->cirrus_blt_height);
a21ae81d
FB		 659 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
660 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
661 s->cirrus_blt_height);
662 cirrus_bitblt_reset(s);
663 return 1;
664}
665
e6e5ad80
FB		 666/***************************************
667 *
668 * bitblt (video-to-video)
669 *
670 ***************************************/
671
672static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
673{
674 return cirrus_bitblt_common_patterncopy(s,
4e12cd94 675 s->vga.vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
b2eb849d 676 s->cirrus_addr_mask));
e6e5ad80
FB		 677}
678
24236869 679static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
e6e5ad80 680{
78935c4a
AJ		 681 int sx = 0, sy = 0;
682 int dx = 0, dy = 0;
683 int depth = 0;
24236869
FB		 684 int notify = 0;
685
92d675d1
AJ		 686 /* make sure to only copy if it's a plain copy ROP */
687 if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
688 *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {
24236869 689
92d675d1
AJ		 690 int width, height;
691
692 depth = s->vga.get_bpp(&s->vga) / 8;
693 s->vga.get_resolution(&s->vga, &width, &height);
694
695 /* extra x, y */
696 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
697 sy = (src / ABS(s->cirrus_blt_srcpitch));
698 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
699 dy = (dst / ABS(s->cirrus_blt_dstpitch));
24236869 700
92d675d1
AJ		 701 /* normalize width */
702 w /= depth;
24236869 703
92d675d1
AJ		 704 /* if we're doing a backward copy, we have to adjust
705 our x/y to be the upper left corner (instead of the lower
706 right corner) */
707 if (s->cirrus_blt_dstpitch < 0) {
708 sx -= (s->cirrus_blt_width / depth) - 1;
709 dx -= (s->cirrus_blt_width / depth) - 1;
710 sy -= s->cirrus_blt_height - 1;
711 dy -= s->cirrus_blt_height - 1;
712 }
713
714 /* are we in the visible portion of memory? */
715 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
716 (sx + w) <= width && (sy + h) <= height &&
717 (dx + w) <= width && (dy + h) <= height) {
718 notify = 1;
719 }
720 }
24236869
FB		 721
722 /* we have to flush all pending changes so that the copy
723 is generated at the appropriate moment in time */
724 if (notify)
725 vga_hw_update();
726
4e12cd94 727 (*s->cirrus_rop) (s, s->vga.vram_ptr +
b2eb849d 728 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
4e12cd94 729 s->vga.vram_ptr +
b2eb849d 730 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
e6e5ad80
FB		 731 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
732 s->cirrus_blt_width, s->cirrus_blt_height);
24236869
FB		 733
734 if (notify)
4e12cd94 735 qemu_console_copy(s->vga.ds,
38334f76
AZ		 736 sx, sy, dx, dy,
737 s->cirrus_blt_width / depth,
738 s->cirrus_blt_height);
24236869
FB		 739
740 /* we don't have to notify the display that this portion has
38334f76 741 changed since qemu_console_copy implies this */
24236869 742
31c05501
AL		 743 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
744 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
745 s->cirrus_blt_height);
24236869
FB		 746}
747
748static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
749{
65d35a09
AJ		 750 if (BLTUNSAFE(s))
751 return 0;
752
4e12cd94
AK		 753 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
754 s->cirrus_blt_srcaddr - s->vga.start_addr,
7d957bd8 755 s->cirrus_blt_width, s->cirrus_blt_height);
24236869 756
e6e5ad80
FB		 757 return 1;
758}
759
760/***************************************
761 *
762 * bitblt (cpu-to-video)
763 *
764 ***************************************/
765
e6e5ad80
FB		 766static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
767{
768 int copy_count;
a5082316 769 uint8_t *end_ptr;
3b46e624 770
e6e5ad80 771 if (s->cirrus_srccounter > 0) {
a5082316
FB		 772 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
773 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
774 the_end:
775 s->cirrus_srccounter = 0;
776 cirrus_bitblt_reset(s);
777 } else {
778 /* at least one scan line */
779 do {
4e12cd94 780 (*s->cirrus_rop)(s, s->vga.vram_ptr +
b2eb849d
AJ		 781 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
782 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
a5082316
FB		 783 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
784 s->cirrus_blt_width, 1);
785 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
786 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
787 if (s->cirrus_srccounter <= 0)
788 goto the_end;
789 /* more bytes than needed can be transfered because of
790 word alignment, so we keep them for the next line */
791 /* XXX: keep alignment to speed up transfer */
792 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
793 copy_count = s->cirrus_srcptr_end - end_ptr;
794 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
795 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
796 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
797 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
798 }
e6e5ad80
FB		 799 }
800}
801
802/***************************************
803 *
804 * bitblt wrapper
805 *
806 ***************************************/
807
808static void cirrus_bitblt_reset(CirrusVGAState * s)
809{
f8b237af
AL		 810 int need_update;
811
4e12cd94 812 s->vga.gr[0x31] &=
e6e5ad80 813 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
f8b237af
AL		 814 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
815 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
e6e5ad80
FB		 816 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
817 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
818 s->cirrus_srccounter = 0;
f8b237af
AL		 819 if (!need_update)
820 return;
8926b517 821 cirrus_update_memory_access(s);
e6e5ad80
FB		 822}
823
824static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
825{
a5082316
FB		 826 int w;
827
e6e5ad80
FB		 828 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
829 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
830 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
831
832 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
833 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 834 s->cirrus_blt_srcpitch = 8;
e6e5ad80 835 } else {
b30d4608 836 /* XXX: check for 24 bpp */
a5082316 837 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
e6e5ad80 838 }
a5082316 839 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
e6e5ad80
FB		 840 } else {
841 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 842 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
5fafdf24 843 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
a5082316
FB		 844 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
845 else
846 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
e6e5ad80 847 } else {
c9c0eae8
FB		 848 /* always align input size to 32 bits */
849 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
e6e5ad80 850 }
a5082316 851 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
e6e5ad80 852 }
a5082316
FB		 853 s->cirrus_srcptr = s->cirrus_bltbuf;
854 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
8926b517 855 cirrus_update_memory_access(s);
e6e5ad80
FB		 856 return 1;
857}
858
859static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
860{
861 /* XXX */
a5082316 862#ifdef DEBUG_BITBLT
e6e5ad80
FB		 863 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
864#endif
865 return 0;
866}
867
868static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
869{
870 int ret;
871
872 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
873 ret = cirrus_bitblt_videotovideo_patterncopy(s);
874 } else {
875 ret = cirrus_bitblt_videotovideo_copy(s);
876 }
e6e5ad80
FB		 877 if (ret)
878 cirrus_bitblt_reset(s);
879 return ret;
880}
881
882static void cirrus_bitblt_start(CirrusVGAState * s)
883{
884 uint8_t blt_rop;
885
4e12cd94 886 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
a5082316 887
4e12cd94
AK		 888 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
889 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
890 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
891 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
e6e5ad80 892 s->cirrus_blt_dstaddr =
4e12cd94 893 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
e6e5ad80 894 s->cirrus_blt_srcaddr =
4e12cd94
AK		 895 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
896 s->cirrus_blt_mode = s->vga.gr[0x30];
897 s->cirrus_blt_modeext = s->vga.gr[0x33];
898 blt_rop = s->vga.gr[0x32];
e6e5ad80 899
a21ae81d 900#ifdef DEBUG_BITBLT
0b74ed78 901 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
5fafdf24 902 blt_rop,
a21ae81d 903 s->cirrus_blt_mode,
a5082316 904 s->cirrus_blt_modeext,
a21ae81d
FB		 905 s->cirrus_blt_width,
906 s->cirrus_blt_height,
907 s->cirrus_blt_dstpitch,
908 s->cirrus_blt_srcpitch,
909 s->cirrus_blt_dstaddr,
a5082316 910 s->cirrus_blt_srcaddr,
4e12cd94 911 s->vga.gr[0x2f]);
a21ae81d
FB		 912#endif
913
e6e5ad80
FB		 914 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
915 case CIRRUS_BLTMODE_PIXELWIDTH8:
916 s->cirrus_blt_pixelwidth = 1;
917 break;
918 case CIRRUS_BLTMODE_PIXELWIDTH16:
919 s->cirrus_blt_pixelwidth = 2;
920 break;
921 case CIRRUS_BLTMODE_PIXELWIDTH24:
922 s->cirrus_blt_pixelwidth = 3;
923 break;
924 case CIRRUS_BLTMODE_PIXELWIDTH32:
925 s->cirrus_blt_pixelwidth = 4;
926 break;
927 default:
a5082316 928#ifdef DEBUG_BITBLT
e6e5ad80
FB		 929 printf("cirrus: bitblt - pixel width is unknown\n");
930#endif
931 goto bitblt_ignore;
932 }
933 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
934
935 if ((s->
936 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
937 CIRRUS_BLTMODE_MEMSYSDEST))
938 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
a5082316 939#ifdef DEBUG_BITBLT
e6e5ad80
FB		 940 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
941#endif
942 goto bitblt_ignore;
943 }
944
a5082316 945 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
5fafdf24 946 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
a21ae81d 947 CIRRUS_BLTMODE_TRANSPARENTCOMP |
5fafdf24
TS		 948 CIRRUS_BLTMODE_PATTERNCOPY |
949 CIRRUS_BLTMODE_COLOREXPAND)) ==
a21ae81d 950 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
a5082316
FB		 951 cirrus_bitblt_fgcol(s);
952 cirrus_bitblt_solidfill(s, blt_rop);
e6e5ad80 953 } else {
5fafdf24
TS		 954 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
955 CIRRUS_BLTMODE_PATTERNCOPY)) ==
a5082316
FB		 956 CIRRUS_BLTMODE_COLOREXPAND) {
957
958 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
b30d4608 959 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
4c8732d7 960 cirrus_bitblt_bgcol(s);
b30d4608 961 else
4c8732d7 962 cirrus_bitblt_fgcol(s);
b30d4608 963 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
a5082316
FB		 964 } else {
965 cirrus_bitblt_fgcol(s);
966 cirrus_bitblt_bgcol(s);
967 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
968 }
e69390ce 969 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
b30d4608
FB		 970 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
971 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
972 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
973 cirrus_bitblt_bgcol(s);
974 else
975 cirrus_bitblt_fgcol(s);
976 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
977 } else {
978 cirrus_bitblt_fgcol(s);
979 cirrus_bitblt_bgcol(s);
980 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
981 }
982 } else {
983 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
984 }
a21ae81d 985 } else {
96cf2df8
TS		 986 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
987 if (s->cirrus_blt_pixelwidth > 2) {
988 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
989 goto bitblt_ignore;
990 }
991 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
992 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
993 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
994 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
995 } else {
996 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
997 }
998 } else {
999 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1000 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1001 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1002 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1003 } else {
1004 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1005 }
1006 }
1007 }
a21ae81d
FB		 1008 // setup bitblt engine.
1009 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1010 if (!cirrus_bitblt_cputovideo(s))
1011 goto bitblt_ignore;
1012 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1013 if (!cirrus_bitblt_videotocpu(s))
1014 goto bitblt_ignore;
1015 } else {
1016 if (!cirrus_bitblt_videotovideo(s))
1017 goto bitblt_ignore;
1018 }
e6e5ad80 1019 }
e6e5ad80
FB		 1020 return;
1021 bitblt_ignore:;
1022 cirrus_bitblt_reset(s);
1023}
1024
1025static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1026{
1027 unsigned old_value;
1028
4e12cd94
AK		 1029 old_value = s->vga.gr[0x31];
1030 s->vga.gr[0x31] = reg_value;
e6e5ad80
FB		 1031
1032 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1033 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1034 cirrus_bitblt_reset(s);
1035 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1036 ((reg_value & CIRRUS_BLT_START) != 0)) {
e6e5ad80
FB		 1037 cirrus_bitblt_start(s);
1038 }
1039}
1040
1041
1042/***************************************
1043 *
1044 * basic parameters
1045 *
1046 ***************************************/
1047
a4a2f59c 1048static void cirrus_get_offsets(VGACommonState *s1,
83acc96b
FB		 1049 uint32_t *pline_offset,
1050 uint32_t *pstart_addr,
1051 uint32_t *pline_compare)
e6e5ad80 1052{
4e12cd94 1053 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
83acc96b 1054 uint32_t start_addr, line_offset, line_compare;
e6e5ad80 1055
4e12cd94
AK		 1056 line_offset = s->vga.cr[0x13]
1057 | ((s->vga.cr[0x1b] & 0x10) << 4);
e6e5ad80
FB		 1058 line_offset <<= 3;
1059 *pline_offset = line_offset;
1060
4e12cd94
AK		 1061 start_addr = (s->vga.cr[0x0c] << 8)
1062 | s->vga.cr[0x0d]
1063 | ((s->vga.cr[0x1b] & 0x01) << 16)
1064 | ((s->vga.cr[0x1b] & 0x0c) << 15)
1065 | ((s->vga.cr[0x1d] & 0x80) << 12);
e6e5ad80 1066 *pstart_addr = start_addr;
83acc96b 1067
4e12cd94
AK		 1068 line_compare = s->vga.cr[0x18] |
1069 ((s->vga.cr[0x07] & 0x10) << 4) |
1070 ((s->vga.cr[0x09] & 0x40) << 3);
83acc96b 1071 *pline_compare = line_compare;
e6e5ad80
FB		 1072}
1073
1074static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1075{
1076 uint32_t ret = 16;
1077
1078 switch (s->cirrus_hidden_dac_data & 0xf) {
1079 case 0:
1080 ret = 15;
1081 break; /* Sierra HiColor */
1082 case 1:
1083 ret = 16;
1084 break; /* XGA HiColor */
1085 default:
1086#ifdef DEBUG_CIRRUS
1087 printf("cirrus: invalid DAC value %x in 16bpp\n",
1088 (s->cirrus_hidden_dac_data & 0xf));
1089#endif
1090 ret = 15; /* XXX */
1091 break;
1092 }
1093 return ret;
1094}
1095
a4a2f59c 1096static int cirrus_get_bpp(VGACommonState *s1)
e6e5ad80 1097{
4e12cd94 1098 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
e6e5ad80
FB		 1099 uint32_t ret = 8;
1100
4e12cd94 1101 if ((s->vga.sr[0x07] & 0x01) != 0) {
e6e5ad80 1102 /* Cirrus SVGA */
4e12cd94 1103 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
e6e5ad80
FB		 1104 case CIRRUS_SR7_BPP_8:
1105 ret = 8;
1106 break;
1107 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1108 ret = cirrus_get_bpp16_depth(s);
1109 break;
1110 case CIRRUS_SR7_BPP_24:
1111 ret = 24;
1112 break;
1113 case CIRRUS_SR7_BPP_16:
1114 ret = cirrus_get_bpp16_depth(s);
1115 break;
1116 case CIRRUS_SR7_BPP_32:
1117 ret = 32;
1118 break;
1119 default:
1120#ifdef DEBUG_CIRRUS
4e12cd94 1121 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
e6e5ad80
FB		 1122#endif
1123 ret = 8;
1124 break;
1125 }
1126 } else {
1127 /* VGA */
aeb3c85f 1128 ret = 0;
e6e5ad80
FB		 1129 }
1130
1131 return ret;
1132}
1133
a4a2f59c 1134static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
78e127ef
FB		 1135{
1136 int width, height;
3b46e624 1137
78e127ef 1138 width = (s->cr[0x01] + 1) * 8;
5fafdf24
TS		 1139 height = s->cr[0x12] |
1140 ((s->cr[0x07] & 0x02) << 7) |
78e127ef
FB		 1141 ((s->cr[0x07] & 0x40) << 3);
1142 height = (height + 1);
1143 /* interlace support */
1144 if (s->cr[0x1a] & 0x01)
1145 height = height * 2;
1146 *pwidth = width;
1147 *pheight = height;
1148}
1149
e6e5ad80
FB		 1150/***************************************
1151 *
1152 * bank memory
1153 *
1154 ***************************************/
1155
1156static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1157{
1158 unsigned offset;
1159 unsigned limit;
1160
4e12cd94
AK		 1161 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */
1162 offset = s->vga.gr[0x09 + bank_index];
e6e5ad80 1163 else /* single bank */
4e12cd94 1164 offset = s->vga.gr[0x09];
e6e5ad80 1165
4e12cd94 1166 if ((s->vga.gr[0x0b] & 0x20) != 0)
e6e5ad80
FB		 1167 offset <<= 14;
1168 else
1169 offset <<= 12;
1170
e3a4e4b6 1171 if (s->real_vram_size <= offset)
e6e5ad80
FB		 1172 limit = 0;
1173 else
e3a4e4b6 1174 limit = s->real_vram_size - offset;
e6e5ad80 1175
4e12cd94 1176 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
e6e5ad80
FB		 1177 if (limit > 0x8000) {
1178 offset += 0x8000;
1179 limit -= 0x8000;
1180 } else {
1181 limit = 0;
1182 }
1183 }
1184
1185 if (limit > 0) {
1186 s->cirrus_bank_base[bank_index] = offset;
1187 s->cirrus_bank_limit[bank_index] = limit;
1188 } else {
1189 s->cirrus_bank_base[bank_index] = 0;
1190 s->cirrus_bank_limit[bank_index] = 0;
1191 }
1192}
1193
1194/***************************************
1195 *
1196 * I/O access between 0x3c4-0x3c5
1197 *
1198 ***************************************/
1199
8a82c322 1200static int cirrus_vga_read_sr(CirrusVGAState * s)
e6e5ad80 1201{
8a82c322 1202 switch (s->vga.sr_index) {
e6e5ad80
FB		 1203 case 0x00: // Standard VGA
1204 case 0x01: // Standard VGA
1205 case 0x02: // Standard VGA
1206 case 0x03: // Standard VGA
1207 case 0x04: // Standard VGA
8a82c322 1208 return s->vga.sr[s->vga.sr_index];
e6e5ad80 1209 case 0x06: // Unlock Cirrus extensions
8a82c322 1210 return s->vga.sr[s->vga.sr_index];
e6e5ad80
FB		 1211 case 0x10:
1212 case 0x30:
1213 case 0x50:
1214 case 0x70: // Graphics Cursor X
1215 case 0x90:
1216 case 0xb0:
1217 case 0xd0:
1218 case 0xf0: // Graphics Cursor X
8a82c322 1219 return s->vga.sr[0x10];
e6e5ad80
FB		 1220 case 0x11:
1221 case 0x31:
1222 case 0x51:
1223 case 0x71: // Graphics Cursor Y
1224 case 0x91:
1225 case 0xb1:
1226 case 0xd1:
a5082316 1227 case 0xf1: // Graphics Cursor Y
8a82c322 1228 return s->vga.sr[0x11];
aeb3c85f
FB		 1229 case 0x05: // ???
1230 case 0x07: // Extended Sequencer Mode
1231 case 0x08: // EEPROM Control
1232 case 0x09: // Scratch Register 0
1233 case 0x0a: // Scratch Register 1
1234 case 0x0b: // VCLK 0
1235 case 0x0c: // VCLK 1
1236 case 0x0d: // VCLK 2
1237 case 0x0e: // VCLK 3
1238 case 0x0f: // DRAM Control
e6e5ad80
FB		 1239 case 0x12: // Graphics Cursor Attribute
1240 case 0x13: // Graphics Cursor Pattern Address
1241 case 0x14: // Scratch Register 2
1242 case 0x15: // Scratch Register 3
1243 case 0x16: // Performance Tuning Register
1244 case 0x17: // Configuration Readback and Extended Control
1245 case 0x18: // Signature Generator Control
1246 case 0x19: // Signal Generator Result
1247 case 0x1a: // Signal Generator Result
1248 case 0x1b: // VCLK 0 Denominator & Post
1249 case 0x1c: // VCLK 1 Denominator & Post
1250 case 0x1d: // VCLK 2 Denominator & Post
1251 case 0x1e: // VCLK 3 Denominator & Post
1252 case 0x1f: // BIOS Write Enable and MCLK select
1253#ifdef DEBUG_CIRRUS
8a82c322 1254 printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
e6e5ad80 1255#endif
8a82c322 1256 return s->vga.sr[s->vga.sr_index];
e6e5ad80
FB		 1257 default:
1258#ifdef DEBUG_CIRRUS
8a82c322 1259 printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
e6e5ad80 1260#endif
8a82c322 1261 return 0xff;
e6e5ad80
FB		 1262 break;
1263 }
e6e5ad80
FB		 1264}
1265
31c63201 1266static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
e6e5ad80 1267{
31c63201 1268 switch (s->vga.sr_index) {
e6e5ad80
FB		 1269 case 0x00: // Standard VGA
1270 case 0x01: // Standard VGA
1271 case 0x02: // Standard VGA
1272 case 0x03: // Standard VGA
1273 case 0x04: // Standard VGA
31c63201
JQ		 1274 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
1275 if (s->vga.sr_index == 1)
1276 s->vga.update_retrace_info(&s->vga);
1277 break;
e6e5ad80 1278 case 0x06: // Unlock Cirrus extensions
31c63201
JQ		 1279 val &= 0x17;
1280 if (val == 0x12) {
1281 s->vga.sr[s->vga.sr_index] = 0x12;
e6e5ad80 1282 } else {
31c63201 1283 s->vga.sr[s->vga.sr_index] = 0x0f;
e6e5ad80
FB		 1284 }
1285 break;
1286 case 0x10:
1287 case 0x30:
1288 case 0x50:
1289 case 0x70: // Graphics Cursor X
1290 case 0x90:
1291 case 0xb0:
1292 case 0xd0:
1293 case 0xf0: // Graphics Cursor X
31c63201
JQ		 1294 s->vga.sr[0x10] = val;
1295 s->hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1296 break;
1297 case 0x11:
1298 case 0x31:
1299 case 0x51:
1300 case 0x71: // Graphics Cursor Y
1301 case 0x91:
1302 case 0xb1:
1303 case 0xd1:
1304 case 0xf1: // Graphics Cursor Y
31c63201
JQ		 1305 s->vga.sr[0x11] = val;
1306 s->hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
e6e5ad80
FB		 1307 break;
1308 case 0x07: // Extended Sequencer Mode
2bec46dc 1309 cirrus_update_memory_access(s);
e6e5ad80
FB		 1310 case 0x08: // EEPROM Control
1311 case 0x09: // Scratch Register 0
1312 case 0x0a: // Scratch Register 1
1313 case 0x0b: // VCLK 0
1314 case 0x0c: // VCLK 1
1315 case 0x0d: // VCLK 2
1316 case 0x0e: // VCLK 3
1317 case 0x0f: // DRAM Control
1318 case 0x12: // Graphics Cursor Attribute
1319 case 0x13: // Graphics Cursor Pattern Address
1320 case 0x14: // Scratch Register 2
1321 case 0x15: // Scratch Register 3
1322 case 0x16: // Performance Tuning Register
e6e5ad80
FB		 1323 case 0x18: // Signature Generator Control
1324 case 0x19: // Signature Generator Result
1325 case 0x1a: // Signature Generator Result
1326 case 0x1b: // VCLK 0 Denominator & Post
1327 case 0x1c: // VCLK 1 Denominator & Post
1328 case 0x1d: // VCLK 2 Denominator & Post
1329 case 0x1e: // VCLK 3 Denominator & Post
1330 case 0x1f: // BIOS Write Enable and MCLK select
31c63201 1331 s->vga.sr[s->vga.sr_index] = val;
e6e5ad80
FB		 1332#ifdef DEBUG_CIRRUS
1333 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
31c63201 1334 s->vga.sr_index, val);
e6e5ad80
FB		 1335#endif
1336 break;
8926b517 1337 case 0x17: // Configuration Readback and Extended Control
31c63201
JQ		 1338 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
1339 | (val & 0xc7);
8926b517
FB		 1340 cirrus_update_memory_access(s);
1341 break;
e6e5ad80
FB		 1342 default:
1343#ifdef DEBUG_CIRRUS
31c63201
JQ		 1344 printf("cirrus: outport sr_index %02x, sr_value %02x\n",
1345 s->vga.sr_index, val);
e6e5ad80
FB		 1346#endif
1347 break;
1348 }
e6e5ad80
FB		 1349}
1350
1351/***************************************
1352 *
1353 * I/O access at 0x3c6
1354 *
1355 ***************************************/
1356
957c9db5 1357static int cirrus_read_hidden_dac(CirrusVGAState * s)
e6e5ad80 1358{
a21ae81d 1359 if (++s->cirrus_hidden_dac_lockindex == 5) {
957c9db5
JQ		 1360 s->cirrus_hidden_dac_lockindex = 0;
1361 return s->cirrus_hidden_dac_data;
e6e5ad80 1362 }
957c9db5 1363 return 0xff;
e6e5ad80
FB		 1364}
1365
1366static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1367{
1368 if (s->cirrus_hidden_dac_lockindex == 4) {
1369 s->cirrus_hidden_dac_data = reg_value;
a21ae81d 1370#if defined(DEBUG_CIRRUS)
e6e5ad80
FB		 1371 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1372#endif
1373 }
1374 s->cirrus_hidden_dac_lockindex = 0;
1375}
1376
1377/***************************************
1378 *
1379 * I/O access at 0x3c9
1380 *
1381 ***************************************/
1382
5deaeee3 1383static int cirrus_vga_read_palette(CirrusVGAState * s)
e6e5ad80 1384{
5deaeee3
JQ		 1385 int val;
1386
1387 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1388 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1389 s->vga.dac_sub_index];
1390 } else {
1391 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
1392 }
4e12cd94
AK		 1393 if (++s->vga.dac_sub_index == 3) {
1394 s->vga.dac_sub_index = 0;
1395 s->vga.dac_read_index++;
e6e5ad80 1396 }
5deaeee3 1397 return val;
e6e5ad80
FB		 1398}
1399
86948bb1 1400static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value)
e6e5ad80 1401{
4e12cd94
AK		 1402 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1403 if (++s->vga.dac_sub_index == 3) {
86948bb1
JQ		 1404 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1405 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1406 s->vga.dac_cache, 3);
1407 } else {
1408 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
1409 }
a5082316 1410 /* XXX update cursor */
4e12cd94
AK		 1411 s->vga.dac_sub_index = 0;
1412 s->vga.dac_write_index++;
e6e5ad80 1413 }
e6e5ad80
FB		 1414}
1415
1416/***************************************
1417 *
1418 * I/O access between 0x3ce-0x3cf
1419 *
1420 ***************************************/
1421
f705db9d 1422static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1423{
1424 switch (reg_index) {
aeb3c85f 1425 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
f705db9d 1426 return s->cirrus_shadow_gr0;
aeb3c85f 1427 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
f705db9d 1428 return s->cirrus_shadow_gr1;
e6e5ad80
FB		 1429 case 0x02: // Standard VGA
1430 case 0x03: // Standard VGA
1431 case 0x04: // Standard VGA
1432 case 0x06: // Standard VGA
1433 case 0x07: // Standard VGA
1434 case 0x08: // Standard VGA
f705db9d 1435 return s->vga.gr[s->vga.gr_index];
e6e5ad80
FB		 1436 case 0x05: // Standard VGA, Cirrus extended mode
1437 default:
1438 break;
1439 }
1440
1441 if (reg_index < 0x3a) {
f705db9d 1442 return s->vga.gr[reg_index];
e6e5ad80
FB		 1443 } else {
1444#ifdef DEBUG_CIRRUS
1445 printf("cirrus: inport gr_index %02x\n", reg_index);
1446#endif
f705db9d 1447 return 0xff;
e6e5ad80 1448 }
e6e5ad80
FB		 1449}
1450
22286bc6
JQ		 1451static void
1452cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
e6e5ad80 1453{
a5082316
FB		 1454#if defined(DEBUG_BITBLT) && 0
1455 printf("gr%02x: %02x\n", reg_index, reg_value);
1456#endif
e6e5ad80
FB		 1457 switch (reg_index) {
1458 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
f22f5b07 1459 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
aeb3c85f 1460 s->cirrus_shadow_gr0 = reg_value;
22286bc6 1461 break;
e6e5ad80 1462 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
f22f5b07 1463 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
aeb3c85f 1464 s->cirrus_shadow_gr1 = reg_value;
22286bc6 1465 break;
e6e5ad80
FB		 1466 case 0x02: // Standard VGA
1467 case 0x03: // Standard VGA
1468 case 0x04: // Standard VGA
1469 case 0x06: // Standard VGA
1470 case 0x07: // Standard VGA
1471 case 0x08: // Standard VGA
22286bc6
JQ		 1472 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1473 break;
e6e5ad80 1474 case 0x05: // Standard VGA, Cirrus extended mode
4e12cd94 1475 s->vga.gr[reg_index] = reg_value & 0x7f;
8926b517 1476 cirrus_update_memory_access(s);
e6e5ad80
FB		 1477 break;
1478 case 0x09: // bank offset #0
1479 case 0x0A: // bank offset #1
4e12cd94 1480 s->vga.gr[reg_index] = reg_value;
8926b517
FB		 1481 cirrus_update_bank_ptr(s, 0);
1482 cirrus_update_bank_ptr(s, 1);
2bec46dc 1483 cirrus_update_memory_access(s);
8926b517 1484 break;
e6e5ad80 1485 case 0x0B:
4e12cd94 1486 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1487 cirrus_update_bank_ptr(s, 0);
1488 cirrus_update_bank_ptr(s, 1);
8926b517 1489 cirrus_update_memory_access(s);
e6e5ad80
FB		 1490 break;
1491 case 0x10: // BGCOLOR 0x0000ff00
1492 case 0x11: // FGCOLOR 0x0000ff00
1493 case 0x12: // BGCOLOR 0x00ff0000
1494 case 0x13: // FGCOLOR 0x00ff0000
1495 case 0x14: // BGCOLOR 0xff000000
1496 case 0x15: // FGCOLOR 0xff000000
1497 case 0x20: // BLT WIDTH 0x0000ff
1498 case 0x22: // BLT HEIGHT 0x0000ff
1499 case 0x24: // BLT DEST PITCH 0x0000ff
1500 case 0x26: // BLT SRC PITCH 0x0000ff
1501 case 0x28: // BLT DEST ADDR 0x0000ff
1502 case 0x29: // BLT DEST ADDR 0x00ff00
1503 case 0x2c: // BLT SRC ADDR 0x0000ff
1504 case 0x2d: // BLT SRC ADDR 0x00ff00
a5082316 1505 case 0x2f: // BLT WRITEMASK
e6e5ad80
FB		 1506 case 0x30: // BLT MODE
1507 case 0x32: // RASTER OP
a21ae81d 1508 case 0x33: // BLT MODEEXT
e6e5ad80
FB		 1509 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1510 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1511 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1512 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
4e12cd94 1513 s->vga.gr[reg_index] = reg_value;
e6e5ad80
FB		 1514 break;
1515 case 0x21: // BLT WIDTH 0x001f00
1516 case 0x23: // BLT HEIGHT 0x001f00
1517 case 0x25: // BLT DEST PITCH 0x001f00
1518 case 0x27: // BLT SRC PITCH 0x001f00
4e12cd94 1519 s->vga.gr[reg_index] = reg_value & 0x1f;
e6e5ad80
FB		 1520 break;
1521 case 0x2a: // BLT DEST ADDR 0x3f0000
4e12cd94 1522 s->vga.gr[reg_index] = reg_value & 0x3f;
a5082316 1523 /* if auto start mode, starts bit blt now */
4e12cd94 1524 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
a5082316
FB		 1525 cirrus_bitblt_start(s);
1526 }
1527 break;
e6e5ad80 1528 case 0x2e: // BLT SRC ADDR 0x3f0000
4e12cd94 1529 s->vga.gr[reg_index] = reg_value & 0x3f;
e6e5ad80
FB		 1530 break;
1531 case 0x31: // BLT STATUS/START
1532 cirrus_write_bitblt(s, reg_value);
1533 break;
1534 default:
1535#ifdef DEBUG_CIRRUS
1536 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1537 reg_value);
1538#endif
1539 break;
1540 }
e6e5ad80
FB		 1541}
1542
1543/***************************************
1544 *
1545 * I/O access between 0x3d4-0x3d5
1546 *
1547 ***************************************/
1548
b863d514 1549static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
e6e5ad80
FB		 1550{
1551 switch (reg_index) {
1552 case 0x00: // Standard VGA
1553 case 0x01: // Standard VGA
1554 case 0x02: // Standard VGA
1555 case 0x03: // Standard VGA
1556 case 0x04: // Standard VGA
1557 case 0x05: // Standard VGA
1558 case 0x06: // Standard VGA
1559 case 0x07: // Standard VGA
1560 case 0x08: // Standard VGA
1561 case 0x09: // Standard VGA
1562 case 0x0a: // Standard VGA
1563 case 0x0b: // Standard VGA
1564 case 0x0c: // Standard VGA
1565 case 0x0d: // Standard VGA
1566 case 0x0e: // Standard VGA
1567 case 0x0f: // Standard VGA
1568 case 0x10: // Standard VGA
1569 case 0x11: // Standard VGA
1570 case 0x12: // Standard VGA
1571 case 0x13: // Standard VGA
1572 case 0x14: // Standard VGA
1573 case 0x15: // Standard VGA
1574 case 0x16: // Standard VGA
1575 case 0x17: // Standard VGA
1576 case 0x18: // Standard VGA
b863d514 1577 return s->vga.cr[s->vga.cr_index];
ca896ef3 1578 case 0x24: // Attribute Controller Toggle Readback (R)
b863d514 1579 return (s->vga.ar_flip_flop << 7);
e6e5ad80
FB		 1580 case 0x19: // Interlace End
1581 case 0x1a: // Miscellaneous Control
1582 case 0x1b: // Extended Display Control
1583 case 0x1c: // Sync Adjust and Genlock
1584 case 0x1d: // Overlay Extended Control
1585 case 0x22: // Graphics Data Latches Readback (R)
e6e5ad80
FB		 1586 case 0x25: // Part Status
1587 case 0x27: // Part ID (R)
b863d514 1588 return s->vga.cr[s->vga.cr_index];
e6e5ad80 1589 case 0x26: // Attribute Controller Index Readback (R)
b863d514 1590 return s->vga.ar_index & 0x3f;
e6e5ad80
FB		 1591 break;
1592 default:
1593#ifdef DEBUG_CIRRUS
1594 printf("cirrus: inport cr_index %02x\n", reg_index);
e6e5ad80 1595#endif
b863d514 1596 return 0xff;
e6e5ad80 1597 }
e6e5ad80
FB		 1598}
1599
4ec1ce04 1600static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
e6e5ad80 1601{
4ec1ce04 1602 switch (s->vga.cr_index) {
e6e5ad80
FB		 1603 case 0x00: // Standard VGA
1604 case 0x01: // Standard VGA
1605 case 0x02: // Standard VGA
1606 case 0x03: // Standard VGA
1607 case 0x04: // Standard VGA
1608 case 0x05: // Standard VGA
1609 case 0x06: // Standard VGA
1610 case 0x07: // Standard VGA
1611 case 0x08: // Standard VGA
1612 case 0x09: // Standard VGA
1613 case 0x0a: // Standard VGA
1614 case 0x0b: // Standard VGA
1615 case 0x0c: // Standard VGA
1616 case 0x0d: // Standard VGA
1617 case 0x0e: // Standard VGA
1618 case 0x0f: // Standard VGA
1619 case 0x10: // Standard VGA
1620 case 0x11: // Standard VGA
1621 case 0x12: // Standard VGA
1622 case 0x13: // Standard VGA
1623 case 0x14: // Standard VGA
1624 case 0x15: // Standard VGA
1625 case 0x16: // Standard VGA
1626 case 0x17: // Standard VGA
1627 case 0x18: // Standard VGA
4ec1ce04
JQ		 1628 /* handle CR0-7 protection */
1629 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
1630 /* can always write bit 4 of CR7 */
1631 if (s->vga.cr_index == 7)
1632 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10);
1633 return;
1634 }
1635 s->vga.cr[s->vga.cr_index] = reg_value;
1636 switch(s->vga.cr_index) {
1637 case 0x00:
1638 case 0x04:
1639 case 0x05:
1640 case 0x06:
1641 case 0x07:
1642 case 0x11:
1643 case 0x17:
1644 s->vga.update_retrace_info(&s->vga);
1645 break;
1646 }
1647 break;
e6e5ad80
FB		 1648 case 0x19: // Interlace End
1649 case 0x1a: // Miscellaneous Control
1650 case 0x1b: // Extended Display Control
1651 case 0x1c: // Sync Adjust and Genlock
ae184e4a 1652 case 0x1d: // Overlay Extended Control
4ec1ce04 1653 s->vga.cr[s->vga.cr_index] = reg_value;
e6e5ad80
FB		 1654#ifdef DEBUG_CIRRUS
1655 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
4ec1ce04 1656 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1657#endif
1658 break;
1659 case 0x22: // Graphics Data Latches Readback (R)
1660 case 0x24: // Attribute Controller Toggle Readback (R)
1661 case 0x26: // Attribute Controller Index Readback (R)
1662 case 0x27: // Part ID (R)
1663 break;
e6e5ad80
FB		 1664 case 0x25: // Part Status
1665 default:
1666#ifdef DEBUG_CIRRUS
4ec1ce04
JQ		 1667 printf("cirrus: outport cr_index %02x, cr_value %02x\n",
1668 s->vga.cr_index, reg_value);
e6e5ad80
FB		 1669#endif
1670 break;
1671 }
e6e5ad80
FB		 1672}
1673
1674/***************************************
1675 *
1676 * memory-mapped I/O (bitblt)
1677 *
1678 ***************************************/
1679
1680static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1681{
1682 int value = 0xff;
1683
1684 switch (address) {
1685 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
f705db9d 1686 value = cirrus_vga_read_gr(s, 0x00);
e6e5ad80
FB		 1687 break;
1688 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
f705db9d 1689 value = cirrus_vga_read_gr(s, 0x10);
e6e5ad80
FB		 1690 break;
1691 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
f705db9d 1692 value = cirrus_vga_read_gr(s, 0x12);
e6e5ad80
FB		 1693 break;
1694 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
f705db9d 1695 value = cirrus_vga_read_gr(s, 0x14);
e6e5ad80
FB		 1696 break;
1697 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
f705db9d 1698 value = cirrus_vga_read_gr(s, 0x01);
e6e5ad80
FB		 1699 break;
1700 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
f705db9d 1701 value = cirrus_vga_read_gr(s, 0x11);
e6e5ad80
FB		 1702 break;
1703 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
f705db9d 1704 value = cirrus_vga_read_gr(s, 0x13);
e6e5ad80
FB		 1705 break;
1706 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
f705db9d 1707 value = cirrus_vga_read_gr(s, 0x15);
e6e5ad80
FB		 1708 break;
1709 case (CIRRUS_MMIO_BLTWIDTH + 0):
f705db9d 1710 value = cirrus_vga_read_gr(s, 0x20);
e6e5ad80
FB		 1711 break;
1712 case (CIRRUS_MMIO_BLTWIDTH + 1):
f705db9d 1713 value = cirrus_vga_read_gr(s, 0x21);
e6e5ad80
FB		 1714 break;
1715 case (CIRRUS_MMIO_BLTHEIGHT + 0):
f705db9d 1716 value = cirrus_vga_read_gr(s, 0x22);
e6e5ad80
FB		 1717 break;
1718 case (CIRRUS_MMIO_BLTHEIGHT + 1):
f705db9d 1719 value = cirrus_vga_read_gr(s, 0x23);
e6e5ad80
FB		 1720 break;
1721 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
f705db9d 1722 value = cirrus_vga_read_gr(s, 0x24);
e6e5ad80
FB		 1723 break;
1724 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
f705db9d 1725 value = cirrus_vga_read_gr(s, 0x25);
e6e5ad80
FB		 1726 break;
1727 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
f705db9d 1728 value = cirrus_vga_read_gr(s, 0x26);
e6e5ad80
FB		 1729 break;
1730 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
f705db9d 1731 value = cirrus_vga_read_gr(s, 0x27);
e6e5ad80
FB		 1732 break;
1733 case (CIRRUS_MMIO_BLTDESTADDR + 0):
f705db9d 1734 value = cirrus_vga_read_gr(s, 0x28);
e6e5ad80
FB		 1735 break;
1736 case (CIRRUS_MMIO_BLTDESTADDR + 1):
f705db9d 1737 value = cirrus_vga_read_gr(s, 0x29);
e6e5ad80
FB		 1738 break;
1739 case (CIRRUS_MMIO_BLTDESTADDR + 2):
f705db9d 1740 value = cirrus_vga_read_gr(s, 0x2a);
e6e5ad80
FB		 1741 break;
1742 case (CIRRUS_MMIO_BLTSRCADDR + 0):
f705db9d 1743 value = cirrus_vga_read_gr(s, 0x2c);
e6e5ad80
FB		 1744 break;
1745 case (CIRRUS_MMIO_BLTSRCADDR + 1):
f705db9d 1746 value = cirrus_vga_read_gr(s, 0x2d);
e6e5ad80
FB		 1747 break;
1748 case (CIRRUS_MMIO_BLTSRCADDR + 2):
f705db9d 1749 value = cirrus_vga_read_gr(s, 0x2e);
e6e5ad80
FB		 1750 break;
1751 case CIRRUS_MMIO_BLTWRITEMASK:
f705db9d 1752 value = cirrus_vga_read_gr(s, 0x2f);
e6e5ad80
FB		 1753 break;
1754 case CIRRUS_MMIO_BLTMODE:
f705db9d 1755 value = cirrus_vga_read_gr(s, 0x30);
e6e5ad80
FB		 1756 break;
1757 case CIRRUS_MMIO_BLTROP:
f705db9d 1758 value = cirrus_vga_read_gr(s, 0x32);
e6e5ad80 1759 break;
a21ae81d 1760 case CIRRUS_MMIO_BLTMODEEXT:
f705db9d 1761 value = cirrus_vga_read_gr(s, 0x33);
a21ae81d 1762 break;
e6e5ad80 1763 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
f705db9d 1764 value = cirrus_vga_read_gr(s, 0x34);
e6e5ad80
FB		 1765 break;
1766 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
f705db9d 1767 value = cirrus_vga_read_gr(s, 0x35);
e6e5ad80
FB		 1768 break;
1769 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
f705db9d 1770 value = cirrus_vga_read_gr(s, 0x38);
e6e5ad80
FB		 1771 break;
1772 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
f705db9d 1773 value = cirrus_vga_read_gr(s, 0x39);
e6e5ad80
FB		 1774 break;
1775 case CIRRUS_MMIO_BLTSTATUS:
f705db9d 1776 value = cirrus_vga_read_gr(s, 0x31);
e6e5ad80
FB		 1777 break;
1778 default:
1779#ifdef DEBUG_CIRRUS
1780 printf("cirrus: mmio read - address 0x%04x\n", address);
1781#endif
1782 break;
1783 }
1784
1785 return (uint8_t) value;
1786}
1787
1788static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1789 uint8_t value)
1790{
1791 switch (address) {
1792 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
22286bc6 1793 cirrus_vga_write_gr(s, 0x00, value);
e6e5ad80
FB		 1794 break;
1795 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
22286bc6 1796 cirrus_vga_write_gr(s, 0x10, value);
e6e5ad80
FB		 1797 break;
1798 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
22286bc6 1799 cirrus_vga_write_gr(s, 0x12, value);
e6e5ad80
FB		 1800 break;
1801 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
22286bc6 1802 cirrus_vga_write_gr(s, 0x14, value);
e6e5ad80
FB		 1803 break;
1804 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
22286bc6 1805 cirrus_vga_write_gr(s, 0x01, value);
e6e5ad80
FB		 1806 break;
1807 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
22286bc6 1808 cirrus_vga_write_gr(s, 0x11, value);
e6e5ad80
FB		 1809 break;
1810 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
22286bc6 1811 cirrus_vga_write_gr(s, 0x13, value);
e6e5ad80
FB		 1812 break;
1813 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
22286bc6 1814 cirrus_vga_write_gr(s, 0x15, value);
e6e5ad80
FB		 1815 break;
1816 case (CIRRUS_MMIO_BLTWIDTH + 0):
22286bc6 1817 cirrus_vga_write_gr(s, 0x20, value);
e6e5ad80
FB		 1818 break;
1819 case (CIRRUS_MMIO_BLTWIDTH + 1):
22286bc6 1820 cirrus_vga_write_gr(s, 0x21, value);
e6e5ad80
FB		 1821 break;
1822 case (CIRRUS_MMIO_BLTHEIGHT + 0):
22286bc6 1823 cirrus_vga_write_gr(s, 0x22, value);
e6e5ad80
FB		 1824 break;
1825 case (CIRRUS_MMIO_BLTHEIGHT + 1):
22286bc6 1826 cirrus_vga_write_gr(s, 0x23, value);
e6e5ad80
FB		 1827 break;
1828 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
22286bc6 1829 cirrus_vga_write_gr(s, 0x24, value);
e6e5ad80
FB		 1830 break;
1831 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
22286bc6 1832 cirrus_vga_write_gr(s, 0x25, value);
e6e5ad80
FB		 1833 break;
1834 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
22286bc6 1835 cirrus_vga_write_gr(s, 0x26, value);
e6e5ad80
FB		 1836 break;
1837 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
22286bc6 1838 cirrus_vga_write_gr(s, 0x27, value);
e6e5ad80
FB		 1839 break;
1840 case (CIRRUS_MMIO_BLTDESTADDR + 0):
22286bc6 1841 cirrus_vga_write_gr(s, 0x28, value);
e6e5ad80
FB		 1842 break;
1843 case (CIRRUS_MMIO_BLTDESTADDR + 1):
22286bc6 1844 cirrus_vga_write_gr(s, 0x29, value);
e6e5ad80
FB		 1845 break;
1846 case (CIRRUS_MMIO_BLTDESTADDR + 2):
22286bc6 1847 cirrus_vga_write_gr(s, 0x2a, value);
e6e5ad80
FB		 1848 break;
1849 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1850 /* ignored */
1851 break;
1852 case (CIRRUS_MMIO_BLTSRCADDR + 0):
22286bc6 1853 cirrus_vga_write_gr(s, 0x2c, value);
e6e5ad80
FB		 1854 break;
1855 case (CIRRUS_MMIO_BLTSRCADDR + 1):
22286bc6 1856 cirrus_vga_write_gr(s, 0x2d, value);
e6e5ad80
FB		 1857 break;
1858 case (CIRRUS_MMIO_BLTSRCADDR + 2):
22286bc6 1859 cirrus_vga_write_gr(s, 0x2e, value);
e6e5ad80
FB		 1860 break;
1861 case CIRRUS_MMIO_BLTWRITEMASK:
22286bc6 1862 cirrus_vga_write_gr(s, 0x2f, value);
e6e5ad80
FB		 1863 break;
1864 case CIRRUS_MMIO_BLTMODE:
22286bc6 1865 cirrus_vga_write_gr(s, 0x30, value);
e6e5ad80
FB		 1866 break;
1867 case CIRRUS_MMIO_BLTROP:
22286bc6 1868 cirrus_vga_write_gr(s, 0x32, value);
e6e5ad80 1869 break;
a21ae81d 1870 case CIRRUS_MMIO_BLTMODEEXT:
22286bc6 1871 cirrus_vga_write_gr(s, 0x33, value);
a21ae81d 1872 break;
e6e5ad80 1873 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
22286bc6 1874 cirrus_vga_write_gr(s, 0x34, value);
e6e5ad80
FB		 1875 break;
1876 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
22286bc6 1877 cirrus_vga_write_gr(s, 0x35, value);
e6e5ad80
FB		 1878 break;
1879 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
22286bc6 1880 cirrus_vga_write_gr(s, 0x38, value);
e6e5ad80
FB		 1881 break;
1882 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
22286bc6 1883 cirrus_vga_write_gr(s, 0x39, value);
e6e5ad80
FB		 1884 break;
1885 case CIRRUS_MMIO_BLTSTATUS:
22286bc6 1886 cirrus_vga_write_gr(s, 0x31, value);
e6e5ad80
FB		 1887 break;
1888 default:
1889#ifdef DEBUG_CIRRUS
1890 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1891 address, value);
1892#endif
1893 break;
1894 }
1895}
1896
e6e5ad80
FB		 1897/***************************************
1898 *
1899 * write mode 4/5
1900 *
1901 * assume TARGET_PAGE_SIZE >= 16
1902 *
1903 ***************************************/
1904
1905static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1906 unsigned mode,
1907 unsigned offset,
1908 uint32_t mem_value)
1909{
1910 int x;
1911 unsigned val = mem_value;
1912 uint8_t *dst;
1913
4e12cd94 1914 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1915 for (x = 0; x < 8; x++) {
1916 if (val & 0x80) {
0b74ed78 1917 *dst = s->cirrus_shadow_gr1;
e6e5ad80 1918 } else if (mode == 5) {
0b74ed78 1919 *dst = s->cirrus_shadow_gr0;
e6e5ad80
FB		 1920 }
1921 val <<= 1;
0b74ed78 1922 dst++;
e6e5ad80 1923 }
b1950430
AK		 1924 memory_region_set_dirty(&s->vga.vram, offset);
1925 memory_region_set_dirty(&s->vga.vram, offset + 7);
e6e5ad80
FB		 1926}
1927
1928static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1929 unsigned mode,
1930 unsigned offset,
1931 uint32_t mem_value)
1932{
1933 int x;
1934 unsigned val = mem_value;
1935 uint8_t *dst;
1936
4e12cd94 1937 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
e6e5ad80
FB		 1938 for (x = 0; x < 8; x++) {
1939 if (val & 0x80) {
0b74ed78 1940 *dst = s->cirrus_shadow_gr1;
4e12cd94 1941 *(dst + 1) = s->vga.gr[0x11];
e6e5ad80 1942 } else if (mode == 5) {
0b74ed78 1943 *dst = s->cirrus_shadow_gr0;
4e12cd94 1944 *(dst + 1) = s->vga.gr[0x10];
e6e5ad80
FB		 1945 }
1946 val <<= 1;
0b74ed78 1947 dst += 2;
e6e5ad80 1948 }
b1950430
AK		 1949 memory_region_set_dirty(&s->vga.vram, offset);
1950 memory_region_set_dirty(&s->vga.vram, offset + 15);
e6e5ad80
FB		 1951}
1952
1953/***************************************
1954 *
1955 * memory access between 0xa0000-0xbffff
1956 *
1957 ***************************************/
1958
a815b166
AK		 1959static uint64_t cirrus_vga_mem_read(void *opaque,
1960 target_phys_addr_t addr,
1961 uint32_t size)
e6e5ad80
FB		 1962{
1963 CirrusVGAState *s = opaque;
1964 unsigned bank_index;
1965 unsigned bank_offset;
1966 uint32_t val;
1967
4e12cd94 1968 if ((s->vga.sr[0x07] & 0x01) == 0) {
b2a5e761 1969 return vga_mem_readb(&s->vga, addr);
e6e5ad80
FB		 1970 }
1971
1972 if (addr < 0x10000) {
1973 /* XXX handle bitblt */
1974 /* video memory */
1975 bank_index = addr >> 15;
1976 bank_offset = addr & 0x7fff;
1977 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
1978 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 1979 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 1980 bank_offset <<= 4;
4e12cd94 1981 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 1982 bank_offset <<= 3;
1983 }
1984 bank_offset &= s->cirrus_addr_mask;
4e12cd94 1985 val = *(s->vga.vram_ptr + bank_offset);
e6e5ad80
FB		 1986 } else
1987 val = 0xff;
1988 } else if (addr >= 0x18000 && addr < 0x18100) {
1989 /* memory-mapped I/O */
1990 val = 0xff;
4e12cd94 1991 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 1992 val = cirrus_mmio_blt_read(s, addr & 0xff);
1993 }
1994 } else {
1995 val = 0xff;
1996#ifdef DEBUG_CIRRUS
0bf9e31a 1997 printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
e6e5ad80
FB		 1998#endif
1999 }
2000 return val;
2001}
2002
a815b166
AK		 2003static void cirrus_vga_mem_write(void *opaque,
2004 target_phys_addr_t addr,
2005 uint64_t mem_value,
2006 uint32_t size)
e6e5ad80
FB		 2007{
2008 CirrusVGAState *s = opaque;
2009 unsigned bank_index;
2010 unsigned bank_offset;
2011 unsigned mode;
2012
4e12cd94 2013 if ((s->vga.sr[0x07] & 0x01) == 0) {
b2a5e761 2014 vga_mem_writeb(&s->vga, addr, mem_value);
e6e5ad80
FB		 2015 return;
2016 }
2017
2018 if (addr < 0x10000) {
2019 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2020 /* bitblt */
2021 *s->cirrus_srcptr++ = (uint8_t) mem_value;
a5082316 2022 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2023 cirrus_bitblt_cputovideo_next(s);
2024 }
2025 } else {
2026 /* video memory */
2027 bank_index = addr >> 15;
2028 bank_offset = addr & 0x7fff;
2029 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2030 bank_offset += s->cirrus_bank_base[bank_index];
4e12cd94 2031 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2032 bank_offset <<= 4;
4e12cd94 2033 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2034 bank_offset <<= 3;
2035 }
2036 bank_offset &= s->cirrus_addr_mask;
4e12cd94
AK		 2037 mode = s->vga.gr[0x05] & 0x7;
2038 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2039 *(s->vga.vram_ptr + bank_offset) = mem_value;
b1950430 2040 memory_region_set_dirty(&s->vga.vram, bank_offset);
e6e5ad80 2041 } else {
4e12cd94 2042 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2043 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2044 bank_offset,
2045 mem_value);
2046 } else {
2047 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2048 bank_offset,
2049 mem_value);
2050 }
2051 }
2052 }
2053 }
2054 } else if (addr >= 0x18000 && addr < 0x18100) {
2055 /* memory-mapped I/O */
4e12cd94 2056 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
e6e5ad80
FB		 2057 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2058 }
2059 } else {
2060#ifdef DEBUG_CIRRUS
0bf9e31a
BS		 2061 printf("cirrus: mem_writeb " TARGET_FMT_plx " value %02x\n", addr,
2062 mem_value);
e6e5ad80
FB		 2063#endif
2064 }
2065}
2066
b1950430
AK		 2067static const MemoryRegionOps cirrus_vga_mem_ops = {
2068 .read = cirrus_vga_mem_read,
2069 .write = cirrus_vga_mem_write,
2070 .endianness = DEVICE_LITTLE_ENDIAN,
a815b166
AK		 2071 .impl = {
2072 .min_access_size = 1,
2073 .max_access_size = 1,
2074 },
e6e5ad80
FB		 2075};
2076
a5082316
FB		 2077/***************************************
2078 *
2079 * hardware cursor
2080 *
2081 ***************************************/
2082
2083static inline void invalidate_cursor1(CirrusVGAState *s)
2084{
2085 if (s->last_hw_cursor_size) {
4e12cd94 2086 vga_invalidate_scanlines(&s->vga,
a5082316
FB		 2087 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2088 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2089 }
2090}
2091
2092static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2093{
2094 const uint8_t *src;
2095 uint32_t content;
2096 int y, y_min, y_max;
2097
4e12cd94
AK		 2098 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2099 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2100 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2101 y_min = 64;
2102 y_max = -1;
2103 for(y = 0; y < 64; y++) {
2104 content = ((uint32_t *)src)[0] |
2105 ((uint32_t *)src)[1] |
2106 ((uint32_t *)src)[2] |
2107 ((uint32_t *)src)[3];
2108 if (content) {
2109 if (y < y_min)
2110 y_min = y;
2111 if (y > y_max)
2112 y_max = y;
2113 }
2114 src += 16;
2115 }
2116 } else {
4e12cd94 2117 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316
FB		 2118 y_min = 32;
2119 y_max = -1;
2120 for(y = 0; y < 32; y++) {
2121 content = ((uint32_t *)src)[0] |
2122 ((uint32_t *)(src + 128))[0];
2123 if (content) {
2124 if (y < y_min)
2125 y_min = y;
2126 if (y > y_max)
2127 y_max = y;
2128 }
2129 src += 4;
2130 }
2131 }
2132 if (y_min > y_max) {
2133 s->last_hw_cursor_y_start = 0;
2134 s->last_hw_cursor_y_end = 0;
2135 } else {
2136 s->last_hw_cursor_y_start = y_min;
2137 s->last_hw_cursor_y_end = y_max + 1;
2138 }
2139}
2140
2141/* NOTE: we do not currently handle the cursor bitmap change, so we
2142 update the cursor only if it moves. */
a4a2f59c 2143static void cirrus_cursor_invalidate(VGACommonState *s1)
a5082316 2144{
4e12cd94 2145 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
a5082316
FB		 2146 int size;
2147
4e12cd94 2148 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
a5082316
FB		 2149 size = 0;
2150 } else {
4e12cd94 2151 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
a5082316
FB		 2152 size = 64;
2153 else
2154 size = 32;
2155 }
2156 /* invalidate last cursor and new cursor if any change */
2157 if (s->last_hw_cursor_size != size ||
2158 s->last_hw_cursor_x != s->hw_cursor_x ||
2159 s->last_hw_cursor_y != s->hw_cursor_y) {
2160
2161 invalidate_cursor1(s);
3b46e624 2162
a5082316
FB		 2163 s->last_hw_cursor_size = size;
2164 s->last_hw_cursor_x = s->hw_cursor_x;
2165 s->last_hw_cursor_y = s->hw_cursor_y;
2166 /* compute the real cursor min and max y */
2167 cirrus_cursor_compute_yrange(s);
2168 invalidate_cursor1(s);
2169 }
2170}
2171
a4a2f59c 2172static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
a5082316 2173{
4e12cd94 2174 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
a5082316
FB		 2175 int w, h, bpp, x1, x2, poffset;
2176 unsigned int color0, color1;
2177 const uint8_t *palette, *src;
2178 uint32_t content;
3b46e624 2179
4e12cd94 2180 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
a5082316
FB		 2181 return;
2182 /* fast test to see if the cursor intersects with the scan line */
4e12cd94 2183 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
a5082316
FB		 2184 h = 64;
2185 } else {
2186 h = 32;
2187 }
2188 if (scr_y < s->hw_cursor_y ||
2189 scr_y >= (s->hw_cursor_y + h))
2190 return;
3b46e624 2191
4e12cd94
AK		 2192 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2193 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2194 src += (s->vga.sr[0x13] & 0x3c) * 256;
a5082316
FB		 2195 src += (scr_y - s->hw_cursor_y) * 16;
2196 poffset = 8;
2197 content = ((uint32_t *)src)[0] |
2198 ((uint32_t *)src)[1] |
2199 ((uint32_t *)src)[2] |
2200 ((uint32_t *)src)[3];
2201 } else {
4e12cd94 2202 src += (s->vga.sr[0x13] & 0x3f) * 256;
a5082316
FB		 2203 src += (scr_y - s->hw_cursor_y) * 4;
2204 poffset = 128;
2205 content = ((uint32_t *)src)[0] |
2206 ((uint32_t *)(src + 128))[0];
2207 }
2208 /* if nothing to draw, no need to continue */
2209 if (!content)
2210 return;
2211 w = h;
2212
2213 x1 = s->hw_cursor_x;
4e12cd94 2214 if (x1 >= s->vga.last_scr_width)
a5082316
FB		 2215 return;
2216 x2 = s->hw_cursor_x + w;
4e12cd94
AK		 2217 if (x2 > s->vga.last_scr_width)
2218 x2 = s->vga.last_scr_width;
a5082316
FB		 2219 w = x2 - x1;
2220 palette = s->cirrus_hidden_palette;
4e12cd94
AK		 2221 color0 = s->vga.rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2222 c6_to_8(palette[0x0 * 3 + 1]),
2223 c6_to_8(palette[0x0 * 3 + 2]));
2224 color1 = s->vga.rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2225 c6_to_8(palette[0xf * 3 + 1]),
2226 c6_to_8(palette[0xf * 3 + 2]));
2227 bpp = ((ds_get_bits_per_pixel(s->vga.ds) + 7) >> 3);
a5082316 2228 d1 += x1 * bpp;
4e12cd94 2229 switch(ds_get_bits_per_pixel(s->vga.ds)) {
a5082316
FB		 2230 default:
2231 break;
2232 case 8:
2233 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2234 break;
2235 case 15:
2236 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2237 break;
2238 case 16:
2239 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2240 break;
2241 case 32:
2242 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2243 break;
2244 }
2245}
2246
e6e5ad80
FB		 2247/***************************************
2248 *
2249 * LFB memory access
2250 *
2251 ***************************************/
2252
899adf81
AK		 2253static uint64_t cirrus_linear_read(void *opaque, target_phys_addr_t addr,
2254 unsigned size)
e6e5ad80 2255{
e05587e8 2256 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2257 uint32_t ret;
2258
e6e5ad80
FB		 2259 addr &= s->cirrus_addr_mask;
2260
4e12cd94 2261 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2262 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2263 /* memory-mapped I/O */
2264 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2265 } else if (0) {
2266 /* XXX handle bitblt */
2267 ret = 0xff;
2268 } else {
2269 /* video memory */
4e12cd94 2270 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2271 addr <<= 4;
4e12cd94 2272 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2273 addr <<= 3;
2274 }
2275 addr &= s->cirrus_addr_mask;
4e12cd94 2276 ret = *(s->vga.vram_ptr + addr);
e6e5ad80
FB		 2277 }
2278
2279 return ret;
2280}
2281
899adf81
AK		 2282static void cirrus_linear_write(void *opaque, target_phys_addr_t addr,
2283 uint64_t val, unsigned size)
e6e5ad80 2284{
e05587e8 2285 CirrusVGAState *s = opaque;
e6e5ad80
FB		 2286 unsigned mode;
2287
2288 addr &= s->cirrus_addr_mask;
3b46e624 2289
4e12cd94 2290 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
78e127ef 2291 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2292 /* memory-mapped I/O */
2293 cirrus_mmio_blt_write(s, addr & 0xff, val);
2294 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2295 /* bitblt */
2296 *s->cirrus_srcptr++ = (uint8_t) val;
a5082316 2297 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2298 cirrus_bitblt_cputovideo_next(s);
2299 }
2300 } else {
2301 /* video memory */
4e12cd94 2302 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
e6e5ad80 2303 addr <<= 4;
4e12cd94 2304 } else if (s->vga.gr[0x0B] & 0x02) {
e6e5ad80
FB		 2305 addr <<= 3;
2306 }
2307 addr &= s->cirrus_addr_mask;
2308
4e12cd94
AK		 2309 mode = s->vga.gr[0x05] & 0x7;
2310 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2311 *(s->vga.vram_ptr + addr) = (uint8_t) val;
b1950430 2312 memory_region_set_dirty(&s->vga.vram, addr);
e6e5ad80 2313 } else {
4e12cd94 2314 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
e6e5ad80
FB		 2315 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2316 } else {
2317 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2318 }
2319 }
2320 }
2321}
2322
a5082316
FB		 2323/***************************************
2324 *
2325 * system to screen memory access
2326 *
2327 ***************************************/
2328
2329
4e56f089
AK		 2330static uint64_t cirrus_linear_bitblt_read(void *opaque,
2331 target_phys_addr_t addr,
2332 unsigned size)
a5082316 2333{
4e56f089 2334 CirrusVGAState *s = opaque;
a5082316
FB		 2335 uint32_t ret;
2336
2337 /* XXX handle bitblt */
4e56f089 2338 (void)s;
a5082316
FB		 2339 ret = 0xff;
2340 return ret;
2341}
2342
4e56f089
AK		 2343static void cirrus_linear_bitblt_write(void *opaque,
2344 target_phys_addr_t addr,
2345 uint64_t val,
2346 unsigned size)
a5082316 2347{
e05587e8 2348 CirrusVGAState *s = opaque;
a5082316
FB		 2349
2350 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2351 /* bitblt */
2352 *s->cirrus_srcptr++ = (uint8_t) val;
2353 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2354 cirrus_bitblt_cputovideo_next(s);
2355 }
2356 }
2357}
2358
b1950430
AK		 2359static const MemoryRegionOps cirrus_linear_bitblt_io_ops = {
2360 .read = cirrus_linear_bitblt_read,
2361 .write = cirrus_linear_bitblt_write,
2362 .endianness = DEVICE_LITTLE_ENDIAN,
4e56f089
AK		 2363 .impl = {
2364 .min_access_size = 1,
2365 .max_access_size = 1,
2366 },
a5082316
FB		 2367};
2368
b1950430 2369static void unmap_bank(CirrusVGAState *s, unsigned bank)
2bec46dc 2370{
b1950430
AK		 2371 if (s->cirrus_bank[bank]) {
2372 memory_region_del_subregion(&s->low_mem_container,
2373 s->cirrus_bank[bank]);
2374 memory_region_destroy(s->cirrus_bank[bank]);
2375 qemu_free(s->cirrus_bank[bank]);
2376 s->cirrus_bank[bank] = NULL;
2bec46dc 2377 }
b1950430 2378}
2bec46dc 2379
b1950430
AK		 2380static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank)
2381{
2382 MemoryRegion *mr;
2383 static const char *names[] = { "vga.bank0", "vga.bank1" };
2bec46dc
AL		 2384
2385 if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
4e12cd94
AK		 2386 && !((s->vga.sr[0x07] & 0x01) == 0)
2387 && !((s->vga.gr[0x0B] & 0x14) == 0x14)
2388 && !(s->vga.gr[0x0B] & 0x02)) {
2bec46dc 2389
b1950430
AK		 2390 mr = qemu_malloc(sizeof(*mr));
2391 memory_region_init_alias(mr, names[bank], &s->vga.vram,
2392 s->cirrus_bank_base[bank], 0x8000);
2393 memory_region_add_subregion_overlap(
2394 &s->low_mem_container,
2395 0x8000 * bank,
2396 mr,
2397 1);
2398 unmap_bank(s, bank);
2399 s->cirrus_bank[bank] = mr;
2400 } else {
2401 unmap_bank(s, bank);
2bec46dc 2402 }
b1950430 2403}
2bec46dc 2404
b1950430
AK		 2405static void map_linear_vram(CirrusVGAState *s)
2406{
2407 if (!s->linear_vram) {
2408 s->linear_vram = true;
2409 memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1);
2410 }
2411 map_linear_vram_bank(s, 0);
2412 map_linear_vram_bank(s, 1);
2bec46dc
AL		 2413}
2414
2415static void unmap_linear_vram(CirrusVGAState *s)
2416{
b1950430
AK		 2417 if (s->linear_vram) {
2418 s->linear_vram = false;
2419 memory_region_del_subregion(&s->pci_bar, &s->vga.vram);
4516e45f 2420 }
b1950430
AK		 2421 unmap_bank(s, 0);
2422 unmap_bank(s, 1);
2bec46dc
AL		 2423}
2424
8926b517
FB		 2425/* Compute the memory access functions */
2426static void cirrus_update_memory_access(CirrusVGAState *s)
2427{
2428 unsigned mode;
2429
4e12cd94 2430 if ((s->vga.sr[0x17] & 0x44) == 0x44) {
8926b517
FB		 2431 goto generic_io;
2432 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2433 goto generic_io;
2434 } else {
4e12cd94 2435 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
8926b517 2436 goto generic_io;
4e12cd94 2437 } else if (s->vga.gr[0x0B] & 0x02) {
8926b517
FB		 2438 goto generic_io;
2439 }
3b46e624 2440
4e12cd94
AK		 2441 mode = s->vga.gr[0x05] & 0x7;
2442 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2bec46dc 2443 map_linear_vram(s);
8926b517
FB		 2444 } else {
2445 generic_io:
2bec46dc 2446 unmap_linear_vram(s);
8926b517
FB		 2447 }
2448 }
2449}
2450
2451
e6e5ad80
FB		 2452/* I/O ports */
2453
0ceac75b 2454static uint32_t cirrus_vga_ioport_read(void *opaque, uint32_t addr)
e6e5ad80 2455{
b6343073
JQ		 2456 CirrusVGAState *c = opaque;
2457 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2458 int val, index;
2459
b6343073 2460 if (vga_ioport_invalid(s, addr)) {
e6e5ad80
FB		 2461 val = 0xff;
2462 } else {
2463 switch (addr) {
2464 case 0x3c0:
b6343073
JQ		 2465 if (s->ar_flip_flop == 0) {
2466 val = s->ar_index;
e6e5ad80
FB		 2467 } else {
2468 val = 0;
2469 }
2470 break;
2471 case 0x3c1:
b6343073 2472 index = s->ar_index & 0x1f;
e6e5ad80 2473 if (index < 21)
b6343073 2474 val = s->ar[index];
e6e5ad80
FB		 2475 else
2476 val = 0;
2477 break;
2478 case 0x3c2:
b6343073 2479 val = s->st00;
e6e5ad80
FB		 2480 break;
2481 case 0x3c4:
b6343073 2482 val = s->sr_index;
e6e5ad80
FB		 2483 break;
2484 case 0x3c5:
8a82c322
JQ		 2485 val = cirrus_vga_read_sr(c);
2486 break;
e6e5ad80 2487#ifdef DEBUG_VGA_REG
b6343073 2488 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
e6e5ad80
FB		 2489#endif
2490 break;
2491 case 0x3c6:
957c9db5 2492 val = cirrus_read_hidden_dac(c);
e6e5ad80
FB		 2493 break;
2494 case 0x3c7:
b6343073 2495 val = s->dac_state;
e6e5ad80 2496 break;
ae184e4a 2497 case 0x3c8:
b6343073
JQ		 2498 val = s->dac_write_index;
2499 c->cirrus_hidden_dac_lockindex = 0;
ae184e4a
FB		 2500 break;
2501 case 0x3c9:
5deaeee3
JQ		 2502 val = cirrus_vga_read_palette(c);
2503 break;
e6e5ad80 2504 case 0x3ca:
b6343073 2505 val = s->fcr;
e6e5ad80
FB		 2506 break;
2507 case 0x3cc:
b6343073 2508 val = s->msr;
e6e5ad80
FB		 2509 break;
2510 case 0x3ce:
b6343073 2511 val = s->gr_index;
e6e5ad80
FB		 2512 break;
2513 case 0x3cf:
f705db9d 2514 val = cirrus_vga_read_gr(c, s->gr_index);
e6e5ad80 2515#ifdef DEBUG_VGA_REG
b6343073 2516 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
e6e5ad80
FB		 2517#endif
2518 break;
2519 case 0x3b4:
2520 case 0x3d4:
b6343073 2521 val = s->cr_index;
e6e5ad80
FB		 2522 break;
2523 case 0x3b5:
2524 case 0x3d5:
b863d514 2525 val = cirrus_vga_read_cr(c, s->cr_index);
e6e5ad80 2526#ifdef DEBUG_VGA_REG
b6343073 2527 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80
FB		 2528#endif
2529 break;
2530 case 0x3ba:
2531 case 0x3da:
2532 /* just toggle to fool polling */
b6343073
JQ		 2533 val = s->st01 = s->retrace(s);
2534 s->ar_flip_flop = 0;
e6e5ad80
FB		 2535 break;
2536 default:
2537 val = 0x00;
2538 break;
2539 }
2540 }
2541#if defined(DEBUG_VGA)
2542 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2543#endif
2544 return val;
2545}
2546
0ceac75b 2547static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
e6e5ad80 2548{
b6343073
JQ		 2549 CirrusVGAState *c = opaque;
2550 VGACommonState *s = &c->vga;
e6e5ad80
FB		 2551 int index;
2552
2553 /* check port range access depending on color/monochrome mode */
b6343073 2554 if (vga_ioport_invalid(s, addr)) {
e6e5ad80 2555 return;
25a18cbd 2556 }
e6e5ad80
FB		 2557#ifdef DEBUG_VGA
2558 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2559#endif
2560
2561 switch (addr) {
2562 case 0x3c0:
b6343073 2563 if (s->ar_flip_flop == 0) {
e6e5ad80 2564 val &= 0x3f;
b6343073 2565 s->ar_index = val;
e6e5ad80 2566 } else {
b6343073 2567 index = s->ar_index & 0x1f;
e6e5ad80
FB		 2568 switch (index) {
2569 case 0x00 ... 0x0f:
b6343073 2570 s->ar[index] = val & 0x3f;
e6e5ad80
FB		 2571 break;
2572 case 0x10:
b6343073 2573 s->ar[index] = val & ~0x10;
e6e5ad80
FB		 2574 break;
2575 case 0x11:
b6343073 2576 s->ar[index] = val;
e6e5ad80
FB		 2577 break;
2578 case 0x12:
b6343073 2579 s->ar[index] = val & ~0xc0;
e6e5ad80
FB		 2580 break;
2581 case 0x13:
b6343073 2582 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2583 break;
2584 case 0x14:
b6343073 2585 s->ar[index] = val & ~0xf0;
e6e5ad80
FB		 2586 break;
2587 default:
2588 break;
2589 }
2590 }
b6343073 2591 s->ar_flip_flop ^= 1;
e6e5ad80
FB		 2592 break;
2593 case 0x3c2:
b6343073
JQ		 2594 s->msr = val & ~0x10;
2595 s->update_retrace_info(s);
e6e5ad80
FB		 2596 break;
2597 case 0x3c4:
b6343073 2598 s->sr_index = val;
e6e5ad80
FB		 2599 break;
2600 case 0x3c5:
e6e5ad80 2601#ifdef DEBUG_VGA_REG
b6343073 2602 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
e6e5ad80 2603#endif
31c63201
JQ		 2604 cirrus_vga_write_sr(c, val);
2605 break;
e6e5ad80
FB		 2606 break;
2607 case 0x3c6:
b6343073 2608 cirrus_write_hidden_dac(c, val);
e6e5ad80
FB		 2609 break;
2610 case 0x3c7:
b6343073
JQ		 2611 s->dac_read_index = val;
2612 s->dac_sub_index = 0;
2613 s->dac_state = 3;
e6e5ad80
FB		 2614 break;
2615 case 0x3c8:
b6343073
JQ		 2616 s->dac_write_index = val;
2617 s->dac_sub_index = 0;
2618 s->dac_state = 0;
e6e5ad80
FB		 2619 break;
2620 case 0x3c9:
86948bb1
JQ		 2621 cirrus_vga_write_palette(c, val);
2622 break;
e6e5ad80 2623 case 0x3ce:
b6343073 2624 s->gr_index = val;
e6e5ad80
FB		 2625 break;
2626 case 0x3cf:
e6e5ad80 2627#ifdef DEBUG_VGA_REG
b6343073 2628 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
e6e5ad80 2629#endif
22286bc6 2630 cirrus_vga_write_gr(c, s->gr_index, val);
e6e5ad80
FB		 2631 break;
2632 case 0x3b4:
2633 case 0x3d4:
b6343073 2634 s->cr_index = val;
e6e5ad80
FB		 2635 break;
2636 case 0x3b5:
2637 case 0x3d5:
e6e5ad80 2638#ifdef DEBUG_VGA_REG
b6343073 2639 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80 2640#endif
4ec1ce04 2641 cirrus_vga_write_cr(c, val);
e6e5ad80
FB		 2642 break;
2643 case 0x3ba:
2644 case 0x3da:
b6343073 2645 s->fcr = val & 0x10;
e6e5ad80
FB		 2646 break;
2647 }
2648}
2649
e36f36e1
FB		 2650/***************************************
2651 *
2652 * memory-mapped I/O access
2653 *
2654 ***************************************/
2655
1e04d4d6
AK		 2656static uint64_t cirrus_mmio_read(void *opaque, target_phys_addr_t addr,
2657 unsigned size)
e36f36e1 2658{
e05587e8 2659 CirrusVGAState *s = opaque;
e36f36e1 2660
e36f36e1
FB		 2661 if (addr >= 0x100) {
2662 return cirrus_mmio_blt_read(s, addr - 0x100);
2663 } else {
0ceac75b 2664 return cirrus_vga_ioport_read(s, addr + 0x3c0);
e36f36e1
FB		 2665 }
2666}
2667
1e04d4d6
AK		 2668static void cirrus_mmio_write(void *opaque, target_phys_addr_t addr,
2669 uint64_t val, unsigned size)
e36f36e1 2670{
e05587e8 2671 CirrusVGAState *s = opaque;
e36f36e1 2672
e36f36e1
FB		 2673 if (addr >= 0x100) {
2674 cirrus_mmio_blt_write(s, addr - 0x100, val);
2675 } else {
0ceac75b 2676 cirrus_vga_ioport_write(s, addr + 0x3c0, val);
e36f36e1
FB		 2677 }
2678}
2679
b1950430
AK		 2680static const MemoryRegionOps cirrus_mmio_io_ops = {
2681 .read = cirrus_mmio_read,
2682 .write = cirrus_mmio_write,
2683 .endianness = DEVICE_LITTLE_ENDIAN,
1e04d4d6
AK		 2684 .impl = {
2685 .min_access_size = 1,
2686 .max_access_size = 1,
2687 },
e36f36e1
FB		 2688};
2689
2c6ab832
FB		 2690/* load/save state */
2691
e59fb374 2692static int cirrus_post_load(void *opaque, int version_id)
2c6ab832
FB		 2693{
2694 CirrusVGAState *s = opaque;
2695
4e12cd94
AK		 2696 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
2697 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
2c6ab832 2698
2bec46dc 2699 cirrus_update_memory_access(s);
2c6ab832 2700 /* force refresh */
4e12cd94 2701 s->vga.graphic_mode = -1;
2c6ab832
FB		 2702 cirrus_update_bank_ptr(s, 0);
2703 cirrus_update_bank_ptr(s, 1);
2704 return 0;
2705}
2706
7e72abc3
JQ		 2707static const VMStateDescription vmstate_cirrus_vga = {
2708 .name = "cirrus_vga",
2709 .version_id = 2,
2710 .minimum_version_id = 1,
2711 .minimum_version_id_old = 1,
2712 .post_load = cirrus_post_load,
2713 .fields = (VMStateField []) {
2714 VMSTATE_UINT32(vga.latch, CirrusVGAState),
2715 VMSTATE_UINT8(vga.sr_index, CirrusVGAState),
2716 VMSTATE_BUFFER(vga.sr, CirrusVGAState),
2717 VMSTATE_UINT8(vga.gr_index, CirrusVGAState),
2718 VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState),
2719 VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState),
2720 VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
2721 VMSTATE_UINT8(vga.ar_index, CirrusVGAState),
2722 VMSTATE_BUFFER(vga.ar, CirrusVGAState),
2723 VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState),
2724 VMSTATE_UINT8(vga.cr_index, CirrusVGAState),
2725 VMSTATE_BUFFER(vga.cr, CirrusVGAState),
2726 VMSTATE_UINT8(vga.msr, CirrusVGAState),
2727 VMSTATE_UINT8(vga.fcr, CirrusVGAState),
2728 VMSTATE_UINT8(vga.st00, CirrusVGAState),
2729 VMSTATE_UINT8(vga.st01, CirrusVGAState),
2730 VMSTATE_UINT8(vga.dac_state, CirrusVGAState),
2731 VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState),
2732 VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState),
2733 VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState),
2734 VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState),
2735 VMSTATE_BUFFER(vga.palette, CirrusVGAState),
2736 VMSTATE_INT32(vga.bank_offset, CirrusVGAState),
2737 VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState),
2738 VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState),
2739 VMSTATE_UINT32(hw_cursor_x, CirrusVGAState),
2740 VMSTATE_UINT32(hw_cursor_y, CirrusVGAState),
2741 /* XXX: we do not save the bitblt state - we assume we do not save
2742 the state when the blitter is active */
2743 VMSTATE_END_OF_LIST()
4f335feb 2744 }
7e72abc3 2745};
4f335feb 2746
7e72abc3
JQ		 2747static const VMStateDescription vmstate_pci_cirrus_vga = {
2748 .name = "cirrus_vga",
2749 .version_id = 2,
2750 .minimum_version_id = 2,
2751 .minimum_version_id_old = 2,
7e72abc3
JQ		 2752 .fields = (VMStateField []) {
2753 VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState),
2754 VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
2755 vmstate_cirrus_vga, CirrusVGAState),
2756 VMSTATE_END_OF_LIST()
2757 }
2758};
4f335feb 2759
e6e5ad80
FB		 2760/***************************************
2761 *
2762 * initialize
2763 *
2764 ***************************************/
2765
4abc796d 2766static void cirrus_reset(void *opaque)
e6e5ad80 2767{
4abc796d 2768 CirrusVGAState *s = opaque;
e6e5ad80 2769
03a3e7ba 2770 vga_common_reset(&s->vga);
ee50c6bc 2771 unmap_linear_vram(s);
4e12cd94 2772 s->vga.sr[0x06] = 0x0f;
4abc796d 2773 if (s->device_id == CIRRUS_ID_CLGD5446) {
78e127ef 2774 /* 4MB 64 bit memory config, always PCI */
4e12cd94
AK		 2775 s->vga.sr[0x1F] = 0x2d; // MemClock
2776 s->vga.gr[0x18] = 0x0f; // fastest memory configuration
2777 s->vga.sr[0x0f] = 0x98;
2778 s->vga.sr[0x17] = 0x20;
2779 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
78e127ef 2780 } else {
4e12cd94
AK		 2781 s->vga.sr[0x1F] = 0x22; // MemClock
2782 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
2783 s->vga.sr[0x17] = s->bustype;
2784 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
78e127ef 2785 }
4e12cd94 2786 s->vga.cr[0x27] = s->device_id;
e6e5ad80 2787
78e127ef
FB		 2788 /* Win2K seems to assume that the pattern buffer is at 0xff
2789 initially ! */
4e12cd94 2790 memset(s->vga.vram_ptr, 0xff, s->real_vram_size);
78e127ef 2791
e6e5ad80
FB		 2792 s->cirrus_hidden_dac_lockindex = 5;
2793 s->cirrus_hidden_dac_data = 0;
4abc796d
BS		 2794}
2795
b1950430
AK		 2796static const MemoryRegionOps cirrus_linear_io_ops = {
2797 .read = cirrus_linear_read,
2798 .write = cirrus_linear_write,
2799 .endianness = DEVICE_LITTLE_ENDIAN,
899adf81
AK		 2800 .impl = {
2801 .min_access_size = 1,
2802 .max_access_size = 1,
2803 },
b1950430
AK		 2804};
2805
4abc796d
BS		 2806static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
2807{
2808 int i;
2809 static int inited;
2810
2811 if (!inited) {
2812 inited = 1;
2813 for(i = 0;i < 256; i++)
2814 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
2815 rop_to_index[CIRRUS_ROP_0] = 0;
2816 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
2817 rop_to_index[CIRRUS_ROP_NOP] = 2;
2818 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
2819 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
2820 rop_to_index[CIRRUS_ROP_SRC] = 5;
2821 rop_to_index[CIRRUS_ROP_1] = 6;
2822 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
2823 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
2824 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
2825 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
2826 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
2827 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
2828 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
2829 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
2830 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
2831 s->device_id = device_id;
2832 if (is_pci)
2833 s->bustype = CIRRUS_BUSTYPE_PCI;
2834 else
2835 s->bustype = CIRRUS_BUSTYPE_ISA;
2836 }
2837
0ceac75b 2838 register_ioport_write(0x3c0, 16, 1, cirrus_vga_ioport_write, s);
4abc796d 2839
0ceac75b
JQ		 2840 register_ioport_write(0x3b4, 2, 1, cirrus_vga_ioport_write, s);
2841 register_ioport_write(0x3d4, 2, 1, cirrus_vga_ioport_write, s);
2842 register_ioport_write(0x3ba, 1, 1, cirrus_vga_ioport_write, s);
2843 register_ioport_write(0x3da, 1, 1, cirrus_vga_ioport_write, s);
4abc796d 2844
0ceac75b 2845 register_ioport_read(0x3c0, 16, 1, cirrus_vga_ioport_read, s);
4abc796d 2846
0ceac75b
JQ		 2847 register_ioport_read(0x3b4, 2, 1, cirrus_vga_ioport_read, s);
2848 register_ioport_read(0x3d4, 2, 1, cirrus_vga_ioport_read, s);
2849 register_ioport_read(0x3ba, 1, 1, cirrus_vga_ioport_read, s);
2850 register_ioport_read(0x3da, 1, 1, cirrus_vga_ioport_read, s);
4abc796d 2851
b1950430
AK		 2852 memory_region_init(&s->low_mem_container,
2853 "cirrus-lowmem-container",
2854 0x20000);
2855
2856 memory_region_init_io(&s->low_mem, &cirrus_vga_mem_ops, s,
2857 "cirrus-low-memory", 0x20000);
2858 memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
2859 memory_region_add_subregion_overlap(get_system_memory(),
2860 isa_mem_base + 0x000a0000,
2861 &s->low_mem_container,
2862 1);
2863 memory_region_set_coalescing(&s->low_mem);
2c6ab832 2864
fefe54e3 2865 /* I/O handler for LFB */
b1950430
AK		 2866 memory_region_init_io(&s->cirrus_linear_io, &cirrus_linear_io_ops, s,
2867 "cirrus-linear-io", VGA_RAM_SIZE);
fefe54e3
AL		 2868
2869 /* I/O handler for LFB */
b1950430
AK		 2870 memory_region_init_io(&s->cirrus_linear_bitblt_io,
2871 &cirrus_linear_bitblt_io_ops,
2872 s,
2873 "cirrus-bitblt-mmio",
2874 0x400000);
fefe54e3
AL		 2875
2876 /* I/O handler for memory-mapped I/O */
b1950430
AK		 2877 memory_region_init_io(&s->cirrus_mmio_io, &cirrus_mmio_io_ops, s,
2878 "cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
fefe54e3
AL		 2879
2880 s->real_vram_size =
2881 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
2882
4e12cd94 2883 /* XXX: s->vga.vram_size must be a power of two */
fefe54e3
AL		 2884 s->cirrus_addr_mask = s->real_vram_size - 1;
2885 s->linear_mmio_mask = s->real_vram_size - 256;
2886
4e12cd94
AK		 2887 s->vga.get_bpp = cirrus_get_bpp;
2888 s->vga.get_offsets = cirrus_get_offsets;
2889 s->vga.get_resolution = cirrus_get_resolution;
2890 s->vga.cursor_invalidate = cirrus_cursor_invalidate;
2891 s->vga.cursor_draw_line = cirrus_cursor_draw_line;
fefe54e3 2892
a08d4367 2893 qemu_register_reset(cirrus_reset, s);
e6e5ad80
FB		 2894}
2895
2896/***************************************
2897 *
2898 * ISA bus support
2899 *
2900 ***************************************/
2901
fbe1b595 2902void isa_cirrus_vga_init(void)
e6e5ad80
FB		 2903{
2904 CirrusVGAState *s;
2905
2906 s = qemu_mallocz(sizeof(CirrusVGAState));
3b46e624 2907
fbe1b595 2908 vga_common_init(&s->vga, VGA_RAM_SIZE);
78e127ef 2909 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
4e12cd94
AK		 2910 s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
2911 s->vga.screen_dump, s->vga.text_update,
2912 &s->vga);
0be71e32 2913 vmstate_register(NULL, 0, &vmstate_cirrus_vga, s);
5245d57a 2914 rom_add_vga(VGABIOS_CIRRUS_FILENAME);
e6e5ad80
FB		 2915 /* XXX ISA-LFB support */
2916}
2917
2918/***************************************
2919 *
2920 * PCI bus support
2921 *
2922 ***************************************/
2923
81a322d4 2924static int pci_cirrus_vga_initfn(PCIDevice *dev)
a414c306
GH		 2925{
2926 PCICirrusVGAState *d = DO_UPCAST(PCICirrusVGAState, dev, dev);
2927 CirrusVGAState *s = &d->cirrus_vga;
5b96d8f9
IY		 2928 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->qdev.info);
2929 int16_t device_id = info->device_id;
a414c306
GH		 2930
2931 /* setup VGA */
2932 vga_common_init(&s->vga, VGA_RAM_SIZE);
2933 cirrus_init_common(s, device_id, 1);
a414c306
GH		 2934 s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
2935 s->vga.screen_dump, s->vga.text_update,
2936 &s->vga);
2937
2938 /* setup PCI */
a414c306 2939
b1950430
AK		 2940 memory_region_init(&s->pci_bar, "cirrus-pci-bar0", 0x2000000);
2941
2942 /* XXX: add byte swapping apertures */
2943 memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io);
2944 memory_region_add_subregion(&s->pci_bar, 0x1000000,
2945 &s->cirrus_linear_bitblt_io);
2946
a414c306
GH		 2947 /* setup memory space */
2948 /* memory #0 LFB */
2949 /* memory #1 memory-mapped I/O */
2950 /* XXX: s->vga.vram_size must be a power of two */
b1950430
AK		 2951 pci_register_bar_region(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH,
2952 &s->pci_bar);
a414c306 2953 if (device_id == CIRRUS_ID_CLGD5446) {
b1950430 2954 pci_register_bar_region(&d->dev, 1, 0, &s->cirrus_mmio_io);
a414c306 2955 }
81a322d4 2956 return 0;
a414c306
GH		 2957}
2958
fbe1b595 2959void pci_cirrus_vga_init(PCIBus *bus)
e6e5ad80 2960{
556cd098 2961 pci_create_simple(bus, -1, "cirrus-vga");
a414c306 2962}
d34cab9f 2963
a414c306 2964static PCIDeviceInfo cirrus_vga_info = {
556cd098
MA		 2965 .qdev.name = "cirrus-vga",
2966 .qdev.desc = "Cirrus CLGD 54xx VGA",
a414c306 2967 .qdev.size = sizeof(PCICirrusVGAState),
be73cfe2 2968 .qdev.vmsd = &vmstate_pci_cirrus_vga,
be92bbf7 2969 .no_hotplug = 1,
a414c306 2970 .init = pci_cirrus_vga_initfn,
8c52c8f3 2971 .romfile = VGABIOS_CIRRUS_FILENAME,
5b96d8f9
IY		 2972 .vendor_id = PCI_VENDOR_ID_CIRRUS,
2973 .device_id = CIRRUS_ID_CLGD5446,
2974 .class_id = PCI_CLASS_DISPLAY_VGA,
a414c306 2975};
e6e5ad80 2976
a414c306
GH		 2977static void cirrus_vga_register(void)
2978{
2979 pci_qdev_register(&cirrus_vga_info);
e6e5ad80 2980}
a414c306 2981device_init(cirrus_vga_register);
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