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dac write index register is r/w (Volker Ruppert)
[mirror_qemu.git] / hw / cirrus_vga.c
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e6e5ad80 1/*
aeb3c85f 2 * QEMU Cirrus CLGD 54xx VGA Emulator.
e6e5ad80
FB		 3 *
4 * Copyright (c) 2004 Fabrice Bellard
aeb3c85f 5 * Copyright (c) 2004 Makoto Suzuki (suzu)
e6e5ad80
FB		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
aeb3c85f
FB		 25/*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
e6e5ad80
FB		 29#include "vl.h"
30#include "vga_int.h"
31
a5082316
FB		 32/*
33 * TODO:
34 * - add support for WRITEMASK (GR2F)
a5082316
FB		 35 * - optimize linear mappings
36 * - optimize bitblt functions
37 */
38
e36f36e1 39//#define DEBUG_CIRRUS
a21ae81d 40//#define DEBUG_BITBLT
e36f36e1 41
e6e5ad80
FB		 42/***************************************
43 *
44 * definitions
45 *
46 ***************************************/
47
48#define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
49
50// ID
51#define CIRRUS_ID_CLGD5422 (0x23<<2)
52#define CIRRUS_ID_CLGD5426 (0x24<<2)
53#define CIRRUS_ID_CLGD5424 (0x25<<2)
54#define CIRRUS_ID_CLGD5428 (0x26<<2)
55#define CIRRUS_ID_CLGD5430 (0x28<<2)
56#define CIRRUS_ID_CLGD5434 (0x2A<<2)
a21ae81d 57#define CIRRUS_ID_CLGD5436 (0x2B<<2)
e6e5ad80
FB		 58#define CIRRUS_ID_CLGD5446 (0x2E<<2)
59
60// sequencer 0x07
61#define CIRRUS_SR7_BPP_VGA 0x00
62#define CIRRUS_SR7_BPP_SVGA 0x01
63#define CIRRUS_SR7_BPP_MASK 0x0e
64#define CIRRUS_SR7_BPP_8 0x00
65#define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
66#define CIRRUS_SR7_BPP_24 0x04
67#define CIRRUS_SR7_BPP_16 0x06
68#define CIRRUS_SR7_BPP_32 0x08
69#define CIRRUS_SR7_ISAADDR_MASK 0xe0
70
71// sequencer 0x0f
72#define CIRRUS_MEMSIZE_512k 0x08
73#define CIRRUS_MEMSIZE_1M 0x10
74#define CIRRUS_MEMSIZE_2M 0x18
75#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
76
77// sequencer 0x12
78#define CIRRUS_CURSOR_SHOW 0x01
79#define CIRRUS_CURSOR_HIDDENPEL 0x02
80#define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
81
82// sequencer 0x17
83#define CIRRUS_BUSTYPE_VLBFAST 0x10
84#define CIRRUS_BUSTYPE_PCI 0x20
85#define CIRRUS_BUSTYPE_VLBSLOW 0x30
86#define CIRRUS_BUSTYPE_ISA 0x38
87#define CIRRUS_MMIO_ENABLE 0x04
88#define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
89#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
90
91// control 0x0b
92#define CIRRUS_BANKING_DUAL 0x01
93#define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
94
95// control 0x30
96#define CIRRUS_BLTMODE_BACKWARDS 0x01
97#define CIRRUS_BLTMODE_MEMSYSDEST 0x02
98#define CIRRUS_BLTMODE_MEMSYSSRC 0x04
99#define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
100#define CIRRUS_BLTMODE_PATTERNCOPY 0x40
101#define CIRRUS_BLTMODE_COLOREXPAND 0x80
102#define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
103#define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
104#define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
105#define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
106#define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
107
108// control 0x31
109#define CIRRUS_BLT_BUSY 0x01
110#define CIRRUS_BLT_START 0x02
111#define CIRRUS_BLT_RESET 0x04
112#define CIRRUS_BLT_FIFOUSED 0x10
a5082316 113#define CIRRUS_BLT_AUTOSTART 0x80
e6e5ad80
FB		 114
115// control 0x32
116#define CIRRUS_ROP_0 0x00
117#define CIRRUS_ROP_SRC_AND_DST 0x05
118#define CIRRUS_ROP_NOP 0x06
119#define CIRRUS_ROP_SRC_AND_NOTDST 0x09
120#define CIRRUS_ROP_NOTDST 0x0b
121#define CIRRUS_ROP_SRC 0x0d
122#define CIRRUS_ROP_1 0x0e
123#define CIRRUS_ROP_NOTSRC_AND_DST 0x50
124#define CIRRUS_ROP_SRC_XOR_DST 0x59
125#define CIRRUS_ROP_SRC_OR_DST 0x6d
126#define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
127#define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
128#define CIRRUS_ROP_SRC_OR_NOTDST 0xad
129#define CIRRUS_ROP_NOTSRC 0xd0
130#define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
131#define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
132
a5082316
FB		 133#define CIRRUS_ROP_NOP_INDEX 2
134#define CIRRUS_ROP_SRC_INDEX 5
135
a21ae81d 136// control 0x33
a5082316 137#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
4c8732d7 138#define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
a5082316 139#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
a21ae81d 140
e6e5ad80
FB		 141// memory-mapped IO
142#define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
143#define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
144#define CIRRUS_MMIO_BLTWIDTH 0x08 // word
145#define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
146#define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
147#define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
148#define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
149#define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
150#define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
151#define CIRRUS_MMIO_BLTMODE 0x18 // byte
152#define CIRRUS_MMIO_BLTROP 0x1a // byte
153#define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
154#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
155#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
156#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
157#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
158#define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
159#define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
160#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
161#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
162#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
163#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
164#define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
165#define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
166#define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
167#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
168#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
169#define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
170#define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
171
172// PCI 0x00: vendor, 0x02: device
173#define PCI_VENDOR_CIRRUS 0x1013
e6e5ad80
FB		 174#define PCI_DEVICE_CLGD5462 0x00d0
175#define PCI_DEVICE_CLGD5465 0x00d6
a21ae81d 176
e6e5ad80
FB		 177// PCI 0x04: command(word), 0x06(word): status
178#define PCI_COMMAND_IOACCESS 0x0001
179#define PCI_COMMAND_MEMACCESS 0x0002
180#define PCI_COMMAND_BUSMASTER 0x0004
181#define PCI_COMMAND_SPECIALCYCLE 0x0008
182#define PCI_COMMAND_MEMWRITEINVALID 0x0010
183#define PCI_COMMAND_PALETTESNOOPING 0x0020
184#define PCI_COMMAND_PARITYDETECTION 0x0040
185#define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
186#define PCI_COMMAND_SERR 0x0100
187#define PCI_COMMAND_BACKTOBACKTRANS 0x0200
188// PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
189#define PCI_CLASS_BASE_DISPLAY 0x03
190// PCI 0x08, 0x00ff0000
191#define PCI_CLASS_SUB_VGA 0x00
192// PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
193#define PCI_CLASS_HEADERTYPE_00h 0x00
194// 0x10-0x3f (headertype 00h)
195// PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
196// 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
197#define PCI_MAP_MEM 0x0
198#define PCI_MAP_IO 0x1
199#define PCI_MAP_MEM_ADDR_MASK (~0xf)
200#define PCI_MAP_IO_ADDR_MASK (~0x3)
201#define PCI_MAP_MEMFLAGS_32BIT 0x0
202#define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
203#define PCI_MAP_MEMFLAGS_64BIT 0x4
204#define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
205// PCI 0x28: cardbus CIS pointer
206// PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
207// PCI 0x30: expansion ROM base address
208#define PCI_ROMBIOS_ENABLED 0x1
209// PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
210// PCI 0x38: reserved
211// PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
212
a21ae81d 213#define CIRRUS_PNPMMIO_SIZE 0x1000
e6e5ad80
FB		 214
215
216/* I/O and memory hook */
217#define CIRRUS_HOOK_NOT_HANDLED 0
218#define CIRRUS_HOOK_HANDLED 1
219
a5082316
FB		 220struct CirrusVGAState;
221typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
222 uint8_t * dst, const uint8_t * src,
e6e5ad80
FB		 223 int dstpitch, int srcpitch,
224 int bltwidth, int bltheight);
a5082316
FB		 225typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
226 uint8_t *dst, int dst_pitch, int width, int height);
e6e5ad80
FB		 227
228typedef struct CirrusVGAState {
4e3e9d0b 229 VGA_STATE_COMMON
e6e5ad80
FB		 230
231 int cirrus_linear_io_addr;
a5082316 232 int cirrus_linear_bitblt_io_addr;
e6e5ad80
FB		 233 int cirrus_mmio_io_addr;
234 uint32_t cirrus_addr_mask;
78e127ef 235 uint32_t linear_mmio_mask;
e6e5ad80
FB		 236 uint8_t cirrus_shadow_gr0;
237 uint8_t cirrus_shadow_gr1;
238 uint8_t cirrus_hidden_dac_lockindex;
239 uint8_t cirrus_hidden_dac_data;
240 uint32_t cirrus_bank_base[2];
241 uint32_t cirrus_bank_limit[2];
242 uint8_t cirrus_hidden_palette[48];
a5082316
FB		 243 uint32_t hw_cursor_x;
244 uint32_t hw_cursor_y;
e6e5ad80
FB		 245 int cirrus_blt_pixelwidth;
246 int cirrus_blt_width;
247 int cirrus_blt_height;
248 int cirrus_blt_dstpitch;
249 int cirrus_blt_srcpitch;
a5082316
FB		 250 uint32_t cirrus_blt_fgcol;
251 uint32_t cirrus_blt_bgcol;
e6e5ad80
FB		 252 uint32_t cirrus_blt_dstaddr;
253 uint32_t cirrus_blt_srcaddr;
254 uint8_t cirrus_blt_mode;
a5082316 255 uint8_t cirrus_blt_modeext;
e6e5ad80 256 cirrus_bitblt_rop_t cirrus_rop;
a5082316 257#define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
e6e5ad80
FB		 258 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
259 uint8_t *cirrus_srcptr;
260 uint8_t *cirrus_srcptr_end;
261 uint32_t cirrus_srccounter;
262 uint8_t *cirrus_dstptr;
263 uint8_t *cirrus_dstptr_end;
264 uint32_t cirrus_dstcounter;
a5082316
FB		 265 /* hwcursor display state */
266 int last_hw_cursor_size;
267 int last_hw_cursor_x;
268 int last_hw_cursor_y;
269 int last_hw_cursor_y_start;
270 int last_hw_cursor_y_end;
78e127ef 271 int real_vram_size; /* XXX: suppress that */
e6e5ad80
FB		 272} CirrusVGAState;
273
274typedef struct PCICirrusVGAState {
275 PCIDevice dev;
276 CirrusVGAState cirrus_vga;
277} PCICirrusVGAState;
278
a5082316
FB		 279static uint8_t rop_to_index[256];
280
e6e5ad80
FB		 281/***************************************
282 *
283 * prototypes.
284 *
285 ***************************************/
286
287
288static void cirrus_bitblt_reset(CirrusVGAState * s);
289
290/***************************************
291 *
292 * raster operations
293 *
294 ***************************************/
295
a5082316
FB		 296static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
297 uint8_t *dst,const uint8_t *src,
298 int dstpitch,int srcpitch,
299 int bltwidth,int bltheight)
300{
e6e5ad80
FB		 301}
302
a5082316
FB		 303static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
304 uint8_t *dst,
305 int dstpitch, int bltwidth,int bltheight)
e6e5ad80 306{
a5082316 307}
e6e5ad80 308
a5082316
FB		 309#define ROP_NAME 0
310#define ROP_OP(d, s) d = 0
311#include "cirrus_vga_rop.h"
e6e5ad80 312
a5082316
FB		 313#define ROP_NAME src_and_dst
314#define ROP_OP(d, s) d = (s) & (d)
315#include "cirrus_vga_rop.h"
e6e5ad80 316
a5082316
FB		 317#define ROP_NAME src_and_notdst
318#define ROP_OP(d, s) d = (s) & (~(d))
319#include "cirrus_vga_rop.h"
e6e5ad80 320
a5082316
FB		 321#define ROP_NAME notdst
322#define ROP_OP(d, s) d = ~(d)
323#include "cirrus_vga_rop.h"
e6e5ad80 324
a5082316
FB		 325#define ROP_NAME src
326#define ROP_OP(d, s) d = s
327#include "cirrus_vga_rop.h"
e6e5ad80 328
a5082316 329#define ROP_NAME 1
4c8732d7 330#define ROP_OP(d, s) d = ~0
a5082316
FB		 331#include "cirrus_vga_rop.h"
332
333#define ROP_NAME notsrc_and_dst
334#define ROP_OP(d, s) d = (~(s)) & (d)
335#include "cirrus_vga_rop.h"
336
337#define ROP_NAME src_xor_dst
338#define ROP_OP(d, s) d = (s) ^ (d)
339#include "cirrus_vga_rop.h"
340
341#define ROP_NAME src_or_dst
342#define ROP_OP(d, s) d = (s) | (d)
343#include "cirrus_vga_rop.h"
344
345#define ROP_NAME notsrc_or_notdst
346#define ROP_OP(d, s) d = (~(s)) | (~(d))
347#include "cirrus_vga_rop.h"
348
349#define ROP_NAME src_notxor_dst
350#define ROP_OP(d, s) d = ~((s) ^ (d))
351#include "cirrus_vga_rop.h"
e6e5ad80 352
a5082316
FB		 353#define ROP_NAME src_or_notdst
354#define ROP_OP(d, s) d = (s) | (~(d))
355#include "cirrus_vga_rop.h"
356
357#define ROP_NAME notsrc
358#define ROP_OP(d, s) d = (~(s))
359#include "cirrus_vga_rop.h"
360
361#define ROP_NAME notsrc_or_dst
362#define ROP_OP(d, s) d = (~(s)) | (d)
363#include "cirrus_vga_rop.h"
364
365#define ROP_NAME notsrc_and_notdst
366#define ROP_OP(d, s) d = (~(s)) & (~(d))
367#include "cirrus_vga_rop.h"
368
369static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
370 cirrus_bitblt_rop_fwd_0,
371 cirrus_bitblt_rop_fwd_src_and_dst,
372 cirrus_bitblt_rop_nop,
373 cirrus_bitblt_rop_fwd_src_and_notdst,
374 cirrus_bitblt_rop_fwd_notdst,
375 cirrus_bitblt_rop_fwd_src,
376 cirrus_bitblt_rop_fwd_1,
377 cirrus_bitblt_rop_fwd_notsrc_and_dst,
378 cirrus_bitblt_rop_fwd_src_xor_dst,
379 cirrus_bitblt_rop_fwd_src_or_dst,
380 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
381 cirrus_bitblt_rop_fwd_src_notxor_dst,
382 cirrus_bitblt_rop_fwd_src_or_notdst,
383 cirrus_bitblt_rop_fwd_notsrc,
384 cirrus_bitblt_rop_fwd_notsrc_or_dst,
385 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
386};
387
388static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
389 cirrus_bitblt_rop_bkwd_0,
390 cirrus_bitblt_rop_bkwd_src_and_dst,
391 cirrus_bitblt_rop_nop,
392 cirrus_bitblt_rop_bkwd_src_and_notdst,
393 cirrus_bitblt_rop_bkwd_notdst,
394 cirrus_bitblt_rop_bkwd_src,
395 cirrus_bitblt_rop_bkwd_1,
396 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
397 cirrus_bitblt_rop_bkwd_src_xor_dst,
398 cirrus_bitblt_rop_bkwd_src_or_dst,
399 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
400 cirrus_bitblt_rop_bkwd_src_notxor_dst,
401 cirrus_bitblt_rop_bkwd_src_or_notdst,
402 cirrus_bitblt_rop_bkwd_notsrc,
403 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
404 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
405};
406
407#define ROP2(name) {\
408 name ## _8,\
409 name ## _16,\
410 name ## _24,\
411 name ## _32,\
412 }
413
414#define ROP_NOP2(func) {\
415 func,\
416 func,\
417 func,\
418 func,\
419 }
420
e69390ce
FB		 421static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
422 ROP2(cirrus_patternfill_0),
423 ROP2(cirrus_patternfill_src_and_dst),
424 ROP_NOP2(cirrus_bitblt_rop_nop),
425 ROP2(cirrus_patternfill_src_and_notdst),
426 ROP2(cirrus_patternfill_notdst),
427 ROP2(cirrus_patternfill_src),
428 ROP2(cirrus_patternfill_1),
429 ROP2(cirrus_patternfill_notsrc_and_dst),
430 ROP2(cirrus_patternfill_src_xor_dst),
431 ROP2(cirrus_patternfill_src_or_dst),
432 ROP2(cirrus_patternfill_notsrc_or_notdst),
433 ROP2(cirrus_patternfill_src_notxor_dst),
434 ROP2(cirrus_patternfill_src_or_notdst),
435 ROP2(cirrus_patternfill_notsrc),
436 ROP2(cirrus_patternfill_notsrc_or_dst),
437 ROP2(cirrus_patternfill_notsrc_and_notdst),
438};
439
a5082316
FB		 440static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
441 ROP2(cirrus_colorexpand_transp_0),
442 ROP2(cirrus_colorexpand_transp_src_and_dst),
443 ROP_NOP2(cirrus_bitblt_rop_nop),
444 ROP2(cirrus_colorexpand_transp_src_and_notdst),
445 ROP2(cirrus_colorexpand_transp_notdst),
446 ROP2(cirrus_colorexpand_transp_src),
447 ROP2(cirrus_colorexpand_transp_1),
448 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
449 ROP2(cirrus_colorexpand_transp_src_xor_dst),
450 ROP2(cirrus_colorexpand_transp_src_or_dst),
451 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
452 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
453 ROP2(cirrus_colorexpand_transp_src_or_notdst),
454 ROP2(cirrus_colorexpand_transp_notsrc),
455 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
456 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
457};
458
4c8732d7
FB		 459static const cirrus_bitblt_rop_t cirrus_colorexpand_transp_inv[16][4] = {
460 ROP2(cirrus_colorexpand_transp_inv_0),
461 ROP2(cirrus_colorexpand_transp_inv_src_and_dst),
462 ROP_NOP2(cirrus_bitblt_rop_nop),
463 ROP2(cirrus_colorexpand_transp_inv_src_and_notdst),
464 ROP2(cirrus_colorexpand_transp_inv_notdst),
465 ROP2(cirrus_colorexpand_transp_inv_src),
466 ROP2(cirrus_colorexpand_transp_inv_1),
467 ROP2(cirrus_colorexpand_transp_inv_notsrc_and_dst),
468 ROP2(cirrus_colorexpand_transp_inv_src_xor_dst),
469 ROP2(cirrus_colorexpand_transp_inv_src_or_dst),
470 ROP2(cirrus_colorexpand_transp_inv_notsrc_or_notdst),
471 ROP2(cirrus_colorexpand_transp_inv_src_notxor_dst),
472 ROP2(cirrus_colorexpand_transp_inv_src_or_notdst),
473 ROP2(cirrus_colorexpand_transp_inv_notsrc),
474 ROP2(cirrus_colorexpand_transp_inv_notsrc_or_dst),
475 ROP2(cirrus_colorexpand_transp_inv_notsrc_and_notdst),
476};
477
a5082316
FB		 478static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
479 ROP2(cirrus_colorexpand_0),
480 ROP2(cirrus_colorexpand_src_and_dst),
481 ROP_NOP2(cirrus_bitblt_rop_nop),
482 ROP2(cirrus_colorexpand_src_and_notdst),
483 ROP2(cirrus_colorexpand_notdst),
484 ROP2(cirrus_colorexpand_src),
485 ROP2(cirrus_colorexpand_1),
486 ROP2(cirrus_colorexpand_notsrc_and_dst),
487 ROP2(cirrus_colorexpand_src_xor_dst),
488 ROP2(cirrus_colorexpand_src_or_dst),
489 ROP2(cirrus_colorexpand_notsrc_or_notdst),
490 ROP2(cirrus_colorexpand_src_notxor_dst),
491 ROP2(cirrus_colorexpand_src_or_notdst),
492 ROP2(cirrus_colorexpand_notsrc),
493 ROP2(cirrus_colorexpand_notsrc_or_dst),
494 ROP2(cirrus_colorexpand_notsrc_and_notdst),
495};
496
497static const cirrus_fill_t cirrus_fill[16][4] = {
498 ROP2(cirrus_fill_0),
499 ROP2(cirrus_fill_src_and_dst),
500 ROP_NOP2(cirrus_bitblt_fill_nop),
501 ROP2(cirrus_fill_src_and_notdst),
502 ROP2(cirrus_fill_notdst),
503 ROP2(cirrus_fill_src),
504 ROP2(cirrus_fill_1),
505 ROP2(cirrus_fill_notsrc_and_dst),
506 ROP2(cirrus_fill_src_xor_dst),
507 ROP2(cirrus_fill_src_or_dst),
508 ROP2(cirrus_fill_notsrc_or_notdst),
509 ROP2(cirrus_fill_src_notxor_dst),
510 ROP2(cirrus_fill_src_or_notdst),
511 ROP2(cirrus_fill_notsrc),
512 ROP2(cirrus_fill_notsrc_or_dst),
513 ROP2(cirrus_fill_notsrc_and_notdst),
514};
515
516static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
e6e5ad80 517{
a5082316
FB		 518 unsigned int color;
519 switch (s->cirrus_blt_pixelwidth) {
520 case 1:
521 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
522 break;
523 case 2:
524 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8);
525 s->cirrus_blt_fgcol = le16_to_cpu(color);
526 break;
527 case 3:
528 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
529 (s->gr[0x11] << 8) | (s->gr[0x13] << 16);
530 break;
531 default:
532 case 4:
533 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) |
534 (s->gr[0x13] << 16) | (s->gr[0x15] << 24);
535 s->cirrus_blt_fgcol = le32_to_cpu(color);
536 break;
e6e5ad80
FB		 537 }
538}
539
a5082316 540static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
e6e5ad80 541{
a5082316 542 unsigned int color;
e6e5ad80
FB		 543 switch (s->cirrus_blt_pixelwidth) {
544 case 1:
a5082316
FB		 545 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
546 break;
e6e5ad80 547 case 2:
a5082316
FB		 548 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8);
549 s->cirrus_blt_bgcol = le16_to_cpu(color);
550 break;
e6e5ad80 551 case 3:
a5082316
FB		 552 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
553 (s->gr[0x10] << 8) | (s->gr[0x12] << 16);
554 break;
e6e5ad80 555 default:
a5082316
FB		 556 case 4:
557 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8) |
558 (s->gr[0x12] << 16) | (s->gr[0x14] << 24);
559 s->cirrus_blt_bgcol = le32_to_cpu(color);
560 break;
e6e5ad80
FB		 561 }
562}
563
564static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
565 int off_pitch, int bytesperline,
566 int lines)
567{
568 int y;
569 int off_cur;
570 int off_cur_end;
571
572 for (y = 0; y < lines; y++) {
573 off_cur = off_begin;
574 off_cur_end = off_cur + bytesperline;
575 off_cur &= TARGET_PAGE_MASK;
576 while (off_cur < off_cur_end) {
577 cpu_physical_memory_set_dirty(s->vram_offset + off_cur);
578 off_cur += TARGET_PAGE_SIZE;
579 }
580 off_begin += off_pitch;
581 }
582}
583
e6e5ad80
FB		 584static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
585 const uint8_t * src)
586{
587 uint8_t work_colorexp[256];
588 uint8_t *dst;
e6e5ad80
FB		 589 int patternbytes = s->cirrus_blt_pixelwidth * 8;
590
591 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316
FB		 592 cirrus_bitblt_rop_t rop_func;
593 cirrus_bitblt_fgcol(s);
594 cirrus_bitblt_bgcol(s);
595 rop_func = cirrus_colorexpand[CIRRUS_ROP_SRC_INDEX][s->cirrus_blt_pixelwidth - 1];
596 rop_func(s, work_colorexp, src, patternbytes, 1, patternbytes, 8);
e6e5ad80
FB		 597 src = work_colorexp;
598 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_COLOREXPAND;
599 }
600 if (s->cirrus_blt_mode & ~CIRRUS_BLTMODE_PATTERNCOPY) {
a5082316 601#ifdef DEBUG_BITBLT
e6e5ad80
FB		 602 printf("cirrus: blt mode %02x (pattercopy) - unimplemented\n",
603 s->cirrus_blt_mode);
604#endif
605 return 0;
606 }
a21ae81d 607
e6e5ad80 608 dst = s->vram_ptr + s->cirrus_blt_dstaddr;
e69390ce
FB		 609 (*s->cirrus_rop) (s, dst, src,
610 s->cirrus_blt_dstpitch, 0,
611 s->cirrus_blt_width, s->cirrus_blt_height);
e6e5ad80 612 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
e69390ce
FB		 613 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
614 s->cirrus_blt_height);
e6e5ad80
FB		 615 return 1;
616}
617
a21ae81d
FB		 618/* fill */
619
a5082316 620static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
a21ae81d 621{
a5082316 622 cirrus_fill_t rop_func;
a21ae81d 623
a5082316
FB		 624 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
625 rop_func(s, s->vram_ptr + s->cirrus_blt_dstaddr,
626 s->cirrus_blt_dstpitch,
627 s->cirrus_blt_width, s->cirrus_blt_height);
a21ae81d
FB		 628 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
629 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
630 s->cirrus_blt_height);
631 cirrus_bitblt_reset(s);
632 return 1;
633}
634
e6e5ad80
FB		 635/***************************************
636 *
637 * bitblt (video-to-video)
638 *
639 ***************************************/
640
641static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
642{
643 return cirrus_bitblt_common_patterncopy(s,
e69390ce
FB		 644 s->vram_ptr +
645 (s->cirrus_blt_srcaddr & ~7));
e6e5ad80
FB		 646}
647
648static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
649{
a5082316 650 (*s->cirrus_rop) (s, s->vram_ptr + s->cirrus_blt_dstaddr,
e6e5ad80
FB		 651 s->vram_ptr + s->cirrus_blt_srcaddr,
652 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
653 s->cirrus_blt_width, s->cirrus_blt_height);
654 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
655 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
656 s->cirrus_blt_height);
657 return 1;
658}
659
660/***************************************
661 *
662 * bitblt (cpu-to-video)
663 *
664 ***************************************/
665
e6e5ad80
FB		 666static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
667{
668 int copy_count;
a5082316
FB		 669 uint8_t *end_ptr;
670
e6e5ad80 671 if (s->cirrus_srccounter > 0) {
a5082316
FB		 672 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
673 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
674 the_end:
675 s->cirrus_srccounter = 0;
676 cirrus_bitblt_reset(s);
677 } else {
678 /* at least one scan line */
679 do {
680 (*s->cirrus_rop)(s, s->vram_ptr + s->cirrus_blt_dstaddr,
681 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
682 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
683 s->cirrus_blt_width, 1);
684 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
685 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
686 if (s->cirrus_srccounter <= 0)
687 goto the_end;
688 /* more bytes than needed can be transfered because of
689 word alignment, so we keep them for the next line */
690 /* XXX: keep alignment to speed up transfer */
691 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
692 copy_count = s->cirrus_srcptr_end - end_ptr;
693 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
694 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
695 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
696 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
697 }
e6e5ad80
FB		 698 }
699}
700
701/***************************************
702 *
703 * bitblt wrapper
704 *
705 ***************************************/
706
707static void cirrus_bitblt_reset(CirrusVGAState * s)
708{
709 s->gr[0x31] &=
710 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
711 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
712 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
713 s->cirrus_srccounter = 0;
714 s->cirrus_dstptr = &s->cirrus_bltbuf[0];
715 s->cirrus_dstptr_end = &s->cirrus_bltbuf[0];
716 s->cirrus_dstcounter = 0;
e6e5ad80
FB		 717}
718
719static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
720{
a5082316
FB		 721 int w;
722
e6e5ad80
FB		 723 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
724 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
725 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
726
727 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
728 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316 729 s->cirrus_blt_srcpitch = 8;
e6e5ad80 730 } else {
a5082316 731 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
e6e5ad80 732 }
a5082316 733 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
e6e5ad80
FB		 734 } else {
735 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
a5082316
FB		 736 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
737 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
738 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
739 else
740 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
e6e5ad80 741 } else {
e6e5ad80
FB		 742 s->cirrus_blt_srcpitch = s->cirrus_blt_width;
743 }
a5082316 744 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
e6e5ad80 745 }
a5082316
FB		 746 s->cirrus_srcptr = s->cirrus_bltbuf;
747 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
e6e5ad80
FB		 748 return 1;
749}
750
751static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
752{
753 /* XXX */
a5082316 754#ifdef DEBUG_BITBLT
e6e5ad80
FB		 755 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
756#endif
757 return 0;
758}
759
760static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
761{
762 int ret;
763
764 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
765 ret = cirrus_bitblt_videotovideo_patterncopy(s);
766 } else {
767 ret = cirrus_bitblt_videotovideo_copy(s);
768 }
e6e5ad80
FB		 769 if (ret)
770 cirrus_bitblt_reset(s);
771 return ret;
772}
773
774static void cirrus_bitblt_start(CirrusVGAState * s)
775{
776 uint8_t blt_rop;
777
a5082316
FB		 778 s->gr[0x31] |= CIRRUS_BLT_BUSY;
779
e6e5ad80
FB		 780 s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1;
781 s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1;
782 s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8));
783 s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8));
784 s->cirrus_blt_dstaddr =
785 (s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16));
786 s->cirrus_blt_srcaddr =
787 (s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16));
788 s->cirrus_blt_mode = s->gr[0x30];
a5082316 789 s->cirrus_blt_modeext = s->gr[0x33];
e6e5ad80
FB		 790 blt_rop = s->gr[0x32];
791
a21ae81d 792#ifdef DEBUG_BITBLT
a5082316 793 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spicth=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
a21ae81d
FB		 794 blt_rop,
795 s->cirrus_blt_mode,
a5082316 796 s->cirrus_blt_modeext,
a21ae81d
FB		 797 s->cirrus_blt_width,
798 s->cirrus_blt_height,
799 s->cirrus_blt_dstpitch,
800 s->cirrus_blt_srcpitch,
801 s->cirrus_blt_dstaddr,
a5082316
FB		 802 s->cirrus_blt_srcaddr,
803 s->sr[0x2f]);
a21ae81d
FB		 804#endif
805
e6e5ad80
FB		 806 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
807 case CIRRUS_BLTMODE_PIXELWIDTH8:
808 s->cirrus_blt_pixelwidth = 1;
809 break;
810 case CIRRUS_BLTMODE_PIXELWIDTH16:
811 s->cirrus_blt_pixelwidth = 2;
812 break;
813 case CIRRUS_BLTMODE_PIXELWIDTH24:
814 s->cirrus_blt_pixelwidth = 3;
815 break;
816 case CIRRUS_BLTMODE_PIXELWIDTH32:
817 s->cirrus_blt_pixelwidth = 4;
818 break;
819 default:
a5082316 820#ifdef DEBUG_BITBLT
e6e5ad80
FB		 821 printf("cirrus: bitblt - pixel width is unknown\n");
822#endif
823 goto bitblt_ignore;
824 }
825 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
826
827 if ((s->
828 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
829 CIRRUS_BLTMODE_MEMSYSDEST))
830 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
a5082316 831#ifdef DEBUG_BITBLT
e6e5ad80
FB		 832 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
833#endif
834 goto bitblt_ignore;
835 }
836
a5082316 837 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
a21ae81d
FB		 838 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
839 CIRRUS_BLTMODE_TRANSPARENTCOMP |
840 CIRRUS_BLTMODE_PATTERNCOPY |
841 CIRRUS_BLTMODE_COLOREXPAND)) ==
842 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
a5082316
FB		 843 cirrus_bitblt_fgcol(s);
844 cirrus_bitblt_solidfill(s, blt_rop);
e6e5ad80 845 } else {
a5082316
FB		 846 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
847 CIRRUS_BLTMODE_PATTERNCOPY)) ==
848 CIRRUS_BLTMODE_COLOREXPAND) {
849
850 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
4c8732d7
FB		 851 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV) {
852 cirrus_bitblt_bgcol(s);
853 s->cirrus_rop = cirrus_colorexpand_transp_inv[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
854 } else {
855 cirrus_bitblt_fgcol(s);
856 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
857 }
a5082316
FB		 858 } else {
859 cirrus_bitblt_fgcol(s);
860 cirrus_bitblt_bgcol(s);
861 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
862 }
e69390ce
FB		 863 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
864 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
a21ae81d 865 } else {
a5082316
FB		 866 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
867 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
868 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
869 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
870 } else {
871 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
872 }
a21ae81d
FB		 873 }
874
875 // setup bitblt engine.
876 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
877 if (!cirrus_bitblt_cputovideo(s))
878 goto bitblt_ignore;
879 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
880 if (!cirrus_bitblt_videotocpu(s))
881 goto bitblt_ignore;
882 } else {
883 if (!cirrus_bitblt_videotovideo(s))
884 goto bitblt_ignore;
885 }
e6e5ad80 886 }
e6e5ad80
FB		 887 return;
888 bitblt_ignore:;
889 cirrus_bitblt_reset(s);
890}
891
892static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
893{
894 unsigned old_value;
895
896 old_value = s->gr[0x31];
897 s->gr[0x31] = reg_value;
898
899 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
900 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
901 cirrus_bitblt_reset(s);
902 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
903 ((reg_value & CIRRUS_BLT_START) != 0)) {
e6e5ad80
FB		 904 cirrus_bitblt_start(s);
905 }
906}
907
908
909/***************************************
910 *
911 * basic parameters
912 *
913 ***************************************/
914
915static void cirrus_get_offsets(VGAState *s1,
916 uint32_t *pline_offset,
917 uint32_t *pstart_addr)
918{
919 CirrusVGAState * s = (CirrusVGAState *)s1;
920 uint32_t start_addr;
921 uint32_t line_offset;
922
923 line_offset = s->cr[0x13]
e36f36e1 924 | ((s->cr[0x1b] & 0x10) << 4);
e6e5ad80
FB		 925 line_offset <<= 3;
926 *pline_offset = line_offset;
927
928 start_addr = (s->cr[0x0c] << 8)
929 | s->cr[0x0d]
930 | ((s->cr[0x1b] & 0x01) << 16)
931 | ((s->cr[0x1b] & 0x0c) << 15)
932 | ((s->cr[0x1d] & 0x80) << 12);
933 *pstart_addr = start_addr;
934}
935
936static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
937{
938 uint32_t ret = 16;
939
940 switch (s->cirrus_hidden_dac_data & 0xf) {
941 case 0:
942 ret = 15;
943 break; /* Sierra HiColor */
944 case 1:
945 ret = 16;
946 break; /* XGA HiColor */
947 default:
948#ifdef DEBUG_CIRRUS
949 printf("cirrus: invalid DAC value %x in 16bpp\n",
950 (s->cirrus_hidden_dac_data & 0xf));
951#endif
952 ret = 15; /* XXX */
953 break;
954 }
955 return ret;
956}
957
958static int cirrus_get_bpp(VGAState *s1)
959{
960 CirrusVGAState * s = (CirrusVGAState *)s1;
961 uint32_t ret = 8;
962
963 if ((s->sr[0x07] & 0x01) != 0) {
964 /* Cirrus SVGA */
965 switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) {
966 case CIRRUS_SR7_BPP_8:
967 ret = 8;
968 break;
969 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
970 ret = cirrus_get_bpp16_depth(s);
971 break;
972 case CIRRUS_SR7_BPP_24:
973 ret = 24;
974 break;
975 case CIRRUS_SR7_BPP_16:
976 ret = cirrus_get_bpp16_depth(s);
977 break;
978 case CIRRUS_SR7_BPP_32:
979 ret = 32;
980 break;
981 default:
982#ifdef DEBUG_CIRRUS
983 printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]);
984#endif
985 ret = 8;
986 break;
987 }
988 } else {
989 /* VGA */
aeb3c85f 990 ret = 0;
e6e5ad80
FB		 991 }
992
993 return ret;
994}
995
78e127ef
FB		 996static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)
997{
998 int width, height;
999
1000 width = (s->cr[0x01] + 1) * 8;
1001 height = s->cr[0x12] |
1002 ((s->cr[0x07] & 0x02) << 7) |
1003 ((s->cr[0x07] & 0x40) << 3);
1004 height = (height + 1);
1005 /* interlace support */
1006 if (s->cr[0x1a] & 0x01)
1007 height = height * 2;
1008 *pwidth = width;
1009 *pheight = height;
1010}
1011
e6e5ad80
FB		 1012/***************************************
1013 *
1014 * bank memory
1015 *
1016 ***************************************/
1017
1018static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1019{
1020 unsigned offset;
1021 unsigned limit;
1022
1023 if ((s->gr[0x0b] & 0x01) != 0) /* dual bank */
1024 offset = s->gr[0x09 + bank_index];
1025 else /* single bank */
1026 offset = s->gr[0x09];
1027
1028 if ((s->gr[0x0b] & 0x20) != 0)
1029 offset <<= 14;
1030 else
1031 offset <<= 12;
1032
1033 if (s->vram_size <= offset)
1034 limit = 0;
1035 else
1036 limit = s->vram_size - offset;
1037
1038 if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1039 if (limit > 0x8000) {
1040 offset += 0x8000;
1041 limit -= 0x8000;
1042 } else {
1043 limit = 0;
1044 }
1045 }
1046
1047 if (limit > 0) {
1048 s->cirrus_bank_base[bank_index] = offset;
1049 s->cirrus_bank_limit[bank_index] = limit;
1050 } else {
1051 s->cirrus_bank_base[bank_index] = 0;
1052 s->cirrus_bank_limit[bank_index] = 0;
1053 }
1054}
1055
1056/***************************************
1057 *
1058 * I/O access between 0x3c4-0x3c5
1059 *
1060 ***************************************/
1061
1062static int
1063cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1064{
1065 switch (reg_index) {
1066 case 0x00: // Standard VGA
1067 case 0x01: // Standard VGA
1068 case 0x02: // Standard VGA
1069 case 0x03: // Standard VGA
1070 case 0x04: // Standard VGA
1071 return CIRRUS_HOOK_NOT_HANDLED;
1072 case 0x06: // Unlock Cirrus extensions
1073 *reg_value = s->sr[reg_index];
1074 break;
e6e5ad80
FB		 1075 case 0x10:
1076 case 0x30:
1077 case 0x50:
1078 case 0x70: // Graphics Cursor X
1079 case 0x90:
1080 case 0xb0:
1081 case 0xd0:
1082 case 0xf0: // Graphics Cursor X
aeb3c85f
FB		 1083 *reg_value = s->sr[0x10];
1084 break;
e6e5ad80
FB		 1085 case 0x11:
1086 case 0x31:
1087 case 0x51:
1088 case 0x71: // Graphics Cursor Y
1089 case 0x91:
1090 case 0xb1:
1091 case 0xd1:
a5082316 1092 case 0xf1: // Graphics Cursor Y
aeb3c85f
FB		 1093 *reg_value = s->sr[0x11];
1094 break;
1095 case 0x05: // ???
1096 case 0x07: // Extended Sequencer Mode
1097 case 0x08: // EEPROM Control
1098 case 0x09: // Scratch Register 0
1099 case 0x0a: // Scratch Register 1
1100 case 0x0b: // VCLK 0
1101 case 0x0c: // VCLK 1
1102 case 0x0d: // VCLK 2
1103 case 0x0e: // VCLK 3
1104 case 0x0f: // DRAM Control
e6e5ad80
FB		 1105 case 0x12: // Graphics Cursor Attribute
1106 case 0x13: // Graphics Cursor Pattern Address
1107 case 0x14: // Scratch Register 2
1108 case 0x15: // Scratch Register 3
1109 case 0x16: // Performance Tuning Register
1110 case 0x17: // Configuration Readback and Extended Control
1111 case 0x18: // Signature Generator Control
1112 case 0x19: // Signal Generator Result
1113 case 0x1a: // Signal Generator Result
1114 case 0x1b: // VCLK 0 Denominator & Post
1115 case 0x1c: // VCLK 1 Denominator & Post
1116 case 0x1d: // VCLK 2 Denominator & Post
1117 case 0x1e: // VCLK 3 Denominator & Post
1118 case 0x1f: // BIOS Write Enable and MCLK select
1119#ifdef DEBUG_CIRRUS
1120 printf("cirrus: handled inport sr_index %02x\n", reg_index);
1121#endif
1122 *reg_value = s->sr[reg_index];
1123 break;
1124 default:
1125#ifdef DEBUG_CIRRUS
1126 printf("cirrus: inport sr_index %02x\n", reg_index);
1127#endif
1128 *reg_value = 0xff;
1129 break;
1130 }
1131
1132 return CIRRUS_HOOK_HANDLED;
1133}
1134
1135static int
1136cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1137{
1138 switch (reg_index) {
1139 case 0x00: // Standard VGA
1140 case 0x01: // Standard VGA
1141 case 0x02: // Standard VGA
1142 case 0x03: // Standard VGA
1143 case 0x04: // Standard VGA
1144 return CIRRUS_HOOK_NOT_HANDLED;
1145 case 0x06: // Unlock Cirrus extensions
1146 reg_value &= 0x17;
1147 if (reg_value == 0x12) {
1148 s->sr[reg_index] = 0x12;
1149 } else {
1150 s->sr[reg_index] = 0x0f;
1151 }
1152 break;
1153 case 0x10:
1154 case 0x30:
1155 case 0x50:
1156 case 0x70: // Graphics Cursor X
1157 case 0x90:
1158 case 0xb0:
1159 case 0xd0:
1160 case 0xf0: // Graphics Cursor X
1161 s->sr[0x10] = reg_value;
a5082316 1162 s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
e6e5ad80
FB		 1163 break;
1164 case 0x11:
1165 case 0x31:
1166 case 0x51:
1167 case 0x71: // Graphics Cursor Y
1168 case 0x91:
1169 case 0xb1:
1170 case 0xd1:
1171 case 0xf1: // Graphics Cursor Y
1172 s->sr[0x11] = reg_value;
a5082316 1173 s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
e6e5ad80
FB		 1174 break;
1175 case 0x07: // Extended Sequencer Mode
1176 case 0x08: // EEPROM Control
1177 case 0x09: // Scratch Register 0
1178 case 0x0a: // Scratch Register 1
1179 case 0x0b: // VCLK 0
1180 case 0x0c: // VCLK 1
1181 case 0x0d: // VCLK 2
1182 case 0x0e: // VCLK 3
1183 case 0x0f: // DRAM Control
1184 case 0x12: // Graphics Cursor Attribute
1185 case 0x13: // Graphics Cursor Pattern Address
1186 case 0x14: // Scratch Register 2
1187 case 0x15: // Scratch Register 3
1188 case 0x16: // Performance Tuning Register
1189 case 0x17: // Configuration Readback and Extended Control
1190 case 0x18: // Signature Generator Control
1191 case 0x19: // Signature Generator Result
1192 case 0x1a: // Signature Generator Result
1193 case 0x1b: // VCLK 0 Denominator & Post
1194 case 0x1c: // VCLK 1 Denominator & Post
1195 case 0x1d: // VCLK 2 Denominator & Post
1196 case 0x1e: // VCLK 3 Denominator & Post
1197 case 0x1f: // BIOS Write Enable and MCLK select
1198 s->sr[reg_index] = reg_value;
1199#ifdef DEBUG_CIRRUS
1200 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1201 reg_index, reg_value);
1202#endif
1203 break;
1204 default:
1205#ifdef DEBUG_CIRRUS
1206 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
1207 reg_value);
1208#endif
1209 break;
1210 }
1211
1212 return CIRRUS_HOOK_HANDLED;
1213}
1214
1215/***************************************
1216 *
1217 * I/O access at 0x3c6
1218 *
1219 ***************************************/
1220
1221static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
1222{
1223 *reg_value = 0xff;
a21ae81d
FB		 1224 if (++s->cirrus_hidden_dac_lockindex == 5) {
1225 *reg_value = s->cirrus_hidden_dac_data;
1226 s->cirrus_hidden_dac_lockindex = 0;
e6e5ad80
FB		 1227 }
1228}
1229
1230static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1231{
1232 if (s->cirrus_hidden_dac_lockindex == 4) {
1233 s->cirrus_hidden_dac_data = reg_value;
a21ae81d 1234#if defined(DEBUG_CIRRUS)
e6e5ad80
FB		 1235 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1236#endif
1237 }
1238 s->cirrus_hidden_dac_lockindex = 0;
1239}
1240
1241/***************************************
1242 *
1243 * I/O access at 0x3c9
1244 *
1245 ***************************************/
1246
1247static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1248{
1249 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1250 return CIRRUS_HOOK_NOT_HANDLED;
a5082316
FB		 1251 *reg_value =
1252 s->cirrus_hidden_palette[(s->dac_read_index & 0x0f) * 3 +
1253 s->dac_sub_index];
e6e5ad80
FB		 1254 if (++s->dac_sub_index == 3) {
1255 s->dac_sub_index = 0;
1256 s->dac_read_index++;
1257 }
1258 return CIRRUS_HOOK_HANDLED;
1259}
1260
1261static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1262{
1263 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1264 return CIRRUS_HOOK_NOT_HANDLED;
1265 s->dac_cache[s->dac_sub_index] = reg_value;
1266 if (++s->dac_sub_index == 3) {
a5082316
FB		 1267 memcpy(&s->cirrus_hidden_palette[(s->dac_write_index & 0x0f) * 3],
1268 s->dac_cache, 3);
1269 /* XXX update cursor */
e6e5ad80
FB		 1270 s->dac_sub_index = 0;
1271 s->dac_write_index++;
1272 }
1273 return CIRRUS_HOOK_HANDLED;
1274}
1275
1276/***************************************
1277 *
1278 * I/O access between 0x3ce-0x3cf
1279 *
1280 ***************************************/
1281
1282static int
1283cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1284{
1285 switch (reg_index) {
aeb3c85f
FB		 1286 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1287 *reg_value = s->cirrus_shadow_gr0;
1288 return CIRRUS_HOOK_HANDLED;
1289 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1290 *reg_value = s->cirrus_shadow_gr1;
1291 return CIRRUS_HOOK_HANDLED;
e6e5ad80
FB		 1292 case 0x02: // Standard VGA
1293 case 0x03: // Standard VGA
1294 case 0x04: // Standard VGA
1295 case 0x06: // Standard VGA
1296 case 0x07: // Standard VGA
1297 case 0x08: // Standard VGA
1298 return CIRRUS_HOOK_NOT_HANDLED;
1299 case 0x05: // Standard VGA, Cirrus extended mode
1300 default:
1301 break;
1302 }
1303
1304 if (reg_index < 0x3a) {
1305 *reg_value = s->gr[reg_index];
1306 } else {
1307#ifdef DEBUG_CIRRUS
1308 printf("cirrus: inport gr_index %02x\n", reg_index);
1309#endif
1310 *reg_value = 0xff;
1311 }
1312
1313 return CIRRUS_HOOK_HANDLED;
1314}
1315
1316static int
1317cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1318{
a5082316
FB		 1319#if defined(DEBUG_BITBLT) && 0
1320 printf("gr%02x: %02x\n", reg_index, reg_value);
1321#endif
e6e5ad80
FB		 1322 switch (reg_index) {
1323 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
aeb3c85f 1324 s->cirrus_shadow_gr0 = reg_value;
e6e5ad80
FB		 1325 return CIRRUS_HOOK_NOT_HANDLED;
1326 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
aeb3c85f 1327 s->cirrus_shadow_gr1 = reg_value;
e6e5ad80
FB		 1328 return CIRRUS_HOOK_NOT_HANDLED;
1329 case 0x02: // Standard VGA
1330 case 0x03: // Standard VGA
1331 case 0x04: // Standard VGA
1332 case 0x06: // Standard VGA
1333 case 0x07: // Standard VGA
1334 case 0x08: // Standard VGA
1335 return CIRRUS_HOOK_NOT_HANDLED;
1336 case 0x05: // Standard VGA, Cirrus extended mode
1337 s->gr[reg_index] = reg_value & 0x7f;
1338 break;
1339 case 0x09: // bank offset #0
1340 case 0x0A: // bank offset #1
1341 case 0x0B:
1342 s->gr[reg_index] = reg_value;
1343 cirrus_update_bank_ptr(s, 0);
1344 cirrus_update_bank_ptr(s, 1);
1345 break;
1346 case 0x10: // BGCOLOR 0x0000ff00
1347 case 0x11: // FGCOLOR 0x0000ff00
1348 case 0x12: // BGCOLOR 0x00ff0000
1349 case 0x13: // FGCOLOR 0x00ff0000
1350 case 0x14: // BGCOLOR 0xff000000
1351 case 0x15: // FGCOLOR 0xff000000
1352 case 0x20: // BLT WIDTH 0x0000ff
1353 case 0x22: // BLT HEIGHT 0x0000ff
1354 case 0x24: // BLT DEST PITCH 0x0000ff
1355 case 0x26: // BLT SRC PITCH 0x0000ff
1356 case 0x28: // BLT DEST ADDR 0x0000ff
1357 case 0x29: // BLT DEST ADDR 0x00ff00
1358 case 0x2c: // BLT SRC ADDR 0x0000ff
1359 case 0x2d: // BLT SRC ADDR 0x00ff00
a5082316 1360 case 0x2f: // BLT WRITEMASK
e6e5ad80
FB		 1361 case 0x30: // BLT MODE
1362 case 0x32: // RASTER OP
a21ae81d 1363 case 0x33: // BLT MODEEXT
e6e5ad80
FB		 1364 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1365 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1366 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1367 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1368 s->gr[reg_index] = reg_value;
1369 break;
1370 case 0x21: // BLT WIDTH 0x001f00
1371 case 0x23: // BLT HEIGHT 0x001f00
1372 case 0x25: // BLT DEST PITCH 0x001f00
1373 case 0x27: // BLT SRC PITCH 0x001f00
1374 s->gr[reg_index] = reg_value & 0x1f;
1375 break;
1376 case 0x2a: // BLT DEST ADDR 0x3f0000
a5082316
FB		 1377 s->gr[reg_index] = reg_value & 0x3f;
1378 /* if auto start mode, starts bit blt now */
1379 if (s->gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1380 cirrus_bitblt_start(s);
1381 }
1382 break;
e6e5ad80
FB		 1383 case 0x2e: // BLT SRC ADDR 0x3f0000
1384 s->gr[reg_index] = reg_value & 0x3f;
1385 break;
1386 case 0x31: // BLT STATUS/START
1387 cirrus_write_bitblt(s, reg_value);
1388 break;
1389 default:
1390#ifdef DEBUG_CIRRUS
1391 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1392 reg_value);
1393#endif
1394 break;
1395 }
1396
1397 return CIRRUS_HOOK_HANDLED;
1398}
1399
1400/***************************************
1401 *
1402 * I/O access between 0x3d4-0x3d5
1403 *
1404 ***************************************/
1405
1406static int
1407cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1408{
1409 switch (reg_index) {
1410 case 0x00: // Standard VGA
1411 case 0x01: // Standard VGA
1412 case 0x02: // Standard VGA
1413 case 0x03: // Standard VGA
1414 case 0x04: // Standard VGA
1415 case 0x05: // Standard VGA
1416 case 0x06: // Standard VGA
1417 case 0x07: // Standard VGA
1418 case 0x08: // Standard VGA
1419 case 0x09: // Standard VGA
1420 case 0x0a: // Standard VGA
1421 case 0x0b: // Standard VGA
1422 case 0x0c: // Standard VGA
1423 case 0x0d: // Standard VGA
1424 case 0x0e: // Standard VGA
1425 case 0x0f: // Standard VGA
1426 case 0x10: // Standard VGA
1427 case 0x11: // Standard VGA
1428 case 0x12: // Standard VGA
1429 case 0x13: // Standard VGA
1430 case 0x14: // Standard VGA
1431 case 0x15: // Standard VGA
1432 case 0x16: // Standard VGA
1433 case 0x17: // Standard VGA
1434 case 0x18: // Standard VGA
1435 return CIRRUS_HOOK_NOT_HANDLED;
1436 case 0x19: // Interlace End
1437 case 0x1a: // Miscellaneous Control
1438 case 0x1b: // Extended Display Control
1439 case 0x1c: // Sync Adjust and Genlock
1440 case 0x1d: // Overlay Extended Control
1441 case 0x22: // Graphics Data Latches Readback (R)
1442 case 0x24: // Attribute Controller Toggle Readback (R)
1443 case 0x25: // Part Status
1444 case 0x27: // Part ID (R)
1445 *reg_value = s->cr[reg_index];
1446 break;
1447 case 0x26: // Attribute Controller Index Readback (R)
1448 *reg_value = s->ar_index & 0x3f;
1449 break;
1450 default:
1451#ifdef DEBUG_CIRRUS
1452 printf("cirrus: inport cr_index %02x\n", reg_index);
1453 *reg_value = 0xff;
1454#endif
1455 break;
1456 }
1457
1458 return CIRRUS_HOOK_HANDLED;
1459}
1460
1461static int
1462cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1463{
1464 switch (reg_index) {
1465 case 0x00: // Standard VGA
1466 case 0x01: // Standard VGA
1467 case 0x02: // Standard VGA
1468 case 0x03: // Standard VGA
1469 case 0x04: // Standard VGA
1470 case 0x05: // Standard VGA
1471 case 0x06: // Standard VGA
1472 case 0x07: // Standard VGA
1473 case 0x08: // Standard VGA
1474 case 0x09: // Standard VGA
1475 case 0x0a: // Standard VGA
1476 case 0x0b: // Standard VGA
1477 case 0x0c: // Standard VGA
1478 case 0x0d: // Standard VGA
1479 case 0x0e: // Standard VGA
1480 case 0x0f: // Standard VGA
1481 case 0x10: // Standard VGA
1482 case 0x11: // Standard VGA
1483 case 0x12: // Standard VGA
1484 case 0x13: // Standard VGA
1485 case 0x14: // Standard VGA
1486 case 0x15: // Standard VGA
1487 case 0x16: // Standard VGA
1488 case 0x17: // Standard VGA
1489 case 0x18: // Standard VGA
1490 return CIRRUS_HOOK_NOT_HANDLED;
1491 case 0x19: // Interlace End
1492 case 0x1a: // Miscellaneous Control
1493 case 0x1b: // Extended Display Control
1494 case 0x1c: // Sync Adjust and Genlock
1495 s->cr[reg_index] = reg_value;
1496#ifdef DEBUG_CIRRUS
1497 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1498 reg_index, reg_value);
1499#endif
1500 break;
1501 case 0x22: // Graphics Data Latches Readback (R)
1502 case 0x24: // Attribute Controller Toggle Readback (R)
1503 case 0x26: // Attribute Controller Index Readback (R)
1504 case 0x27: // Part ID (R)
1505 break;
1506 case 0x1d: // Overlay Extended Control
1507 case 0x25: // Part Status
1508 default:
1509#ifdef DEBUG_CIRRUS
1510 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
1511 reg_value);
1512#endif
1513 break;
1514 }
1515
1516 return CIRRUS_HOOK_HANDLED;
1517}
1518
1519/***************************************
1520 *
1521 * memory-mapped I/O (bitblt)
1522 *
1523 ***************************************/
1524
1525static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1526{
1527 int value = 0xff;
1528
1529 switch (address) {
1530 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1531 cirrus_hook_read_gr(s, 0x00, &value);
1532 break;
1533 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1534 cirrus_hook_read_gr(s, 0x10, &value);
1535 break;
1536 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1537 cirrus_hook_read_gr(s, 0x12, &value);
1538 break;
1539 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1540 cirrus_hook_read_gr(s, 0x14, &value);
1541 break;
1542 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1543 cirrus_hook_read_gr(s, 0x01, &value);
1544 break;
1545 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1546 cirrus_hook_read_gr(s, 0x11, &value);
1547 break;
1548 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1549 cirrus_hook_read_gr(s, 0x13, &value);
1550 break;
1551 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1552 cirrus_hook_read_gr(s, 0x15, &value);
1553 break;
1554 case (CIRRUS_MMIO_BLTWIDTH + 0):
1555 cirrus_hook_read_gr(s, 0x20, &value);
1556 break;
1557 case (CIRRUS_MMIO_BLTWIDTH + 1):
1558 cirrus_hook_read_gr(s, 0x21, &value);
1559 break;
1560 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1561 cirrus_hook_read_gr(s, 0x22, &value);
1562 break;
1563 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1564 cirrus_hook_read_gr(s, 0x23, &value);
1565 break;
1566 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1567 cirrus_hook_read_gr(s, 0x24, &value);
1568 break;
1569 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1570 cirrus_hook_read_gr(s, 0x25, &value);
1571 break;
1572 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1573 cirrus_hook_read_gr(s, 0x26, &value);
1574 break;
1575 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1576 cirrus_hook_read_gr(s, 0x27, &value);
1577 break;
1578 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1579 cirrus_hook_read_gr(s, 0x28, &value);
1580 break;
1581 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1582 cirrus_hook_read_gr(s, 0x29, &value);
1583 break;
1584 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1585 cirrus_hook_read_gr(s, 0x2a, &value);
1586 break;
1587 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1588 cirrus_hook_read_gr(s, 0x2c, &value);
1589 break;
1590 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1591 cirrus_hook_read_gr(s, 0x2d, &value);
1592 break;
1593 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1594 cirrus_hook_read_gr(s, 0x2e, &value);
1595 break;
1596 case CIRRUS_MMIO_BLTWRITEMASK:
1597 cirrus_hook_read_gr(s, 0x2f, &value);
1598 break;
1599 case CIRRUS_MMIO_BLTMODE:
1600 cirrus_hook_read_gr(s, 0x30, &value);
1601 break;
1602 case CIRRUS_MMIO_BLTROP:
1603 cirrus_hook_read_gr(s, 0x32, &value);
1604 break;
a21ae81d
FB		 1605 case CIRRUS_MMIO_BLTMODEEXT:
1606 cirrus_hook_read_gr(s, 0x33, &value);
1607 break;
e6e5ad80
FB		 1608 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1609 cirrus_hook_read_gr(s, 0x34, &value);
1610 break;
1611 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1612 cirrus_hook_read_gr(s, 0x35, &value);
1613 break;
1614 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1615 cirrus_hook_read_gr(s, 0x38, &value);
1616 break;
1617 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1618 cirrus_hook_read_gr(s, 0x39, &value);
1619 break;
1620 case CIRRUS_MMIO_BLTSTATUS:
1621 cirrus_hook_read_gr(s, 0x31, &value);
1622 break;
1623 default:
1624#ifdef DEBUG_CIRRUS
1625 printf("cirrus: mmio read - address 0x%04x\n", address);
1626#endif
1627 break;
1628 }
1629
1630 return (uint8_t) value;
1631}
1632
1633static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1634 uint8_t value)
1635{
1636 switch (address) {
1637 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1638 cirrus_hook_write_gr(s, 0x00, value);
1639 break;
1640 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1641 cirrus_hook_write_gr(s, 0x10, value);
1642 break;
1643 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1644 cirrus_hook_write_gr(s, 0x12, value);
1645 break;
1646 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1647 cirrus_hook_write_gr(s, 0x14, value);
1648 break;
1649 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1650 cirrus_hook_write_gr(s, 0x01, value);
1651 break;
1652 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1653 cirrus_hook_write_gr(s, 0x11, value);
1654 break;
1655 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1656 cirrus_hook_write_gr(s, 0x13, value);
1657 break;
1658 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1659 cirrus_hook_write_gr(s, 0x15, value);
1660 break;
1661 case (CIRRUS_MMIO_BLTWIDTH + 0):
1662 cirrus_hook_write_gr(s, 0x20, value);
1663 break;
1664 case (CIRRUS_MMIO_BLTWIDTH + 1):
1665 cirrus_hook_write_gr(s, 0x21, value);
1666 break;
1667 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1668 cirrus_hook_write_gr(s, 0x22, value);
1669 break;
1670 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1671 cirrus_hook_write_gr(s, 0x23, value);
1672 break;
1673 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1674 cirrus_hook_write_gr(s, 0x24, value);
1675 break;
1676 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1677 cirrus_hook_write_gr(s, 0x25, value);
1678 break;
1679 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1680 cirrus_hook_write_gr(s, 0x26, value);
1681 break;
1682 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1683 cirrus_hook_write_gr(s, 0x27, value);
1684 break;
1685 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1686 cirrus_hook_write_gr(s, 0x28, value);
1687 break;
1688 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1689 cirrus_hook_write_gr(s, 0x29, value);
1690 break;
1691 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1692 cirrus_hook_write_gr(s, 0x2a, value);
1693 break;
1694 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1695 /* ignored */
1696 break;
1697 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1698 cirrus_hook_write_gr(s, 0x2c, value);
1699 break;
1700 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1701 cirrus_hook_write_gr(s, 0x2d, value);
1702 break;
1703 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1704 cirrus_hook_write_gr(s, 0x2e, value);
1705 break;
1706 case CIRRUS_MMIO_BLTWRITEMASK:
1707 cirrus_hook_write_gr(s, 0x2f, value);
1708 break;
1709 case CIRRUS_MMIO_BLTMODE:
1710 cirrus_hook_write_gr(s, 0x30, value);
1711 break;
1712 case CIRRUS_MMIO_BLTROP:
1713 cirrus_hook_write_gr(s, 0x32, value);
1714 break;
a21ae81d
FB		 1715 case CIRRUS_MMIO_BLTMODEEXT:
1716 cirrus_hook_write_gr(s, 0x33, value);
1717 break;
e6e5ad80
FB		 1718 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1719 cirrus_hook_write_gr(s, 0x34, value);
1720 break;
1721 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1722 cirrus_hook_write_gr(s, 0x35, value);
1723 break;
1724 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1725 cirrus_hook_write_gr(s, 0x38, value);
1726 break;
1727 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1728 cirrus_hook_write_gr(s, 0x39, value);
1729 break;
1730 case CIRRUS_MMIO_BLTSTATUS:
1731 cirrus_hook_write_gr(s, 0x31, value);
1732 break;
1733 default:
1734#ifdef DEBUG_CIRRUS
1735 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1736 address, value);
1737#endif
1738 break;
1739 }
1740}
1741
e6e5ad80
FB		 1742/***************************************
1743 *
1744 * write mode 4/5
1745 *
1746 * assume TARGET_PAGE_SIZE >= 16
1747 *
1748 ***************************************/
1749
1750static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1751 unsigned mode,
1752 unsigned offset,
1753 uint32_t mem_value)
1754{
1755 int x;
1756 unsigned val = mem_value;
1757 uint8_t *dst;
1758
1759 dst = s->vram_ptr + offset;
1760 for (x = 0; x < 8; x++) {
1761 if (val & 0x80) {
aeb3c85f 1762 *dst++ = s->cirrus_shadow_gr1;
e6e5ad80 1763 } else if (mode == 5) {
aeb3c85f 1764 *dst++ = s->cirrus_shadow_gr0;
e6e5ad80
FB		 1765 }
1766 val <<= 1;
1767 }
1768 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1769 cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
1770}
1771
1772static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1773 unsigned mode,
1774 unsigned offset,
1775 uint32_t mem_value)
1776{
1777 int x;
1778 unsigned val = mem_value;
1779 uint8_t *dst;
1780
1781 dst = s->vram_ptr + offset;
1782 for (x = 0; x < 8; x++) {
1783 if (val & 0x80) {
aeb3c85f 1784 *dst++ = s->cirrus_shadow_gr1;
e6e5ad80
FB		 1785 *dst++ = s->gr[0x11];
1786 } else if (mode == 5) {
aeb3c85f 1787 *dst++ = s->cirrus_shadow_gr0;
e6e5ad80
FB		 1788 *dst++ = s->gr[0x10];
1789 }
1790 val <<= 1;
1791 }
1792 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1793 cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);
1794}
1795
1796/***************************************
1797 *
1798 * memory access between 0xa0000-0xbffff
1799 *
1800 ***************************************/
1801
1802static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
1803{
1804 CirrusVGAState *s = opaque;
1805 unsigned bank_index;
1806 unsigned bank_offset;
1807 uint32_t val;
1808
1809 if ((s->sr[0x07] & 0x01) == 0) {
1810 return vga_mem_readb(s, addr);
1811 }
1812
aeb3c85f
FB		 1813 addr &= 0x1ffff;
1814
e6e5ad80
FB		 1815 if (addr < 0x10000) {
1816 /* XXX handle bitblt */
1817 /* video memory */
1818 bank_index = addr >> 15;
1819 bank_offset = addr & 0x7fff;
1820 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
1821 bank_offset += s->cirrus_bank_base[bank_index];
1822 if ((s->gr[0x0B] & 0x14) == 0x14) {
1823 bank_offset <<= 4;
1824 } else if (s->gr[0x0B] & 0x02) {
1825 bank_offset <<= 3;
1826 }
1827 bank_offset &= s->cirrus_addr_mask;
1828 val = *(s->vram_ptr + bank_offset);
1829 } else
1830 val = 0xff;
1831 } else if (addr >= 0x18000 && addr < 0x18100) {
1832 /* memory-mapped I/O */
1833 val = 0xff;
1834 if ((s->sr[0x17] & 0x44) == 0x04) {
1835 val = cirrus_mmio_blt_read(s, addr & 0xff);
1836 }
1837 } else {
1838 val = 0xff;
1839#ifdef DEBUG_CIRRUS
1840 printf("cirrus: mem_readb %06x\n", addr);
1841#endif
1842 }
1843 return val;
1844}
1845
1846static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
1847{
1848 uint32_t v;
1849#ifdef TARGET_WORDS_BIGENDIAN
1850 v = cirrus_vga_mem_readb(opaque, addr) << 8;
1851 v |= cirrus_vga_mem_readb(opaque, addr + 1);
1852#else
1853 v = cirrus_vga_mem_readb(opaque, addr);
1854 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
1855#endif
1856 return v;
1857}
1858
1859static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
1860{
1861 uint32_t v;
1862#ifdef TARGET_WORDS_BIGENDIAN
1863 v = cirrus_vga_mem_readb(opaque, addr) << 24;
1864 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
1865 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
1866 v |= cirrus_vga_mem_readb(opaque, addr + 3);
1867#else
1868 v = cirrus_vga_mem_readb(opaque, addr);
1869 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
1870 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
1871 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
1872#endif
1873 return v;
1874}
1875
1876static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
1877 uint32_t mem_value)
1878{
1879 CirrusVGAState *s = opaque;
1880 unsigned bank_index;
1881 unsigned bank_offset;
1882 unsigned mode;
1883
1884 if ((s->sr[0x07] & 0x01) == 0) {
1885 vga_mem_writeb(s, addr, mem_value);
1886 return;
1887 }
1888
aeb3c85f
FB		 1889 addr &= 0x1ffff;
1890
e6e5ad80
FB		 1891 if (addr < 0x10000) {
1892 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
1893 /* bitblt */
1894 *s->cirrus_srcptr++ = (uint8_t) mem_value;
a5082316 1895 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 1896 cirrus_bitblt_cputovideo_next(s);
1897 }
1898 } else {
1899 /* video memory */
1900 bank_index = addr >> 15;
1901 bank_offset = addr & 0x7fff;
1902 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
1903 bank_offset += s->cirrus_bank_base[bank_index];
1904 if ((s->gr[0x0B] & 0x14) == 0x14) {
1905 bank_offset <<= 4;
1906 } else if (s->gr[0x0B] & 0x02) {
1907 bank_offset <<= 3;
1908 }
1909 bank_offset &= s->cirrus_addr_mask;
1910 mode = s->gr[0x05] & 0x7;
1911 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
1912 *(s->vram_ptr + bank_offset) = mem_value;
1913 cpu_physical_memory_set_dirty(s->vram_offset +
1914 bank_offset);
1915 } else {
1916 if ((s->gr[0x0B] & 0x14) != 0x14) {
1917 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
1918 bank_offset,
1919 mem_value);
1920 } else {
1921 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
1922 bank_offset,
1923 mem_value);
1924 }
1925 }
1926 }
1927 }
1928 } else if (addr >= 0x18000 && addr < 0x18100) {
1929 /* memory-mapped I/O */
1930 if ((s->sr[0x17] & 0x44) == 0x04) {
1931 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
1932 }
1933 } else {
1934#ifdef DEBUG_CIRRUS
1935 printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
1936#endif
1937 }
1938}
1939
1940static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1941{
1942#ifdef TARGET_WORDS_BIGENDIAN
1943 cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
1944 cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
1945#else
1946 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
1947 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
1948#endif
1949}
1950
1951static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1952{
1953#ifdef TARGET_WORDS_BIGENDIAN
1954 cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
1955 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
1956 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
1957 cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
1958#else
1959 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
1960 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
1961 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
1962 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
1963#endif
1964}
1965
1966static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = {
1967 cirrus_vga_mem_readb,
1968 cirrus_vga_mem_readw,
1969 cirrus_vga_mem_readl,
1970};
1971
1972static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = {
1973 cirrus_vga_mem_writeb,
1974 cirrus_vga_mem_writew,
1975 cirrus_vga_mem_writel,
1976};
1977
a5082316
FB		 1978/***************************************
1979 *
1980 * hardware cursor
1981 *
1982 ***************************************/
1983
1984static inline void invalidate_cursor1(CirrusVGAState *s)
1985{
1986 if (s->last_hw_cursor_size) {
1987 vga_invalidate_scanlines((VGAState *)s,
1988 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
1989 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
1990 }
1991}
1992
1993static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
1994{
1995 const uint8_t *src;
1996 uint32_t content;
1997 int y, y_min, y_max;
1998
78e127ef 1999 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
a5082316
FB		 2000 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2001 src += (s->sr[0x13] & 0x3c) * 256;
2002 y_min = 64;
2003 y_max = -1;
2004 for(y = 0; y < 64; y++) {
2005 content = ((uint32_t *)src)[0] |
2006 ((uint32_t *)src)[1] |
2007 ((uint32_t *)src)[2] |
2008 ((uint32_t *)src)[3];
2009 if (content) {
2010 if (y < y_min)
2011 y_min = y;
2012 if (y > y_max)
2013 y_max = y;
2014 }
2015 src += 16;
2016 }
2017 } else {
2018 src += (s->sr[0x13] & 0x3f) * 256;
2019 y_min = 32;
2020 y_max = -1;
2021 for(y = 0; y < 32; y++) {
2022 content = ((uint32_t *)src)[0] |
2023 ((uint32_t *)(src + 128))[0];
2024 if (content) {
2025 if (y < y_min)
2026 y_min = y;
2027 if (y > y_max)
2028 y_max = y;
2029 }
2030 src += 4;
2031 }
2032 }
2033 if (y_min > y_max) {
2034 s->last_hw_cursor_y_start = 0;
2035 s->last_hw_cursor_y_end = 0;
2036 } else {
2037 s->last_hw_cursor_y_start = y_min;
2038 s->last_hw_cursor_y_end = y_max + 1;
2039 }
2040}
2041
2042/* NOTE: we do not currently handle the cursor bitmap change, so we
2043 update the cursor only if it moves. */
2044static void cirrus_cursor_invalidate(VGAState *s1)
2045{
2046 CirrusVGAState *s = (CirrusVGAState *)s1;
2047 int size;
2048
2049 if (!s->sr[0x12] & CIRRUS_CURSOR_SHOW) {
2050 size = 0;
2051 } else {
2052 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE)
2053 size = 64;
2054 else
2055 size = 32;
2056 }
2057 /* invalidate last cursor and new cursor if any change */
2058 if (s->last_hw_cursor_size != size ||
2059 s->last_hw_cursor_x != s->hw_cursor_x ||
2060 s->last_hw_cursor_y != s->hw_cursor_y) {
2061
2062 invalidate_cursor1(s);
2063
2064 s->last_hw_cursor_size = size;
2065 s->last_hw_cursor_x = s->hw_cursor_x;
2066 s->last_hw_cursor_y = s->hw_cursor_y;
2067 /* compute the real cursor min and max y */
2068 cirrus_cursor_compute_yrange(s);
2069 invalidate_cursor1(s);
2070 }
2071}
2072
2073static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2074{
2075 CirrusVGAState *s = (CirrusVGAState *)s1;
2076 int w, h, bpp, x1, x2, poffset;
2077 unsigned int color0, color1;
2078 const uint8_t *palette, *src;
2079 uint32_t content;
2080
2081 if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW))
2082 return;
2083 /* fast test to see if the cursor intersects with the scan line */
2084 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2085 h = 64;
2086 } else {
2087 h = 32;
2088 }
2089 if (scr_y < s->hw_cursor_y ||
2090 scr_y >= (s->hw_cursor_y + h))
2091 return;
2092
78e127ef 2093 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
a5082316
FB		 2094 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2095 src += (s->sr[0x13] & 0x3c) * 256;
2096 src += (scr_y - s->hw_cursor_y) * 16;
2097 poffset = 8;
2098 content = ((uint32_t *)src)[0] |
2099 ((uint32_t *)src)[1] |
2100 ((uint32_t *)src)[2] |
2101 ((uint32_t *)src)[3];
2102 } else {
2103 src += (s->sr[0x13] & 0x3f) * 256;
2104 src += (scr_y - s->hw_cursor_y) * 4;
2105 poffset = 128;
2106 content = ((uint32_t *)src)[0] |
2107 ((uint32_t *)(src + 128))[0];
2108 }
2109 /* if nothing to draw, no need to continue */
2110 if (!content)
2111 return;
2112 w = h;
2113
2114 x1 = s->hw_cursor_x;
2115 if (x1 >= s->last_scr_width)
2116 return;
2117 x2 = s->hw_cursor_x + w;
2118 if (x2 > s->last_scr_width)
2119 x2 = s->last_scr_width;
2120 w = x2 - x1;
2121 palette = s->cirrus_hidden_palette;
2122 color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2123 c6_to_8(palette[0x0 * 3 + 1]),
2124 c6_to_8(palette[0x0 * 3 + 2]));
2125 color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2126 c6_to_8(palette[0xf * 3 + 1]),
2127 c6_to_8(palette[0xf * 3 + 2]));
2128 bpp = ((s->ds->depth + 7) >> 3);
2129 d1 += x1 * bpp;
2130 switch(s->ds->depth) {
2131 default:
2132 break;
2133 case 8:
2134 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2135 break;
2136 case 15:
2137 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2138 break;
2139 case 16:
2140 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2141 break;
2142 case 32:
2143 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2144 break;
2145 }
2146}
2147
e6e5ad80
FB		 2148/***************************************
2149 *
2150 * LFB memory access
2151 *
2152 ***************************************/
2153
2154static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2155{
2156 CirrusVGAState *s = (CirrusVGAState *) opaque;
2157 uint32_t ret;
2158
e6e5ad80
FB		 2159 addr &= s->cirrus_addr_mask;
2160
78e127ef
FB		 2161 if (((s->sr[0x17] & 0x44) == 0x44) &&
2162 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2163 /* memory-mapped I/O */
2164 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2165 } else if (0) {
2166 /* XXX handle bitblt */
2167 ret = 0xff;
2168 } else {
2169 /* video memory */
2170 if ((s->gr[0x0B] & 0x14) == 0x14) {
2171 addr <<= 4;
2172 } else if (s->gr[0x0B] & 0x02) {
2173 addr <<= 3;
2174 }
2175 addr &= s->cirrus_addr_mask;
2176 ret = *(s->vram_ptr + addr);
2177 }
2178
2179 return ret;
2180}
2181
2182static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2183{
2184 uint32_t v;
2185#ifdef TARGET_WORDS_BIGENDIAN
2186 v = cirrus_linear_readb(opaque, addr) << 8;
2187 v |= cirrus_linear_readb(opaque, addr + 1);
2188#else
2189 v = cirrus_linear_readb(opaque, addr);
2190 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2191#endif
2192 return v;
2193}
2194
2195static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2196{
2197 uint32_t v;
2198#ifdef TARGET_WORDS_BIGENDIAN
2199 v = cirrus_linear_readb(opaque, addr) << 24;
2200 v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2201 v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2202 v |= cirrus_linear_readb(opaque, addr + 3);
2203#else
2204 v = cirrus_linear_readb(opaque, addr);
2205 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2206 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2207 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2208#endif
2209 return v;
2210}
2211
2212static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2213 uint32_t val)
2214{
2215 CirrusVGAState *s = (CirrusVGAState *) opaque;
2216 unsigned mode;
2217
2218 addr &= s->cirrus_addr_mask;
78e127ef
FB		 2219
2220 if (((s->sr[0x17] & 0x44) == 0x44) &&
2221 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
e6e5ad80
FB		 2222 /* memory-mapped I/O */
2223 cirrus_mmio_blt_write(s, addr & 0xff, val);
2224 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2225 /* bitblt */
2226 *s->cirrus_srcptr++ = (uint8_t) val;
a5082316 2227 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
e6e5ad80
FB		 2228 cirrus_bitblt_cputovideo_next(s);
2229 }
2230 } else {
2231 /* video memory */
2232 if ((s->gr[0x0B] & 0x14) == 0x14) {
2233 addr <<= 4;
2234 } else if (s->gr[0x0B] & 0x02) {
2235 addr <<= 3;
2236 }
2237 addr &= s->cirrus_addr_mask;
2238
2239 mode = s->gr[0x05] & 0x7;
2240 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2241 *(s->vram_ptr + addr) = (uint8_t) val;
2242 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2243 } else {
2244 if ((s->gr[0x0B] & 0x14) != 0x14) {
2245 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2246 } else {
2247 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2248 }
2249 }
2250 }
2251}
2252
2253static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2254 uint32_t val)
2255{
2256#ifdef TARGET_WORDS_BIGENDIAN
2257 cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2258 cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2259#else
2260 cirrus_linear_writeb(opaque, addr, val & 0xff);
2261 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2262#endif
2263}
2264
2265static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2266 uint32_t val)
2267{
2268#ifdef TARGET_WORDS_BIGENDIAN
2269 cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2270 cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2271 cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2272 cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2273#else
2274 cirrus_linear_writeb(opaque, addr, val & 0xff);
2275 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2276 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2277 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2278#endif
2279}
2280
2281
2282static CPUReadMemoryFunc *cirrus_linear_read[3] = {
2283 cirrus_linear_readb,
2284 cirrus_linear_readw,
2285 cirrus_linear_readl,
2286};
2287
2288static CPUWriteMemoryFunc *cirrus_linear_write[3] = {
2289 cirrus_linear_writeb,
2290 cirrus_linear_writew,
2291 cirrus_linear_writel,
2292};
2293
a5082316
FB		 2294/***************************************
2295 *
2296 * system to screen memory access
2297 *
2298 ***************************************/
2299
2300
2301static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2302{
2303 uint32_t ret;
2304
2305 /* XXX handle bitblt */
2306 ret = 0xff;
2307 return ret;
2308}
2309
2310static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2311{
2312 uint32_t v;
2313#ifdef TARGET_WORDS_BIGENDIAN
2314 v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2315 v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2316#else
2317 v = cirrus_linear_bitblt_readb(opaque, addr);
2318 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2319#endif
2320 return v;
2321}
2322
2323static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2324{
2325 uint32_t v;
2326#ifdef TARGET_WORDS_BIGENDIAN
2327 v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2328 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2329 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2330 v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2331#else
2332 v = cirrus_linear_bitblt_readb(opaque, addr);
2333 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2334 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2335 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2336#endif
2337 return v;
2338}
2339
2340static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2341 uint32_t val)
2342{
2343 CirrusVGAState *s = (CirrusVGAState *) opaque;
2344
2345 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2346 /* bitblt */
2347 *s->cirrus_srcptr++ = (uint8_t) val;
2348 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2349 cirrus_bitblt_cputovideo_next(s);
2350 }
2351 }
2352}
2353
2354static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2355 uint32_t val)
2356{
2357#ifdef TARGET_WORDS_BIGENDIAN
2358 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2359 cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2360#else
2361 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2362 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2363#endif
2364}
2365
2366static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2367 uint32_t val)
2368{
2369#ifdef TARGET_WORDS_BIGENDIAN
2370 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2371 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2372 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2373 cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2374#else
2375 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2376 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2377 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2378 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2379#endif
2380}
2381
2382
2383static CPUReadMemoryFunc *cirrus_linear_bitblt_read[3] = {
2384 cirrus_linear_bitblt_readb,
2385 cirrus_linear_bitblt_readw,
2386 cirrus_linear_bitblt_readl,
2387};
2388
2389static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = {
2390 cirrus_linear_bitblt_writeb,
2391 cirrus_linear_bitblt_writew,
2392 cirrus_linear_bitblt_writel,
2393};
2394
e6e5ad80
FB		 2395/* I/O ports */
2396
2397static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
2398{
2399 CirrusVGAState *s = opaque;
2400 int val, index;
2401
2402 /* check port range access depending on color/monochrome mode */
2403 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2404 || (addr >= 0x3d0 && addr <= 0x3df
2405 && !(s->msr & MSR_COLOR_EMULATION))) {
2406 val = 0xff;
2407 } else {
2408 switch (addr) {
2409 case 0x3c0:
2410 if (s->ar_flip_flop == 0) {
2411 val = s->ar_index;
2412 } else {
2413 val = 0;
2414 }
2415 break;
2416 case 0x3c1:
2417 index = s->ar_index & 0x1f;
2418 if (index < 21)
2419 val = s->ar[index];
2420 else
2421 val = 0;
2422 break;
2423 case 0x3c2:
2424 val = s->st00;
2425 break;
2426 case 0x3c4:
2427 val = s->sr_index;
2428 break;
2429 case 0x3c5:
2430 if (cirrus_hook_read_sr(s, s->sr_index, &val))
2431 break;
2432 val = s->sr[s->sr_index];
2433#ifdef DEBUG_VGA_REG
2434 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2435#endif
2436 break;
2437 case 0x3c6:
2438 cirrus_read_hidden_dac(s, &val);
2439 break;
2440 case 0x3c7:
2441 val = s->dac_state;
2442 break;
2443 case 0x3c9:
2444 if (cirrus_hook_read_palette(s, &val))
2445 break;
2446 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
2447 if (++s->dac_sub_index == 3) {
2448 s->dac_sub_index = 0;
2449 s->dac_read_index++;
2450 }
2451 break;
2452 case 0x3ca:
2453 val = s->fcr;
2454 break;
2455 case 0x3cc:
2456 val = s->msr;
2457 break;
2458 case 0x3ce:
2459 val = s->gr_index;
2460 break;
2461 case 0x3cf:
2462 if (cirrus_hook_read_gr(s, s->gr_index, &val))
2463 break;
2464 val = s->gr[s->gr_index];
2465#ifdef DEBUG_VGA_REG
2466 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2467#endif
2468 break;
2469 case 0x3b4:
2470 case 0x3d4:
2471 val = s->cr_index;
2472 break;
2473 case 0x3b5:
2474 case 0x3d5:
2475 if (cirrus_hook_read_cr(s, s->cr_index, &val))
2476 break;
2477 val = s->cr[s->cr_index];
2478#ifdef DEBUG_VGA_REG
2479 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
e6e5ad80
FB		 2480#endif
2481 break;
2482 case 0x3ba:
2483 case 0x3da:
2484 /* just toggle to fool polling */
2485 s->st01 ^= ST01_V_RETRACE | ST01_DISP_ENABLE;
2486 val = s->st01;
2487 s->ar_flip_flop = 0;
2488 break;
2489 default:
2490 val = 0x00;
2491 break;
2492 }
2493 }
2494#if defined(DEBUG_VGA)
2495 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2496#endif
2497 return val;
2498}
2499
2500static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2501{
2502 CirrusVGAState *s = opaque;
2503 int index;
2504
2505 /* check port range access depending on color/monochrome mode */
2506 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2507 || (addr >= 0x3d0 && addr <= 0x3df
2508 && !(s->msr & MSR_COLOR_EMULATION)))
2509 return;
2510
2511#ifdef DEBUG_VGA
2512 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2513#endif
2514
2515 switch (addr) {
2516 case 0x3c0:
2517 if (s->ar_flip_flop == 0) {
2518 val &= 0x3f;
2519 s->ar_index = val;
2520 } else {
2521 index = s->ar_index & 0x1f;
2522 switch (index) {
2523 case 0x00 ... 0x0f:
2524 s->ar[index] = val & 0x3f;
2525 break;
2526 case 0x10:
2527 s->ar[index] = val & ~0x10;
2528 break;
2529 case 0x11:
2530 s->ar[index] = val;
2531 break;
2532 case 0x12:
2533 s->ar[index] = val & ~0xc0;
2534 break;
2535 case 0x13:
2536 s->ar[index] = val & ~0xf0;
2537 break;
2538 case 0x14:
2539 s->ar[index] = val & ~0xf0;
2540 break;
2541 default:
2542 break;
2543 }
2544 }
2545 s->ar_flip_flop ^= 1;
2546 break;
2547 case 0x3c2:
2548 s->msr = val & ~0x10;
2549 break;
2550 case 0x3c4:
2551 s->sr_index = val;
2552 break;
2553 case 0x3c5:
2554 if (cirrus_hook_write_sr(s, s->sr_index, val))
2555 break;
2556#ifdef DEBUG_VGA_REG
2557 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2558#endif
2559 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
2560 break;
2561 case 0x3c6:
2562 cirrus_write_hidden_dac(s, val);
2563 break;
2564 case 0x3c7:
2565 s->dac_read_index = val;
2566 s->dac_sub_index = 0;
2567 s->dac_state = 3;
2568 break;
2569 case 0x3c8:
2570 s->dac_write_index = val;
2571 s->dac_sub_index = 0;
2572 s->dac_state = 0;
2573 break;
2574 case 0x3c9:
2575 if (cirrus_hook_write_palette(s, val))
2576 break;
2577 s->dac_cache[s->dac_sub_index] = val;
2578 if (++s->dac_sub_index == 3) {
2579 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
2580 s->dac_sub_index = 0;
2581 s->dac_write_index++;
2582 }
2583 break;
2584 case 0x3ce:
2585 s->gr_index = val;
2586 break;
2587 case 0x3cf:
2588 if (cirrus_hook_write_gr(s, s->gr_index, val))
2589 break;
2590#ifdef DEBUG_VGA_REG
2591 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2592#endif
2593 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
2594 break;
2595 case 0x3b4:
2596 case 0x3d4:
2597 s->cr_index = val;
2598 break;
2599 case 0x3b5:
2600 case 0x3d5:
2601 if (cirrus_hook_write_cr(s, s->cr_index, val))
2602 break;
2603#ifdef DEBUG_VGA_REG
2604 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2605#endif
2606 /* handle CR0-7 protection */
2607 if ((s->cr[11] & 0x80) && s->cr_index <= 7) {
2608 /* can always write bit 4 of CR7 */
2609 if (s->cr_index == 7)
2610 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
2611 return;
2612 }
2613 switch (s->cr_index) {
2614 case 0x01: /* horizontal display end */
2615 case 0x07:
2616 case 0x09:
2617 case 0x0c:
2618 case 0x0d:
2619 case 0x12: /* veritcal display end */
2620 s->cr[s->cr_index] = val;
2621 break;
2622
2623 default:
2624 s->cr[s->cr_index] = val;
2625 break;
2626 }
2627 break;
2628 case 0x3ba:
2629 case 0x3da:
2630 s->fcr = val & 0x10;
2631 break;
2632 }
2633}
2634
e36f36e1
FB		 2635/***************************************
2636 *
2637 * memory-mapped I/O access
2638 *
2639 ***************************************/
2640
2641static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
2642{
2643 CirrusVGAState *s = (CirrusVGAState *) opaque;
2644
2645 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2646
2647 if (addr >= 0x100) {
2648 return cirrus_mmio_blt_read(s, addr - 0x100);
2649 } else {
2650 return vga_ioport_read(s, addr + 0x3c0);
2651 }
2652}
2653
2654static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
2655{
2656 uint32_t v;
2657#ifdef TARGET_WORDS_BIGENDIAN
2658 v = cirrus_mmio_readb(opaque, addr) << 8;
2659 v |= cirrus_mmio_readb(opaque, addr + 1);
2660#else
2661 v = cirrus_mmio_readb(opaque, addr);
2662 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2663#endif
2664 return v;
2665}
2666
2667static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
2668{
2669 uint32_t v;
2670#ifdef TARGET_WORDS_BIGENDIAN
2671 v = cirrus_mmio_readb(opaque, addr) << 24;
2672 v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
2673 v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
2674 v |= cirrus_mmio_readb(opaque, addr + 3);
2675#else
2676 v = cirrus_mmio_readb(opaque, addr);
2677 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2678 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
2679 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
2680#endif
2681 return v;
2682}
2683
2684static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
2685 uint32_t val)
2686{
2687 CirrusVGAState *s = (CirrusVGAState *) opaque;
2688
2689 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2690
2691 if (addr >= 0x100) {
2692 cirrus_mmio_blt_write(s, addr - 0x100, val);
2693 } else {
2694 vga_ioport_write(s, addr + 0x3c0, val);
2695 }
2696}
2697
2698static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
2699 uint32_t val)
2700{
2701#ifdef TARGET_WORDS_BIGENDIAN
2702 cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
2703 cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
2704#else
2705 cirrus_mmio_writeb(opaque, addr, val & 0xff);
2706 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2707#endif
2708}
2709
2710static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
2711 uint32_t val)
2712{
2713#ifdef TARGET_WORDS_BIGENDIAN
2714 cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
2715 cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2716 cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2717 cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
2718#else
2719 cirrus_mmio_writeb(opaque, addr, val & 0xff);
2720 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2721 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2722 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2723#endif
2724}
2725
2726
2727static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
2728 cirrus_mmio_readb,
2729 cirrus_mmio_readw,
2730 cirrus_mmio_readl,
2731};
2732
2733static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
2734 cirrus_mmio_writeb,
2735 cirrus_mmio_writew,
2736 cirrus_mmio_writel,
2737};
2738
e6e5ad80
FB		 2739/***************************************
2740 *
2741 * initialize
2742 *
2743 ***************************************/
2744
78e127ef 2745static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
e6e5ad80 2746{
a5082316
FB		 2747 int vga_io_memory, i;
2748 static int inited;
2749
2750 if (!inited) {
2751 inited = 1;
2752 for(i = 0;i < 256; i++)
2753 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
2754 rop_to_index[CIRRUS_ROP_0] = 0;
2755 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
2756 rop_to_index[CIRRUS_ROP_NOP] = 2;
2757 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
2758 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
2759 rop_to_index[CIRRUS_ROP_SRC] = 5;
2760 rop_to_index[CIRRUS_ROP_1] = 6;
2761 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
2762 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
2763 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
2764 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
2765 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
2766 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
2767 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
2768 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
2769 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
2770 }
e6e5ad80
FB		 2771
2772 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
2773
2774 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
2775 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
2776 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
2777 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
2778
2779 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
2780
2781 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
2782 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
2783 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
2784 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
2785
2786 vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
2787 cirrus_vga_mem_write, s);
2788 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
2789 vga_io_memory);
2790
2791 s->sr[0x06] = 0x0f;
e6e5ad80 2792 s->sr[0x1F] = 0x22; // MemClock
78e127ef
FB		 2793 if (device_id == CIRRUS_ID_CLGD5446) {
2794 /* 4MB 64 bit memory config, always PCI */
2795#if 1
2796 s->sr[0x0f] = 0x98;
2797 s->sr[0x17] = 0x20;
2798 s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
2799 s->real_vram_size = 4096 * 1024;
2800#else
2801 s->sr[0x0f] = 0x18;
2802 s->sr[0x17] = 0x20;
2803 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
2804 s->real_vram_size = 2048 * 1024;
2805#endif
2806 } else {
2807 s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
2808 if (is_pci)
2809 s->sr[0x17] = CIRRUS_BUSTYPE_PCI;
2810 else
2811 s->sr[0x17] = CIRRUS_BUSTYPE_ISA;
2812 s->real_vram_size = 2048 * 1024;
2813 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
2814 }
20ba3ae1 2815 s->cr[0x27] = device_id;
e6e5ad80 2816
78e127ef
FB		 2817 /* Win2K seems to assume that the pattern buffer is at 0xff
2818 initially ! */
2819 memset(s->vram_ptr, 0xff, s->real_vram_size);
2820
e6e5ad80
FB		 2821 s->cirrus_hidden_dac_lockindex = 5;
2822 s->cirrus_hidden_dac_data = 0;
2823
2824 /* I/O handler for LFB */
2825 s->cirrus_linear_io_addr =
2826 cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write,
2827 s);
a5082316
FB		 2828 /* I/O handler for LFB */
2829 s->cirrus_linear_bitblt_io_addr =
2830 cpu_register_io_memory(0, cirrus_linear_bitblt_read, cirrus_linear_bitblt_write,
2831 s);
2832
e6e5ad80
FB		 2833 /* I/O handler for memory-mapped I/O */
2834 s->cirrus_mmio_io_addr =
2835 cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
2836
2837 /* XXX: s->vram_size must be a power of two */
78e127ef
FB		 2838 s->cirrus_addr_mask = s->real_vram_size - 1;
2839 s->linear_mmio_mask = s->real_vram_size - 256;
e6e5ad80
FB		 2840
2841 s->get_bpp = cirrus_get_bpp;
2842 s->get_offsets = cirrus_get_offsets;
78e127ef 2843 s->get_resolution = cirrus_get_resolution;
a5082316
FB		 2844 s->cursor_invalidate = cirrus_cursor_invalidate;
2845 s->cursor_draw_line = cirrus_cursor_draw_line;
e6e5ad80
FB		 2846}
2847
2848/***************************************
2849 *
2850 * ISA bus support
2851 *
2852 ***************************************/
2853
2854void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
2855 unsigned long vga_ram_offset, int vga_ram_size)
2856{
2857 CirrusVGAState *s;
2858
2859 s = qemu_mallocz(sizeof(CirrusVGAState));
2860
2861 vga_common_init((VGAState *)s,
2862 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
78e127ef 2863 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
e6e5ad80
FB		 2864 /* XXX ISA-LFB support */
2865}
2866
2867/***************************************
2868 *
2869 * PCI bus support
2870 *
2871 ***************************************/
2872
2873static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
2874 uint32_t addr, uint32_t size, int type)
2875{
2876 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
2877
a5082316 2878 /* XXX: add byte swapping apertures */
e6e5ad80
FB		 2879 cpu_register_physical_memory(addr, s->vram_size,
2880 s->cirrus_linear_io_addr);
a5082316
FB		 2881 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
2882 s->cirrus_linear_bitblt_io_addr);
e6e5ad80
FB		 2883}
2884
2885static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
2886 uint32_t addr, uint32_t size, int type)
2887{
2888 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
2889
2890 cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
2891 s->cirrus_mmio_io_addr);
2892}
2893
46e50e9d 2894void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
e6e5ad80
FB		 2895 unsigned long vga_ram_offset, int vga_ram_size)
2896{
2897 PCICirrusVGAState *d;
2898 uint8_t *pci_conf;
2899 CirrusVGAState *s;
20ba3ae1
FB		 2900 int device_id;
2901
2902 device_id = CIRRUS_ID_CLGD5446;
e6e5ad80
FB		 2903
2904 /* setup PCI configuration registers */
46e50e9d 2905 d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
e6e5ad80 2906 sizeof(PCICirrusVGAState),
46e50e9d 2907 -1, NULL, NULL);
e6e5ad80
FB		 2908 pci_conf = d->dev.config;
2909 pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff);
2910 pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8);
20ba3ae1
FB		 2911 pci_conf[0x02] = (uint8_t) (device_id & 0xff);
2912 pci_conf[0x03] = (uint8_t) (device_id >> 8);
e6e5ad80
FB		 2913 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
2914 pci_conf[0x0a] = PCI_CLASS_SUB_VGA;
2915 pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY;
2916 pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
2917
2918 /* setup VGA */
2919 s = &d->cirrus_vga;
2920 vga_common_init((VGAState *)s,
2921 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
78e127ef 2922 cirrus_init_common(s, device_id, 1);
e6e5ad80
FB		 2923
2924 /* setup memory space */
2925 /* memory #0 LFB */
2926 /* memory #1 memory-mapped I/O */
2927 /* XXX: s->vram_size must be a power of two */
a5082316 2928 pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
a21ae81d 2929 PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
20ba3ae1 2930 if (device_id == CIRRUS_ID_CLGD5446) {
a21ae81d
FB		 2931 pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
2932 PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
2933 }
e6e5ad80
FB		 2934 /* XXX: ROM BIOS */
2935}
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