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system/cpus: rename qemu_mutex_lock_iothread() to bql_lock()
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CommitLineData
dd83b06a
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1/*
2 * QEMU CPU model
3 *
1590bbcb 4 * Copyright (c) 2012-2014 SUSE LINUX Products GmbH
dd83b06a
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5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
1ef26b1f 21#include "qemu/osdep.h"
da34e65c 22#include "qapi/error.h"
2e5b09fd 23#include "hw/core/cpu.h"
b3946626 24#include "sysemu/hw_accel.h"
066e9b27 25#include "qemu/notify.h"
91b1df8c 26#include "qemu/log.h"
db725815 27#include "qemu/main-loop.h"
508127e2 28#include "exec/log.h"
4a795202 29#include "exec/cpu-common.h"
9262685b 30#include "qemu/error-report.h"
90c84c56 31#include "qemu/qemu-print.h"
14a48c1d 32#include "sysemu/tcg.h"
ed860129 33#include "hw/boards.h"
62a48a2a 34#include "hw/qdev-properties.h"
78f314cf 35#include "trace.h"
30865f31 36#include "qemu/plugin.h"
066e9b27 37
5ce46cb3 38CPUState *cpu_by_arch_id(int64_t id)
69e5ff06 39{
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40 CPUState *cpu;
41
42 CPU_FOREACH(cpu) {
43 CPUClass *cc = CPU_GET_CLASS(cpu);
69e5ff06 44
38fcbd3f 45 if (cc->get_arch_id(cpu) == id) {
5ce46cb3 46 return cpu;
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47 }
48 }
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EH
49 return NULL;
50}
51
52bool cpu_exists(int64_t id)
53{
54 return !!cpu_by_arch_id(id);
69e5ff06
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55}
56
3c72234c
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57CPUState *cpu_create(const char *typename)
58{
59 Error *err = NULL;
60 CPUState *cpu = CPU(object_new(typename));
118bfd76 61 if (!qdev_realize(DEVICE(cpu), NULL, &err)) {
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62 error_report_err(err);
63 object_unref(OBJECT(cpu));
4482e05c 64 exit(EXIT_FAILURE);
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65 }
66 return cpu;
67}
68
8d04fb55
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69/* Resetting the IRQ comes from across the code base so we take the
70 * BQL here if we need to. cpu_interrupt assumes it is held.*/
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71void cpu_reset_interrupt(CPUState *cpu, int mask)
72{
195801d7 73 bool need_lock = !bql_locked();
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74
75 if (need_lock) {
195801d7 76 bql_lock();
8d04fb55 77 }
d8ed887b 78 cpu->interrupt_request &= ~mask;
8d04fb55 79 if (need_lock) {
195801d7 80 bql_unlock();
8d04fb55 81 }
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82}
83
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84void cpu_exit(CPUState *cpu)
85{
d73415a3 86 qatomic_set(&cpu->exit_request, 1);
ab096a75
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87 /* Ensure cpu_exec will see the exit request after TCG has exited. */
88 smp_wmb();
e62de981 89 qatomic_set(&cpu->neg.icount_decr.u16.high, -1);
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90}
91
a010bdbe 92static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
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93{
94 return 0;
95}
96
97static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
98{
99 return 0;
100}
101
90c84c56 102void cpu_dump_state(CPUState *cpu, FILE *f, int flags)
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103{
104 CPUClass *cc = CPU_GET_CLASS(cpu);
105
106 if (cc->dump_state) {
97577fd4 107 cpu_synchronize_state(cpu);
90c84c56 108 cc->dump_state(cpu, f, flags);
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109 }
110}
111
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112void cpu_reset(CPUState *cpu)
113{
781c67ca 114 device_cold_reset(DEVICE(cpu));
2cc2d082 115
78f314cf 116 trace_cpu_reset(cpu->cpu_index);
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117}
118
3b750f1b 119static void cpu_common_reset_hold(Object *obj)
dd83b06a 120{
3b750f1b 121 CPUState *cpu = CPU(obj);
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AF
122 CPUClass *cc = CPU_GET_CLASS(cpu);
123
124 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
125 qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index);
126 log_cpu_state(cpu, cc->reset_dump_flags);
127 }
128
259186a7 129 cpu->interrupt_request = 0;
6ad1da66 130 cpu->halted = cpu->start_powered_off;
93afeade 131 cpu->mem_io_pc = 0;
efee7340 132 cpu->icount_extra = 0;
e62de981 133 qatomic_set(&cpu->neg.icount_decr.u32, 0);
464dacf6 134 cpu->neg.can_do_io = true;
f9d8f667 135 cpu->exception_index = -1;
bac05aa9 136 cpu->crash_occurred = false;
9b990ee5 137 cpu->cflags_next_tb = -1;
ce7cf6a9 138
1b5120d7 139 cpu_exec_reset_hold(cpu);
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140}
141
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142static bool cpu_common_has_work(CPUState *cs)
143{
144 return false;
145}
146
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147ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
148{
3a9d0d7b
PMD
149 ObjectClass *oc;
150 CPUClass *cc;
151
152 oc = object_class_by_name(typename);
153 cc = CPU_CLASS(oc);
154 assert(cc->class_by_name);
155 assert(cpu_model);
156 oc = cc->class_by_name(cpu_model);
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157 if (object_class_dynamic_cast(oc, typename) &&
158 !object_class_is_abstract(oc)) {
159 return oc;
3a9d0d7b 160 }
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161
162 return NULL;
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163}
164
62a48a2a 165static void cpu_common_parse_features(const char *typename, char *features,
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166 Error **errp)
167{
1590bbcb 168 char *val;
62a48a2a 169 static bool cpu_globals_initialized;
2278b939
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170 /* Single "key=value" string being parsed */
171 char *featurestr = features ? strtok(features, ",") : NULL;
62a48a2a 172
2278b939
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173 /* should be called only once, catch invalid users */
174 assert(!cpu_globals_initialized);
62a48a2a 175 cpu_globals_initialized = true;
1590bbcb 176
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177 while (featurestr) {
178 val = strchr(featurestr, '=');
179 if (val) {
62a48a2a 180 GlobalProperty *prop = g_new0(typeof(*prop), 1);
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181 *val = 0;
182 val++;
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183 prop->driver = typename;
184 prop->property = g_strdup(featurestr);
185 prop->value = g_strdup(val);
62a48a2a 186 qdev_prop_register_global(prop);
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187 } else {
188 error_setg(errp, "Expected key=value format, found %s.",
189 featurestr);
190 return;
191 }
192 featurestr = strtok(NULL, ",");
193 }
194}
195
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196static void cpu_common_realizefn(DeviceState *dev, Error **errp)
197{
13eed94e 198 CPUState *cpu = CPU(dev);
ed860129
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199 Object *machine = qdev_get_machine();
200
201 /* qdev_get_machine() can return something that's not TYPE_MACHINE
202 * if this is one of the user-only emulators; in that case there's
203 * no need to check the ignore_memory_transaction_failures board flag.
204 */
205 if (object_dynamic_cast(machine, TYPE_MACHINE)) {
bec552e2 206 MachineClass *mc = MACHINE_GET_CLASS(machine);
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207
208 if (mc) {
209 cpu->ignore_memory_transaction_failures =
210 mc->ignore_memory_transaction_failures;
211 }
212 }
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213
214 if (dev->hotplugged) {
215 cpu_synchronize_post_init(cpu);
6afb4721 216 cpu_resume(cpu);
13eed94e 217 }
2bfe11c8 218
b4ff2128
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219 /* Plugin initialization must wait until the cpu is fully realized. */
220 if (tcg_enabled()) {
221 qemu_plugin_vcpu_init_hook(cpu);
222 }
223
2bfe11c8 224 /* NOTE: latest generic point where the cpu is fully realized */
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225}
226
b69c3c21 227static void cpu_common_unrealizefn(DeviceState *dev)
7bbc124e
LV
228{
229 CPUState *cpu = CPU(dev);
7df5e3d6 230
b4ff2128
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231 /* Call the plugin hook before clearing the cpu is fully unrealized */
232 if (tcg_enabled()) {
233 qemu_plugin_vcpu_exit_hook(cpu);
234 }
235
82e95ec8 236 /* NOTE: latest generic point before the cpu is fully unrealized */
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LV
237 cpu_exec_unrealizefn(cpu);
238}
239
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240static void cpu_common_initfn(Object *obj)
241{
242 CPUState *cpu = CPU(obj);
243 CPUClass *cc = CPU_GET_CLASS(obj);
244
a07f953e 245 cpu->cpu_index = UNASSIGNED_CPU_INDEX;
7ea7b9ad 246 cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX;
35143f01 247 cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
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248 /* user-mode doesn't have configurable SMP topology */
249 /* the default value is changed by qemu_init_vcpu() for system-mode */
fa5376dd
MAL
250 cpu->nr_cores = 1;
251 cpu->nr_threads = 1;
c8cc6879 252 cpu->cflags_next_tb = -1;
fa5376dd 253
376692b9 254 qemu_mutex_init(&cpu->work_mutex);
bd688fc9 255 qemu_lockcnt_init(&cpu->in_ioctl_lock);
0c0fcc20 256 QSIMPLEQ_INIT(&cpu->work_list);
7c39163e
EH
257 QTAILQ_INIT(&cpu->breakpoints);
258 QTAILQ_INIT(&cpu->watchpoints);
b7d48952 259
39e329e3 260 cpu_exec_initfn(cpu);
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261}
262
b7bca733
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263static void cpu_common_finalize(Object *obj)
264{
611dbe46
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265 CPUState *cpu = CPU(obj);
266
bd688fc9 267 qemu_lockcnt_destroy(&cpu->in_ioctl_lock);
611dbe46 268 qemu_mutex_destroy(&cpu->work_mutex);
b7bca733
BR
269}
270
997395d3
IM
271static int64_t cpu_common_get_arch_id(CPUState *cpu)
272{
273 return cpu->cpu_index;
274}
275
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276static void cpu_class_init(ObjectClass *klass, void *data)
277{
961f8395 278 DeviceClass *dc = DEVICE_CLASS(klass);
3b750f1b 279 ResettableClass *rc = RESETTABLE_CLASS(klass);
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280 CPUClass *k = CPU_CLASS(klass);
281
1590bbcb 282 k->parse_features = cpu_common_parse_features;
997395d3 283 k->get_arch_id = cpu_common_get_arch_id;
8c2e1b00 284 k->has_work = cpu_common_has_work;
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285 k->gdb_read_register = cpu_common_gdb_read_register;
286 k->gdb_write_register = cpu_common_gdb_write_register;
ba31cc72 287 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
4f658099 288 dc->realize = cpu_common_realizefn;
7bbc124e 289 dc->unrealize = cpu_common_unrealizefn;
3b750f1b 290 rc->phases.hold = cpu_common_reset_hold;
995b87de 291 cpu_class_init_props(dc);
ffa95714
MA
292 /*
293 * Reason: CPUs still need special care by board code: wiring up
294 * IRQs, adding reset handlers, halting non-first CPUs, ...
295 */
e90f2a8c 296 dc->user_creatable = false;
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297}
298
961f8395 299static const TypeInfo cpu_type_info = {
dd83b06a 300 .name = TYPE_CPU,
961f8395 301 .parent = TYPE_DEVICE,
dd83b06a 302 .instance_size = sizeof(CPUState),
a0e372f0 303 .instance_init = cpu_common_initfn,
b7bca733 304 .instance_finalize = cpu_common_finalize,
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305 .abstract = true,
306 .class_size = sizeof(CPUClass),
307 .class_init = cpu_class_init,
308};
309
310static void cpu_register_types(void)
311{
312 type_register_static(&cpu_type_info);
313}
314
315type_init(cpu_register_types)