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Commit | Line | Data |
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dd83b06a AF |
1 | /* |
2 | * QEMU CPU model | |
3 | * | |
1590bbcb | 4 | * Copyright (c) 2012-2014 SUSE LINUX Products GmbH |
dd83b06a AF |
5 | * |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
1ef26b1f | 21 | #include "qemu/osdep.h" |
da34e65c | 22 | #include "qapi/error.h" |
2e5b09fd | 23 | #include "hw/core/cpu.h" |
b3946626 | 24 | #include "sysemu/hw_accel.h" |
066e9b27 | 25 | #include "qemu/notify.h" |
91b1df8c | 26 | #include "qemu/log.h" |
db725815 | 27 | #include "qemu/main-loop.h" |
508127e2 | 28 | #include "exec/log.h" |
9262685b | 29 | #include "qemu/error-report.h" |
90c84c56 | 30 | #include "qemu/qemu-print.h" |
14a48c1d | 31 | #include "sysemu/tcg.h" |
ed860129 | 32 | #include "hw/boards.h" |
62a48a2a | 33 | #include "hw/qdev-properties.h" |
0ab8ed18 | 34 | #include "trace-root.h" |
30865f31 | 35 | #include "qemu/plugin.h" |
066e9b27 | 36 | |
290dae46 PB |
37 | CPUInterruptHandler cpu_interrupt_handler; |
38 | ||
5ce46cb3 | 39 | CPUState *cpu_by_arch_id(int64_t id) |
69e5ff06 | 40 | { |
38fcbd3f AF |
41 | CPUState *cpu; |
42 | ||
43 | CPU_FOREACH(cpu) { | |
44 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
69e5ff06 | 45 | |
38fcbd3f | 46 | if (cc->get_arch_id(cpu) == id) { |
5ce46cb3 | 47 | return cpu; |
38fcbd3f AF |
48 | } |
49 | } | |
5ce46cb3 EH |
50 | return NULL; |
51 | } | |
52 | ||
53 | bool cpu_exists(int64_t id) | |
54 | { | |
55 | return !!cpu_by_arch_id(id); | |
69e5ff06 IM |
56 | } |
57 | ||
3c72234c IM |
58 | CPUState *cpu_create(const char *typename) |
59 | { | |
60 | Error *err = NULL; | |
61 | CPUState *cpu = CPU(object_new(typename)); | |
ce189ab2 | 62 | qdev_realize(DEVICE(cpu), NULL, &err); |
3c72234c IM |
63 | if (err != NULL) { |
64 | error_report_err(err); | |
65 | object_unref(OBJECT(cpu)); | |
4482e05c | 66 | exit(EXIT_FAILURE); |
3c72234c IM |
67 | } |
68 | return cpu; | |
69 | } | |
70 | ||
444d5590 AF |
71 | bool cpu_paging_enabled(const CPUState *cpu) |
72 | { | |
73 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
74 | ||
75 | return cc->get_paging_enabled(cpu); | |
76 | } | |
77 | ||
78 | static bool cpu_common_get_paging_enabled(const CPUState *cpu) | |
79 | { | |
6db297ea | 80 | return false; |
444d5590 AF |
81 | } |
82 | ||
a23bbfda AF |
83 | void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, |
84 | Error **errp) | |
85 | { | |
86 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
87 | ||
fbe95bfb | 88 | cc->get_memory_mapping(cpu, list, errp); |
a23bbfda AF |
89 | } |
90 | ||
91 | static void cpu_common_get_memory_mapping(CPUState *cpu, | |
92 | MemoryMappingList *list, | |
93 | Error **errp) | |
94 | { | |
95 | error_setg(errp, "Obtaining memory mappings is unsupported on this CPU."); | |
96 | } | |
97 | ||
8d04fb55 JK |
98 | /* Resetting the IRQ comes from across the code base so we take the |
99 | * BQL here if we need to. cpu_interrupt assumes it is held.*/ | |
d8ed887b AF |
100 | void cpu_reset_interrupt(CPUState *cpu, int mask) |
101 | { | |
8d04fb55 JK |
102 | bool need_lock = !qemu_mutex_iothread_locked(); |
103 | ||
104 | if (need_lock) { | |
105 | qemu_mutex_lock_iothread(); | |
106 | } | |
d8ed887b | 107 | cpu->interrupt_request &= ~mask; |
8d04fb55 JK |
108 | if (need_lock) { |
109 | qemu_mutex_unlock_iothread(); | |
110 | } | |
d8ed887b AF |
111 | } |
112 | ||
60a3e17a AF |
113 | void cpu_exit(CPUState *cpu) |
114 | { | |
027d9a7d | 115 | atomic_set(&cpu->exit_request, 1); |
ab096a75 PB |
116 | /* Ensure cpu_exec will see the exit request after TCG has exited. */ |
117 | smp_wmb(); | |
5e140196 | 118 | atomic_set(&cpu->icount_decr_ptr->u16.high, -1); |
60a3e17a AF |
119 | } |
120 | ||
c72bf468 JF |
121 | int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, |
122 | void *opaque) | |
123 | { | |
124 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
125 | ||
126 | return (*cc->write_elf32_qemunote)(f, cpu, opaque); | |
127 | } | |
128 | ||
129 | static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f, | |
130 | CPUState *cpu, void *opaque) | |
131 | { | |
b09afd58 | 132 | return 0; |
c72bf468 JF |
133 | } |
134 | ||
135 | int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, | |
136 | int cpuid, void *opaque) | |
137 | { | |
138 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
139 | ||
140 | return (*cc->write_elf32_note)(f, cpu, cpuid, opaque); | |
141 | } | |
142 | ||
143 | static int cpu_common_write_elf32_note(WriteCoreDumpFunction f, | |
144 | CPUState *cpu, int cpuid, | |
145 | void *opaque) | |
146 | { | |
147 | return -1; | |
148 | } | |
149 | ||
150 | int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
151 | void *opaque) | |
152 | { | |
153 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
154 | ||
155 | return (*cc->write_elf64_qemunote)(f, cpu, opaque); | |
156 | } | |
157 | ||
158 | static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f, | |
159 | CPUState *cpu, void *opaque) | |
160 | { | |
b09afd58 | 161 | return 0; |
c72bf468 JF |
162 | } |
163 | ||
164 | int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, | |
165 | int cpuid, void *opaque) | |
166 | { | |
167 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
168 | ||
169 | return (*cc->write_elf64_note)(f, cpu, cpuid, opaque); | |
170 | } | |
171 | ||
172 | static int cpu_common_write_elf64_note(WriteCoreDumpFunction f, | |
173 | CPUState *cpu, int cpuid, | |
174 | void *opaque) | |
175 | { | |
176 | return -1; | |
177 | } | |
178 | ||
179 | ||
a010bdbe | 180 | static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg) |
5b50e790 AF |
181 | { |
182 | return 0; | |
183 | } | |
184 | ||
185 | static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg) | |
186 | { | |
187 | return 0; | |
188 | } | |
189 | ||
568496c0 SF |
190 | static bool cpu_common_debug_check_watchpoint(CPUState *cpu, CPUWatchpoint *wp) |
191 | { | |
192 | /* If no extra check is required, QEMU watchpoint match can be considered | |
193 | * as an architectural match. | |
194 | */ | |
195 | return true; | |
196 | } | |
197 | ||
bf7663c4 GK |
198 | static bool cpu_common_virtio_is_big_endian(CPUState *cpu) |
199 | { | |
200 | return target_words_bigendian(); | |
201 | } | |
5b50e790 | 202 | |
cffe7b32 | 203 | static void cpu_common_noop(CPUState *cpu) |
86025ee4 PM |
204 | { |
205 | } | |
206 | ||
9585db68 RH |
207 | static bool cpu_common_exec_interrupt(CPUState *cpu, int int_req) |
208 | { | |
209 | return false; | |
210 | } | |
211 | ||
cfe35d48 | 212 | #if !defined(CONFIG_USER_ONLY) |
c86f106b AN |
213 | GuestPanicInformation *cpu_get_crash_info(CPUState *cpu) |
214 | { | |
215 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
216 | GuestPanicInformation *res = NULL; | |
217 | ||
218 | if (cc->get_crash_info) { | |
219 | res = cc->get_crash_info(cpu); | |
220 | } | |
221 | return res; | |
222 | } | |
cfe35d48 | 223 | #endif |
c86f106b | 224 | |
90c84c56 | 225 | void cpu_dump_state(CPUState *cpu, FILE *f, int flags) |
878096ee AF |
226 | { |
227 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
228 | ||
229 | if (cc->dump_state) { | |
97577fd4 | 230 | cpu_synchronize_state(cpu); |
90c84c56 | 231 | cc->dump_state(cpu, f, flags); |
878096ee AF |
232 | } |
233 | } | |
234 | ||
11cb6c15 | 235 | void cpu_dump_statistics(CPUState *cpu, int flags) |
878096ee AF |
236 | { |
237 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
238 | ||
239 | if (cc->dump_statistics) { | |
11cb6c15 | 240 | cc->dump_statistics(cpu, flags); |
878096ee AF |
241 | } |
242 | } | |
243 | ||
dd83b06a AF |
244 | void cpu_reset(CPUState *cpu) |
245 | { | |
781c67ca | 246 | device_cold_reset(DEVICE(cpu)); |
2cc2d082 LV |
247 | |
248 | trace_guest_cpu_reset(cpu); | |
dd83b06a AF |
249 | } |
250 | ||
781c67ca | 251 | static void cpu_common_reset(DeviceState *dev) |
dd83b06a | 252 | { |
781c67ca | 253 | CPUState *cpu = CPU(dev); |
91b1df8c AF |
254 | CPUClass *cc = CPU_GET_CLASS(cpu); |
255 | ||
256 | if (qemu_loglevel_mask(CPU_LOG_RESET)) { | |
257 | qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index); | |
258 | log_cpu_state(cpu, cc->reset_dump_flags); | |
259 | } | |
260 | ||
259186a7 | 261 | cpu->interrupt_request = 0; |
259186a7 | 262 | cpu->halted = 0; |
93afeade | 263 | cpu->mem_io_pc = 0; |
efee7340 | 264 | cpu->icount_extra = 0; |
5e140196 | 265 | atomic_set(&cpu->icount_decr_ptr->u32, 0); |
414b15c9 | 266 | cpu->can_do_io = 1; |
f9d8f667 | 267 | cpu->exception_index = -1; |
bac05aa9 | 268 | cpu->crash_occurred = false; |
9b990ee5 | 269 | cpu->cflags_next_tb = -1; |
ce7cf6a9 | 270 | |
ba7d3d18 | 271 | if (tcg_enabled()) { |
f3ced3c5 | 272 | cpu_tb_jmp_cache_clear(cpu); |
1f5c00cf | 273 | |
2cd53943 | 274 | tcg_flush_softmmu_tlb(cpu); |
ba7d3d18 | 275 | } |
dd83b06a AF |
276 | } |
277 | ||
8c2e1b00 AF |
278 | static bool cpu_common_has_work(CPUState *cs) |
279 | { | |
280 | return false; | |
281 | } | |
282 | ||
2b8c2754 AF |
283 | ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model) |
284 | { | |
99193d8f | 285 | CPUClass *cc = CPU_CLASS(object_class_by_name(typename)); |
2b8c2754 | 286 | |
99193d8f | 287 | assert(cpu_model && cc->class_by_name); |
2b8c2754 AF |
288 | return cc->class_by_name(cpu_model); |
289 | } | |
290 | ||
62a48a2a | 291 | static void cpu_common_parse_features(const char *typename, char *features, |
1590bbcb AF |
292 | Error **errp) |
293 | { | |
1590bbcb | 294 | char *val; |
62a48a2a | 295 | static bool cpu_globals_initialized; |
2278b939 IM |
296 | /* Single "key=value" string being parsed */ |
297 | char *featurestr = features ? strtok(features, ",") : NULL; | |
62a48a2a | 298 | |
2278b939 IM |
299 | /* should be called only once, catch invalid users */ |
300 | assert(!cpu_globals_initialized); | |
62a48a2a | 301 | cpu_globals_initialized = true; |
1590bbcb | 302 | |
1590bbcb AF |
303 | while (featurestr) { |
304 | val = strchr(featurestr, '='); | |
305 | if (val) { | |
62a48a2a | 306 | GlobalProperty *prop = g_new0(typeof(*prop), 1); |
1590bbcb AF |
307 | *val = 0; |
308 | val++; | |
62a48a2a IM |
309 | prop->driver = typename; |
310 | prop->property = g_strdup(featurestr); | |
311 | prop->value = g_strdup(val); | |
62a48a2a | 312 | qdev_prop_register_global(prop); |
1590bbcb AF |
313 | } else { |
314 | error_setg(errp, "Expected key=value format, found %s.", | |
315 | featurestr); | |
316 | return; | |
317 | } | |
318 | featurestr = strtok(NULL, ","); | |
319 | } | |
320 | } | |
321 | ||
4f658099 AF |
322 | static void cpu_common_realizefn(DeviceState *dev, Error **errp) |
323 | { | |
13eed94e | 324 | CPUState *cpu = CPU(dev); |
ed860129 PM |
325 | Object *machine = qdev_get_machine(); |
326 | ||
327 | /* qdev_get_machine() can return something that's not TYPE_MACHINE | |
328 | * if this is one of the user-only emulators; in that case there's | |
329 | * no need to check the ignore_memory_transaction_failures board flag. | |
330 | */ | |
331 | if (object_dynamic_cast(machine, TYPE_MACHINE)) { | |
332 | ObjectClass *oc = object_get_class(machine); | |
333 | MachineClass *mc = MACHINE_CLASS(oc); | |
334 | ||
335 | if (mc) { | |
336 | cpu->ignore_memory_transaction_failures = | |
337 | mc->ignore_memory_transaction_failures; | |
338 | } | |
339 | } | |
13eed94e IM |
340 | |
341 | if (dev->hotplugged) { | |
342 | cpu_synchronize_post_init(cpu); | |
6afb4721 | 343 | cpu_resume(cpu); |
13eed94e | 344 | } |
2bfe11c8 LV |
345 | |
346 | /* NOTE: latest generic point where the cpu is fully realized */ | |
347 | trace_init_vcpu(cpu); | |
4f658099 AF |
348 | } |
349 | ||
b69c3c21 | 350 | static void cpu_common_unrealizefn(DeviceState *dev) |
7bbc124e LV |
351 | { |
352 | CPUState *cpu = CPU(dev); | |
82e95ec8 LV |
353 | /* NOTE: latest generic point before the cpu is fully unrealized */ |
354 | trace_fini_vcpu(cpu); | |
30865f31 | 355 | qemu_plugin_vcpu_exit_hook(cpu); |
7bbc124e LV |
356 | cpu_exec_unrealizefn(cpu); |
357 | } | |
358 | ||
a0e372f0 AF |
359 | static void cpu_common_initfn(Object *obj) |
360 | { | |
361 | CPUState *cpu = CPU(obj); | |
362 | CPUClass *cc = CPU_GET_CLASS(obj); | |
363 | ||
a07f953e | 364 | cpu->cpu_index = UNASSIGNED_CPU_INDEX; |
7ea7b9ad | 365 | cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX; |
35143f01 | 366 | cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs; |
fa5376dd MAL |
367 | /* *-user doesn't have configurable SMP topology */ |
368 | /* the default value is changed by qemu_init_vcpu() for softmmu */ | |
369 | cpu->nr_cores = 1; | |
370 | cpu->nr_threads = 1; | |
371 | ||
376692b9 | 372 | qemu_mutex_init(&cpu->work_mutex); |
0c0fcc20 | 373 | QSIMPLEQ_INIT(&cpu->work_list); |
7c39163e EH |
374 | QTAILQ_INIT(&cpu->breakpoints); |
375 | QTAILQ_INIT(&cpu->watchpoints); | |
b7d48952 | 376 | |
39e329e3 | 377 | cpu_exec_initfn(cpu); |
a0e372f0 AF |
378 | } |
379 | ||
b7bca733 BR |
380 | static void cpu_common_finalize(Object *obj) |
381 | { | |
611dbe46 LQ |
382 | CPUState *cpu = CPU(obj); |
383 | ||
384 | qemu_mutex_destroy(&cpu->work_mutex); | |
b7bca733 BR |
385 | } |
386 | ||
997395d3 IM |
387 | static int64_t cpu_common_get_arch_id(CPUState *cpu) |
388 | { | |
389 | return cpu->cpu_index; | |
390 | } | |
391 | ||
40612000 JB |
392 | static vaddr cpu_adjust_watchpoint_address(CPUState *cpu, vaddr addr, int len) |
393 | { | |
394 | return addr; | |
395 | } | |
396 | ||
290dae46 PB |
397 | static void generic_handle_interrupt(CPUState *cpu, int mask) |
398 | { | |
399 | cpu->interrupt_request |= mask; | |
400 | ||
401 | if (!qemu_cpu_is_self(cpu)) { | |
402 | qemu_cpu_kick(cpu); | |
403 | } | |
404 | } | |
405 | ||
406 | CPUInterruptHandler cpu_interrupt_handler = generic_handle_interrupt; | |
407 | ||
dd83b06a AF |
408 | static void cpu_class_init(ObjectClass *klass, void *data) |
409 | { | |
961f8395 | 410 | DeviceClass *dc = DEVICE_CLASS(klass); |
dd83b06a AF |
411 | CPUClass *k = CPU_CLASS(klass); |
412 | ||
1590bbcb | 413 | k->parse_features = cpu_common_parse_features; |
997395d3 | 414 | k->get_arch_id = cpu_common_get_arch_id; |
8c2e1b00 | 415 | k->has_work = cpu_common_has_work; |
444d5590 | 416 | k->get_paging_enabled = cpu_common_get_paging_enabled; |
a23bbfda | 417 | k->get_memory_mapping = cpu_common_get_memory_mapping; |
c72bf468 JF |
418 | k->write_elf32_qemunote = cpu_common_write_elf32_qemunote; |
419 | k->write_elf32_note = cpu_common_write_elf32_note; | |
420 | k->write_elf64_qemunote = cpu_common_write_elf64_qemunote; | |
421 | k->write_elf64_note = cpu_common_write_elf64_note; | |
5b50e790 AF |
422 | k->gdb_read_register = cpu_common_gdb_read_register; |
423 | k->gdb_write_register = cpu_common_gdb_write_register; | |
bf7663c4 | 424 | k->virtio_is_big_endian = cpu_common_virtio_is_big_endian; |
cffe7b32 | 425 | k->debug_excp_handler = cpu_common_noop; |
568496c0 | 426 | k->debug_check_watchpoint = cpu_common_debug_check_watchpoint; |
cffe7b32 RH |
427 | k->cpu_exec_enter = cpu_common_noop; |
428 | k->cpu_exec_exit = cpu_common_noop; | |
9585db68 | 429 | k->cpu_exec_interrupt = cpu_common_exec_interrupt; |
40612000 | 430 | k->adjust_watchpoint_address = cpu_adjust_watchpoint_address; |
ba31cc72 | 431 | set_bit(DEVICE_CATEGORY_CPU, dc->categories); |
4f658099 | 432 | dc->realize = cpu_common_realizefn; |
7bbc124e | 433 | dc->unrealize = cpu_common_unrealizefn; |
781c67ca | 434 | dc->reset = cpu_common_reset; |
4f67d30b | 435 | device_class_set_props(dc, cpu_common_props); |
ffa95714 MA |
436 | /* |
437 | * Reason: CPUs still need special care by board code: wiring up | |
438 | * IRQs, adding reset handlers, halting non-first CPUs, ... | |
439 | */ | |
e90f2a8c | 440 | dc->user_creatable = false; |
dd83b06a AF |
441 | } |
442 | ||
961f8395 | 443 | static const TypeInfo cpu_type_info = { |
dd83b06a | 444 | .name = TYPE_CPU, |
961f8395 | 445 | .parent = TYPE_DEVICE, |
dd83b06a | 446 | .instance_size = sizeof(CPUState), |
a0e372f0 | 447 | .instance_init = cpu_common_initfn, |
b7bca733 | 448 | .instance_finalize = cpu_common_finalize, |
dd83b06a AF |
449 | .abstract = true, |
450 | .class_size = sizeof(CPUClass), | |
451 | .class_init = cpu_class_init, | |
452 | }; | |
453 | ||
454 | static void cpu_register_types(void) | |
455 | { | |
456 | type_register_static(&cpu_type_info); | |
457 | } | |
458 | ||
459 | type_init(cpu_register_types) |