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Commit | Line | Data |
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36d20cb2 MA |
1 | /* |
2 | * QEMU Machine | |
3 | * | |
4 | * Copyright (C) 2014 Red Hat Inc | |
5 | * | |
6 | * Authors: | |
7 | * Marcel Apfelbaum <marcel.a@redhat.com> | |
8 | * | |
9 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
10 | * See the COPYING file in the top-level directory. | |
11 | */ | |
12 | ||
18c86e2b | 13 | #include "qemu/osdep.h" |
6f479566 LX |
14 | #include "qemu/option.h" |
15 | #include "qapi/qmp/qerror.h" | |
16 | #include "sysemu/replay.h" | |
fc6b3cf9 | 17 | #include "qemu/units.h" |
36d20cb2 | 18 | #include "hw/boards.h" |
f66dc873 | 19 | #include "hw/loader.h" |
da34e65c | 20 | #include "qapi/error.h" |
9af23989 | 21 | #include "qapi/qapi-visit-common.h" |
6b1b1440 | 22 | #include "qapi/visitor.h" |
33cd52b5 | 23 | #include "hw/sysbus.h" |
f66dc873 | 24 | #include "sysemu/cpus.h" |
33cd52b5 | 25 | #include "sysemu/sysemu.h" |
f66dc873 PB |
26 | #include "sysemu/reset.h" |
27 | #include "sysemu/runstate.h" | |
3bfe5716 | 28 | #include "sysemu/numa.h" |
33cd52b5 | 29 | #include "qemu/error-report.h" |
c6ff347c | 30 | #include "sysemu/qtest.h" |
edc24ccd | 31 | #include "hw/pci/pci.h" |
f6a0d06b | 32 | #include "hw/mem/nvdimm.h" |
f66dc873 | 33 | #include "migration/global_state.h" |
82b911aa | 34 | #include "migration/vmstate.h" |
e0292d7c | 35 | #include "exec/confidential-guest-support.h" |
6b1b1440 | 36 | |
576a00bd CH |
37 | GlobalProperty hw_compat_5_2[] = {}; |
38 | const size_t hw_compat_5_2_len = G_N_ELEMENTS(hw_compat_5_2); | |
39 | ||
6a558822 SH |
40 | GlobalProperty hw_compat_5_1[] = { |
41 | { "vhost-scsi", "num_queues", "1"}, | |
a4eef071 | 42 | { "vhost-user-blk", "num-queues", "1"}, |
6a558822 | 43 | { "vhost-user-scsi", "num_queues", "1"}, |
9445e1e1 | 44 | { "virtio-blk-device", "num-queues", "1"}, |
6a558822 | 45 | { "virtio-scsi-device", "num_queues", "1"}, |
6eb7a071 | 46 | { "nvme", "use-intel-id", "on"}, |
b1b0393c | 47 | { "pvpanic", "events", "1"}, /* PVPANIC_PANICKED */ |
6a558822 | 48 | }; |
3ff3c5d3 CH |
49 | const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1); |
50 | ||
7483cbba | 51 | GlobalProperty hw_compat_5_0[] = { |
2ebc2121 | 52 | { "pci-host-bridge", "x-config-reg-migration-enabled", "off" }, |
7483cbba | 53 | { "virtio-balloon-device", "page-poison", "false" }, |
f983ff95 PB |
54 | { "vmport", "x-read-set-eax", "off" }, |
55 | { "vmport", "x-signal-unsupported-cmd", "off" }, | |
56 | { "vmport", "x-report-vmx-type", "off" }, | |
57 | { "vmport", "x-cmds-v2", "off" }, | |
d55f5182 | 58 | { "virtio-device", "x-disable-legacy-check", "true" }, |
7483cbba | 59 | }; |
541aaa1d CH |
60 | const size_t hw_compat_5_0_len = G_N_ELEMENTS(hw_compat_5_0); |
61 | ||
5f258577 | 62 | GlobalProperty hw_compat_4_2[] = { |
c9b7d9ec DP |
63 | { "virtio-blk-device", "queue-size", "128"}, |
64 | { "virtio-scsi-device", "virtqueue_size", "128"}, | |
5f258577 | 65 | { "virtio-blk-device", "x-enable-wce-if-config-wce", "off" }, |
1bf8a989 DP |
66 | { "virtio-blk-device", "seg-max-adjust", "off"}, |
67 | { "virtio-scsi-device", "seg_max_adjust", "off"}, | |
68 | { "vhost-blk-device", "seg_max_adjust", "off"}, | |
7bacaf5f | 69 | { "usb-host", "suppress-remote-wake", "off" }, |
32187f3d | 70 | { "usb-redir", "suppress-remote-wake", "off" }, |
ed71c09f GH |
71 | { "qxl", "revision", "4" }, |
72 | { "qxl-vga", "revision", "4" }, | |
394f0f72 | 73 | { "fw_cfg", "acpi-mr-restore", "false" }, |
c126b4c5 | 74 | { "virtio-device", "use-disabled-flag", "false" }, |
5f258577 EY |
75 | }; |
76 | const size_t hw_compat_4_2_len = G_N_ELEMENTS(hw_compat_4_2); | |
77 | ||
eb1556c4 JS |
78 | GlobalProperty hw_compat_4_1[] = { |
79 | { "virtio-pci", "x-pcie-flr-init", "off" }, | |
80 | }; | |
9aec2e52 CH |
81 | const size_t hw_compat_4_1_len = G_N_ELEMENTS(hw_compat_4_1); |
82 | ||
8e8cbed0 | 83 | GlobalProperty hw_compat_4_0[] = { |
0a719662 GH |
84 | { "VGA", "edid", "false" }, |
85 | { "secondary-vga", "edid", "false" }, | |
86 | { "bochs-display", "edid", "false" }, | |
87 | { "virtio-vga", "edid", "false" }, | |
02501fc3 | 88 | { "virtio-gpu-device", "edid", "false" }, |
e57f2c31 | 89 | { "virtio-device", "use-started", "false" }, |
2bbadb08 | 90 | { "virtio-balloon-device", "qemu-4-0-config-size", "true" }, |
032cfe6a | 91 | { "pl031", "migrate-tick-offset", "false" }, |
0a719662 | 92 | }; |
9bf2650b CH |
93 | const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0); |
94 | ||
abd93cc7 | 95 | GlobalProperty hw_compat_3_1[] = { |
6c36bddf EH |
96 | { "pcie-root-port", "x-speed", "2_5" }, |
97 | { "pcie-root-port", "x-width", "1" }, | |
98 | { "memory-backend-file", "x-use-canonical-path-for-ramblock-id", "true" }, | |
99 | { "memory-backend-memfd", "x-use-canonical-path-for-ramblock-id", "true" }, | |
b6148757 MAL |
100 | { "tpm-crb", "ppi", "false" }, |
101 | { "tpm-tis", "ppi", "false" }, | |
b63e1050 GH |
102 | { "usb-kbd", "serial", "42" }, |
103 | { "usb-mouse", "serial", "42" }, | |
442bac16 | 104 | { "usb-tablet", "serial", "42" }, |
5c81161f SG |
105 | { "virtio-blk-device", "discard", "false" }, |
106 | { "virtio-blk-device", "write-zeroes", "false" }, | |
2bbadb08 | 107 | { "virtio-balloon-device", "qemu-4-0-config-size", "false" }, |
c8557f1b | 108 | { "pcie-root-port-base", "disable-acs", "true" }, /* Added in 4.1 */ |
abd93cc7 MAL |
109 | }; |
110 | const size_t hw_compat_3_1_len = G_N_ELEMENTS(hw_compat_3_1); | |
111 | ||
ddb3235d MAL |
112 | GlobalProperty hw_compat_3_0[] = {}; |
113 | const size_t hw_compat_3_0_len = G_N_ELEMENTS(hw_compat_3_0); | |
114 | ||
0d47310b | 115 | GlobalProperty hw_compat_2_12[] = { |
6c36bddf EH |
116 | { "migration", "decompress-error-check", "off" }, |
117 | { "hda-audio", "use-timer", "false" }, | |
118 | { "cirrus-vga", "global-vmstate", "true" }, | |
119 | { "VGA", "global-vmstate", "true" }, | |
120 | { "vmware-svga", "global-vmstate", "true" }, | |
121 | { "qxl-vga", "global-vmstate", "true" }, | |
0d47310b MAL |
122 | }; |
123 | const size_t hw_compat_2_12_len = G_N_ELEMENTS(hw_compat_2_12); | |
124 | ||
43df70a9 | 125 | GlobalProperty hw_compat_2_11[] = { |
6c36bddf EH |
126 | { "hpet", "hpet-offset-saved", "false" }, |
127 | { "virtio-blk-pci", "vectors", "2" }, | |
128 | { "vhost-user-blk-pci", "vectors", "2" }, | |
129 | { "e1000", "migrate_tso_props", "off" }, | |
43df70a9 MAL |
130 | }; |
131 | const size_t hw_compat_2_11_len = G_N_ELEMENTS(hw_compat_2_11); | |
132 | ||
503224f4 | 133 | GlobalProperty hw_compat_2_10[] = { |
6c36bddf EH |
134 | { "virtio-mouse-device", "wheel-axis", "false" }, |
135 | { "virtio-tablet-device", "wheel-axis", "false" }, | |
503224f4 MAL |
136 | }; |
137 | const size_t hw_compat_2_10_len = G_N_ELEMENTS(hw_compat_2_10); | |
138 | ||
3e803152 | 139 | GlobalProperty hw_compat_2_9[] = { |
6c36bddf EH |
140 | { "pci-bridge", "shpc", "off" }, |
141 | { "intel-iommu", "pt", "off" }, | |
142 | { "virtio-net-device", "x-mtu-bypass-backend", "off" }, | |
143 | { "pcie-root-port", "x-migrate-msix", "false" }, | |
3e803152 MAL |
144 | }; |
145 | const size_t hw_compat_2_9_len = G_N_ELEMENTS(hw_compat_2_9); | |
146 | ||
edc24ccd | 147 | GlobalProperty hw_compat_2_8[] = { |
6c36bddf EH |
148 | { "fw_cfg_mem", "x-file-slots", "0x10" }, |
149 | { "fw_cfg_io", "x-file-slots", "0x10" }, | |
150 | { "pflash_cfi01", "old-multiple-chip-handling", "on" }, | |
151 | { "pci-bridge", "shpc", "on" }, | |
152 | { TYPE_PCI_DEVICE, "x-pcie-extcap-init", "off" }, | |
153 | { "virtio-pci", "x-pcie-deverr-init", "off" }, | |
154 | { "virtio-pci", "x-pcie-lnkctl-init", "off" }, | |
155 | { "virtio-pci", "x-pcie-pm-init", "off" }, | |
156 | { "cirrus-vga", "vgamem_mb", "8" }, | |
157 | { "isa-cirrus-vga", "vgamem_mb", "8" }, | |
edc24ccd MAL |
158 | }; |
159 | const size_t hw_compat_2_8_len = G_N_ELEMENTS(hw_compat_2_8); | |
160 | ||
5a995064 | 161 | GlobalProperty hw_compat_2_7[] = { |
6c36bddf EH |
162 | { "virtio-pci", "page-per-vq", "on" }, |
163 | { "virtio-serial-device", "emergency-write", "off" }, | |
164 | { "ioapic", "version", "0x11" }, | |
165 | { "intel-iommu", "x-buggy-eim", "true" }, | |
166 | { "virtio-pci", "x-ignore-backend-features", "on" }, | |
5a995064 MAL |
167 | }; |
168 | const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7); | |
169 | ||
ff8f261f | 170 | GlobalProperty hw_compat_2_6[] = { |
6c36bddf | 171 | { "virtio-mmio", "format_transport_address", "off" }, |
dd56040d DDAG |
172 | /* Optional because not all virtio-pci devices support legacy mode */ |
173 | { "virtio-pci", "disable-modern", "on", .optional = true }, | |
174 | { "virtio-pci", "disable-legacy", "off", .optional = true }, | |
ff8f261f MAL |
175 | }; |
176 | const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6); | |
177 | ||
fe759610 | 178 | GlobalProperty hw_compat_2_5[] = { |
6c36bddf EH |
179 | { "isa-fdc", "fallback", "144" }, |
180 | { "pvscsi", "x-old-pci-configuration", "on" }, | |
181 | { "pvscsi", "x-disable-pcie", "on" }, | |
182 | { "vmxnet3", "x-old-msi-offsets", "on" }, | |
183 | { "vmxnet3", "x-disable-pcie", "on" }, | |
fe759610 MAL |
184 | }; |
185 | const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5); | |
186 | ||
2f99b9c2 | 187 | GlobalProperty hw_compat_2_4[] = { |
11a18c84 PMD |
188 | /* Optional because the 'scsi' property is Linux-only */ |
189 | { "virtio-blk-device", "scsi", "true", .optional = true }, | |
6c36bddf EH |
190 | { "e1000", "extra_mac_registers", "off" }, |
191 | { "virtio-pci", "x-disable-pcie", "on" }, | |
192 | { "virtio-pci", "migrate-extra", "off" }, | |
193 | { "fw_cfg_mem", "dma_enabled", "off" }, | |
194 | { "fw_cfg_io", "dma_enabled", "off" } | |
2f99b9c2 MAL |
195 | }; |
196 | const size_t hw_compat_2_4_len = G_N_ELEMENTS(hw_compat_2_4); | |
197 | ||
8995dd90 | 198 | GlobalProperty hw_compat_2_3[] = { |
6c36bddf EH |
199 | { "virtio-blk-pci", "any_layout", "off" }, |
200 | { "virtio-balloon-pci", "any_layout", "off" }, | |
201 | { "virtio-serial-pci", "any_layout", "off" }, | |
202 | { "virtio-9p-pci", "any_layout", "off" }, | |
203 | { "virtio-rng-pci", "any_layout", "off" }, | |
204 | { TYPE_PCI_DEVICE, "x-pcie-lnksta-dllla", "off" }, | |
205 | { "migration", "send-configuration", "off" }, | |
206 | { "migration", "send-section-footer", "off" }, | |
207 | { "migration", "store-global-state", "off" }, | |
8995dd90 MAL |
208 | }; |
209 | const size_t hw_compat_2_3_len = G_N_ELEMENTS(hw_compat_2_3); | |
210 | ||
1c30044e MAL |
211 | GlobalProperty hw_compat_2_2[] = {}; |
212 | const size_t hw_compat_2_2_len = G_N_ELEMENTS(hw_compat_2_2); | |
213 | ||
c4fc5695 | 214 | GlobalProperty hw_compat_2_1[] = { |
6c36bddf EH |
215 | { "intel-hda", "old_msi_addr", "on" }, |
216 | { "VGA", "qemu-extended-regs", "off" }, | |
217 | { "secondary-vga", "qemu-extended-regs", "off" }, | |
218 | { "virtio-scsi-pci", "any_layout", "off" }, | |
219 | { "usb-mouse", "usb_version", "1" }, | |
220 | { "usb-kbd", "usb_version", "1" }, | |
221 | { "virtio-pci", "virtio-pci-bus-master-bug-migration", "on" }, | |
c4fc5695 MAL |
222 | }; |
223 | const size_t hw_compat_2_1_len = G_N_ELEMENTS(hw_compat_2_1); | |
224 | ||
c5e3c918 PB |
225 | MachineState *current_machine; |
226 | ||
6b1b1440 MA |
227 | static char *machine_get_kernel(Object *obj, Error **errp) |
228 | { | |
229 | MachineState *ms = MACHINE(obj); | |
230 | ||
231 | return g_strdup(ms->kernel_filename); | |
232 | } | |
233 | ||
234 | static void machine_set_kernel(Object *obj, const char *value, Error **errp) | |
235 | { | |
236 | MachineState *ms = MACHINE(obj); | |
237 | ||
556068ee | 238 | g_free(ms->kernel_filename); |
6b1b1440 MA |
239 | ms->kernel_filename = g_strdup(value); |
240 | } | |
241 | ||
242 | static char *machine_get_initrd(Object *obj, Error **errp) | |
243 | { | |
244 | MachineState *ms = MACHINE(obj); | |
245 | ||
246 | return g_strdup(ms->initrd_filename); | |
247 | } | |
248 | ||
249 | static void machine_set_initrd(Object *obj, const char *value, Error **errp) | |
250 | { | |
251 | MachineState *ms = MACHINE(obj); | |
252 | ||
556068ee | 253 | g_free(ms->initrd_filename); |
6b1b1440 MA |
254 | ms->initrd_filename = g_strdup(value); |
255 | } | |
256 | ||
257 | static char *machine_get_append(Object *obj, Error **errp) | |
258 | { | |
259 | MachineState *ms = MACHINE(obj); | |
260 | ||
261 | return g_strdup(ms->kernel_cmdline); | |
262 | } | |
263 | ||
264 | static void machine_set_append(Object *obj, const char *value, Error **errp) | |
265 | { | |
266 | MachineState *ms = MACHINE(obj); | |
267 | ||
556068ee | 268 | g_free(ms->kernel_cmdline); |
6b1b1440 MA |
269 | ms->kernel_cmdline = g_strdup(value); |
270 | } | |
271 | ||
272 | static char *machine_get_dtb(Object *obj, Error **errp) | |
273 | { | |
274 | MachineState *ms = MACHINE(obj); | |
275 | ||
276 | return g_strdup(ms->dtb); | |
277 | } | |
278 | ||
279 | static void machine_set_dtb(Object *obj, const char *value, Error **errp) | |
280 | { | |
281 | MachineState *ms = MACHINE(obj); | |
282 | ||
556068ee | 283 | g_free(ms->dtb); |
6b1b1440 MA |
284 | ms->dtb = g_strdup(value); |
285 | } | |
286 | ||
287 | static char *machine_get_dumpdtb(Object *obj, Error **errp) | |
288 | { | |
289 | MachineState *ms = MACHINE(obj); | |
290 | ||
291 | return g_strdup(ms->dumpdtb); | |
292 | } | |
293 | ||
294 | static void machine_set_dumpdtb(Object *obj, const char *value, Error **errp) | |
295 | { | |
296 | MachineState *ms = MACHINE(obj); | |
297 | ||
556068ee | 298 | g_free(ms->dumpdtb); |
6b1b1440 MA |
299 | ms->dumpdtb = g_strdup(value); |
300 | } | |
301 | ||
302 | static void machine_get_phandle_start(Object *obj, Visitor *v, | |
d7bce999 EB |
303 | const char *name, void *opaque, |
304 | Error **errp) | |
6b1b1440 MA |
305 | { |
306 | MachineState *ms = MACHINE(obj); | |
307 | int64_t value = ms->phandle_start; | |
308 | ||
51e72bc1 | 309 | visit_type_int(v, name, &value, errp); |
6b1b1440 MA |
310 | } |
311 | ||
312 | static void machine_set_phandle_start(Object *obj, Visitor *v, | |
d7bce999 EB |
313 | const char *name, void *opaque, |
314 | Error **errp) | |
6b1b1440 MA |
315 | { |
316 | MachineState *ms = MACHINE(obj); | |
6b1b1440 MA |
317 | int64_t value; |
318 | ||
668f62ec | 319 | if (!visit_type_int(v, name, &value, errp)) { |
6b1b1440 MA |
320 | return; |
321 | } | |
322 | ||
323 | ms->phandle_start = value; | |
324 | } | |
325 | ||
326 | static char *machine_get_dt_compatible(Object *obj, Error **errp) | |
327 | { | |
328 | MachineState *ms = MACHINE(obj); | |
329 | ||
330 | return g_strdup(ms->dt_compatible); | |
331 | } | |
332 | ||
333 | static void machine_set_dt_compatible(Object *obj, const char *value, Error **errp) | |
334 | { | |
335 | MachineState *ms = MACHINE(obj); | |
336 | ||
556068ee | 337 | g_free(ms->dt_compatible); |
6b1b1440 MA |
338 | ms->dt_compatible = g_strdup(value); |
339 | } | |
340 | ||
341 | static bool machine_get_dump_guest_core(Object *obj, Error **errp) | |
342 | { | |
343 | MachineState *ms = MACHINE(obj); | |
344 | ||
345 | return ms->dump_guest_core; | |
346 | } | |
347 | ||
348 | static void machine_set_dump_guest_core(Object *obj, bool value, Error **errp) | |
349 | { | |
350 | MachineState *ms = MACHINE(obj); | |
351 | ||
352 | ms->dump_guest_core = value; | |
353 | } | |
354 | ||
355 | static bool machine_get_mem_merge(Object *obj, Error **errp) | |
356 | { | |
357 | MachineState *ms = MACHINE(obj); | |
358 | ||
359 | return ms->mem_merge; | |
360 | } | |
361 | ||
362 | static void machine_set_mem_merge(Object *obj, bool value, Error **errp) | |
363 | { | |
364 | MachineState *ms = MACHINE(obj); | |
365 | ||
366 | ms->mem_merge = value; | |
367 | } | |
368 | ||
369 | static bool machine_get_usb(Object *obj, Error **errp) | |
370 | { | |
371 | MachineState *ms = MACHINE(obj); | |
372 | ||
373 | return ms->usb; | |
374 | } | |
375 | ||
376 | static void machine_set_usb(Object *obj, bool value, Error **errp) | |
377 | { | |
378 | MachineState *ms = MACHINE(obj); | |
379 | ||
380 | ms->usb = value; | |
c6e76503 | 381 | ms->usb_disabled = !value; |
6b1b1440 MA |
382 | } |
383 | ||
cfc58cf3 EH |
384 | static bool machine_get_graphics(Object *obj, Error **errp) |
385 | { | |
386 | MachineState *ms = MACHINE(obj); | |
387 | ||
388 | return ms->enable_graphics; | |
389 | } | |
390 | ||
391 | static void machine_set_graphics(Object *obj, bool value, Error **errp) | |
392 | { | |
393 | MachineState *ms = MACHINE(obj); | |
394 | ||
395 | ms->enable_graphics = value; | |
396 | } | |
397 | ||
6b1b1440 MA |
398 | static char *machine_get_firmware(Object *obj, Error **errp) |
399 | { | |
400 | MachineState *ms = MACHINE(obj); | |
401 | ||
402 | return g_strdup(ms->firmware); | |
403 | } | |
404 | ||
405 | static void machine_set_firmware(Object *obj, const char *value, Error **errp) | |
406 | { | |
407 | MachineState *ms = MACHINE(obj); | |
408 | ||
556068ee | 409 | g_free(ms->firmware); |
6b1b1440 MA |
410 | ms->firmware = g_strdup(value); |
411 | } | |
412 | ||
9850c604 AG |
413 | static void machine_set_suppress_vmdesc(Object *obj, bool value, Error **errp) |
414 | { | |
415 | MachineState *ms = MACHINE(obj); | |
416 | ||
417 | ms->suppress_vmdesc = value; | |
418 | } | |
419 | ||
420 | static bool machine_get_suppress_vmdesc(Object *obj, Error **errp) | |
421 | { | |
422 | MachineState *ms = MACHINE(obj); | |
423 | ||
424 | return ms->suppress_vmdesc; | |
425 | } | |
426 | ||
db588194 BS |
427 | static char *machine_get_memory_encryption(Object *obj, Error **errp) |
428 | { | |
429 | MachineState *ms = MACHINE(obj); | |
430 | ||
e0292d7c DG |
431 | if (ms->cgs) { |
432 | return g_strdup(object_get_canonical_path_component(OBJECT(ms->cgs))); | |
433 | } | |
434 | ||
435 | return NULL; | |
db588194 BS |
436 | } |
437 | ||
438 | static void machine_set_memory_encryption(Object *obj, const char *value, | |
439 | Error **errp) | |
440 | { | |
e0292d7c DG |
441 | Object *cgs = |
442 | object_resolve_path_component(object_get_objects_root(), value); | |
443 | ||
444 | if (!cgs) { | |
445 | error_setg(errp, "No such memory encryption object '%s'", value); | |
446 | return; | |
447 | } | |
db588194 | 448 | |
e0292d7c DG |
449 | object_property_set_link(obj, "confidential-guest-support", cgs, errp); |
450 | } | |
451 | ||
452 | static void machine_check_confidential_guest_support(const Object *obj, | |
453 | const char *name, | |
454 | Object *new_target, | |
455 | Error **errp) | |
456 | { | |
457 | /* | |
458 | * So far the only constraint is that the target has the | |
459 | * TYPE_CONFIDENTIAL_GUEST_SUPPORT interface, and that's checked | |
460 | * by the QOM core | |
461 | */ | |
db588194 BS |
462 | } |
463 | ||
f6a0d06b EA |
464 | static bool machine_get_nvdimm(Object *obj, Error **errp) |
465 | { | |
466 | MachineState *ms = MACHINE(obj); | |
467 | ||
468 | return ms->nvdimms_state->is_enabled; | |
469 | } | |
470 | ||
471 | static void machine_set_nvdimm(Object *obj, bool value, Error **errp) | |
472 | { | |
473 | MachineState *ms = MACHINE(obj); | |
474 | ||
475 | ms->nvdimms_state->is_enabled = value; | |
476 | } | |
477 | ||
244b3f44 TX |
478 | static bool machine_get_hmat(Object *obj, Error **errp) |
479 | { | |
480 | MachineState *ms = MACHINE(obj); | |
481 | ||
482 | return ms->numa_state->hmat_enabled; | |
483 | } | |
484 | ||
485 | static void machine_set_hmat(Object *obj, bool value, Error **errp) | |
486 | { | |
487 | MachineState *ms = MACHINE(obj); | |
488 | ||
489 | ms->numa_state->hmat_enabled = value; | |
490 | } | |
491 | ||
f6a0d06b EA |
492 | static char *machine_get_nvdimm_persistence(Object *obj, Error **errp) |
493 | { | |
494 | MachineState *ms = MACHINE(obj); | |
495 | ||
496 | return g_strdup(ms->nvdimms_state->persistence_string); | |
497 | } | |
498 | ||
499 | static void machine_set_nvdimm_persistence(Object *obj, const char *value, | |
500 | Error **errp) | |
501 | { | |
502 | MachineState *ms = MACHINE(obj); | |
503 | NVDIMMState *nvdimms_state = ms->nvdimms_state; | |
504 | ||
505 | if (strcmp(value, "cpu") == 0) { | |
506 | nvdimms_state->persistence = 3; | |
507 | } else if (strcmp(value, "mem-ctrl") == 0) { | |
508 | nvdimms_state->persistence = 2; | |
509 | } else { | |
510 | error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option", | |
511 | value); | |
512 | return; | |
513 | } | |
514 | ||
515 | g_free(nvdimms_state->persistence_string); | |
516 | nvdimms_state->persistence_string = g_strdup(value); | |
517 | } | |
518 | ||
0bd1909d | 519 | void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type) |
33cd52b5 | 520 | { |
54aa3de7 | 521 | QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type)); |
33cd52b5 AG |
522 | } |
523 | ||
0bd1909d | 524 | static void validate_sysbus_device(SysBusDevice *sbdev, void *opaque) |
33cd52b5 | 525 | { |
0bd1909d EH |
526 | MachineState *machine = opaque; |
527 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
528 | bool allowed = false; | |
529 | strList *wl; | |
33cd52b5 | 530 | |
0bd1909d EH |
531 | for (wl = mc->allowed_dynamic_sysbus_devices; |
532 | !allowed && wl; | |
533 | wl = wl->next) { | |
534 | allowed |= !!object_dynamic_cast(OBJECT(sbdev), wl->value); | |
535 | } | |
536 | ||
537 | if (!allowed) { | |
538 | error_report("Option '-device %s' cannot be handled by this machine", | |
539 | object_class_get_name(object_get_class(OBJECT(sbdev)))); | |
540 | exit(1); | |
33cd52b5 | 541 | } |
0bd1909d EH |
542 | } |
543 | ||
aa8b1839 IM |
544 | static char *machine_get_memdev(Object *obj, Error **errp) |
545 | { | |
546 | MachineState *ms = MACHINE(obj); | |
547 | ||
548 | return g_strdup(ms->ram_memdev_id); | |
549 | } | |
550 | ||
551 | static void machine_set_memdev(Object *obj, const char *value, Error **errp) | |
552 | { | |
553 | MachineState *ms = MACHINE(obj); | |
554 | ||
555 | g_free(ms->ram_memdev_id); | |
556 | ms->ram_memdev_id = g_strdup(value); | |
557 | } | |
558 | ||
559 | ||
0bd1909d EH |
560 | static void machine_init_notify(Notifier *notifier, void *data) |
561 | { | |
562 | MachineState *machine = MACHINE(qdev_get_machine()); | |
33cd52b5 AG |
563 | |
564 | /* | |
0bd1909d EH |
565 | * Loop through all dynamically created sysbus devices and check if they are |
566 | * all allowed. If a device is not allowed, error out. | |
33cd52b5 | 567 | */ |
0bd1909d | 568 | foreach_dynamic_sysbus_device(validate_sysbus_device, machine); |
33cd52b5 AG |
569 | } |
570 | ||
f2d672c2 IM |
571 | HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine) |
572 | { | |
573 | int i; | |
f2d672c2 | 574 | HotpluggableCPUList *head = NULL; |
d342eb76 IM |
575 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
576 | ||
577 | /* force board to initialize possible_cpus if it hasn't been done yet */ | |
578 | mc->possible_cpu_arch_ids(machine); | |
f2d672c2 | 579 | |
f2d672c2 | 580 | for (i = 0; i < machine->possible_cpus->len; i++) { |
d342eb76 | 581 | Object *cpu; |
f2d672c2 IM |
582 | HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1); |
583 | ||
d342eb76 | 584 | cpu_item->type = g_strdup(machine->possible_cpus->cpus[i].type); |
f2d672c2 IM |
585 | cpu_item->vcpus_count = machine->possible_cpus->cpus[i].vcpus_count; |
586 | cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props, | |
587 | sizeof(*cpu_item->props)); | |
588 | ||
589 | cpu = machine->possible_cpus->cpus[i].cpu; | |
590 | if (cpu) { | |
591 | cpu_item->has_qom_path = true; | |
592 | cpu_item->qom_path = object_get_canonical_path(cpu); | |
593 | } | |
54aa3de7 | 594 | QAPI_LIST_PREPEND(head, cpu_item); |
f2d672c2 IM |
595 | } |
596 | return head; | |
597 | } | |
598 | ||
7c88e65d IM |
599 | /** |
600 | * machine_set_cpu_numa_node: | |
601 | * @machine: machine object to modify | |
602 | * @props: specifies which cpu objects to assign to | |
603 | * numa node specified by @props.node_id | |
604 | * @errp: if an error occurs, a pointer to an area to store the error | |
605 | * | |
606 | * Associate NUMA node specified by @props.node_id with cpu slots that | |
607 | * match socket/core/thread-ids specified by @props. It's recommended to use | |
608 | * query-hotpluggable-cpus.props values to specify affected cpu slots, | |
609 | * which would lead to exact 1:1 mapping of cpu slots to NUMA node. | |
610 | * | |
611 | * However for CLI convenience it's possible to pass in subset of properties, | |
612 | * which would affect all cpu slots that match it. | |
613 | * Ex for pc machine: | |
614 | * -smp 4,cores=2,sockets=2 -numa node,nodeid=0 -numa node,nodeid=1 \ | |
615 | * -numa cpu,node-id=0,socket_id=0 \ | |
616 | * -numa cpu,node-id=1,socket_id=1 | |
617 | * will assign all child cores of socket 0 to node 0 and | |
618 | * of socket 1 to node 1. | |
619 | * | |
620 | * On attempt of reassigning (already assigned) cpu slot to another NUMA node, | |
621 | * return error. | |
622 | * Empty subset is disallowed and function will return with error in this case. | |
623 | */ | |
624 | void machine_set_cpu_numa_node(MachineState *machine, | |
625 | const CpuInstanceProperties *props, Error **errp) | |
626 | { | |
627 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
244b3f44 | 628 | NodeInfo *numa_info = machine->numa_state->nodes; |
7c88e65d IM |
629 | bool match = false; |
630 | int i; | |
631 | ||
632 | if (!mc->possible_cpu_arch_ids) { | |
633 | error_setg(errp, "mapping of CPUs to NUMA node is not supported"); | |
634 | return; | |
635 | } | |
636 | ||
637 | /* disabling node mapping is not supported, forbid it */ | |
638 | assert(props->has_node_id); | |
639 | ||
640 | /* force board to initialize possible_cpus if it hasn't been done yet */ | |
641 | mc->possible_cpu_arch_ids(machine); | |
642 | ||
643 | for (i = 0; i < machine->possible_cpus->len; i++) { | |
644 | CPUArchId *slot = &machine->possible_cpus->cpus[i]; | |
645 | ||
646 | /* reject unsupported by board properties */ | |
647 | if (props->has_thread_id && !slot->props.has_thread_id) { | |
648 | error_setg(errp, "thread-id is not supported"); | |
649 | return; | |
650 | } | |
651 | ||
652 | if (props->has_core_id && !slot->props.has_core_id) { | |
653 | error_setg(errp, "core-id is not supported"); | |
654 | return; | |
655 | } | |
656 | ||
657 | if (props->has_socket_id && !slot->props.has_socket_id) { | |
658 | error_setg(errp, "socket-id is not supported"); | |
659 | return; | |
660 | } | |
661 | ||
176d2cda LX |
662 | if (props->has_die_id && !slot->props.has_die_id) { |
663 | error_setg(errp, "die-id is not supported"); | |
664 | return; | |
665 | } | |
666 | ||
7c88e65d IM |
667 | /* skip slots with explicit mismatch */ |
668 | if (props->has_thread_id && props->thread_id != slot->props.thread_id) { | |
669 | continue; | |
670 | } | |
671 | ||
672 | if (props->has_core_id && props->core_id != slot->props.core_id) { | |
673 | continue; | |
674 | } | |
675 | ||
176d2cda LX |
676 | if (props->has_die_id && props->die_id != slot->props.die_id) { |
677 | continue; | |
678 | } | |
679 | ||
7c88e65d IM |
680 | if (props->has_socket_id && props->socket_id != slot->props.socket_id) { |
681 | continue; | |
682 | } | |
683 | ||
684 | /* reject assignment if slot is already assigned, for compatibility | |
685 | * of legacy cpu_index mapping with SPAPR core based mapping do not | |
686 | * error out if cpu thread and matched core have the same node-id */ | |
687 | if (slot->props.has_node_id && | |
688 | slot->props.node_id != props->node_id) { | |
689 | error_setg(errp, "CPU is already assigned to node-id: %" PRId64, | |
690 | slot->props.node_id); | |
691 | return; | |
692 | } | |
693 | ||
694 | /* assign slot to node as it's matched '-numa cpu' key */ | |
695 | match = true; | |
696 | slot->props.node_id = props->node_id; | |
697 | slot->props.has_node_id = props->has_node_id; | |
244b3f44 TX |
698 | |
699 | if (machine->numa_state->hmat_enabled) { | |
700 | if ((numa_info[props->node_id].initiator < MAX_NODES) && | |
701 | (props->node_id != numa_info[props->node_id].initiator)) { | |
702 | error_setg(errp, "The initiator of CPU NUMA node %" PRId64 | |
703 | " should be itself", props->node_id); | |
704 | return; | |
705 | } | |
706 | numa_info[props->node_id].has_cpu = true; | |
707 | numa_info[props->node_id].initiator = props->node_id; | |
708 | } | |
7c88e65d IM |
709 | } |
710 | ||
711 | if (!match) { | |
712 | error_setg(errp, "no match found"); | |
713 | } | |
714 | } | |
715 | ||
6f479566 LX |
716 | static void smp_parse(MachineState *ms, QemuOpts *opts) |
717 | { | |
718 | if (opts) { | |
719 | unsigned cpus = qemu_opt_get_number(opts, "cpus", 0); | |
720 | unsigned sockets = qemu_opt_get_number(opts, "sockets", 0); | |
721 | unsigned cores = qemu_opt_get_number(opts, "cores", 0); | |
722 | unsigned threads = qemu_opt_get_number(opts, "threads", 0); | |
723 | ||
724 | /* compute missing values, prefer sockets over cores over threads */ | |
725 | if (cpus == 0 || sockets == 0) { | |
726 | cores = cores > 0 ? cores : 1; | |
727 | threads = threads > 0 ? threads : 1; | |
728 | if (cpus == 0) { | |
729 | sockets = sockets > 0 ? sockets : 1; | |
730 | cpus = cores * threads * sockets; | |
731 | } else { | |
732 | ms->smp.max_cpus = | |
733 | qemu_opt_get_number(opts, "maxcpus", cpus); | |
734 | sockets = ms->smp.max_cpus / (cores * threads); | |
735 | } | |
736 | } else if (cores == 0) { | |
737 | threads = threads > 0 ? threads : 1; | |
738 | cores = cpus / (sockets * threads); | |
739 | cores = cores > 0 ? cores : 1; | |
740 | } else if (threads == 0) { | |
741 | threads = cpus / (cores * sockets); | |
742 | threads = threads > 0 ? threads : 1; | |
743 | } else if (sockets * cores * threads < cpus) { | |
744 | error_report("cpu topology: " | |
745 | "sockets (%u) * cores (%u) * threads (%u) < " | |
746 | "smp_cpus (%u)", | |
747 | sockets, cores, threads, cpus); | |
748 | exit(1); | |
749 | } | |
750 | ||
751 | ms->smp.max_cpus = | |
752 | qemu_opt_get_number(opts, "maxcpus", cpus); | |
753 | ||
754 | if (ms->smp.max_cpus < cpus) { | |
755 | error_report("maxcpus must be equal to or greater than smp"); | |
756 | exit(1); | |
757 | } | |
758 | ||
c4332cd1 IM |
759 | if (sockets * cores * threads != ms->smp.max_cpus) { |
760 | error_report("Invalid CPU topology: " | |
761 | "sockets (%u) * cores (%u) * threads (%u) " | |
762 | "!= maxcpus (%u)", | |
6f479566 LX |
763 | sockets, cores, threads, |
764 | ms->smp.max_cpus); | |
765 | exit(1); | |
766 | } | |
767 | ||
6f479566 LX |
768 | ms->smp.cpus = cpus; |
769 | ms->smp.cores = cores; | |
770 | ms->smp.threads = threads; | |
8cb30e3a | 771 | ms->smp.sockets = sockets; |
6f479566 LX |
772 | } |
773 | ||
774 | if (ms->smp.cpus > 1) { | |
775 | Error *blocker = NULL; | |
776 | error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp"); | |
777 | replay_add_blocker(blocker); | |
778 | } | |
779 | } | |
780 | ||
076b35b5 ND |
781 | static void machine_class_init(ObjectClass *oc, void *data) |
782 | { | |
783 | MachineClass *mc = MACHINE_CLASS(oc); | |
784 | ||
785 | /* Default 128 MB as guest ram size */ | |
d23b6caa | 786 | mc->default_ram_size = 128 * MiB; |
71ae9e94 | 787 | mc->rom_file_has_mr = true; |
6f479566 | 788 | mc->smp_parse = smp_parse; |
26b81df4 | 789 | |
55641213 LV |
790 | /* numa node memory size aligned on 8MB by default. |
791 | * On Linux, each node's border has to be 8MB aligned | |
792 | */ | |
793 | mc->numa_mem_align_shift = 23; | |
794 | ||
26b81df4 | 795 | object_class_property_add_str(oc, "kernel", |
d2623129 | 796 | machine_get_kernel, machine_set_kernel); |
26b81df4 | 797 | object_class_property_set_description(oc, "kernel", |
7eecec7d | 798 | "Linux kernel image file"); |
26b81df4 EH |
799 | |
800 | object_class_property_add_str(oc, "initrd", | |
d2623129 | 801 | machine_get_initrd, machine_set_initrd); |
26b81df4 | 802 | object_class_property_set_description(oc, "initrd", |
7eecec7d | 803 | "Linux initial ramdisk file"); |
26b81df4 EH |
804 | |
805 | object_class_property_add_str(oc, "append", | |
d2623129 | 806 | machine_get_append, machine_set_append); |
26b81df4 | 807 | object_class_property_set_description(oc, "append", |
7eecec7d | 808 | "Linux kernel command line"); |
26b81df4 EH |
809 | |
810 | object_class_property_add_str(oc, "dtb", | |
d2623129 | 811 | machine_get_dtb, machine_set_dtb); |
26b81df4 | 812 | object_class_property_set_description(oc, "dtb", |
7eecec7d | 813 | "Linux kernel device tree file"); |
26b81df4 EH |
814 | |
815 | object_class_property_add_str(oc, "dumpdtb", | |
d2623129 | 816 | machine_get_dumpdtb, machine_set_dumpdtb); |
26b81df4 | 817 | object_class_property_set_description(oc, "dumpdtb", |
7eecec7d | 818 | "Dump current dtb to a file and quit"); |
26b81df4 EH |
819 | |
820 | object_class_property_add(oc, "phandle-start", "int", | |
821 | machine_get_phandle_start, machine_set_phandle_start, | |
d2623129 | 822 | NULL, NULL); |
26b81df4 | 823 | object_class_property_set_description(oc, "phandle-start", |
7eecec7d | 824 | "The first phandle ID we may generate dynamically"); |
26b81df4 EH |
825 | |
826 | object_class_property_add_str(oc, "dt-compatible", | |
d2623129 | 827 | machine_get_dt_compatible, machine_set_dt_compatible); |
26b81df4 | 828 | object_class_property_set_description(oc, "dt-compatible", |
7eecec7d | 829 | "Overrides the \"compatible\" property of the dt root node"); |
26b81df4 EH |
830 | |
831 | object_class_property_add_bool(oc, "dump-guest-core", | |
d2623129 | 832 | machine_get_dump_guest_core, machine_set_dump_guest_core); |
26b81df4 | 833 | object_class_property_set_description(oc, "dump-guest-core", |
7eecec7d | 834 | "Include guest memory in a core dump"); |
26b81df4 EH |
835 | |
836 | object_class_property_add_bool(oc, "mem-merge", | |
d2623129 | 837 | machine_get_mem_merge, machine_set_mem_merge); |
26b81df4 | 838 | object_class_property_set_description(oc, "mem-merge", |
7eecec7d | 839 | "Enable/disable memory merge support"); |
26b81df4 EH |
840 | |
841 | object_class_property_add_bool(oc, "usb", | |
d2623129 | 842 | machine_get_usb, machine_set_usb); |
26b81df4 | 843 | object_class_property_set_description(oc, "usb", |
7eecec7d | 844 | "Set on/off to enable/disable usb"); |
26b81df4 EH |
845 | |
846 | object_class_property_add_bool(oc, "graphics", | |
d2623129 | 847 | machine_get_graphics, machine_set_graphics); |
26b81df4 | 848 | object_class_property_set_description(oc, "graphics", |
7eecec7d | 849 | "Set on/off to enable/disable graphics emulation"); |
26b81df4 | 850 | |
26b81df4 | 851 | object_class_property_add_str(oc, "firmware", |
d2623129 | 852 | machine_get_firmware, machine_set_firmware); |
26b81df4 | 853 | object_class_property_set_description(oc, "firmware", |
7eecec7d | 854 | "Firmware image"); |
26b81df4 EH |
855 | |
856 | object_class_property_add_bool(oc, "suppress-vmdesc", | |
d2623129 | 857 | machine_get_suppress_vmdesc, machine_set_suppress_vmdesc); |
26b81df4 | 858 | object_class_property_set_description(oc, "suppress-vmdesc", |
7eecec7d | 859 | "Set on to disable self-describing migration"); |
26b81df4 | 860 | |
e0292d7c DG |
861 | object_class_property_add_link(oc, "confidential-guest-support", |
862 | TYPE_CONFIDENTIAL_GUEST_SUPPORT, | |
863 | offsetof(MachineState, cgs), | |
864 | machine_check_confidential_guest_support, | |
865 | OBJ_PROP_LINK_STRONG); | |
866 | object_class_property_set_description(oc, "confidential-guest-support", | |
867 | "Set confidential guest scheme to support"); | |
868 | ||
869 | /* For compatibility */ | |
db588194 | 870 | object_class_property_add_str(oc, "memory-encryption", |
d2623129 | 871 | machine_get_memory_encryption, machine_set_memory_encryption); |
db588194 | 872 | object_class_property_set_description(oc, "memory-encryption", |
7eecec7d | 873 | "Set memory encryption object to use"); |
acd5b054 EH |
874 | |
875 | object_class_property_add_str(oc, "memory-backend", | |
876 | machine_get_memdev, machine_set_memdev); | |
877 | object_class_property_set_description(oc, "memory-backend", | |
878 | "Set RAM backend" | |
879 | "Valid value is ID of hostmem based backend"); | |
076b35b5 ND |
880 | } |
881 | ||
dcb3d601 EH |
882 | static void machine_class_base_init(ObjectClass *oc, void *data) |
883 | { | |
2c920e45 PB |
884 | MachineClass *mc = MACHINE_CLASS(oc); |
885 | mc->max_cpus = mc->max_cpus ?: 1; | |
886 | mc->min_cpus = mc->min_cpus ?: 1; | |
887 | mc->default_cpus = mc->default_cpus ?: 1; | |
888 | ||
dcb3d601 EH |
889 | if (!object_class_is_abstract(oc)) { |
890 | const char *cname = object_class_get_name(oc); | |
891 | assert(g_str_has_suffix(cname, TYPE_MACHINE_SUFFIX)); | |
98cec76a EH |
892 | mc->name = g_strndup(cname, |
893 | strlen(cname) - strlen(TYPE_MACHINE_SUFFIX)); | |
b66bbee3 | 894 | mc->compat_props = g_ptr_array_new(); |
dcb3d601 EH |
895 | } |
896 | } | |
897 | ||
6b1b1440 MA |
898 | static void machine_initfn(Object *obj) |
899 | { | |
33cd52b5 | 900 | MachineState *ms = MACHINE(obj); |
b2fc91db | 901 | MachineClass *mc = MACHINE_GET_CLASS(obj); |
33cd52b5 | 902 | |
e0d17dfd PB |
903 | container_get(obj, "/peripheral"); |
904 | container_get(obj, "/peripheral-anon"); | |
905 | ||
47c8ca53 | 906 | ms->dump_guest_core = true; |
75cc7f01 | 907 | ms->mem_merge = true; |
cfc58cf3 | 908 | ms->enable_graphics = true; |
58c91595 | 909 | ms->kernel_cmdline = g_strdup(""); |
d8870d02 | 910 | |
f6a0d06b EA |
911 | if (mc->nvdimm_supported) { |
912 | Object *obj = OBJECT(ms); | |
913 | ||
914 | ms->nvdimms_state = g_new0(NVDIMMState, 1); | |
915 | object_property_add_bool(obj, "nvdimm", | |
d2623129 | 916 | machine_get_nvdimm, machine_set_nvdimm); |
f6a0d06b EA |
917 | object_property_set_description(obj, "nvdimm", |
918 | "Set on/off to enable/disable " | |
7eecec7d | 919 | "NVDIMM instantiation"); |
f6a0d06b EA |
920 | |
921 | object_property_add_str(obj, "nvdimm-persistence", | |
922 | machine_get_nvdimm_persistence, | |
d2623129 | 923 | machine_set_nvdimm_persistence); |
f6a0d06b EA |
924 | object_property_set_description(obj, "nvdimm-persistence", |
925 | "Set NVDIMM persistence" | |
7eecec7d | 926 | "Valid values are cpu, mem-ctrl"); |
f6a0d06b EA |
927 | } |
928 | ||
fcd3f2cc | 929 | if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) { |
aa570207 | 930 | ms->numa_state = g_new0(NumaState, 1); |
244b3f44 | 931 | object_property_add_bool(obj, "hmat", |
d2623129 | 932 | machine_get_hmat, machine_set_hmat); |
244b3f44 TX |
933 | object_property_set_description(obj, "hmat", |
934 | "Set on/off to enable/disable " | |
935 | "ACPI Heterogeneous Memory Attribute " | |
7eecec7d | 936 | "Table (HMAT)"); |
aa570207 | 937 | } |
f6a0d06b | 938 | |
33cd52b5 AG |
939 | /* Register notifier when init is done for sysbus sanity checks */ |
940 | ms->sysbus_notifier.notify = machine_init_notify; | |
941 | qemu_add_machine_init_done_notifier(&ms->sysbus_notifier); | |
8b0e484c PB |
942 | |
943 | /* default to mc->default_cpus */ | |
944 | ms->smp.cpus = mc->default_cpus; | |
945 | ms->smp.max_cpus = mc->default_cpus; | |
946 | ms->smp.cores = 1; | |
947 | ms->smp.threads = 1; | |
948 | ms->smp.sockets = 1; | |
6b1b1440 MA |
949 | } |
950 | ||
951 | static void machine_finalize(Object *obj) | |
952 | { | |
953 | MachineState *ms = MACHINE(obj); | |
954 | ||
6b1b1440 MA |
955 | g_free(ms->kernel_filename); |
956 | g_free(ms->initrd_filename); | |
957 | g_free(ms->kernel_cmdline); | |
958 | g_free(ms->dtb); | |
959 | g_free(ms->dumpdtb); | |
960 | g_free(ms->dt_compatible); | |
961 | g_free(ms->firmware); | |
2ff4f67c | 962 | g_free(ms->device_memory); |
f6a0d06b | 963 | g_free(ms->nvdimms_state); |
aa570207 | 964 | g_free(ms->numa_state); |
6b1b1440 | 965 | } |
36d20cb2 | 966 | |
5e97b623 MA |
967 | bool machine_usb(MachineState *machine) |
968 | { | |
969 | return machine->usb; | |
970 | } | |
971 | ||
6cabe7fa MA |
972 | int machine_phandle_start(MachineState *machine) |
973 | { | |
974 | return machine->phandle_start; | |
975 | } | |
976 | ||
47c8ca53 MA |
977 | bool machine_dump_guest_core(MachineState *machine) |
978 | { | |
979 | return machine->dump_guest_core; | |
980 | } | |
981 | ||
75cc7f01 MA |
982 | bool machine_mem_merge(MachineState *machine) |
983 | { | |
984 | return machine->mem_merge; | |
985 | } | |
986 | ||
ec78f811 IM |
987 | static char *cpu_slot_to_string(const CPUArchId *cpu) |
988 | { | |
989 | GString *s = g_string_new(NULL); | |
990 | if (cpu->props.has_socket_id) { | |
991 | g_string_append_printf(s, "socket-id: %"PRId64, cpu->props.socket_id); | |
992 | } | |
176d2cda LX |
993 | if (cpu->props.has_die_id) { |
994 | g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); | |
995 | } | |
ec78f811 IM |
996 | if (cpu->props.has_core_id) { |
997 | if (s->len) { | |
998 | g_string_append_printf(s, ", "); | |
999 | } | |
1000 | g_string_append_printf(s, "core-id: %"PRId64, cpu->props.core_id); | |
1001 | } | |
1002 | if (cpu->props.has_thread_id) { | |
1003 | if (s->len) { | |
1004 | g_string_append_printf(s, ", "); | |
1005 | } | |
1006 | g_string_append_printf(s, "thread-id: %"PRId64, cpu->props.thread_id); | |
1007 | } | |
1008 | return g_string_free(s, false); | |
1009 | } | |
1010 | ||
244b3f44 TX |
1011 | static void numa_validate_initiator(NumaState *numa_state) |
1012 | { | |
1013 | int i; | |
1014 | NodeInfo *numa_info = numa_state->nodes; | |
1015 | ||
1016 | for (i = 0; i < numa_state->num_nodes; i++) { | |
1017 | if (numa_info[i].initiator == MAX_NODES) { | |
1018 | error_report("The initiator of NUMA node %d is missing, use " | |
1019 | "'-numa node,initiator' option to declare it", i); | |
1020 | exit(1); | |
1021 | } | |
1022 | ||
1023 | if (!numa_info[numa_info[i].initiator].present) { | |
1024 | error_report("NUMA node %" PRIu16 " is missing, use " | |
1025 | "'-numa node' option to declare it first", | |
1026 | numa_info[i].initiator); | |
1027 | exit(1); | |
1028 | } | |
1029 | ||
1030 | if (!numa_info[numa_info[i].initiator].has_cpu) { | |
1031 | error_report("The initiator of NUMA node %d is invalid", i); | |
1032 | exit(1); | |
1033 | } | |
1034 | } | |
1035 | } | |
1036 | ||
7a3099fc | 1037 | static void machine_numa_finish_cpu_init(MachineState *machine) |
ec78f811 IM |
1038 | { |
1039 | int i; | |
60bed6a3 | 1040 | bool default_mapping; |
ec78f811 IM |
1041 | GString *s = g_string_new(NULL); |
1042 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
1043 | const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(machine); | |
1044 | ||
aa570207 | 1045 | assert(machine->numa_state->num_nodes); |
60bed6a3 IM |
1046 | for (i = 0; i < possible_cpus->len; i++) { |
1047 | if (possible_cpus->cpus[i].props.has_node_id) { | |
1048 | break; | |
1049 | } | |
1050 | } | |
1051 | default_mapping = (i == possible_cpus->len); | |
1052 | ||
ec78f811 IM |
1053 | for (i = 0; i < possible_cpus->len; i++) { |
1054 | const CPUArchId *cpu_slot = &possible_cpus->cpus[i]; | |
1055 | ||
ec78f811 | 1056 | if (!cpu_slot->props.has_node_id) { |
d41f3e75 IM |
1057 | /* fetch default mapping from board and enable it */ |
1058 | CpuInstanceProperties props = cpu_slot->props; | |
1059 | ||
79e07936 | 1060 | props.node_id = mc->get_default_cpu_node_id(machine, i); |
d41f3e75 | 1061 | if (!default_mapping) { |
60bed6a3 IM |
1062 | /* record slots with not set mapping, |
1063 | * TODO: make it hard error in future */ | |
1064 | char *cpu_str = cpu_slot_to_string(cpu_slot); | |
1065 | g_string_append_printf(s, "%sCPU %d [%s]", | |
1066 | s->len ? ", " : "", i, cpu_str); | |
1067 | g_free(cpu_str); | |
d41f3e75 IM |
1068 | |
1069 | /* non mapped cpus used to fallback to node 0 */ | |
1070 | props.node_id = 0; | |
60bed6a3 | 1071 | } |
d41f3e75 IM |
1072 | |
1073 | props.has_node_id = true; | |
1074 | machine_set_cpu_numa_node(machine, &props, &error_fatal); | |
ec78f811 IM |
1075 | } |
1076 | } | |
244b3f44 TX |
1077 | |
1078 | if (machine->numa_state->hmat_enabled) { | |
1079 | numa_validate_initiator(machine->numa_state); | |
1080 | } | |
1081 | ||
c6ff347c | 1082 | if (s->len && !qtest_enabled()) { |
3dc6f869 AF |
1083 | warn_report("CPU(s) not present in any NUMA nodes: %s", |
1084 | s->str); | |
1085 | warn_report("All CPU(s) up to maxcpus should be described " | |
1086 | "in NUMA config, ability to start up with partial NUMA " | |
1087 | "mappings is obsoleted and will be removed in future"); | |
ec78f811 IM |
1088 | } |
1089 | g_string_free(s, true); | |
1090 | } | |
1091 | ||
82b911aa IM |
1092 | MemoryRegion *machine_consume_memdev(MachineState *machine, |
1093 | HostMemoryBackend *backend) | |
1094 | { | |
1095 | MemoryRegion *ret = host_memory_backend_get_memory(backend); | |
1096 | ||
1097 | if (memory_region_is_mapped(ret)) { | |
7a309cc9 MA |
1098 | error_report("memory backend %s can't be used multiple times.", |
1099 | object_get_canonical_path_component(OBJECT(backend))); | |
82b911aa IM |
1100 | exit(EXIT_FAILURE); |
1101 | } | |
1102 | host_memory_backend_set_mapped(backend, true); | |
1103 | vmstate_register_ram_global(ret); | |
1104 | return ret; | |
1105 | } | |
1106 | ||
3df8c4f3 PB |
1107 | bool machine_smp_parse(MachineState *ms, QemuOpts *opts, Error **errp) |
1108 | { | |
1109 | MachineClass *mc = MACHINE_GET_CLASS(ms); | |
1110 | ||
1111 | mc->smp_parse(ms, opts); | |
1112 | ||
1113 | /* sanity-check smp_cpus and max_cpus against mc */ | |
1114 | if (ms->smp.cpus < mc->min_cpus) { | |
1115 | error_setg(errp, "Invalid SMP CPUs %d. The min CPUs " | |
1116 | "supported by machine '%s' is %d", | |
1117 | ms->smp.cpus, | |
1118 | mc->name, mc->min_cpus); | |
1119 | return false; | |
1120 | } else if (ms->smp.max_cpus > mc->max_cpus) { | |
1121 | error_setg(errp, "Invalid SMP CPUs %d. The max CPUs " | |
1122 | "supported by machine '%s' is %d", | |
1123 | current_machine->smp.max_cpus, | |
1124 | mc->name, mc->max_cpus); | |
1125 | return false; | |
1126 | } | |
1127 | return true; | |
1128 | } | |
1129 | ||
482dfe9a IM |
1130 | void machine_run_board_init(MachineState *machine) |
1131 | { | |
1132 | MachineClass *machine_class = MACHINE_GET_CLASS(machine); | |
61ad65d0 RH |
1133 | ObjectClass *oc = object_class_by_name(machine->cpu_type); |
1134 | CPUClass *cc; | |
ec78f811 | 1135 | |
a3ef9bfb PB |
1136 | /* This checkpoint is required by replay to separate prior clock |
1137 | reading from the other reads, because timer polling functions query | |
1138 | clock values from the log. */ | |
1139 | replay_checkpoint(CHECKPOINT_INIT); | |
1140 | ||
82b911aa IM |
1141 | if (machine->ram_memdev_id) { |
1142 | Object *o; | |
1143 | o = object_resolve_path_type(machine->ram_memdev_id, | |
1144 | TYPE_MEMORY_BACKEND, NULL); | |
1145 | machine->ram = machine_consume_memdev(machine, MEMORY_BACKEND(o)); | |
1146 | } | |
1147 | ||
fcd3f2cc | 1148 | if (machine->numa_state) { |
aa570207 TX |
1149 | numa_complete_configuration(machine); |
1150 | if (machine->numa_state->num_nodes) { | |
1151 | machine_numa_finish_cpu_init(machine); | |
1152 | } | |
3aeaac8f | 1153 | } |
c9cf636d AF |
1154 | |
1155 | /* If the machine supports the valid_cpu_types check and the user | |
1156 | * specified a CPU with -cpu check here that the user CPU is supported. | |
1157 | */ | |
1158 | if (machine_class->valid_cpu_types && machine->cpu_type) { | |
c9cf636d AF |
1159 | int i; |
1160 | ||
1161 | for (i = 0; machine_class->valid_cpu_types[i]; i++) { | |
61ad65d0 | 1162 | if (object_class_dynamic_cast(oc, |
c9cf636d AF |
1163 | machine_class->valid_cpu_types[i])) { |
1164 | /* The user specificed CPU is in the valid field, we are | |
1165 | * good to go. | |
1166 | */ | |
1167 | break; | |
1168 | } | |
1169 | } | |
1170 | ||
1171 | if (!machine_class->valid_cpu_types[i]) { | |
1172 | /* The user specified CPU is not valid */ | |
1173 | error_report("Invalid CPU type: %s", machine->cpu_type); | |
1174 | error_printf("The valid types are: %s", | |
1175 | machine_class->valid_cpu_types[0]); | |
1176 | for (i = 1; machine_class->valid_cpu_types[i]; i++) { | |
1177 | error_printf(", %s", machine_class->valid_cpu_types[i]); | |
1178 | } | |
1179 | error_printf("\n"); | |
1180 | ||
1181 | exit(1); | |
1182 | } | |
1183 | } | |
1184 | ||
61ad65d0 RH |
1185 | /* Check if CPU type is deprecated and warn if so */ |
1186 | cc = CPU_CLASS(oc); | |
1187 | if (cc && cc->deprecation_note) { | |
1188 | warn_report("CPU model %s is deprecated -- %s", machine->cpu_type, | |
1189 | cc->deprecation_note); | |
1190 | } | |
1191 | ||
e0292d7c | 1192 | if (machine->cgs) { |
6e6a6ca7 | 1193 | /* |
e0292d7c | 1194 | * With confidential guests, the host can't see the real |
6e6a6ca7 DG |
1195 | * contents of RAM, so there's no point in it trying to merge |
1196 | * areas. | |
1197 | */ | |
1198 | machine_set_mem_merge(OBJECT(machine), false, &error_abort); | |
1199 | } | |
1200 | ||
482dfe9a | 1201 | machine_class->init(machine); |
2f181fbd | 1202 | phase_advance(PHASE_MACHINE_INITIALIZED); |
482dfe9a IM |
1203 | } |
1204 | ||
6b21670c PB |
1205 | static NotifierList machine_init_done_notifiers = |
1206 | NOTIFIER_LIST_INITIALIZER(machine_init_done_notifiers); | |
1207 | ||
6b21670c PB |
1208 | void qemu_add_machine_init_done_notifier(Notifier *notify) |
1209 | { | |
1210 | notifier_list_add(&machine_init_done_notifiers, notify); | |
2f181fbd | 1211 | if (phase_check(PHASE_MACHINE_READY)) { |
6b21670c PB |
1212 | notify->notify(notify, NULL); |
1213 | } | |
1214 | } | |
1215 | ||
1216 | void qemu_remove_machine_init_done_notifier(Notifier *notify) | |
1217 | { | |
1218 | notifier_remove(notify); | |
1219 | } | |
1220 | ||
f66dc873 | 1221 | void qdev_machine_creation_done(void) |
6b21670c | 1222 | { |
f66dc873 PB |
1223 | cpu_synchronize_all_post_init(); |
1224 | ||
1225 | if (current_machine->boot_once) { | |
1226 | qemu_boot_set(current_machine->boot_once, &error_fatal); | |
1227 | qemu_register_reset(restore_boot_order, g_strdup(current_machine->boot_order)); | |
1228 | } | |
1229 | ||
1230 | /* | |
1231 | * ok, initial machine setup is done, starting from now we can | |
1232 | * only create hotpluggable devices | |
1233 | */ | |
2f181fbd | 1234 | phase_advance(PHASE_MACHINE_READY); |
f66dc873 PB |
1235 | qdev_assert_realized_properly(); |
1236 | ||
1237 | /* TODO: once all bus devices are qdevified, this should be done | |
1238 | * when bus is created by qdev.c */ | |
1239 | /* | |
1240 | * TODO: If we had a main 'reset container' that the whole system | |
1241 | * lived in, we could reset that using the multi-phase reset | |
1242 | * APIs. For the moment, we just reset the sysbus, which will cause | |
1243 | * all devices hanging off it (and all their child buses, recursively) | |
1244 | * to be reset. Note that this will *not* reset any Device objects | |
1245 | * which are not attached to some part of the qbus tree! | |
1246 | */ | |
1247 | qemu_register_reset(resettable_cold_reset_fn, sysbus_get_default()); | |
1248 | ||
6b21670c | 1249 | notifier_list_notify(&machine_init_done_notifiers, NULL); |
f66dc873 PB |
1250 | |
1251 | if (rom_check_and_register_reset() != 0) { | |
f66dc873 PB |
1252 | exit(1); |
1253 | } | |
1254 | ||
1255 | replay_start(); | |
1256 | ||
1257 | /* This checkpoint is required by replay to separate prior clock | |
1258 | reading from the other reads, because timer polling functions query | |
1259 | clock values from the log. */ | |
1260 | replay_checkpoint(CHECKPOINT_RESET); | |
1261 | qemu_system_reset(SHUTDOWN_CAUSE_NONE); | |
1262 | register_global_state(); | |
6b21670c PB |
1263 | } |
1264 | ||
36d20cb2 MA |
1265 | static const TypeInfo machine_info = { |
1266 | .name = TYPE_MACHINE, | |
1267 | .parent = TYPE_OBJECT, | |
1268 | .abstract = true, | |
1269 | .class_size = sizeof(MachineClass), | |
076b35b5 | 1270 | .class_init = machine_class_init, |
dcb3d601 | 1271 | .class_base_init = machine_class_base_init, |
36d20cb2 | 1272 | .instance_size = sizeof(MachineState), |
6b1b1440 MA |
1273 | .instance_init = machine_initfn, |
1274 | .instance_finalize = machine_finalize, | |
36d20cb2 MA |
1275 | }; |
1276 | ||
1277 | static void machine_register_types(void) | |
1278 | { | |
1279 | type_register_static(&machine_info); | |
1280 | } | |
1281 | ||
1282 | type_init(machine_register_types) |