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Commit | Line | Data |
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36d20cb2 MA |
1 | /* |
2 | * QEMU Machine | |
3 | * | |
4 | * Copyright (C) 2014 Red Hat Inc | |
5 | * | |
6 | * Authors: | |
7 | * Marcel Apfelbaum <marcel.a@redhat.com> | |
8 | * | |
9 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
10 | * See the COPYING file in the top-level directory. | |
11 | */ | |
12 | ||
18c86e2b | 13 | #include "qemu/osdep.h" |
6f479566 LX |
14 | #include "qemu/option.h" |
15 | #include "qapi/qmp/qerror.h" | |
16 | #include "sysemu/replay.h" | |
fc6b3cf9 | 17 | #include "qemu/units.h" |
36d20cb2 | 18 | #include "hw/boards.h" |
f66dc873 | 19 | #include "hw/loader.h" |
da34e65c | 20 | #include "qapi/error.h" |
9af23989 | 21 | #include "qapi/qapi-visit-common.h" |
6b1b1440 | 22 | #include "qapi/visitor.h" |
33cd52b5 | 23 | #include "hw/sysbus.h" |
f66dc873 | 24 | #include "sysemu/cpus.h" |
33cd52b5 | 25 | #include "sysemu/sysemu.h" |
f66dc873 PB |
26 | #include "sysemu/reset.h" |
27 | #include "sysemu/runstate.h" | |
3bfe5716 | 28 | #include "sysemu/numa.h" |
33cd52b5 | 29 | #include "qemu/error-report.h" |
c6ff347c | 30 | #include "sysemu/qtest.h" |
edc24ccd | 31 | #include "hw/pci/pci.h" |
f6a0d06b | 32 | #include "hw/mem/nvdimm.h" |
f66dc873 | 33 | #include "migration/global_state.h" |
82b911aa | 34 | #include "migration/vmstate.h" |
6b1b1440 | 35 | |
576a00bd CH |
36 | GlobalProperty hw_compat_5_2[] = {}; |
37 | const size_t hw_compat_5_2_len = G_N_ELEMENTS(hw_compat_5_2); | |
38 | ||
6a558822 SH |
39 | GlobalProperty hw_compat_5_1[] = { |
40 | { "vhost-scsi", "num_queues", "1"}, | |
a4eef071 | 41 | { "vhost-user-blk", "num-queues", "1"}, |
6a558822 | 42 | { "vhost-user-scsi", "num_queues", "1"}, |
9445e1e1 | 43 | { "virtio-blk-device", "num-queues", "1"}, |
6a558822 | 44 | { "virtio-scsi-device", "num_queues", "1"}, |
6eb7a071 | 45 | { "nvme", "use-intel-id", "on"}, |
b1b0393c | 46 | { "pvpanic", "events", "1"}, /* PVPANIC_PANICKED */ |
6a558822 | 47 | }; |
3ff3c5d3 CH |
48 | const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1); |
49 | ||
7483cbba | 50 | GlobalProperty hw_compat_5_0[] = { |
2ebc2121 | 51 | { "pci-host-bridge", "x-config-reg-migration-enabled", "off" }, |
7483cbba | 52 | { "virtio-balloon-device", "page-poison", "false" }, |
f983ff95 PB |
53 | { "vmport", "x-read-set-eax", "off" }, |
54 | { "vmport", "x-signal-unsupported-cmd", "off" }, | |
55 | { "vmport", "x-report-vmx-type", "off" }, | |
56 | { "vmport", "x-cmds-v2", "off" }, | |
d55f5182 | 57 | { "virtio-device", "x-disable-legacy-check", "true" }, |
7483cbba | 58 | }; |
541aaa1d CH |
59 | const size_t hw_compat_5_0_len = G_N_ELEMENTS(hw_compat_5_0); |
60 | ||
5f258577 | 61 | GlobalProperty hw_compat_4_2[] = { |
c9b7d9ec DP |
62 | { "virtio-blk-device", "queue-size", "128"}, |
63 | { "virtio-scsi-device", "virtqueue_size", "128"}, | |
5f258577 | 64 | { "virtio-blk-device", "x-enable-wce-if-config-wce", "off" }, |
1bf8a989 DP |
65 | { "virtio-blk-device", "seg-max-adjust", "off"}, |
66 | { "virtio-scsi-device", "seg_max_adjust", "off"}, | |
67 | { "vhost-blk-device", "seg_max_adjust", "off"}, | |
7bacaf5f | 68 | { "usb-host", "suppress-remote-wake", "off" }, |
32187f3d | 69 | { "usb-redir", "suppress-remote-wake", "off" }, |
ed71c09f GH |
70 | { "qxl", "revision", "4" }, |
71 | { "qxl-vga", "revision", "4" }, | |
394f0f72 | 72 | { "fw_cfg", "acpi-mr-restore", "false" }, |
c126b4c5 | 73 | { "virtio-device", "use-disabled-flag", "false" }, |
5f258577 EY |
74 | }; |
75 | const size_t hw_compat_4_2_len = G_N_ELEMENTS(hw_compat_4_2); | |
76 | ||
eb1556c4 JS |
77 | GlobalProperty hw_compat_4_1[] = { |
78 | { "virtio-pci", "x-pcie-flr-init", "off" }, | |
79 | }; | |
9aec2e52 CH |
80 | const size_t hw_compat_4_1_len = G_N_ELEMENTS(hw_compat_4_1); |
81 | ||
8e8cbed0 | 82 | GlobalProperty hw_compat_4_0[] = { |
0a719662 GH |
83 | { "VGA", "edid", "false" }, |
84 | { "secondary-vga", "edid", "false" }, | |
85 | { "bochs-display", "edid", "false" }, | |
86 | { "virtio-vga", "edid", "false" }, | |
02501fc3 | 87 | { "virtio-gpu-device", "edid", "false" }, |
e57f2c31 | 88 | { "virtio-device", "use-started", "false" }, |
2bbadb08 | 89 | { "virtio-balloon-device", "qemu-4-0-config-size", "true" }, |
032cfe6a | 90 | { "pl031", "migrate-tick-offset", "false" }, |
0a719662 | 91 | }; |
9bf2650b CH |
92 | const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0); |
93 | ||
abd93cc7 | 94 | GlobalProperty hw_compat_3_1[] = { |
6c36bddf EH |
95 | { "pcie-root-port", "x-speed", "2_5" }, |
96 | { "pcie-root-port", "x-width", "1" }, | |
97 | { "memory-backend-file", "x-use-canonical-path-for-ramblock-id", "true" }, | |
98 | { "memory-backend-memfd", "x-use-canonical-path-for-ramblock-id", "true" }, | |
b6148757 MAL |
99 | { "tpm-crb", "ppi", "false" }, |
100 | { "tpm-tis", "ppi", "false" }, | |
b63e1050 GH |
101 | { "usb-kbd", "serial", "42" }, |
102 | { "usb-mouse", "serial", "42" }, | |
442bac16 | 103 | { "usb-tablet", "serial", "42" }, |
5c81161f SG |
104 | { "virtio-blk-device", "discard", "false" }, |
105 | { "virtio-blk-device", "write-zeroes", "false" }, | |
2bbadb08 | 106 | { "virtio-balloon-device", "qemu-4-0-config-size", "false" }, |
c8557f1b | 107 | { "pcie-root-port-base", "disable-acs", "true" }, /* Added in 4.1 */ |
abd93cc7 MAL |
108 | }; |
109 | const size_t hw_compat_3_1_len = G_N_ELEMENTS(hw_compat_3_1); | |
110 | ||
ddb3235d MAL |
111 | GlobalProperty hw_compat_3_0[] = {}; |
112 | const size_t hw_compat_3_0_len = G_N_ELEMENTS(hw_compat_3_0); | |
113 | ||
0d47310b | 114 | GlobalProperty hw_compat_2_12[] = { |
6c36bddf EH |
115 | { "migration", "decompress-error-check", "off" }, |
116 | { "hda-audio", "use-timer", "false" }, | |
117 | { "cirrus-vga", "global-vmstate", "true" }, | |
118 | { "VGA", "global-vmstate", "true" }, | |
119 | { "vmware-svga", "global-vmstate", "true" }, | |
120 | { "qxl-vga", "global-vmstate", "true" }, | |
0d47310b MAL |
121 | }; |
122 | const size_t hw_compat_2_12_len = G_N_ELEMENTS(hw_compat_2_12); | |
123 | ||
43df70a9 | 124 | GlobalProperty hw_compat_2_11[] = { |
6c36bddf EH |
125 | { "hpet", "hpet-offset-saved", "false" }, |
126 | { "virtio-blk-pci", "vectors", "2" }, | |
127 | { "vhost-user-blk-pci", "vectors", "2" }, | |
128 | { "e1000", "migrate_tso_props", "off" }, | |
43df70a9 MAL |
129 | }; |
130 | const size_t hw_compat_2_11_len = G_N_ELEMENTS(hw_compat_2_11); | |
131 | ||
503224f4 | 132 | GlobalProperty hw_compat_2_10[] = { |
6c36bddf EH |
133 | { "virtio-mouse-device", "wheel-axis", "false" }, |
134 | { "virtio-tablet-device", "wheel-axis", "false" }, | |
503224f4 MAL |
135 | }; |
136 | const size_t hw_compat_2_10_len = G_N_ELEMENTS(hw_compat_2_10); | |
137 | ||
3e803152 | 138 | GlobalProperty hw_compat_2_9[] = { |
6c36bddf EH |
139 | { "pci-bridge", "shpc", "off" }, |
140 | { "intel-iommu", "pt", "off" }, | |
141 | { "virtio-net-device", "x-mtu-bypass-backend", "off" }, | |
142 | { "pcie-root-port", "x-migrate-msix", "false" }, | |
3e803152 MAL |
143 | }; |
144 | const size_t hw_compat_2_9_len = G_N_ELEMENTS(hw_compat_2_9); | |
145 | ||
edc24ccd | 146 | GlobalProperty hw_compat_2_8[] = { |
6c36bddf EH |
147 | { "fw_cfg_mem", "x-file-slots", "0x10" }, |
148 | { "fw_cfg_io", "x-file-slots", "0x10" }, | |
149 | { "pflash_cfi01", "old-multiple-chip-handling", "on" }, | |
150 | { "pci-bridge", "shpc", "on" }, | |
151 | { TYPE_PCI_DEVICE, "x-pcie-extcap-init", "off" }, | |
152 | { "virtio-pci", "x-pcie-deverr-init", "off" }, | |
153 | { "virtio-pci", "x-pcie-lnkctl-init", "off" }, | |
154 | { "virtio-pci", "x-pcie-pm-init", "off" }, | |
155 | { "cirrus-vga", "vgamem_mb", "8" }, | |
156 | { "isa-cirrus-vga", "vgamem_mb", "8" }, | |
edc24ccd MAL |
157 | }; |
158 | const size_t hw_compat_2_8_len = G_N_ELEMENTS(hw_compat_2_8); | |
159 | ||
5a995064 | 160 | GlobalProperty hw_compat_2_7[] = { |
6c36bddf EH |
161 | { "virtio-pci", "page-per-vq", "on" }, |
162 | { "virtio-serial-device", "emergency-write", "off" }, | |
163 | { "ioapic", "version", "0x11" }, | |
164 | { "intel-iommu", "x-buggy-eim", "true" }, | |
165 | { "virtio-pci", "x-ignore-backend-features", "on" }, | |
5a995064 MAL |
166 | }; |
167 | const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7); | |
168 | ||
ff8f261f | 169 | GlobalProperty hw_compat_2_6[] = { |
6c36bddf | 170 | { "virtio-mmio", "format_transport_address", "off" }, |
dd56040d DDAG |
171 | /* Optional because not all virtio-pci devices support legacy mode */ |
172 | { "virtio-pci", "disable-modern", "on", .optional = true }, | |
173 | { "virtio-pci", "disable-legacy", "off", .optional = true }, | |
ff8f261f MAL |
174 | }; |
175 | const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6); | |
176 | ||
fe759610 | 177 | GlobalProperty hw_compat_2_5[] = { |
6c36bddf EH |
178 | { "isa-fdc", "fallback", "144" }, |
179 | { "pvscsi", "x-old-pci-configuration", "on" }, | |
180 | { "pvscsi", "x-disable-pcie", "on" }, | |
181 | { "vmxnet3", "x-old-msi-offsets", "on" }, | |
182 | { "vmxnet3", "x-disable-pcie", "on" }, | |
fe759610 MAL |
183 | }; |
184 | const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5); | |
185 | ||
2f99b9c2 | 186 | GlobalProperty hw_compat_2_4[] = { |
11a18c84 PMD |
187 | /* Optional because the 'scsi' property is Linux-only */ |
188 | { "virtio-blk-device", "scsi", "true", .optional = true }, | |
6c36bddf EH |
189 | { "e1000", "extra_mac_registers", "off" }, |
190 | { "virtio-pci", "x-disable-pcie", "on" }, | |
191 | { "virtio-pci", "migrate-extra", "off" }, | |
192 | { "fw_cfg_mem", "dma_enabled", "off" }, | |
193 | { "fw_cfg_io", "dma_enabled", "off" } | |
2f99b9c2 MAL |
194 | }; |
195 | const size_t hw_compat_2_4_len = G_N_ELEMENTS(hw_compat_2_4); | |
196 | ||
8995dd90 | 197 | GlobalProperty hw_compat_2_3[] = { |
6c36bddf EH |
198 | { "virtio-blk-pci", "any_layout", "off" }, |
199 | { "virtio-balloon-pci", "any_layout", "off" }, | |
200 | { "virtio-serial-pci", "any_layout", "off" }, | |
201 | { "virtio-9p-pci", "any_layout", "off" }, | |
202 | { "virtio-rng-pci", "any_layout", "off" }, | |
203 | { TYPE_PCI_DEVICE, "x-pcie-lnksta-dllla", "off" }, | |
204 | { "migration", "send-configuration", "off" }, | |
205 | { "migration", "send-section-footer", "off" }, | |
206 | { "migration", "store-global-state", "off" }, | |
8995dd90 MAL |
207 | }; |
208 | const size_t hw_compat_2_3_len = G_N_ELEMENTS(hw_compat_2_3); | |
209 | ||
1c30044e MAL |
210 | GlobalProperty hw_compat_2_2[] = {}; |
211 | const size_t hw_compat_2_2_len = G_N_ELEMENTS(hw_compat_2_2); | |
212 | ||
c4fc5695 | 213 | GlobalProperty hw_compat_2_1[] = { |
6c36bddf EH |
214 | { "intel-hda", "old_msi_addr", "on" }, |
215 | { "VGA", "qemu-extended-regs", "off" }, | |
216 | { "secondary-vga", "qemu-extended-regs", "off" }, | |
217 | { "virtio-scsi-pci", "any_layout", "off" }, | |
218 | { "usb-mouse", "usb_version", "1" }, | |
219 | { "usb-kbd", "usb_version", "1" }, | |
220 | { "virtio-pci", "virtio-pci-bus-master-bug-migration", "on" }, | |
c4fc5695 MAL |
221 | }; |
222 | const size_t hw_compat_2_1_len = G_N_ELEMENTS(hw_compat_2_1); | |
223 | ||
c5e3c918 PB |
224 | MachineState *current_machine; |
225 | ||
6b1b1440 MA |
226 | static char *machine_get_kernel(Object *obj, Error **errp) |
227 | { | |
228 | MachineState *ms = MACHINE(obj); | |
229 | ||
230 | return g_strdup(ms->kernel_filename); | |
231 | } | |
232 | ||
233 | static void machine_set_kernel(Object *obj, const char *value, Error **errp) | |
234 | { | |
235 | MachineState *ms = MACHINE(obj); | |
236 | ||
556068ee | 237 | g_free(ms->kernel_filename); |
6b1b1440 MA |
238 | ms->kernel_filename = g_strdup(value); |
239 | } | |
240 | ||
241 | static char *machine_get_initrd(Object *obj, Error **errp) | |
242 | { | |
243 | MachineState *ms = MACHINE(obj); | |
244 | ||
245 | return g_strdup(ms->initrd_filename); | |
246 | } | |
247 | ||
248 | static void machine_set_initrd(Object *obj, const char *value, Error **errp) | |
249 | { | |
250 | MachineState *ms = MACHINE(obj); | |
251 | ||
556068ee | 252 | g_free(ms->initrd_filename); |
6b1b1440 MA |
253 | ms->initrd_filename = g_strdup(value); |
254 | } | |
255 | ||
256 | static char *machine_get_append(Object *obj, Error **errp) | |
257 | { | |
258 | MachineState *ms = MACHINE(obj); | |
259 | ||
260 | return g_strdup(ms->kernel_cmdline); | |
261 | } | |
262 | ||
263 | static void machine_set_append(Object *obj, const char *value, Error **errp) | |
264 | { | |
265 | MachineState *ms = MACHINE(obj); | |
266 | ||
556068ee | 267 | g_free(ms->kernel_cmdline); |
6b1b1440 MA |
268 | ms->kernel_cmdline = g_strdup(value); |
269 | } | |
270 | ||
271 | static char *machine_get_dtb(Object *obj, Error **errp) | |
272 | { | |
273 | MachineState *ms = MACHINE(obj); | |
274 | ||
275 | return g_strdup(ms->dtb); | |
276 | } | |
277 | ||
278 | static void machine_set_dtb(Object *obj, const char *value, Error **errp) | |
279 | { | |
280 | MachineState *ms = MACHINE(obj); | |
281 | ||
556068ee | 282 | g_free(ms->dtb); |
6b1b1440 MA |
283 | ms->dtb = g_strdup(value); |
284 | } | |
285 | ||
286 | static char *machine_get_dumpdtb(Object *obj, Error **errp) | |
287 | { | |
288 | MachineState *ms = MACHINE(obj); | |
289 | ||
290 | return g_strdup(ms->dumpdtb); | |
291 | } | |
292 | ||
293 | static void machine_set_dumpdtb(Object *obj, const char *value, Error **errp) | |
294 | { | |
295 | MachineState *ms = MACHINE(obj); | |
296 | ||
556068ee | 297 | g_free(ms->dumpdtb); |
6b1b1440 MA |
298 | ms->dumpdtb = g_strdup(value); |
299 | } | |
300 | ||
301 | static void machine_get_phandle_start(Object *obj, Visitor *v, | |
d7bce999 EB |
302 | const char *name, void *opaque, |
303 | Error **errp) | |
6b1b1440 MA |
304 | { |
305 | MachineState *ms = MACHINE(obj); | |
306 | int64_t value = ms->phandle_start; | |
307 | ||
51e72bc1 | 308 | visit_type_int(v, name, &value, errp); |
6b1b1440 MA |
309 | } |
310 | ||
311 | static void machine_set_phandle_start(Object *obj, Visitor *v, | |
d7bce999 EB |
312 | const char *name, void *opaque, |
313 | Error **errp) | |
6b1b1440 MA |
314 | { |
315 | MachineState *ms = MACHINE(obj); | |
6b1b1440 MA |
316 | int64_t value; |
317 | ||
668f62ec | 318 | if (!visit_type_int(v, name, &value, errp)) { |
6b1b1440 MA |
319 | return; |
320 | } | |
321 | ||
322 | ms->phandle_start = value; | |
323 | } | |
324 | ||
325 | static char *machine_get_dt_compatible(Object *obj, Error **errp) | |
326 | { | |
327 | MachineState *ms = MACHINE(obj); | |
328 | ||
329 | return g_strdup(ms->dt_compatible); | |
330 | } | |
331 | ||
332 | static void machine_set_dt_compatible(Object *obj, const char *value, Error **errp) | |
333 | { | |
334 | MachineState *ms = MACHINE(obj); | |
335 | ||
556068ee | 336 | g_free(ms->dt_compatible); |
6b1b1440 MA |
337 | ms->dt_compatible = g_strdup(value); |
338 | } | |
339 | ||
340 | static bool machine_get_dump_guest_core(Object *obj, Error **errp) | |
341 | { | |
342 | MachineState *ms = MACHINE(obj); | |
343 | ||
344 | return ms->dump_guest_core; | |
345 | } | |
346 | ||
347 | static void machine_set_dump_guest_core(Object *obj, bool value, Error **errp) | |
348 | { | |
349 | MachineState *ms = MACHINE(obj); | |
350 | ||
351 | ms->dump_guest_core = value; | |
352 | } | |
353 | ||
354 | static bool machine_get_mem_merge(Object *obj, Error **errp) | |
355 | { | |
356 | MachineState *ms = MACHINE(obj); | |
357 | ||
358 | return ms->mem_merge; | |
359 | } | |
360 | ||
361 | static void machine_set_mem_merge(Object *obj, bool value, Error **errp) | |
362 | { | |
363 | MachineState *ms = MACHINE(obj); | |
364 | ||
365 | ms->mem_merge = value; | |
366 | } | |
367 | ||
368 | static bool machine_get_usb(Object *obj, Error **errp) | |
369 | { | |
370 | MachineState *ms = MACHINE(obj); | |
371 | ||
372 | return ms->usb; | |
373 | } | |
374 | ||
375 | static void machine_set_usb(Object *obj, bool value, Error **errp) | |
376 | { | |
377 | MachineState *ms = MACHINE(obj); | |
378 | ||
379 | ms->usb = value; | |
c6e76503 | 380 | ms->usb_disabled = !value; |
6b1b1440 MA |
381 | } |
382 | ||
cfc58cf3 EH |
383 | static bool machine_get_graphics(Object *obj, Error **errp) |
384 | { | |
385 | MachineState *ms = MACHINE(obj); | |
386 | ||
387 | return ms->enable_graphics; | |
388 | } | |
389 | ||
390 | static void machine_set_graphics(Object *obj, bool value, Error **errp) | |
391 | { | |
392 | MachineState *ms = MACHINE(obj); | |
393 | ||
394 | ms->enable_graphics = value; | |
395 | } | |
396 | ||
6b1b1440 MA |
397 | static char *machine_get_firmware(Object *obj, Error **errp) |
398 | { | |
399 | MachineState *ms = MACHINE(obj); | |
400 | ||
401 | return g_strdup(ms->firmware); | |
402 | } | |
403 | ||
404 | static void machine_set_firmware(Object *obj, const char *value, Error **errp) | |
405 | { | |
406 | MachineState *ms = MACHINE(obj); | |
407 | ||
556068ee | 408 | g_free(ms->firmware); |
6b1b1440 MA |
409 | ms->firmware = g_strdup(value); |
410 | } | |
411 | ||
9850c604 AG |
412 | static void machine_set_suppress_vmdesc(Object *obj, bool value, Error **errp) |
413 | { | |
414 | MachineState *ms = MACHINE(obj); | |
415 | ||
416 | ms->suppress_vmdesc = value; | |
417 | } | |
418 | ||
419 | static bool machine_get_suppress_vmdesc(Object *obj, Error **errp) | |
420 | { | |
421 | MachineState *ms = MACHINE(obj); | |
422 | ||
423 | return ms->suppress_vmdesc; | |
424 | } | |
425 | ||
db588194 BS |
426 | static char *machine_get_memory_encryption(Object *obj, Error **errp) |
427 | { | |
428 | MachineState *ms = MACHINE(obj); | |
429 | ||
430 | return g_strdup(ms->memory_encryption); | |
431 | } | |
432 | ||
433 | static void machine_set_memory_encryption(Object *obj, const char *value, | |
434 | Error **errp) | |
435 | { | |
436 | MachineState *ms = MACHINE(obj); | |
437 | ||
438 | g_free(ms->memory_encryption); | |
439 | ms->memory_encryption = g_strdup(value); | |
440 | } | |
441 | ||
f6a0d06b EA |
442 | static bool machine_get_nvdimm(Object *obj, Error **errp) |
443 | { | |
444 | MachineState *ms = MACHINE(obj); | |
445 | ||
446 | return ms->nvdimms_state->is_enabled; | |
447 | } | |
448 | ||
449 | static void machine_set_nvdimm(Object *obj, bool value, Error **errp) | |
450 | { | |
451 | MachineState *ms = MACHINE(obj); | |
452 | ||
453 | ms->nvdimms_state->is_enabled = value; | |
454 | } | |
455 | ||
244b3f44 TX |
456 | static bool machine_get_hmat(Object *obj, Error **errp) |
457 | { | |
458 | MachineState *ms = MACHINE(obj); | |
459 | ||
460 | return ms->numa_state->hmat_enabled; | |
461 | } | |
462 | ||
463 | static void machine_set_hmat(Object *obj, bool value, Error **errp) | |
464 | { | |
465 | MachineState *ms = MACHINE(obj); | |
466 | ||
467 | ms->numa_state->hmat_enabled = value; | |
468 | } | |
469 | ||
f6a0d06b EA |
470 | static char *machine_get_nvdimm_persistence(Object *obj, Error **errp) |
471 | { | |
472 | MachineState *ms = MACHINE(obj); | |
473 | ||
474 | return g_strdup(ms->nvdimms_state->persistence_string); | |
475 | } | |
476 | ||
477 | static void machine_set_nvdimm_persistence(Object *obj, const char *value, | |
478 | Error **errp) | |
479 | { | |
480 | MachineState *ms = MACHINE(obj); | |
481 | NVDIMMState *nvdimms_state = ms->nvdimms_state; | |
482 | ||
483 | if (strcmp(value, "cpu") == 0) { | |
484 | nvdimms_state->persistence = 3; | |
485 | } else if (strcmp(value, "mem-ctrl") == 0) { | |
486 | nvdimms_state->persistence = 2; | |
487 | } else { | |
488 | error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option", | |
489 | value); | |
490 | return; | |
491 | } | |
492 | ||
493 | g_free(nvdimms_state->persistence_string); | |
494 | nvdimms_state->persistence_string = g_strdup(value); | |
495 | } | |
496 | ||
0bd1909d | 497 | void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type) |
33cd52b5 | 498 | { |
54aa3de7 | 499 | QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type)); |
33cd52b5 AG |
500 | } |
501 | ||
0bd1909d | 502 | static void validate_sysbus_device(SysBusDevice *sbdev, void *opaque) |
33cd52b5 | 503 | { |
0bd1909d EH |
504 | MachineState *machine = opaque; |
505 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
506 | bool allowed = false; | |
507 | strList *wl; | |
33cd52b5 | 508 | |
0bd1909d EH |
509 | for (wl = mc->allowed_dynamic_sysbus_devices; |
510 | !allowed && wl; | |
511 | wl = wl->next) { | |
512 | allowed |= !!object_dynamic_cast(OBJECT(sbdev), wl->value); | |
513 | } | |
514 | ||
515 | if (!allowed) { | |
516 | error_report("Option '-device %s' cannot be handled by this machine", | |
517 | object_class_get_name(object_get_class(OBJECT(sbdev)))); | |
518 | exit(1); | |
33cd52b5 | 519 | } |
0bd1909d EH |
520 | } |
521 | ||
aa8b1839 IM |
522 | static char *machine_get_memdev(Object *obj, Error **errp) |
523 | { | |
524 | MachineState *ms = MACHINE(obj); | |
525 | ||
526 | return g_strdup(ms->ram_memdev_id); | |
527 | } | |
528 | ||
529 | static void machine_set_memdev(Object *obj, const char *value, Error **errp) | |
530 | { | |
531 | MachineState *ms = MACHINE(obj); | |
532 | ||
533 | g_free(ms->ram_memdev_id); | |
534 | ms->ram_memdev_id = g_strdup(value); | |
535 | } | |
536 | ||
537 | ||
0bd1909d EH |
538 | static void machine_init_notify(Notifier *notifier, void *data) |
539 | { | |
540 | MachineState *machine = MACHINE(qdev_get_machine()); | |
33cd52b5 AG |
541 | |
542 | /* | |
0bd1909d EH |
543 | * Loop through all dynamically created sysbus devices and check if they are |
544 | * all allowed. If a device is not allowed, error out. | |
33cd52b5 | 545 | */ |
0bd1909d | 546 | foreach_dynamic_sysbus_device(validate_sysbus_device, machine); |
33cd52b5 AG |
547 | } |
548 | ||
f2d672c2 IM |
549 | HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine) |
550 | { | |
551 | int i; | |
f2d672c2 | 552 | HotpluggableCPUList *head = NULL; |
d342eb76 IM |
553 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
554 | ||
555 | /* force board to initialize possible_cpus if it hasn't been done yet */ | |
556 | mc->possible_cpu_arch_ids(machine); | |
f2d672c2 | 557 | |
f2d672c2 | 558 | for (i = 0; i < machine->possible_cpus->len; i++) { |
d342eb76 | 559 | Object *cpu; |
f2d672c2 IM |
560 | HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1); |
561 | ||
d342eb76 | 562 | cpu_item->type = g_strdup(machine->possible_cpus->cpus[i].type); |
f2d672c2 IM |
563 | cpu_item->vcpus_count = machine->possible_cpus->cpus[i].vcpus_count; |
564 | cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props, | |
565 | sizeof(*cpu_item->props)); | |
566 | ||
567 | cpu = machine->possible_cpus->cpus[i].cpu; | |
568 | if (cpu) { | |
569 | cpu_item->has_qom_path = true; | |
570 | cpu_item->qom_path = object_get_canonical_path(cpu); | |
571 | } | |
54aa3de7 | 572 | QAPI_LIST_PREPEND(head, cpu_item); |
f2d672c2 IM |
573 | } |
574 | return head; | |
575 | } | |
576 | ||
7c88e65d IM |
577 | /** |
578 | * machine_set_cpu_numa_node: | |
579 | * @machine: machine object to modify | |
580 | * @props: specifies which cpu objects to assign to | |
581 | * numa node specified by @props.node_id | |
582 | * @errp: if an error occurs, a pointer to an area to store the error | |
583 | * | |
584 | * Associate NUMA node specified by @props.node_id with cpu slots that | |
585 | * match socket/core/thread-ids specified by @props. It's recommended to use | |
586 | * query-hotpluggable-cpus.props values to specify affected cpu slots, | |
587 | * which would lead to exact 1:1 mapping of cpu slots to NUMA node. | |
588 | * | |
589 | * However for CLI convenience it's possible to pass in subset of properties, | |
590 | * which would affect all cpu slots that match it. | |
591 | * Ex for pc machine: | |
592 | * -smp 4,cores=2,sockets=2 -numa node,nodeid=0 -numa node,nodeid=1 \ | |
593 | * -numa cpu,node-id=0,socket_id=0 \ | |
594 | * -numa cpu,node-id=1,socket_id=1 | |
595 | * will assign all child cores of socket 0 to node 0 and | |
596 | * of socket 1 to node 1. | |
597 | * | |
598 | * On attempt of reassigning (already assigned) cpu slot to another NUMA node, | |
599 | * return error. | |
600 | * Empty subset is disallowed and function will return with error in this case. | |
601 | */ | |
602 | void machine_set_cpu_numa_node(MachineState *machine, | |
603 | const CpuInstanceProperties *props, Error **errp) | |
604 | { | |
605 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
244b3f44 | 606 | NodeInfo *numa_info = machine->numa_state->nodes; |
7c88e65d IM |
607 | bool match = false; |
608 | int i; | |
609 | ||
610 | if (!mc->possible_cpu_arch_ids) { | |
611 | error_setg(errp, "mapping of CPUs to NUMA node is not supported"); | |
612 | return; | |
613 | } | |
614 | ||
615 | /* disabling node mapping is not supported, forbid it */ | |
616 | assert(props->has_node_id); | |
617 | ||
618 | /* force board to initialize possible_cpus if it hasn't been done yet */ | |
619 | mc->possible_cpu_arch_ids(machine); | |
620 | ||
621 | for (i = 0; i < machine->possible_cpus->len; i++) { | |
622 | CPUArchId *slot = &machine->possible_cpus->cpus[i]; | |
623 | ||
624 | /* reject unsupported by board properties */ | |
625 | if (props->has_thread_id && !slot->props.has_thread_id) { | |
626 | error_setg(errp, "thread-id is not supported"); | |
627 | return; | |
628 | } | |
629 | ||
630 | if (props->has_core_id && !slot->props.has_core_id) { | |
631 | error_setg(errp, "core-id is not supported"); | |
632 | return; | |
633 | } | |
634 | ||
635 | if (props->has_socket_id && !slot->props.has_socket_id) { | |
636 | error_setg(errp, "socket-id is not supported"); | |
637 | return; | |
638 | } | |
639 | ||
176d2cda LX |
640 | if (props->has_die_id && !slot->props.has_die_id) { |
641 | error_setg(errp, "die-id is not supported"); | |
642 | return; | |
643 | } | |
644 | ||
7c88e65d IM |
645 | /* skip slots with explicit mismatch */ |
646 | if (props->has_thread_id && props->thread_id != slot->props.thread_id) { | |
647 | continue; | |
648 | } | |
649 | ||
650 | if (props->has_core_id && props->core_id != slot->props.core_id) { | |
651 | continue; | |
652 | } | |
653 | ||
176d2cda LX |
654 | if (props->has_die_id && props->die_id != slot->props.die_id) { |
655 | continue; | |
656 | } | |
657 | ||
7c88e65d IM |
658 | if (props->has_socket_id && props->socket_id != slot->props.socket_id) { |
659 | continue; | |
660 | } | |
661 | ||
662 | /* reject assignment if slot is already assigned, for compatibility | |
663 | * of legacy cpu_index mapping with SPAPR core based mapping do not | |
664 | * error out if cpu thread and matched core have the same node-id */ | |
665 | if (slot->props.has_node_id && | |
666 | slot->props.node_id != props->node_id) { | |
667 | error_setg(errp, "CPU is already assigned to node-id: %" PRId64, | |
668 | slot->props.node_id); | |
669 | return; | |
670 | } | |
671 | ||
672 | /* assign slot to node as it's matched '-numa cpu' key */ | |
673 | match = true; | |
674 | slot->props.node_id = props->node_id; | |
675 | slot->props.has_node_id = props->has_node_id; | |
244b3f44 TX |
676 | |
677 | if (machine->numa_state->hmat_enabled) { | |
678 | if ((numa_info[props->node_id].initiator < MAX_NODES) && | |
679 | (props->node_id != numa_info[props->node_id].initiator)) { | |
680 | error_setg(errp, "The initiator of CPU NUMA node %" PRId64 | |
681 | " should be itself", props->node_id); | |
682 | return; | |
683 | } | |
684 | numa_info[props->node_id].has_cpu = true; | |
685 | numa_info[props->node_id].initiator = props->node_id; | |
686 | } | |
7c88e65d IM |
687 | } |
688 | ||
689 | if (!match) { | |
690 | error_setg(errp, "no match found"); | |
691 | } | |
692 | } | |
693 | ||
6f479566 LX |
694 | static void smp_parse(MachineState *ms, QemuOpts *opts) |
695 | { | |
696 | if (opts) { | |
697 | unsigned cpus = qemu_opt_get_number(opts, "cpus", 0); | |
698 | unsigned sockets = qemu_opt_get_number(opts, "sockets", 0); | |
699 | unsigned cores = qemu_opt_get_number(opts, "cores", 0); | |
700 | unsigned threads = qemu_opt_get_number(opts, "threads", 0); | |
701 | ||
702 | /* compute missing values, prefer sockets over cores over threads */ | |
703 | if (cpus == 0 || sockets == 0) { | |
704 | cores = cores > 0 ? cores : 1; | |
705 | threads = threads > 0 ? threads : 1; | |
706 | if (cpus == 0) { | |
707 | sockets = sockets > 0 ? sockets : 1; | |
708 | cpus = cores * threads * sockets; | |
709 | } else { | |
710 | ms->smp.max_cpus = | |
711 | qemu_opt_get_number(opts, "maxcpus", cpus); | |
712 | sockets = ms->smp.max_cpus / (cores * threads); | |
713 | } | |
714 | } else if (cores == 0) { | |
715 | threads = threads > 0 ? threads : 1; | |
716 | cores = cpus / (sockets * threads); | |
717 | cores = cores > 0 ? cores : 1; | |
718 | } else if (threads == 0) { | |
719 | threads = cpus / (cores * sockets); | |
720 | threads = threads > 0 ? threads : 1; | |
721 | } else if (sockets * cores * threads < cpus) { | |
722 | error_report("cpu topology: " | |
723 | "sockets (%u) * cores (%u) * threads (%u) < " | |
724 | "smp_cpus (%u)", | |
725 | sockets, cores, threads, cpus); | |
726 | exit(1); | |
727 | } | |
728 | ||
729 | ms->smp.max_cpus = | |
730 | qemu_opt_get_number(opts, "maxcpus", cpus); | |
731 | ||
732 | if (ms->smp.max_cpus < cpus) { | |
733 | error_report("maxcpus must be equal to or greater than smp"); | |
734 | exit(1); | |
735 | } | |
736 | ||
c4332cd1 IM |
737 | if (sockets * cores * threads != ms->smp.max_cpus) { |
738 | error_report("Invalid CPU topology: " | |
739 | "sockets (%u) * cores (%u) * threads (%u) " | |
740 | "!= maxcpus (%u)", | |
6f479566 LX |
741 | sockets, cores, threads, |
742 | ms->smp.max_cpus); | |
743 | exit(1); | |
744 | } | |
745 | ||
6f479566 LX |
746 | ms->smp.cpus = cpus; |
747 | ms->smp.cores = cores; | |
748 | ms->smp.threads = threads; | |
8cb30e3a | 749 | ms->smp.sockets = sockets; |
6f479566 LX |
750 | } |
751 | ||
752 | if (ms->smp.cpus > 1) { | |
753 | Error *blocker = NULL; | |
754 | error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp"); | |
755 | replay_add_blocker(blocker); | |
756 | } | |
757 | } | |
758 | ||
076b35b5 ND |
759 | static void machine_class_init(ObjectClass *oc, void *data) |
760 | { | |
761 | MachineClass *mc = MACHINE_CLASS(oc); | |
762 | ||
763 | /* Default 128 MB as guest ram size */ | |
d23b6caa | 764 | mc->default_ram_size = 128 * MiB; |
71ae9e94 | 765 | mc->rom_file_has_mr = true; |
6f479566 | 766 | mc->smp_parse = smp_parse; |
26b81df4 | 767 | |
55641213 LV |
768 | /* numa node memory size aligned on 8MB by default. |
769 | * On Linux, each node's border has to be 8MB aligned | |
770 | */ | |
771 | mc->numa_mem_align_shift = 23; | |
772 | ||
26b81df4 | 773 | object_class_property_add_str(oc, "kernel", |
d2623129 | 774 | machine_get_kernel, machine_set_kernel); |
26b81df4 | 775 | object_class_property_set_description(oc, "kernel", |
7eecec7d | 776 | "Linux kernel image file"); |
26b81df4 EH |
777 | |
778 | object_class_property_add_str(oc, "initrd", | |
d2623129 | 779 | machine_get_initrd, machine_set_initrd); |
26b81df4 | 780 | object_class_property_set_description(oc, "initrd", |
7eecec7d | 781 | "Linux initial ramdisk file"); |
26b81df4 EH |
782 | |
783 | object_class_property_add_str(oc, "append", | |
d2623129 | 784 | machine_get_append, machine_set_append); |
26b81df4 | 785 | object_class_property_set_description(oc, "append", |
7eecec7d | 786 | "Linux kernel command line"); |
26b81df4 EH |
787 | |
788 | object_class_property_add_str(oc, "dtb", | |
d2623129 | 789 | machine_get_dtb, machine_set_dtb); |
26b81df4 | 790 | object_class_property_set_description(oc, "dtb", |
7eecec7d | 791 | "Linux kernel device tree file"); |
26b81df4 EH |
792 | |
793 | object_class_property_add_str(oc, "dumpdtb", | |
d2623129 | 794 | machine_get_dumpdtb, machine_set_dumpdtb); |
26b81df4 | 795 | object_class_property_set_description(oc, "dumpdtb", |
7eecec7d | 796 | "Dump current dtb to a file and quit"); |
26b81df4 EH |
797 | |
798 | object_class_property_add(oc, "phandle-start", "int", | |
799 | machine_get_phandle_start, machine_set_phandle_start, | |
d2623129 | 800 | NULL, NULL); |
26b81df4 | 801 | object_class_property_set_description(oc, "phandle-start", |
7eecec7d | 802 | "The first phandle ID we may generate dynamically"); |
26b81df4 EH |
803 | |
804 | object_class_property_add_str(oc, "dt-compatible", | |
d2623129 | 805 | machine_get_dt_compatible, machine_set_dt_compatible); |
26b81df4 | 806 | object_class_property_set_description(oc, "dt-compatible", |
7eecec7d | 807 | "Overrides the \"compatible\" property of the dt root node"); |
26b81df4 EH |
808 | |
809 | object_class_property_add_bool(oc, "dump-guest-core", | |
d2623129 | 810 | machine_get_dump_guest_core, machine_set_dump_guest_core); |
26b81df4 | 811 | object_class_property_set_description(oc, "dump-guest-core", |
7eecec7d | 812 | "Include guest memory in a core dump"); |
26b81df4 EH |
813 | |
814 | object_class_property_add_bool(oc, "mem-merge", | |
d2623129 | 815 | machine_get_mem_merge, machine_set_mem_merge); |
26b81df4 | 816 | object_class_property_set_description(oc, "mem-merge", |
7eecec7d | 817 | "Enable/disable memory merge support"); |
26b81df4 EH |
818 | |
819 | object_class_property_add_bool(oc, "usb", | |
d2623129 | 820 | machine_get_usb, machine_set_usb); |
26b81df4 | 821 | object_class_property_set_description(oc, "usb", |
7eecec7d | 822 | "Set on/off to enable/disable usb"); |
26b81df4 EH |
823 | |
824 | object_class_property_add_bool(oc, "graphics", | |
d2623129 | 825 | machine_get_graphics, machine_set_graphics); |
26b81df4 | 826 | object_class_property_set_description(oc, "graphics", |
7eecec7d | 827 | "Set on/off to enable/disable graphics emulation"); |
26b81df4 | 828 | |
26b81df4 | 829 | object_class_property_add_str(oc, "firmware", |
d2623129 | 830 | machine_get_firmware, machine_set_firmware); |
26b81df4 | 831 | object_class_property_set_description(oc, "firmware", |
7eecec7d | 832 | "Firmware image"); |
26b81df4 EH |
833 | |
834 | object_class_property_add_bool(oc, "suppress-vmdesc", | |
d2623129 | 835 | machine_get_suppress_vmdesc, machine_set_suppress_vmdesc); |
26b81df4 | 836 | object_class_property_set_description(oc, "suppress-vmdesc", |
7eecec7d | 837 | "Set on to disable self-describing migration"); |
26b81df4 | 838 | |
db588194 | 839 | object_class_property_add_str(oc, "memory-encryption", |
d2623129 | 840 | machine_get_memory_encryption, machine_set_memory_encryption); |
db588194 | 841 | object_class_property_set_description(oc, "memory-encryption", |
7eecec7d | 842 | "Set memory encryption object to use"); |
acd5b054 EH |
843 | |
844 | object_class_property_add_str(oc, "memory-backend", | |
845 | machine_get_memdev, machine_set_memdev); | |
846 | object_class_property_set_description(oc, "memory-backend", | |
847 | "Set RAM backend" | |
848 | "Valid value is ID of hostmem based backend"); | |
076b35b5 ND |
849 | } |
850 | ||
dcb3d601 EH |
851 | static void machine_class_base_init(ObjectClass *oc, void *data) |
852 | { | |
2c920e45 PB |
853 | MachineClass *mc = MACHINE_CLASS(oc); |
854 | mc->max_cpus = mc->max_cpus ?: 1; | |
855 | mc->min_cpus = mc->min_cpus ?: 1; | |
856 | mc->default_cpus = mc->default_cpus ?: 1; | |
857 | ||
dcb3d601 EH |
858 | if (!object_class_is_abstract(oc)) { |
859 | const char *cname = object_class_get_name(oc); | |
860 | assert(g_str_has_suffix(cname, TYPE_MACHINE_SUFFIX)); | |
98cec76a EH |
861 | mc->name = g_strndup(cname, |
862 | strlen(cname) - strlen(TYPE_MACHINE_SUFFIX)); | |
b66bbee3 | 863 | mc->compat_props = g_ptr_array_new(); |
dcb3d601 EH |
864 | } |
865 | } | |
866 | ||
6b1b1440 MA |
867 | static void machine_initfn(Object *obj) |
868 | { | |
33cd52b5 | 869 | MachineState *ms = MACHINE(obj); |
b2fc91db | 870 | MachineClass *mc = MACHINE_GET_CLASS(obj); |
33cd52b5 | 871 | |
e0d17dfd PB |
872 | container_get(obj, "/peripheral"); |
873 | container_get(obj, "/peripheral-anon"); | |
874 | ||
47c8ca53 | 875 | ms->dump_guest_core = true; |
75cc7f01 | 876 | ms->mem_merge = true; |
cfc58cf3 | 877 | ms->enable_graphics = true; |
58c91595 | 878 | ms->kernel_cmdline = g_strdup(""); |
d8870d02 | 879 | |
f6a0d06b EA |
880 | if (mc->nvdimm_supported) { |
881 | Object *obj = OBJECT(ms); | |
882 | ||
883 | ms->nvdimms_state = g_new0(NVDIMMState, 1); | |
884 | object_property_add_bool(obj, "nvdimm", | |
d2623129 | 885 | machine_get_nvdimm, machine_set_nvdimm); |
f6a0d06b EA |
886 | object_property_set_description(obj, "nvdimm", |
887 | "Set on/off to enable/disable " | |
7eecec7d | 888 | "NVDIMM instantiation"); |
f6a0d06b EA |
889 | |
890 | object_property_add_str(obj, "nvdimm-persistence", | |
891 | machine_get_nvdimm_persistence, | |
d2623129 | 892 | machine_set_nvdimm_persistence); |
f6a0d06b EA |
893 | object_property_set_description(obj, "nvdimm-persistence", |
894 | "Set NVDIMM persistence" | |
7eecec7d | 895 | "Valid values are cpu, mem-ctrl"); |
f6a0d06b EA |
896 | } |
897 | ||
fcd3f2cc | 898 | if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) { |
aa570207 | 899 | ms->numa_state = g_new0(NumaState, 1); |
244b3f44 | 900 | object_property_add_bool(obj, "hmat", |
d2623129 | 901 | machine_get_hmat, machine_set_hmat); |
244b3f44 TX |
902 | object_property_set_description(obj, "hmat", |
903 | "Set on/off to enable/disable " | |
904 | "ACPI Heterogeneous Memory Attribute " | |
7eecec7d | 905 | "Table (HMAT)"); |
aa570207 | 906 | } |
f6a0d06b | 907 | |
33cd52b5 AG |
908 | /* Register notifier when init is done for sysbus sanity checks */ |
909 | ms->sysbus_notifier.notify = machine_init_notify; | |
910 | qemu_add_machine_init_done_notifier(&ms->sysbus_notifier); | |
8b0e484c PB |
911 | |
912 | /* default to mc->default_cpus */ | |
913 | ms->smp.cpus = mc->default_cpus; | |
914 | ms->smp.max_cpus = mc->default_cpus; | |
915 | ms->smp.cores = 1; | |
916 | ms->smp.threads = 1; | |
917 | ms->smp.sockets = 1; | |
6b1b1440 MA |
918 | } |
919 | ||
920 | static void machine_finalize(Object *obj) | |
921 | { | |
922 | MachineState *ms = MACHINE(obj); | |
923 | ||
6b1b1440 MA |
924 | g_free(ms->kernel_filename); |
925 | g_free(ms->initrd_filename); | |
926 | g_free(ms->kernel_cmdline); | |
927 | g_free(ms->dtb); | |
928 | g_free(ms->dumpdtb); | |
929 | g_free(ms->dt_compatible); | |
930 | g_free(ms->firmware); | |
2ff4f67c | 931 | g_free(ms->device_memory); |
f6a0d06b | 932 | g_free(ms->nvdimms_state); |
aa570207 | 933 | g_free(ms->numa_state); |
6b1b1440 | 934 | } |
36d20cb2 | 935 | |
5e97b623 MA |
936 | bool machine_usb(MachineState *machine) |
937 | { | |
938 | return machine->usb; | |
939 | } | |
940 | ||
6cabe7fa MA |
941 | int machine_phandle_start(MachineState *machine) |
942 | { | |
943 | return machine->phandle_start; | |
944 | } | |
945 | ||
47c8ca53 MA |
946 | bool machine_dump_guest_core(MachineState *machine) |
947 | { | |
948 | return machine->dump_guest_core; | |
949 | } | |
950 | ||
75cc7f01 MA |
951 | bool machine_mem_merge(MachineState *machine) |
952 | { | |
953 | return machine->mem_merge; | |
954 | } | |
955 | ||
ec78f811 IM |
956 | static char *cpu_slot_to_string(const CPUArchId *cpu) |
957 | { | |
958 | GString *s = g_string_new(NULL); | |
959 | if (cpu->props.has_socket_id) { | |
960 | g_string_append_printf(s, "socket-id: %"PRId64, cpu->props.socket_id); | |
961 | } | |
176d2cda LX |
962 | if (cpu->props.has_die_id) { |
963 | g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); | |
964 | } | |
ec78f811 IM |
965 | if (cpu->props.has_core_id) { |
966 | if (s->len) { | |
967 | g_string_append_printf(s, ", "); | |
968 | } | |
969 | g_string_append_printf(s, "core-id: %"PRId64, cpu->props.core_id); | |
970 | } | |
971 | if (cpu->props.has_thread_id) { | |
972 | if (s->len) { | |
973 | g_string_append_printf(s, ", "); | |
974 | } | |
975 | g_string_append_printf(s, "thread-id: %"PRId64, cpu->props.thread_id); | |
976 | } | |
977 | return g_string_free(s, false); | |
978 | } | |
979 | ||
244b3f44 TX |
980 | static void numa_validate_initiator(NumaState *numa_state) |
981 | { | |
982 | int i; | |
983 | NodeInfo *numa_info = numa_state->nodes; | |
984 | ||
985 | for (i = 0; i < numa_state->num_nodes; i++) { | |
986 | if (numa_info[i].initiator == MAX_NODES) { | |
987 | error_report("The initiator of NUMA node %d is missing, use " | |
988 | "'-numa node,initiator' option to declare it", i); | |
989 | exit(1); | |
990 | } | |
991 | ||
992 | if (!numa_info[numa_info[i].initiator].present) { | |
993 | error_report("NUMA node %" PRIu16 " is missing, use " | |
994 | "'-numa node' option to declare it first", | |
995 | numa_info[i].initiator); | |
996 | exit(1); | |
997 | } | |
998 | ||
999 | if (!numa_info[numa_info[i].initiator].has_cpu) { | |
1000 | error_report("The initiator of NUMA node %d is invalid", i); | |
1001 | exit(1); | |
1002 | } | |
1003 | } | |
1004 | } | |
1005 | ||
7a3099fc | 1006 | static void machine_numa_finish_cpu_init(MachineState *machine) |
ec78f811 IM |
1007 | { |
1008 | int i; | |
60bed6a3 | 1009 | bool default_mapping; |
ec78f811 IM |
1010 | GString *s = g_string_new(NULL); |
1011 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
1012 | const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(machine); | |
1013 | ||
aa570207 | 1014 | assert(machine->numa_state->num_nodes); |
60bed6a3 IM |
1015 | for (i = 0; i < possible_cpus->len; i++) { |
1016 | if (possible_cpus->cpus[i].props.has_node_id) { | |
1017 | break; | |
1018 | } | |
1019 | } | |
1020 | default_mapping = (i == possible_cpus->len); | |
1021 | ||
ec78f811 IM |
1022 | for (i = 0; i < possible_cpus->len; i++) { |
1023 | const CPUArchId *cpu_slot = &possible_cpus->cpus[i]; | |
1024 | ||
ec78f811 | 1025 | if (!cpu_slot->props.has_node_id) { |
d41f3e75 IM |
1026 | /* fetch default mapping from board and enable it */ |
1027 | CpuInstanceProperties props = cpu_slot->props; | |
1028 | ||
79e07936 | 1029 | props.node_id = mc->get_default_cpu_node_id(machine, i); |
d41f3e75 | 1030 | if (!default_mapping) { |
60bed6a3 IM |
1031 | /* record slots with not set mapping, |
1032 | * TODO: make it hard error in future */ | |
1033 | char *cpu_str = cpu_slot_to_string(cpu_slot); | |
1034 | g_string_append_printf(s, "%sCPU %d [%s]", | |
1035 | s->len ? ", " : "", i, cpu_str); | |
1036 | g_free(cpu_str); | |
d41f3e75 IM |
1037 | |
1038 | /* non mapped cpus used to fallback to node 0 */ | |
1039 | props.node_id = 0; | |
60bed6a3 | 1040 | } |
d41f3e75 IM |
1041 | |
1042 | props.has_node_id = true; | |
1043 | machine_set_cpu_numa_node(machine, &props, &error_fatal); | |
ec78f811 IM |
1044 | } |
1045 | } | |
244b3f44 TX |
1046 | |
1047 | if (machine->numa_state->hmat_enabled) { | |
1048 | numa_validate_initiator(machine->numa_state); | |
1049 | } | |
1050 | ||
c6ff347c | 1051 | if (s->len && !qtest_enabled()) { |
3dc6f869 AF |
1052 | warn_report("CPU(s) not present in any NUMA nodes: %s", |
1053 | s->str); | |
1054 | warn_report("All CPU(s) up to maxcpus should be described " | |
1055 | "in NUMA config, ability to start up with partial NUMA " | |
1056 | "mappings is obsoleted and will be removed in future"); | |
ec78f811 IM |
1057 | } |
1058 | g_string_free(s, true); | |
1059 | } | |
1060 | ||
82b911aa IM |
1061 | MemoryRegion *machine_consume_memdev(MachineState *machine, |
1062 | HostMemoryBackend *backend) | |
1063 | { | |
1064 | MemoryRegion *ret = host_memory_backend_get_memory(backend); | |
1065 | ||
1066 | if (memory_region_is_mapped(ret)) { | |
7a309cc9 MA |
1067 | error_report("memory backend %s can't be used multiple times.", |
1068 | object_get_canonical_path_component(OBJECT(backend))); | |
82b911aa IM |
1069 | exit(EXIT_FAILURE); |
1070 | } | |
1071 | host_memory_backend_set_mapped(backend, true); | |
1072 | vmstate_register_ram_global(ret); | |
1073 | return ret; | |
1074 | } | |
1075 | ||
3df8c4f3 PB |
1076 | bool machine_smp_parse(MachineState *ms, QemuOpts *opts, Error **errp) |
1077 | { | |
1078 | MachineClass *mc = MACHINE_GET_CLASS(ms); | |
1079 | ||
1080 | mc->smp_parse(ms, opts); | |
1081 | ||
1082 | /* sanity-check smp_cpus and max_cpus against mc */ | |
1083 | if (ms->smp.cpus < mc->min_cpus) { | |
1084 | error_setg(errp, "Invalid SMP CPUs %d. The min CPUs " | |
1085 | "supported by machine '%s' is %d", | |
1086 | ms->smp.cpus, | |
1087 | mc->name, mc->min_cpus); | |
1088 | return false; | |
1089 | } else if (ms->smp.max_cpus > mc->max_cpus) { | |
1090 | error_setg(errp, "Invalid SMP CPUs %d. The max CPUs " | |
1091 | "supported by machine '%s' is %d", | |
1092 | current_machine->smp.max_cpus, | |
1093 | mc->name, mc->max_cpus); | |
1094 | return false; | |
1095 | } | |
1096 | return true; | |
1097 | } | |
1098 | ||
482dfe9a IM |
1099 | void machine_run_board_init(MachineState *machine) |
1100 | { | |
1101 | MachineClass *machine_class = MACHINE_GET_CLASS(machine); | |
61ad65d0 RH |
1102 | ObjectClass *oc = object_class_by_name(machine->cpu_type); |
1103 | CPUClass *cc; | |
ec78f811 | 1104 | |
a3ef9bfb PB |
1105 | /* This checkpoint is required by replay to separate prior clock |
1106 | reading from the other reads, because timer polling functions query | |
1107 | clock values from the log. */ | |
1108 | replay_checkpoint(CHECKPOINT_INIT); | |
1109 | ||
82b911aa IM |
1110 | if (machine->ram_memdev_id) { |
1111 | Object *o; | |
1112 | o = object_resolve_path_type(machine->ram_memdev_id, | |
1113 | TYPE_MEMORY_BACKEND, NULL); | |
1114 | machine->ram = machine_consume_memdev(machine, MEMORY_BACKEND(o)); | |
1115 | } | |
1116 | ||
fcd3f2cc | 1117 | if (machine->numa_state) { |
aa570207 TX |
1118 | numa_complete_configuration(machine); |
1119 | if (machine->numa_state->num_nodes) { | |
1120 | machine_numa_finish_cpu_init(machine); | |
1121 | } | |
3aeaac8f | 1122 | } |
c9cf636d AF |
1123 | |
1124 | /* If the machine supports the valid_cpu_types check and the user | |
1125 | * specified a CPU with -cpu check here that the user CPU is supported. | |
1126 | */ | |
1127 | if (machine_class->valid_cpu_types && machine->cpu_type) { | |
c9cf636d AF |
1128 | int i; |
1129 | ||
1130 | for (i = 0; machine_class->valid_cpu_types[i]; i++) { | |
61ad65d0 | 1131 | if (object_class_dynamic_cast(oc, |
c9cf636d AF |
1132 | machine_class->valid_cpu_types[i])) { |
1133 | /* The user specificed CPU is in the valid field, we are | |
1134 | * good to go. | |
1135 | */ | |
1136 | break; | |
1137 | } | |
1138 | } | |
1139 | ||
1140 | if (!machine_class->valid_cpu_types[i]) { | |
1141 | /* The user specified CPU is not valid */ | |
1142 | error_report("Invalid CPU type: %s", machine->cpu_type); | |
1143 | error_printf("The valid types are: %s", | |
1144 | machine_class->valid_cpu_types[0]); | |
1145 | for (i = 1; machine_class->valid_cpu_types[i]; i++) { | |
1146 | error_printf(", %s", machine_class->valid_cpu_types[i]); | |
1147 | } | |
1148 | error_printf("\n"); | |
1149 | ||
1150 | exit(1); | |
1151 | } | |
1152 | } | |
1153 | ||
61ad65d0 RH |
1154 | /* Check if CPU type is deprecated and warn if so */ |
1155 | cc = CPU_CLASS(oc); | |
1156 | if (cc && cc->deprecation_note) { | |
1157 | warn_report("CPU model %s is deprecated -- %s", machine->cpu_type, | |
1158 | cc->deprecation_note); | |
1159 | } | |
1160 | ||
6e6a6ca7 DG |
1161 | if (machine->memory_encryption) { |
1162 | /* | |
1163 | * With memory encryption, the host can't see the real | |
1164 | * contents of RAM, so there's no point in it trying to merge | |
1165 | * areas. | |
1166 | */ | |
1167 | machine_set_mem_merge(OBJECT(machine), false, &error_abort); | |
1168 | } | |
1169 | ||
482dfe9a | 1170 | machine_class->init(machine); |
2f181fbd | 1171 | phase_advance(PHASE_MACHINE_INITIALIZED); |
482dfe9a IM |
1172 | } |
1173 | ||
6b21670c PB |
1174 | static NotifierList machine_init_done_notifiers = |
1175 | NOTIFIER_LIST_INITIALIZER(machine_init_done_notifiers); | |
1176 | ||
6b21670c PB |
1177 | void qemu_add_machine_init_done_notifier(Notifier *notify) |
1178 | { | |
1179 | notifier_list_add(&machine_init_done_notifiers, notify); | |
2f181fbd | 1180 | if (phase_check(PHASE_MACHINE_READY)) { |
6b21670c PB |
1181 | notify->notify(notify, NULL); |
1182 | } | |
1183 | } | |
1184 | ||
1185 | void qemu_remove_machine_init_done_notifier(Notifier *notify) | |
1186 | { | |
1187 | notifier_remove(notify); | |
1188 | } | |
1189 | ||
f66dc873 | 1190 | void qdev_machine_creation_done(void) |
6b21670c | 1191 | { |
f66dc873 PB |
1192 | cpu_synchronize_all_post_init(); |
1193 | ||
1194 | if (current_machine->boot_once) { | |
1195 | qemu_boot_set(current_machine->boot_once, &error_fatal); | |
1196 | qemu_register_reset(restore_boot_order, g_strdup(current_machine->boot_order)); | |
1197 | } | |
1198 | ||
1199 | /* | |
1200 | * ok, initial machine setup is done, starting from now we can | |
1201 | * only create hotpluggable devices | |
1202 | */ | |
2f181fbd | 1203 | phase_advance(PHASE_MACHINE_READY); |
f66dc873 PB |
1204 | qdev_assert_realized_properly(); |
1205 | ||
1206 | /* TODO: once all bus devices are qdevified, this should be done | |
1207 | * when bus is created by qdev.c */ | |
1208 | /* | |
1209 | * TODO: If we had a main 'reset container' that the whole system | |
1210 | * lived in, we could reset that using the multi-phase reset | |
1211 | * APIs. For the moment, we just reset the sysbus, which will cause | |
1212 | * all devices hanging off it (and all their child buses, recursively) | |
1213 | * to be reset. Note that this will *not* reset any Device objects | |
1214 | * which are not attached to some part of the qbus tree! | |
1215 | */ | |
1216 | qemu_register_reset(resettable_cold_reset_fn, sysbus_get_default()); | |
1217 | ||
6b21670c | 1218 | notifier_list_notify(&machine_init_done_notifiers, NULL); |
f66dc873 PB |
1219 | |
1220 | if (rom_check_and_register_reset() != 0) { | |
f66dc873 PB |
1221 | exit(1); |
1222 | } | |
1223 | ||
1224 | replay_start(); | |
1225 | ||
1226 | /* This checkpoint is required by replay to separate prior clock | |
1227 | reading from the other reads, because timer polling functions query | |
1228 | clock values from the log. */ | |
1229 | replay_checkpoint(CHECKPOINT_RESET); | |
1230 | qemu_system_reset(SHUTDOWN_CAUSE_NONE); | |
1231 | register_global_state(); | |
6b21670c PB |
1232 | } |
1233 | ||
36d20cb2 MA |
1234 | static const TypeInfo machine_info = { |
1235 | .name = TYPE_MACHINE, | |
1236 | .parent = TYPE_OBJECT, | |
1237 | .abstract = true, | |
1238 | .class_size = sizeof(MachineClass), | |
076b35b5 | 1239 | .class_init = machine_class_init, |
dcb3d601 | 1240 | .class_base_init = machine_class_base_init, |
36d20cb2 | 1241 | .instance_size = sizeof(MachineState), |
6b1b1440 MA |
1242 | .instance_init = machine_initfn, |
1243 | .instance_finalize = machine_finalize, | |
36d20cb2 MA |
1244 | }; |
1245 | ||
1246 | static void machine_register_types(void) | |
1247 | { | |
1248 | type_register_static(&machine_info); | |
1249 | } | |
1250 | ||
1251 | type_init(machine_register_types) |