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Commit | Line | Data |
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36d20cb2 MA |
1 | /* |
2 | * QEMU Machine | |
3 | * | |
4 | * Copyright (C) 2014 Red Hat Inc | |
5 | * | |
6 | * Authors: | |
7 | * Marcel Apfelbaum <marcel.a@redhat.com> | |
8 | * | |
9 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
10 | * See the COPYING file in the top-level directory. | |
11 | */ | |
12 | ||
18c86e2b | 13 | #include "qemu/osdep.h" |
cc6ff741 | 14 | #include "qemu/accel.h" |
6f479566 | 15 | #include "sysemu/replay.h" |
36d20cb2 | 16 | #include "hw/boards.h" |
f66dc873 | 17 | #include "hw/loader.h" |
da34e65c | 18 | #include "qapi/error.h" |
fe68090e | 19 | #include "qapi/qapi-visit-machine.h" |
fb56b7a0 | 20 | #include "qom/object_interfaces.h" |
f66dc873 | 21 | #include "sysemu/cpus.h" |
33cd52b5 | 22 | #include "sysemu/sysemu.h" |
f66dc873 PB |
23 | #include "sysemu/reset.h" |
24 | #include "sysemu/runstate.h" | |
fb56b7a0 | 25 | #include "sysemu/xen.h" |
c6ff347c | 26 | #include "sysemu/qtest.h" |
4565917b | 27 | #include "hw/pci/pci_bridge.h" |
f6a0d06b | 28 | #include "hw/mem/nvdimm.h" |
f66dc873 | 29 | #include "migration/global_state.h" |
e0292d7c | 30 | #include "exec/confidential-guest-support.h" |
9f88a7a3 | 31 | #include "hw/virtio/virtio-pci.h" |
53da8b5a | 32 | #include "hw/virtio/virtio-net.h" |
9dd5e808 | 33 | #include "hw/virtio/virtio-iommu.h" |
7a2c7da6 | 34 | #include "audio/audio.h" |
6b1b1440 | 35 | |
f037f5b4 PM |
36 | GlobalProperty hw_compat_9_0[] = { |
37 | {"arm-cpu", "backcompat-cntfrq", "true" }, | |
38 | }; | |
85fa9acd PB |
39 | const size_t hw_compat_9_0_len = G_N_ELEMENTS(hw_compat_9_0); |
40 | ||
70c25c92 HX |
41 | GlobalProperty hw_compat_8_2[] = { |
42 | { "migration", "zero-page-detection", "legacy"}, | |
9dd5e808 | 43 | { TYPE_VIRTIO_IOMMU_PCI, "granule", "4k" }, |
9b588be3 | 44 | { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "64" }, |
70c25c92 | 45 | }; |
2b10a676 CH |
46 | const size_t hw_compat_8_2_len = G_N_ELEMENTS(hw_compat_8_2); |
47 | ||
4565917b MT |
48 | GlobalProperty hw_compat_8_1[] = { |
49 | { TYPE_PCI_BRIDGE, "x-pci-express-writeable-slt-bug", "true" }, | |
a1e88d2d | 50 | { "ramfb", "x-migrate", "off" }, |
d90014fc CLG |
51 | { "vfio-pci-nohotplug", "x-ramfb-migrate", "off" }, |
52 | { "igb", "x-pcie-flr-init", "off" }, | |
4565917b | 53 | }; |
95f5c89e CH |
54 | const size_t hw_compat_8_1_len = G_N_ELEMENTS(hw_compat_8_1); |
55 | ||
77c259a4 JQ |
56 | GlobalProperty hw_compat_8_0[] = { |
57 | { "migration", "multifd-flush-after-each-section", "on"}, | |
7c228c5f | 58 | { TYPE_PCI_DEVICE, "x-pcie-ari-nextfn-1", "on" }, |
53da8b5a YB |
59 | { TYPE_VIRTIO_NET, "host_uso", "off"}, |
60 | { TYPE_VIRTIO_NET, "guest_uso4", "off"}, | |
61 | { TYPE_VIRTIO_NET, "guest_uso6", "off"}, | |
77c259a4 | 62 | }; |
f9be4771 CH |
63 | const size_t hw_compat_8_0_len = G_N_ELEMENTS(hw_compat_8_0); |
64 | ||
3b95a71b | 65 | GlobalProperty hw_compat_7_2[] = { |
5fb7d149 | 66 | { "e1000e", "migrate-timadj", "off" }, |
3b95a71b | 67 | { "virtio-mem", "x-early-migration", "false" }, |
6621883f | 68 | { "migration", "x-preempt-pre-7-2", "true" }, |
5ed3dabe | 69 | { TYPE_PCI_DEVICE, "x-pcie-err-unc-mask", "off" }, |
3b95a71b | 70 | }; |
db723c80 CH |
71 | const size_t hw_compat_7_2_len = G_N_ELEMENTS(hw_compat_7_2); |
72 | ||
69e1c14a KX |
73 | GlobalProperty hw_compat_7_1[] = { |
74 | { "virtio-device", "queue_reset", "false" }, | |
bad9c5a5 | 75 | { "virtio-rng-pci", "vectors", "0" }, |
62bdb887 DDAG |
76 | { "virtio-rng-pci-transitional", "vectors", "0" }, |
77 | { "virtio-rng-pci-non-transitional", "vectors", "0" }, | |
69e1c14a | 78 | }; |
f514e147 CH |
79 | const size_t hw_compat_7_1_len = G_N_ELEMENTS(hw_compat_7_1); |
80 | ||
39f29e59 PM |
81 | GlobalProperty hw_compat_7_0[] = { |
82 | { "arm-gicv3-common", "force-8-bit-prio", "on" }, | |
36d83272 | 83 | { "nvme-ns", "eui64-default", "on"}, |
39f29e59 | 84 | }; |
0ca70366 CH |
85 | const size_t hw_compat_7_0_len = G_N_ELEMENTS(hw_compat_7_0); |
86 | ||
a83c2844 DDAG |
87 | GlobalProperty hw_compat_6_2[] = { |
88 | { "PIIX4_PM", "x-not-migrate-acpi-index", "on"}, | |
89 | }; | |
01854af2 CH |
90 | const size_t hw_compat_6_2_len = G_N_ELEMENTS(hw_compat_6_2); |
91 | ||
46ce0171 SG |
92 | GlobalProperty hw_compat_6_1[] = { |
93 | { "vhost-user-vsock-device", "seqpacket", "off" }, | |
916b0f0b | 94 | { "nvme-ns", "shared", "off" }, |
46ce0171 | 95 | }; |
52e64f5b YW |
96 | const size_t hw_compat_6_1_len = G_N_ELEMENTS(hw_compat_6_1); |
97 | ||
a6091108 PM |
98 | GlobalProperty hw_compat_6_0[] = { |
99 | { "gpex-pcihost", "allow-unmapped-accesses", "false" }, | |
ff6e1624 | 100 | { "i8042", "extended-state", "false"}, |
3276dde4 | 101 | { "nvme-ns", "eui64-default", "off"}, |
a1d7e475 | 102 | { "e1000", "init-vet", "off" }, |
d8970569 | 103 | { "e1000e", "init-vet", "off" }, |
d6a9378f | 104 | { "vhost-vsock-device", "seqpacket", "off" }, |
a6091108 | 105 | }; |
da7e13c0 CH |
106 | const size_t hw_compat_6_0_len = G_N_ELEMENTS(hw_compat_6_0); |
107 | ||
6be8cf56 IY |
108 | GlobalProperty hw_compat_5_2[] = { |
109 | { "ICH9-LPC", "smm-compat", "on"}, | |
110 | { "PIIX4_PM", "smm-compat", "on"}, | |
fb0b154c | 111 | { "virtio-blk-device", "report-discard-granularity", "off" }, |
3fd641ac | 112 | { "virtio-net-pci-base", "vectors", "3"}, |
fa905f65 | 113 | { "nvme", "msix-exclusive-bar", "on"}, |
6be8cf56 | 114 | }; |
576a00bd CH |
115 | const size_t hw_compat_5_2_len = G_N_ELEMENTS(hw_compat_5_2); |
116 | ||
6a558822 SH |
117 | GlobalProperty hw_compat_5_1[] = { |
118 | { "vhost-scsi", "num_queues", "1"}, | |
a4eef071 | 119 | { "vhost-user-blk", "num-queues", "1"}, |
6a558822 | 120 | { "vhost-user-scsi", "num_queues", "1"}, |
9445e1e1 | 121 | { "virtio-blk-device", "num-queues", "1"}, |
6a558822 | 122 | { "virtio-scsi-device", "num_queues", "1"}, |
6eb7a071 | 123 | { "nvme", "use-intel-id", "on"}, |
b1b0393c | 124 | { "pvpanic", "events", "1"}, /* PVPANIC_PANICKED */ |
e6fa978d | 125 | { "pl011", "migrate-clk", "off" }, |
d83f46d1 | 126 | { "virtio-pci", "x-ats-page-aligned", "off"}, |
6a558822 | 127 | }; |
3ff3c5d3 CH |
128 | const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1); |
129 | ||
7483cbba | 130 | GlobalProperty hw_compat_5_0[] = { |
2ebc2121 | 131 | { "pci-host-bridge", "x-config-reg-migration-enabled", "off" }, |
7483cbba | 132 | { "virtio-balloon-device", "page-poison", "false" }, |
f983ff95 PB |
133 | { "vmport", "x-read-set-eax", "off" }, |
134 | { "vmport", "x-signal-unsupported-cmd", "off" }, | |
135 | { "vmport", "x-report-vmx-type", "off" }, | |
136 | { "vmport", "x-cmds-v2", "off" }, | |
d55f5182 | 137 | { "virtio-device", "x-disable-legacy-check", "true" }, |
7483cbba | 138 | }; |
541aaa1d CH |
139 | const size_t hw_compat_5_0_len = G_N_ELEMENTS(hw_compat_5_0); |
140 | ||
5f258577 | 141 | GlobalProperty hw_compat_4_2[] = { |
c9b7d9ec DP |
142 | { "virtio-blk-device", "queue-size", "128"}, |
143 | { "virtio-scsi-device", "virtqueue_size", "128"}, | |
5f258577 | 144 | { "virtio-blk-device", "x-enable-wce-if-config-wce", "off" }, |
1bf8a989 DP |
145 | { "virtio-blk-device", "seg-max-adjust", "off"}, |
146 | { "virtio-scsi-device", "seg_max_adjust", "off"}, | |
147 | { "vhost-blk-device", "seg_max_adjust", "off"}, | |
7bacaf5f | 148 | { "usb-host", "suppress-remote-wake", "off" }, |
32187f3d | 149 | { "usb-redir", "suppress-remote-wake", "off" }, |
ed71c09f GH |
150 | { "qxl", "revision", "4" }, |
151 | { "qxl-vga", "revision", "4" }, | |
394f0f72 | 152 | { "fw_cfg", "acpi-mr-restore", "false" }, |
c126b4c5 | 153 | { "virtio-device", "use-disabled-flag", "false" }, |
5f258577 EY |
154 | }; |
155 | const size_t hw_compat_4_2_len = G_N_ELEMENTS(hw_compat_4_2); | |
156 | ||
eb1556c4 JS |
157 | GlobalProperty hw_compat_4_1[] = { |
158 | { "virtio-pci", "x-pcie-flr-init", "off" }, | |
159 | }; | |
9aec2e52 CH |
160 | const size_t hw_compat_4_1_len = G_N_ELEMENTS(hw_compat_4_1); |
161 | ||
8e8cbed0 | 162 | GlobalProperty hw_compat_4_0[] = { |
0a719662 GH |
163 | { "VGA", "edid", "false" }, |
164 | { "secondary-vga", "edid", "false" }, | |
165 | { "bochs-display", "edid", "false" }, | |
166 | { "virtio-vga", "edid", "false" }, | |
02501fc3 | 167 | { "virtio-gpu-device", "edid", "false" }, |
e57f2c31 | 168 | { "virtio-device", "use-started", "false" }, |
2bbadb08 | 169 | { "virtio-balloon-device", "qemu-4-0-config-size", "true" }, |
032cfe6a | 170 | { "pl031", "migrate-tick-offset", "false" }, |
0a719662 | 171 | }; |
9bf2650b CH |
172 | const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0); |
173 | ||
abd93cc7 | 174 | GlobalProperty hw_compat_3_1[] = { |
6c36bddf EH |
175 | { "pcie-root-port", "x-speed", "2_5" }, |
176 | { "pcie-root-port", "x-width", "1" }, | |
177 | { "memory-backend-file", "x-use-canonical-path-for-ramblock-id", "true" }, | |
178 | { "memory-backend-memfd", "x-use-canonical-path-for-ramblock-id", "true" }, | |
b6148757 MAL |
179 | { "tpm-crb", "ppi", "false" }, |
180 | { "tpm-tis", "ppi", "false" }, | |
b63e1050 GH |
181 | { "usb-kbd", "serial", "42" }, |
182 | { "usb-mouse", "serial", "42" }, | |
442bac16 | 183 | { "usb-tablet", "serial", "42" }, |
5c81161f SG |
184 | { "virtio-blk-device", "discard", "false" }, |
185 | { "virtio-blk-device", "write-zeroes", "false" }, | |
2bbadb08 | 186 | { "virtio-balloon-device", "qemu-4-0-config-size", "false" }, |
c8557f1b | 187 | { "pcie-root-port-base", "disable-acs", "true" }, /* Added in 4.1 */ |
abd93cc7 MAL |
188 | }; |
189 | const size_t hw_compat_3_1_len = G_N_ELEMENTS(hw_compat_3_1); | |
190 | ||
ddb3235d MAL |
191 | GlobalProperty hw_compat_3_0[] = {}; |
192 | const size_t hw_compat_3_0_len = G_N_ELEMENTS(hw_compat_3_0); | |
193 | ||
0d47310b | 194 | GlobalProperty hw_compat_2_12[] = { |
6c36bddf EH |
195 | { "hda-audio", "use-timer", "false" }, |
196 | { "cirrus-vga", "global-vmstate", "true" }, | |
197 | { "VGA", "global-vmstate", "true" }, | |
198 | { "vmware-svga", "global-vmstate", "true" }, | |
199 | { "qxl-vga", "global-vmstate", "true" }, | |
0d47310b MAL |
200 | }; |
201 | const size_t hw_compat_2_12_len = G_N_ELEMENTS(hw_compat_2_12); | |
202 | ||
43df70a9 | 203 | GlobalProperty hw_compat_2_11[] = { |
6c36bddf EH |
204 | { "hpet", "hpet-offset-saved", "false" }, |
205 | { "virtio-blk-pci", "vectors", "2" }, | |
206 | { "vhost-user-blk-pci", "vectors", "2" }, | |
207 | { "e1000", "migrate_tso_props", "off" }, | |
43df70a9 MAL |
208 | }; |
209 | const size_t hw_compat_2_11_len = G_N_ELEMENTS(hw_compat_2_11); | |
210 | ||
503224f4 | 211 | GlobalProperty hw_compat_2_10[] = { |
6c36bddf EH |
212 | { "virtio-mouse-device", "wheel-axis", "false" }, |
213 | { "virtio-tablet-device", "wheel-axis", "false" }, | |
503224f4 MAL |
214 | }; |
215 | const size_t hw_compat_2_10_len = G_N_ELEMENTS(hw_compat_2_10); | |
216 | ||
3e803152 | 217 | GlobalProperty hw_compat_2_9[] = { |
6c36bddf EH |
218 | { "pci-bridge", "shpc", "off" }, |
219 | { "intel-iommu", "pt", "off" }, | |
220 | { "virtio-net-device", "x-mtu-bypass-backend", "off" }, | |
221 | { "pcie-root-port", "x-migrate-msix", "false" }, | |
3e803152 MAL |
222 | }; |
223 | const size_t hw_compat_2_9_len = G_N_ELEMENTS(hw_compat_2_9); | |
224 | ||
edc24ccd | 225 | GlobalProperty hw_compat_2_8[] = { |
6c36bddf EH |
226 | { "fw_cfg_mem", "x-file-slots", "0x10" }, |
227 | { "fw_cfg_io", "x-file-slots", "0x10" }, | |
228 | { "pflash_cfi01", "old-multiple-chip-handling", "on" }, | |
229 | { "pci-bridge", "shpc", "on" }, | |
230 | { TYPE_PCI_DEVICE, "x-pcie-extcap-init", "off" }, | |
231 | { "virtio-pci", "x-pcie-deverr-init", "off" }, | |
232 | { "virtio-pci", "x-pcie-lnkctl-init", "off" }, | |
233 | { "virtio-pci", "x-pcie-pm-init", "off" }, | |
234 | { "cirrus-vga", "vgamem_mb", "8" }, | |
235 | { "isa-cirrus-vga", "vgamem_mb", "8" }, | |
edc24ccd MAL |
236 | }; |
237 | const size_t hw_compat_2_8_len = G_N_ELEMENTS(hw_compat_2_8); | |
238 | ||
5a995064 | 239 | GlobalProperty hw_compat_2_7[] = { |
6c36bddf EH |
240 | { "virtio-pci", "page-per-vq", "on" }, |
241 | { "virtio-serial-device", "emergency-write", "off" }, | |
242 | { "ioapic", "version", "0x11" }, | |
243 | { "intel-iommu", "x-buggy-eim", "true" }, | |
244 | { "virtio-pci", "x-ignore-backend-features", "on" }, | |
5a995064 MAL |
245 | }; |
246 | const size_t hw_compat_2_7_len = G_N_ELEMENTS(hw_compat_2_7); | |
247 | ||
ff8f261f | 248 | GlobalProperty hw_compat_2_6[] = { |
6c36bddf | 249 | { "virtio-mmio", "format_transport_address", "off" }, |
dd56040d DDAG |
250 | /* Optional because not all virtio-pci devices support legacy mode */ |
251 | { "virtio-pci", "disable-modern", "on", .optional = true }, | |
252 | { "virtio-pci", "disable-legacy", "off", .optional = true }, | |
ff8f261f MAL |
253 | }; |
254 | const size_t hw_compat_2_6_len = G_N_ELEMENTS(hw_compat_2_6); | |
255 | ||
fe759610 | 256 | GlobalProperty hw_compat_2_5[] = { |
6c36bddf EH |
257 | { "isa-fdc", "fallback", "144" }, |
258 | { "pvscsi", "x-old-pci-configuration", "on" }, | |
259 | { "pvscsi", "x-disable-pcie", "on" }, | |
260 | { "vmxnet3", "x-old-msi-offsets", "on" }, | |
261 | { "vmxnet3", "x-disable-pcie", "on" }, | |
fe759610 MAL |
262 | }; |
263 | const size_t hw_compat_2_5_len = G_N_ELEMENTS(hw_compat_2_5); | |
264 | ||
2f99b9c2 | 265 | GlobalProperty hw_compat_2_4[] = { |
11a18c84 PMD |
266 | /* Optional because the 'scsi' property is Linux-only */ |
267 | { "virtio-blk-device", "scsi", "true", .optional = true }, | |
6c36bddf EH |
268 | { "e1000", "extra_mac_registers", "off" }, |
269 | { "virtio-pci", "x-disable-pcie", "on" }, | |
270 | { "virtio-pci", "migrate-extra", "off" }, | |
271 | { "fw_cfg_mem", "dma_enabled", "off" }, | |
272 | { "fw_cfg_io", "dma_enabled", "off" } | |
2f99b9c2 MAL |
273 | }; |
274 | const size_t hw_compat_2_4_len = G_N_ELEMENTS(hw_compat_2_4); | |
275 | ||
8995dd90 | 276 | GlobalProperty hw_compat_2_3[] = { |
6c36bddf EH |
277 | { "virtio-blk-pci", "any_layout", "off" }, |
278 | { "virtio-balloon-pci", "any_layout", "off" }, | |
279 | { "virtio-serial-pci", "any_layout", "off" }, | |
280 | { "virtio-9p-pci", "any_layout", "off" }, | |
281 | { "virtio-rng-pci", "any_layout", "off" }, | |
282 | { TYPE_PCI_DEVICE, "x-pcie-lnksta-dllla", "off" }, | |
283 | { "migration", "send-configuration", "off" }, | |
284 | { "migration", "send-section-footer", "off" }, | |
285 | { "migration", "store-global-state", "off" }, | |
8995dd90 MAL |
286 | }; |
287 | const size_t hw_compat_2_3_len = G_N_ELEMENTS(hw_compat_2_3); | |
288 | ||
1c30044e MAL |
289 | GlobalProperty hw_compat_2_2[] = {}; |
290 | const size_t hw_compat_2_2_len = G_N_ELEMENTS(hw_compat_2_2); | |
291 | ||
c4fc5695 | 292 | GlobalProperty hw_compat_2_1[] = { |
6c36bddf EH |
293 | { "intel-hda", "old_msi_addr", "on" }, |
294 | { "VGA", "qemu-extended-regs", "off" }, | |
295 | { "secondary-vga", "qemu-extended-regs", "off" }, | |
296 | { "virtio-scsi-pci", "any_layout", "off" }, | |
297 | { "usb-mouse", "usb_version", "1" }, | |
298 | { "usb-kbd", "usb_version", "1" }, | |
299 | { "virtio-pci", "virtio-pci-bus-master-bug-migration", "on" }, | |
c4fc5695 MAL |
300 | }; |
301 | const size_t hw_compat_2_1_len = G_N_ELEMENTS(hw_compat_2_1); | |
302 | ||
c5e3c918 PB |
303 | MachineState *current_machine; |
304 | ||
6b1b1440 MA |
305 | static char *machine_get_kernel(Object *obj, Error **errp) |
306 | { | |
307 | MachineState *ms = MACHINE(obj); | |
308 | ||
309 | return g_strdup(ms->kernel_filename); | |
310 | } | |
311 | ||
312 | static void machine_set_kernel(Object *obj, const char *value, Error **errp) | |
313 | { | |
314 | MachineState *ms = MACHINE(obj); | |
315 | ||
556068ee | 316 | g_free(ms->kernel_filename); |
6b1b1440 MA |
317 | ms->kernel_filename = g_strdup(value); |
318 | } | |
319 | ||
320 | static char *machine_get_initrd(Object *obj, Error **errp) | |
321 | { | |
322 | MachineState *ms = MACHINE(obj); | |
323 | ||
324 | return g_strdup(ms->initrd_filename); | |
325 | } | |
326 | ||
327 | static void machine_set_initrd(Object *obj, const char *value, Error **errp) | |
328 | { | |
329 | MachineState *ms = MACHINE(obj); | |
330 | ||
556068ee | 331 | g_free(ms->initrd_filename); |
6b1b1440 MA |
332 | ms->initrd_filename = g_strdup(value); |
333 | } | |
334 | ||
335 | static char *machine_get_append(Object *obj, Error **errp) | |
336 | { | |
337 | MachineState *ms = MACHINE(obj); | |
338 | ||
339 | return g_strdup(ms->kernel_cmdline); | |
340 | } | |
341 | ||
342 | static void machine_set_append(Object *obj, const char *value, Error **errp) | |
343 | { | |
344 | MachineState *ms = MACHINE(obj); | |
345 | ||
556068ee | 346 | g_free(ms->kernel_cmdline); |
6b1b1440 MA |
347 | ms->kernel_cmdline = g_strdup(value); |
348 | } | |
349 | ||
350 | static char *machine_get_dtb(Object *obj, Error **errp) | |
351 | { | |
352 | MachineState *ms = MACHINE(obj); | |
353 | ||
354 | return g_strdup(ms->dtb); | |
355 | } | |
356 | ||
357 | static void machine_set_dtb(Object *obj, const char *value, Error **errp) | |
358 | { | |
359 | MachineState *ms = MACHINE(obj); | |
360 | ||
556068ee | 361 | g_free(ms->dtb); |
6b1b1440 MA |
362 | ms->dtb = g_strdup(value); |
363 | } | |
364 | ||
365 | static char *machine_get_dumpdtb(Object *obj, Error **errp) | |
366 | { | |
367 | MachineState *ms = MACHINE(obj); | |
368 | ||
369 | return g_strdup(ms->dumpdtb); | |
370 | } | |
371 | ||
372 | static void machine_set_dumpdtb(Object *obj, const char *value, Error **errp) | |
373 | { | |
374 | MachineState *ms = MACHINE(obj); | |
375 | ||
556068ee | 376 | g_free(ms->dumpdtb); |
6b1b1440 MA |
377 | ms->dumpdtb = g_strdup(value); |
378 | } | |
379 | ||
380 | static void machine_get_phandle_start(Object *obj, Visitor *v, | |
d7bce999 EB |
381 | const char *name, void *opaque, |
382 | Error **errp) | |
6b1b1440 MA |
383 | { |
384 | MachineState *ms = MACHINE(obj); | |
385 | int64_t value = ms->phandle_start; | |
386 | ||
51e72bc1 | 387 | visit_type_int(v, name, &value, errp); |
6b1b1440 MA |
388 | } |
389 | ||
390 | static void machine_set_phandle_start(Object *obj, Visitor *v, | |
d7bce999 EB |
391 | const char *name, void *opaque, |
392 | Error **errp) | |
6b1b1440 MA |
393 | { |
394 | MachineState *ms = MACHINE(obj); | |
6b1b1440 MA |
395 | int64_t value; |
396 | ||
668f62ec | 397 | if (!visit_type_int(v, name, &value, errp)) { |
6b1b1440 MA |
398 | return; |
399 | } | |
400 | ||
401 | ms->phandle_start = value; | |
402 | } | |
403 | ||
404 | static char *machine_get_dt_compatible(Object *obj, Error **errp) | |
405 | { | |
406 | MachineState *ms = MACHINE(obj); | |
407 | ||
408 | return g_strdup(ms->dt_compatible); | |
409 | } | |
410 | ||
411 | static void machine_set_dt_compatible(Object *obj, const char *value, Error **errp) | |
412 | { | |
413 | MachineState *ms = MACHINE(obj); | |
414 | ||
556068ee | 415 | g_free(ms->dt_compatible); |
6b1b1440 MA |
416 | ms->dt_compatible = g_strdup(value); |
417 | } | |
418 | ||
419 | static bool machine_get_dump_guest_core(Object *obj, Error **errp) | |
420 | { | |
421 | MachineState *ms = MACHINE(obj); | |
422 | ||
423 | return ms->dump_guest_core; | |
424 | } | |
425 | ||
426 | static void machine_set_dump_guest_core(Object *obj, bool value, Error **errp) | |
427 | { | |
428 | MachineState *ms = MACHINE(obj); | |
429 | ||
430 | ms->dump_guest_core = value; | |
431 | } | |
432 | ||
433 | static bool machine_get_mem_merge(Object *obj, Error **errp) | |
434 | { | |
435 | MachineState *ms = MACHINE(obj); | |
436 | ||
437 | return ms->mem_merge; | |
438 | } | |
439 | ||
440 | static void machine_set_mem_merge(Object *obj, bool value, Error **errp) | |
441 | { | |
442 | MachineState *ms = MACHINE(obj); | |
443 | ||
444 | ms->mem_merge = value; | |
445 | } | |
446 | ||
447 | static bool machine_get_usb(Object *obj, Error **errp) | |
448 | { | |
449 | MachineState *ms = MACHINE(obj); | |
450 | ||
451 | return ms->usb; | |
452 | } | |
453 | ||
454 | static void machine_set_usb(Object *obj, bool value, Error **errp) | |
455 | { | |
456 | MachineState *ms = MACHINE(obj); | |
457 | ||
458 | ms->usb = value; | |
c6e76503 | 459 | ms->usb_disabled = !value; |
6b1b1440 MA |
460 | } |
461 | ||
cfc58cf3 EH |
462 | static bool machine_get_graphics(Object *obj, Error **errp) |
463 | { | |
464 | MachineState *ms = MACHINE(obj); | |
465 | ||
466 | return ms->enable_graphics; | |
467 | } | |
468 | ||
469 | static void machine_set_graphics(Object *obj, bool value, Error **errp) | |
470 | { | |
471 | MachineState *ms = MACHINE(obj); | |
472 | ||
473 | ms->enable_graphics = value; | |
474 | } | |
475 | ||
6b1b1440 MA |
476 | static char *machine_get_firmware(Object *obj, Error **errp) |
477 | { | |
478 | MachineState *ms = MACHINE(obj); | |
479 | ||
480 | return g_strdup(ms->firmware); | |
481 | } | |
482 | ||
483 | static void machine_set_firmware(Object *obj, const char *value, Error **errp) | |
484 | { | |
485 | MachineState *ms = MACHINE(obj); | |
486 | ||
556068ee | 487 | g_free(ms->firmware); |
6b1b1440 MA |
488 | ms->firmware = g_strdup(value); |
489 | } | |
490 | ||
9850c604 AG |
491 | static void machine_set_suppress_vmdesc(Object *obj, bool value, Error **errp) |
492 | { | |
493 | MachineState *ms = MACHINE(obj); | |
494 | ||
495 | ms->suppress_vmdesc = value; | |
496 | } | |
497 | ||
498 | static bool machine_get_suppress_vmdesc(Object *obj, Error **errp) | |
499 | { | |
500 | MachineState *ms = MACHINE(obj); | |
501 | ||
502 | return ms->suppress_vmdesc; | |
503 | } | |
504 | ||
db588194 BS |
505 | static char *machine_get_memory_encryption(Object *obj, Error **errp) |
506 | { | |
507 | MachineState *ms = MACHINE(obj); | |
508 | ||
e0292d7c DG |
509 | if (ms->cgs) { |
510 | return g_strdup(object_get_canonical_path_component(OBJECT(ms->cgs))); | |
511 | } | |
512 | ||
513 | return NULL; | |
db588194 BS |
514 | } |
515 | ||
516 | static void machine_set_memory_encryption(Object *obj, const char *value, | |
517 | Error **errp) | |
518 | { | |
e0292d7c DG |
519 | Object *cgs = |
520 | object_resolve_path_component(object_get_objects_root(), value); | |
521 | ||
522 | if (!cgs) { | |
523 | error_setg(errp, "No such memory encryption object '%s'", value); | |
524 | return; | |
525 | } | |
db588194 | 526 | |
e0292d7c DG |
527 | object_property_set_link(obj, "confidential-guest-support", cgs, errp); |
528 | } | |
529 | ||
530 | static void machine_check_confidential_guest_support(const Object *obj, | |
531 | const char *name, | |
532 | Object *new_target, | |
533 | Error **errp) | |
534 | { | |
535 | /* | |
536 | * So far the only constraint is that the target has the | |
537 | * TYPE_CONFIDENTIAL_GUEST_SUPPORT interface, and that's checked | |
538 | * by the QOM core | |
539 | */ | |
db588194 BS |
540 | } |
541 | ||
f6a0d06b EA |
542 | static bool machine_get_nvdimm(Object *obj, Error **errp) |
543 | { | |
544 | MachineState *ms = MACHINE(obj); | |
545 | ||
546 | return ms->nvdimms_state->is_enabled; | |
547 | } | |
548 | ||
549 | static void machine_set_nvdimm(Object *obj, bool value, Error **errp) | |
550 | { | |
551 | MachineState *ms = MACHINE(obj); | |
552 | ||
553 | ms->nvdimms_state->is_enabled = value; | |
554 | } | |
555 | ||
244b3f44 TX |
556 | static bool machine_get_hmat(Object *obj, Error **errp) |
557 | { | |
558 | MachineState *ms = MACHINE(obj); | |
559 | ||
560 | return ms->numa_state->hmat_enabled; | |
561 | } | |
562 | ||
563 | static void machine_set_hmat(Object *obj, bool value, Error **errp) | |
564 | { | |
565 | MachineState *ms = MACHINE(obj); | |
566 | ||
567 | ms->numa_state->hmat_enabled = value; | |
568 | } | |
569 | ||
ce9d03fb PB |
570 | static void machine_get_mem(Object *obj, Visitor *v, const char *name, |
571 | void *opaque, Error **errp) | |
572 | { | |
573 | MachineState *ms = MACHINE(obj); | |
574 | MemorySizeConfiguration mem = { | |
575 | .has_size = true, | |
576 | .size = ms->ram_size, | |
577 | .has_max_size = !!ms->ram_slots, | |
578 | .max_size = ms->maxram_size, | |
579 | .has_slots = !!ms->ram_slots, | |
580 | .slots = ms->ram_slots, | |
581 | }; | |
582 | MemorySizeConfiguration *p_mem = &mem; | |
583 | ||
584 | visit_type_MemorySizeConfiguration(v, name, &p_mem, &error_abort); | |
585 | } | |
586 | ||
587 | static void machine_set_mem(Object *obj, Visitor *v, const char *name, | |
588 | void *opaque, Error **errp) | |
589 | { | |
05e385d2 | 590 | ERRP_GUARD(); |
ce9d03fb PB |
591 | MachineState *ms = MACHINE(obj); |
592 | MachineClass *mc = MACHINE_GET_CLASS(obj); | |
593 | MemorySizeConfiguration *mem; | |
594 | ||
ce9d03fb PB |
595 | if (!visit_type_MemorySizeConfiguration(v, name, &mem, errp)) { |
596 | return; | |
597 | } | |
598 | ||
599 | if (!mem->has_size) { | |
600 | mem->has_size = true; | |
601 | mem->size = mc->default_ram_size; | |
602 | } | |
603 | mem->size = QEMU_ALIGN_UP(mem->size, 8192); | |
604 | if (mc->fixup_ram_size) { | |
605 | mem->size = mc->fixup_ram_size(mem->size); | |
606 | } | |
607 | if ((ram_addr_t)mem->size != mem->size) { | |
608 | error_setg(errp, "ram size too large"); | |
609 | goto out_free; | |
610 | } | |
611 | ||
612 | if (mem->has_max_size) { | |
613 | if (mem->max_size < mem->size) { | |
614 | error_setg(errp, "invalid value of maxmem: " | |
615 | "maximum memory size (0x%" PRIx64 ") must be at least " | |
616 | "the initial memory size (0x%" PRIx64 ")", | |
617 | mem->max_size, mem->size); | |
618 | goto out_free; | |
619 | } | |
620 | if (mem->has_slots && mem->slots && mem->max_size == mem->size) { | |
621 | error_setg(errp, "invalid value of maxmem: " | |
622 | "memory slots were specified but maximum memory size " | |
623 | "(0x%" PRIx64 ") is equal to the initial memory size " | |
624 | "(0x%" PRIx64 ")", mem->max_size, mem->size); | |
625 | goto out_free; | |
626 | } | |
627 | ms->maxram_size = mem->max_size; | |
628 | } else { | |
629 | if (mem->has_slots) { | |
630 | error_setg(errp, "slots specified but no max-size"); | |
631 | goto out_free; | |
632 | } | |
633 | ms->maxram_size = mem->size; | |
634 | } | |
635 | ms->ram_size = mem->size; | |
636 | ms->ram_slots = mem->has_slots ? mem->slots : 0; | |
637 | out_free: | |
638 | qapi_free_MemorySizeConfiguration(mem); | |
639 | } | |
640 | ||
f6a0d06b EA |
641 | static char *machine_get_nvdimm_persistence(Object *obj, Error **errp) |
642 | { | |
643 | MachineState *ms = MACHINE(obj); | |
644 | ||
645 | return g_strdup(ms->nvdimms_state->persistence_string); | |
646 | } | |
647 | ||
648 | static void machine_set_nvdimm_persistence(Object *obj, const char *value, | |
649 | Error **errp) | |
650 | { | |
651 | MachineState *ms = MACHINE(obj); | |
652 | NVDIMMState *nvdimms_state = ms->nvdimms_state; | |
653 | ||
654 | if (strcmp(value, "cpu") == 0) { | |
655 | nvdimms_state->persistence = 3; | |
656 | } else if (strcmp(value, "mem-ctrl") == 0) { | |
657 | nvdimms_state->persistence = 2; | |
658 | } else { | |
659 | error_setg(errp, "-machine nvdimm-persistence=%s: unsupported option", | |
660 | value); | |
661 | return; | |
662 | } | |
663 | ||
664 | g_free(nvdimms_state->persistence_string); | |
665 | nvdimms_state->persistence_string = g_strdup(value); | |
666 | } | |
667 | ||
0bd1909d | 668 | void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type) |
33cd52b5 | 669 | { |
54aa3de7 | 670 | QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type)); |
33cd52b5 AG |
671 | } |
672 | ||
0fb124db | 673 | bool device_is_dynamic_sysbus(MachineClass *mc, DeviceState *dev) |
33cd52b5 | 674 | { |
0fb124db PM |
675 | Object *obj = OBJECT(dev); |
676 | ||
677 | if (!object_dynamic_cast(obj, TYPE_SYS_BUS_DEVICE)) { | |
678 | return false; | |
679 | } | |
33cd52b5 | 680 | |
b5fdf410 DH |
681 | return device_type_is_dynamic_sysbus(mc, object_get_typename(obj)); |
682 | } | |
683 | ||
684 | bool device_type_is_dynamic_sysbus(MachineClass *mc, const char *type) | |
685 | { | |
686 | bool allowed = false; | |
687 | strList *wl; | |
688 | ObjectClass *klass = object_class_by_name(type); | |
689 | ||
0bd1909d EH |
690 | for (wl = mc->allowed_dynamic_sysbus_devices; |
691 | !allowed && wl; | |
692 | wl = wl->next) { | |
b5fdf410 | 693 | allowed |= !!object_class_dynamic_cast(klass, wl->value); |
0bd1909d EH |
694 | } |
695 | ||
0fb124db PM |
696 | return allowed; |
697 | } | |
698 | ||
7a2c7da6 MK |
699 | static char *machine_get_audiodev(Object *obj, Error **errp) |
700 | { | |
701 | MachineState *ms = MACHINE(obj); | |
702 | ||
703 | return g_strdup(ms->audiodev); | |
704 | } | |
705 | ||
706 | static void machine_set_audiodev(Object *obj, const char *value, | |
707 | Error **errp) | |
708 | { | |
709 | MachineState *ms = MACHINE(obj); | |
710 | ||
711 | if (!audio_state_by_name(value, errp)) { | |
712 | return; | |
713 | } | |
714 | ||
715 | g_free(ms->audiodev); | |
716 | ms->audiodev = g_strdup(value); | |
717 | } | |
718 | ||
f2d672c2 IM |
719 | HotpluggableCPUList *machine_query_hotpluggable_cpus(MachineState *machine) |
720 | { | |
721 | int i; | |
f2d672c2 | 722 | HotpluggableCPUList *head = NULL; |
d342eb76 IM |
723 | MachineClass *mc = MACHINE_GET_CLASS(machine); |
724 | ||
725 | /* force board to initialize possible_cpus if it hasn't been done yet */ | |
726 | mc->possible_cpu_arch_ids(machine); | |
f2d672c2 | 727 | |
f2d672c2 | 728 | for (i = 0; i < machine->possible_cpus->len; i++) { |
97e03106 | 729 | CPUState *cpu; |
f2d672c2 IM |
730 | HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1); |
731 | ||
d342eb76 | 732 | cpu_item->type = g_strdup(machine->possible_cpus->cpus[i].type); |
f2d672c2 IM |
733 | cpu_item->vcpus_count = machine->possible_cpus->cpus[i].vcpus_count; |
734 | cpu_item->props = g_memdup(&machine->possible_cpus->cpus[i].props, | |
735 | sizeof(*cpu_item->props)); | |
736 | ||
737 | cpu = machine->possible_cpus->cpus[i].cpu; | |
738 | if (cpu) { | |
97e03106 | 739 | cpu_item->qom_path = object_get_canonical_path(OBJECT(cpu)); |
f2d672c2 | 740 | } |
54aa3de7 | 741 | QAPI_LIST_PREPEND(head, cpu_item); |
f2d672c2 IM |
742 | } |
743 | return head; | |
744 | } | |
745 | ||
7c88e65d IM |
746 | /** |
747 | * machine_set_cpu_numa_node: | |
748 | * @machine: machine object to modify | |
749 | * @props: specifies which cpu objects to assign to | |
750 | * numa node specified by @props.node_id | |
751 | * @errp: if an error occurs, a pointer to an area to store the error | |
752 | * | |
753 | * Associate NUMA node specified by @props.node_id with cpu slots that | |
754 | * match socket/core/thread-ids specified by @props. It's recommended to use | |
755 | * query-hotpluggable-cpus.props values to specify affected cpu slots, | |
756 | * which would lead to exact 1:1 mapping of cpu slots to NUMA node. | |
757 | * | |
758 | * However for CLI convenience it's possible to pass in subset of properties, | |
759 | * which would affect all cpu slots that match it. | |
760 | * Ex for pc machine: | |
761 | * -smp 4,cores=2,sockets=2 -numa node,nodeid=0 -numa node,nodeid=1 \ | |
762 | * -numa cpu,node-id=0,socket_id=0 \ | |
763 | * -numa cpu,node-id=1,socket_id=1 | |
764 | * will assign all child cores of socket 0 to node 0 and | |
765 | * of socket 1 to node 1. | |
766 | * | |
767 | * On attempt of reassigning (already assigned) cpu slot to another NUMA node, | |
768 | * return error. | |
769 | * Empty subset is disallowed and function will return with error in this case. | |
770 | */ | |
771 | void machine_set_cpu_numa_node(MachineState *machine, | |
772 | const CpuInstanceProperties *props, Error **errp) | |
773 | { | |
774 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
244b3f44 | 775 | NodeInfo *numa_info = machine->numa_state->nodes; |
7c88e65d IM |
776 | bool match = false; |
777 | int i; | |
778 | ||
779 | if (!mc->possible_cpu_arch_ids) { | |
780 | error_setg(errp, "mapping of CPUs to NUMA node is not supported"); | |
781 | return; | |
782 | } | |
783 | ||
784 | /* disabling node mapping is not supported, forbid it */ | |
785 | assert(props->has_node_id); | |
786 | ||
787 | /* force board to initialize possible_cpus if it hasn't been done yet */ | |
788 | mc->possible_cpu_arch_ids(machine); | |
789 | ||
790 | for (i = 0; i < machine->possible_cpus->len; i++) { | |
791 | CPUArchId *slot = &machine->possible_cpus->cpus[i]; | |
792 | ||
793 | /* reject unsupported by board properties */ | |
794 | if (props->has_thread_id && !slot->props.has_thread_id) { | |
795 | error_setg(errp, "thread-id is not supported"); | |
796 | return; | |
797 | } | |
798 | ||
799 | if (props->has_core_id && !slot->props.has_core_id) { | |
800 | error_setg(errp, "core-id is not supported"); | |
801 | return; | |
802 | } | |
803 | ||
098de99a ZL |
804 | if (props->has_module_id && !slot->props.has_module_id) { |
805 | error_setg(errp, "module-id is not supported"); | |
806 | return; | |
807 | } | |
808 | ||
1dcf7001 GS |
809 | if (props->has_cluster_id && !slot->props.has_cluster_id) { |
810 | error_setg(errp, "cluster-id is not supported"); | |
811 | return; | |
812 | } | |
813 | ||
7c88e65d IM |
814 | if (props->has_socket_id && !slot->props.has_socket_id) { |
815 | error_setg(errp, "socket-id is not supported"); | |
816 | return; | |
817 | } | |
818 | ||
176d2cda LX |
819 | if (props->has_die_id && !slot->props.has_die_id) { |
820 | error_setg(errp, "die-id is not supported"); | |
821 | return; | |
822 | } | |
823 | ||
7c88e65d IM |
824 | /* skip slots with explicit mismatch */ |
825 | if (props->has_thread_id && props->thread_id != slot->props.thread_id) { | |
826 | continue; | |
827 | } | |
828 | ||
829 | if (props->has_core_id && props->core_id != slot->props.core_id) { | |
830 | continue; | |
831 | } | |
832 | ||
098de99a ZL |
833 | if (props->has_module_id && |
834 | props->module_id != slot->props.module_id) { | |
835 | continue; | |
836 | } | |
837 | ||
1dcf7001 GS |
838 | if (props->has_cluster_id && |
839 | props->cluster_id != slot->props.cluster_id) { | |
840 | continue; | |
841 | } | |
842 | ||
176d2cda LX |
843 | if (props->has_die_id && props->die_id != slot->props.die_id) { |
844 | continue; | |
845 | } | |
846 | ||
7c88e65d IM |
847 | if (props->has_socket_id && props->socket_id != slot->props.socket_id) { |
848 | continue; | |
849 | } | |
850 | ||
851 | /* reject assignment if slot is already assigned, for compatibility | |
852 | * of legacy cpu_index mapping with SPAPR core based mapping do not | |
853 | * error out if cpu thread and matched core have the same node-id */ | |
854 | if (slot->props.has_node_id && | |
855 | slot->props.node_id != props->node_id) { | |
856 | error_setg(errp, "CPU is already assigned to node-id: %" PRId64, | |
857 | slot->props.node_id); | |
858 | return; | |
859 | } | |
860 | ||
861 | /* assign slot to node as it's matched '-numa cpu' key */ | |
862 | match = true; | |
863 | slot->props.node_id = props->node_id; | |
864 | slot->props.has_node_id = props->has_node_id; | |
244b3f44 TX |
865 | |
866 | if (machine->numa_state->hmat_enabled) { | |
867 | if ((numa_info[props->node_id].initiator < MAX_NODES) && | |
868 | (props->node_id != numa_info[props->node_id].initiator)) { | |
869 | error_setg(errp, "The initiator of CPU NUMA node %" PRId64 | |
f74d339c MP |
870 | " should be itself (got %" PRIu16 ")", |
871 | props->node_id, numa_info[props->node_id].initiator); | |
244b3f44 TX |
872 | return; |
873 | } | |
874 | numa_info[props->node_id].has_cpu = true; | |
875 | numa_info[props->node_id].initiator = props->node_id; | |
876 | } | |
7c88e65d IM |
877 | } |
878 | ||
879 | if (!match) { | |
880 | error_setg(errp, "no match found"); | |
881 | } | |
882 | } | |
883 | ||
fe68090e PB |
884 | static void machine_get_smp(Object *obj, Visitor *v, const char *name, |
885 | void *opaque, Error **errp) | |
886 | { | |
887 | MachineState *ms = MACHINE(obj); | |
888 | SMPConfiguration *config = &(SMPConfiguration){ | |
003f230e | 889 | .has_cpus = true, .cpus = ms->smp.cpus, |
5de1aff2 PM |
890 | .has_drawers = true, .drawers = ms->smp.drawers, |
891 | .has_books = true, .books = ms->smp.books, | |
fe68090e PB |
892 | .has_sockets = true, .sockets = ms->smp.sockets, |
893 | .has_dies = true, .dies = ms->smp.dies, | |
864c3b5c | 894 | .has_clusters = true, .clusters = ms->smp.clusters, |
8ec0a463 | 895 | .has_modules = true, .modules = ms->smp.modules, |
003f230e | 896 | .has_cores = true, .cores = ms->smp.cores, |
fe68090e | 897 | .has_threads = true, .threads = ms->smp.threads, |
fe68090e PB |
898 | .has_maxcpus = true, .maxcpus = ms->smp.max_cpus, |
899 | }; | |
864c3b5c | 900 | |
fe68090e PB |
901 | if (!visit_type_SMPConfiguration(v, name, &config, &error_abort)) { |
902 | return; | |
903 | } | |
904 | } | |
905 | ||
906 | static void machine_set_smp(Object *obj, Visitor *v, const char *name, | |
907 | void *opaque, Error **errp) | |
908 | { | |
fe68090e | 909 | MachineState *ms = MACHINE(obj); |
e7f944bb | 910 | g_autoptr(SMPConfiguration) config = NULL; |
fe68090e PB |
911 | |
912 | if (!visit_type_SMPConfiguration(v, name, &config, errp)) { | |
913 | return; | |
914 | } | |
915 | ||
3e2f1498 | 916 | machine_parse_smp_config(ms, config, errp); |
fe68090e PB |
917 | } |
918 | ||
8c4da4b5 PB |
919 | static void machine_get_boot(Object *obj, Visitor *v, const char *name, |
920 | void *opaque, Error **errp) | |
921 | { | |
922 | MachineState *ms = MACHINE(obj); | |
923 | BootConfiguration *config = &ms->boot_config; | |
924 | visit_type_BootConfiguration(v, name, &config, &error_abort); | |
925 | } | |
926 | ||
927 | static void machine_free_boot_config(MachineState *ms) | |
928 | { | |
929 | g_free(ms->boot_config.order); | |
930 | g_free(ms->boot_config.once); | |
931 | g_free(ms->boot_config.splash); | |
932 | } | |
933 | ||
934 | static void machine_copy_boot_config(MachineState *ms, BootConfiguration *config) | |
97ec4d21 PB |
935 | { |
936 | MachineClass *machine_class = MACHINE_GET_CLASS(ms); | |
8c4da4b5 PB |
937 | |
938 | machine_free_boot_config(ms); | |
939 | ms->boot_config = *config; | |
fe8ac1fa | 940 | if (!config->order) { |
8c4da4b5 PB |
941 | ms->boot_config.order = g_strdup(machine_class->default_boot_order); |
942 | } | |
943 | } | |
944 | ||
945 | static void machine_set_boot(Object *obj, Visitor *v, const char *name, | |
946 | void *opaque, Error **errp) | |
947 | { | |
97ec4d21 | 948 | ERRP_GUARD(); |
8c4da4b5 PB |
949 | MachineState *ms = MACHINE(obj); |
950 | BootConfiguration *config = NULL; | |
97ec4d21 | 951 | |
8c4da4b5 | 952 | if (!visit_type_BootConfiguration(v, name, &config, errp)) { |
97ec4d21 PB |
953 | return; |
954 | } | |
fe8ac1fa | 955 | if (config->order) { |
8c4da4b5 | 956 | validate_bootdevices(config->order, errp); |
97ec4d21 | 957 | if (*errp) { |
8c4da4b5 | 958 | goto out_free; |
97ec4d21 | 959 | } |
97ec4d21 | 960 | } |
fe8ac1fa | 961 | if (config->once) { |
8c4da4b5 | 962 | validate_bootdevices(config->once, errp); |
97ec4d21 | 963 | if (*errp) { |
8c4da4b5 | 964 | goto out_free; |
97ec4d21 | 965 | } |
97ec4d21 PB |
966 | } |
967 | ||
8c4da4b5 PB |
968 | machine_copy_boot_config(ms, config); |
969 | /* Strings live in ms->boot_config. */ | |
970 | free(config); | |
971 | return; | |
97ec4d21 | 972 | |
8c4da4b5 PB |
973 | out_free: |
974 | qapi_free_BootConfiguration(config); | |
97ec4d21 PB |
975 | } |
976 | ||
7a2c7da6 MK |
977 | void machine_add_audiodev_property(MachineClass *mc) |
978 | { | |
979 | ObjectClass *oc = OBJECT_CLASS(mc); | |
980 | ||
981 | object_class_property_add_str(oc, "audiodev", | |
982 | machine_get_audiodev, | |
983 | machine_set_audiodev); | |
984 | object_class_property_set_description(oc, "audiodev", | |
985 | "Audiodev to use for default machine devices"); | |
986 | } | |
987 | ||
076b35b5 ND |
988 | static void machine_class_init(ObjectClass *oc, void *data) |
989 | { | |
990 | MachineClass *mc = MACHINE_CLASS(oc); | |
991 | ||
992 | /* Default 128 MB as guest ram size */ | |
d23b6caa | 993 | mc->default_ram_size = 128 * MiB; |
71ae9e94 | 994 | mc->rom_file_has_mr = true; |
26b81df4 | 995 | |
55641213 LV |
996 | /* numa node memory size aligned on 8MB by default. |
997 | * On Linux, each node's border has to be 8MB aligned | |
998 | */ | |
999 | mc->numa_mem_align_shift = 23; | |
1000 | ||
26b81df4 | 1001 | object_class_property_add_str(oc, "kernel", |
d2623129 | 1002 | machine_get_kernel, machine_set_kernel); |
26b81df4 | 1003 | object_class_property_set_description(oc, "kernel", |
7eecec7d | 1004 | "Linux kernel image file"); |
26b81df4 EH |
1005 | |
1006 | object_class_property_add_str(oc, "initrd", | |
d2623129 | 1007 | machine_get_initrd, machine_set_initrd); |
26b81df4 | 1008 | object_class_property_set_description(oc, "initrd", |
7eecec7d | 1009 | "Linux initial ramdisk file"); |
26b81df4 EH |
1010 | |
1011 | object_class_property_add_str(oc, "append", | |
d2623129 | 1012 | machine_get_append, machine_set_append); |
26b81df4 | 1013 | object_class_property_set_description(oc, "append", |
7eecec7d | 1014 | "Linux kernel command line"); |
26b81df4 EH |
1015 | |
1016 | object_class_property_add_str(oc, "dtb", | |
d2623129 | 1017 | machine_get_dtb, machine_set_dtb); |
26b81df4 | 1018 | object_class_property_set_description(oc, "dtb", |
7eecec7d | 1019 | "Linux kernel device tree file"); |
26b81df4 EH |
1020 | |
1021 | object_class_property_add_str(oc, "dumpdtb", | |
d2623129 | 1022 | machine_get_dumpdtb, machine_set_dumpdtb); |
26b81df4 | 1023 | object_class_property_set_description(oc, "dumpdtb", |
7eecec7d | 1024 | "Dump current dtb to a file and quit"); |
26b81df4 | 1025 | |
8c4da4b5 PB |
1026 | object_class_property_add(oc, "boot", "BootConfiguration", |
1027 | machine_get_boot, machine_set_boot, | |
1028 | NULL, NULL); | |
1029 | object_class_property_set_description(oc, "boot", | |
1030 | "Boot configuration"); | |
1031 | ||
fe68090e PB |
1032 | object_class_property_add(oc, "smp", "SMPConfiguration", |
1033 | machine_get_smp, machine_set_smp, | |
1034 | NULL, NULL); | |
1035 | object_class_property_set_description(oc, "smp", | |
1036 | "CPU topology"); | |
1037 | ||
26b81df4 EH |
1038 | object_class_property_add(oc, "phandle-start", "int", |
1039 | machine_get_phandle_start, machine_set_phandle_start, | |
d2623129 | 1040 | NULL, NULL); |
26b81df4 | 1041 | object_class_property_set_description(oc, "phandle-start", |
7eecec7d | 1042 | "The first phandle ID we may generate dynamically"); |
26b81df4 EH |
1043 | |
1044 | object_class_property_add_str(oc, "dt-compatible", | |
d2623129 | 1045 | machine_get_dt_compatible, machine_set_dt_compatible); |
26b81df4 | 1046 | object_class_property_set_description(oc, "dt-compatible", |
7eecec7d | 1047 | "Overrides the \"compatible\" property of the dt root node"); |
26b81df4 EH |
1048 | |
1049 | object_class_property_add_bool(oc, "dump-guest-core", | |
d2623129 | 1050 | machine_get_dump_guest_core, machine_set_dump_guest_core); |
26b81df4 | 1051 | object_class_property_set_description(oc, "dump-guest-core", |
7eecec7d | 1052 | "Include guest memory in a core dump"); |
26b81df4 EH |
1053 | |
1054 | object_class_property_add_bool(oc, "mem-merge", | |
d2623129 | 1055 | machine_get_mem_merge, machine_set_mem_merge); |
26b81df4 | 1056 | object_class_property_set_description(oc, "mem-merge", |
7eecec7d | 1057 | "Enable/disable memory merge support"); |
26b81df4 EH |
1058 | |
1059 | object_class_property_add_bool(oc, "usb", | |
d2623129 | 1060 | machine_get_usb, machine_set_usb); |
26b81df4 | 1061 | object_class_property_set_description(oc, "usb", |
7eecec7d | 1062 | "Set on/off to enable/disable usb"); |
26b81df4 EH |
1063 | |
1064 | object_class_property_add_bool(oc, "graphics", | |
d2623129 | 1065 | machine_get_graphics, machine_set_graphics); |
26b81df4 | 1066 | object_class_property_set_description(oc, "graphics", |
7eecec7d | 1067 | "Set on/off to enable/disable graphics emulation"); |
26b81df4 | 1068 | |
26b81df4 | 1069 | object_class_property_add_str(oc, "firmware", |
d2623129 | 1070 | machine_get_firmware, machine_set_firmware); |
26b81df4 | 1071 | object_class_property_set_description(oc, "firmware", |
7eecec7d | 1072 | "Firmware image"); |
26b81df4 EH |
1073 | |
1074 | object_class_property_add_bool(oc, "suppress-vmdesc", | |
d2623129 | 1075 | machine_get_suppress_vmdesc, machine_set_suppress_vmdesc); |
26b81df4 | 1076 | object_class_property_set_description(oc, "suppress-vmdesc", |
7eecec7d | 1077 | "Set on to disable self-describing migration"); |
26b81df4 | 1078 | |
e0292d7c DG |
1079 | object_class_property_add_link(oc, "confidential-guest-support", |
1080 | TYPE_CONFIDENTIAL_GUEST_SUPPORT, | |
1081 | offsetof(MachineState, cgs), | |
1082 | machine_check_confidential_guest_support, | |
1083 | OBJ_PROP_LINK_STRONG); | |
1084 | object_class_property_set_description(oc, "confidential-guest-support", | |
1085 | "Set confidential guest scheme to support"); | |
1086 | ||
1087 | /* For compatibility */ | |
db588194 | 1088 | object_class_property_add_str(oc, "memory-encryption", |
d2623129 | 1089 | machine_get_memory_encryption, machine_set_memory_encryption); |
db588194 | 1090 | object_class_property_set_description(oc, "memory-encryption", |
7eecec7d | 1091 | "Set memory encryption object to use"); |
acd5b054 | 1092 | |
26f88d84 PB |
1093 | object_class_property_add_link(oc, "memory-backend", TYPE_MEMORY_BACKEND, |
1094 | offsetof(MachineState, memdev), object_property_allow_set_link, | |
1095 | OBJ_PROP_LINK_STRONG); | |
acd5b054 EH |
1096 | object_class_property_set_description(oc, "memory-backend", |
1097 | "Set RAM backend" | |
1098 | "Valid value is ID of hostmem based backend"); | |
ce9d03fb PB |
1099 | |
1100 | object_class_property_add(oc, "memory", "MemorySizeConfiguration", | |
1101 | machine_get_mem, machine_set_mem, | |
1102 | NULL, NULL); | |
1103 | object_class_property_set_description(oc, "memory", | |
1104 | "Memory size configuration"); | |
076b35b5 ND |
1105 | } |
1106 | ||
dcb3d601 EH |
1107 | static void machine_class_base_init(ObjectClass *oc, void *data) |
1108 | { | |
2c920e45 PB |
1109 | MachineClass *mc = MACHINE_CLASS(oc); |
1110 | mc->max_cpus = mc->max_cpus ?: 1; | |
1111 | mc->min_cpus = mc->min_cpus ?: 1; | |
1112 | mc->default_cpus = mc->default_cpus ?: 1; | |
1113 | ||
dcb3d601 EH |
1114 | if (!object_class_is_abstract(oc)) { |
1115 | const char *cname = object_class_get_name(oc); | |
1116 | assert(g_str_has_suffix(cname, TYPE_MACHINE_SUFFIX)); | |
98cec76a EH |
1117 | mc->name = g_strndup(cname, |
1118 | strlen(cname) - strlen(TYPE_MACHINE_SUFFIX)); | |
b66bbee3 | 1119 | mc->compat_props = g_ptr_array_new(); |
dcb3d601 EH |
1120 | } |
1121 | } | |
1122 | ||
6b1b1440 MA |
1123 | static void machine_initfn(Object *obj) |
1124 | { | |
33cd52b5 | 1125 | MachineState *ms = MACHINE(obj); |
b2fc91db | 1126 | MachineClass *mc = MACHINE_GET_CLASS(obj); |
33cd52b5 | 1127 | |
e0d17dfd PB |
1128 | container_get(obj, "/peripheral"); |
1129 | container_get(obj, "/peripheral-anon"); | |
1130 | ||
47c8ca53 | 1131 | ms->dump_guest_core = true; |
75cc7f01 | 1132 | ms->mem_merge = true; |
cfc58cf3 | 1133 | ms->enable_graphics = true; |
58c91595 | 1134 | ms->kernel_cmdline = g_strdup(""); |
ce9d03fb PB |
1135 | ms->ram_size = mc->default_ram_size; |
1136 | ms->maxram_size = mc->default_ram_size; | |
d8870d02 | 1137 | |
f6a0d06b | 1138 | if (mc->nvdimm_supported) { |
f6a0d06b EA |
1139 | ms->nvdimms_state = g_new0(NVDIMMState, 1); |
1140 | object_property_add_bool(obj, "nvdimm", | |
d2623129 | 1141 | machine_get_nvdimm, machine_set_nvdimm); |
f6a0d06b EA |
1142 | object_property_set_description(obj, "nvdimm", |
1143 | "Set on/off to enable/disable " | |
7eecec7d | 1144 | "NVDIMM instantiation"); |
f6a0d06b EA |
1145 | |
1146 | object_property_add_str(obj, "nvdimm-persistence", | |
1147 | machine_get_nvdimm_persistence, | |
d2623129 | 1148 | machine_set_nvdimm_persistence); |
f6a0d06b EA |
1149 | object_property_set_description(obj, "nvdimm-persistence", |
1150 | "Set NVDIMM persistence" | |
7eecec7d | 1151 | "Valid values are cpu, mem-ctrl"); |
f6a0d06b EA |
1152 | } |
1153 | ||
fcd3f2cc | 1154 | if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) { |
aa570207 | 1155 | ms->numa_state = g_new0(NumaState, 1); |
244b3f44 | 1156 | object_property_add_bool(obj, "hmat", |
d2623129 | 1157 | machine_get_hmat, machine_set_hmat); |
244b3f44 TX |
1158 | object_property_set_description(obj, "hmat", |
1159 | "Set on/off to enable/disable " | |
1160 | "ACPI Heterogeneous Memory Attribute " | |
7eecec7d | 1161 | "Table (HMAT)"); |
aa570207 | 1162 | } |
f6a0d06b | 1163 | |
8b0e484c PB |
1164 | /* default to mc->default_cpus */ |
1165 | ms->smp.cpus = mc->default_cpus; | |
1166 | ms->smp.max_cpus = mc->default_cpus; | |
5de1aff2 PM |
1167 | ms->smp.drawers = 1; |
1168 | ms->smp.books = 1; | |
003f230e | 1169 | ms->smp.sockets = 1; |
67872eb8 | 1170 | ms->smp.dies = 1; |
864c3b5c | 1171 | ms->smp.clusters = 1; |
dcba73b4 | 1172 | ms->smp.modules = 1; |
003f230e | 1173 | ms->smp.cores = 1; |
8b0e484c | 1174 | ms->smp.threads = 1; |
8c4da4b5 PB |
1175 | |
1176 | machine_copy_boot_config(ms, &(BootConfiguration){ 0 }); | |
6b1b1440 MA |
1177 | } |
1178 | ||
1179 | static void machine_finalize(Object *obj) | |
1180 | { | |
1181 | MachineState *ms = MACHINE(obj); | |
1182 | ||
8c4da4b5 | 1183 | machine_free_boot_config(ms); |
6b1b1440 MA |
1184 | g_free(ms->kernel_filename); |
1185 | g_free(ms->initrd_filename); | |
1186 | g_free(ms->kernel_cmdline); | |
1187 | g_free(ms->dtb); | |
1188 | g_free(ms->dumpdtb); | |
1189 | g_free(ms->dt_compatible); | |
1190 | g_free(ms->firmware); | |
2ff4f67c | 1191 | g_free(ms->device_memory); |
f6a0d06b | 1192 | g_free(ms->nvdimms_state); |
aa570207 | 1193 | g_free(ms->numa_state); |
7a2c7da6 | 1194 | g_free(ms->audiodev); |
6b1b1440 | 1195 | } |
36d20cb2 | 1196 | |
5e97b623 MA |
1197 | bool machine_usb(MachineState *machine) |
1198 | { | |
1199 | return machine->usb; | |
1200 | } | |
1201 | ||
6cabe7fa MA |
1202 | int machine_phandle_start(MachineState *machine) |
1203 | { | |
1204 | return machine->phandle_start; | |
1205 | } | |
1206 | ||
47c8ca53 MA |
1207 | bool machine_dump_guest_core(MachineState *machine) |
1208 | { | |
1209 | return machine->dump_guest_core; | |
1210 | } | |
1211 | ||
75cc7f01 MA |
1212 | bool machine_mem_merge(MachineState *machine) |
1213 | { | |
1214 | return machine->mem_merge; | |
1215 | } | |
1216 | ||
37662d85 XL |
1217 | bool machine_require_guest_memfd(MachineState *machine) |
1218 | { | |
1219 | return machine->require_guest_memfd; | |
1220 | } | |
1221 | ||
ec78f811 IM |
1222 | static char *cpu_slot_to_string(const CPUArchId *cpu) |
1223 | { | |
1224 | GString *s = g_string_new(NULL); | |
1225 | if (cpu->props.has_socket_id) { | |
1226 | g_string_append_printf(s, "socket-id: %"PRId64, cpu->props.socket_id); | |
1227 | } | |
176d2cda | 1228 | if (cpu->props.has_die_id) { |
3a23a0c0 YW |
1229 | if (s->len) { |
1230 | g_string_append_printf(s, ", "); | |
1231 | } | |
176d2cda LX |
1232 | g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); |
1233 | } | |
1dcf7001 GS |
1234 | if (cpu->props.has_cluster_id) { |
1235 | if (s->len) { | |
1236 | g_string_append_printf(s, ", "); | |
1237 | } | |
1238 | g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluster_id); | |
1239 | } | |
098de99a ZL |
1240 | if (cpu->props.has_module_id) { |
1241 | if (s->len) { | |
1242 | g_string_append_printf(s, ", "); | |
1243 | } | |
1244 | g_string_append_printf(s, "module-id: %"PRId64, cpu->props.module_id); | |
1245 | } | |
ec78f811 IM |
1246 | if (cpu->props.has_core_id) { |
1247 | if (s->len) { | |
1248 | g_string_append_printf(s, ", "); | |
1249 | } | |
1250 | g_string_append_printf(s, "core-id: %"PRId64, cpu->props.core_id); | |
1251 | } | |
1252 | if (cpu->props.has_thread_id) { | |
1253 | if (s->len) { | |
1254 | g_string_append_printf(s, ", "); | |
1255 | } | |
1256 | g_string_append_printf(s, "thread-id: %"PRId64, cpu->props.thread_id); | |
1257 | } | |
1258 | return g_string_free(s, false); | |
1259 | } | |
1260 | ||
244b3f44 TX |
1261 | static void numa_validate_initiator(NumaState *numa_state) |
1262 | { | |
1263 | int i; | |
1264 | NodeInfo *numa_info = numa_state->nodes; | |
1265 | ||
1266 | for (i = 0; i < numa_state->num_nodes; i++) { | |
1267 | if (numa_info[i].initiator == MAX_NODES) { | |
83bcae98 | 1268 | continue; |
244b3f44 TX |
1269 | } |
1270 | ||
1271 | if (!numa_info[numa_info[i].initiator].present) { | |
1272 | error_report("NUMA node %" PRIu16 " is missing, use " | |
1273 | "'-numa node' option to declare it first", | |
1274 | numa_info[i].initiator); | |
1275 | exit(1); | |
1276 | } | |
1277 | ||
1278 | if (!numa_info[numa_info[i].initiator].has_cpu) { | |
1279 | error_report("The initiator of NUMA node %d is invalid", i); | |
1280 | exit(1); | |
1281 | } | |
1282 | } | |
1283 | } | |
1284 | ||
7a3099fc | 1285 | static void machine_numa_finish_cpu_init(MachineState *machine) |
ec78f811 IM |
1286 | { |
1287 | int i; | |
60bed6a3 | 1288 | bool default_mapping; |
ec78f811 IM |
1289 | GString *s = g_string_new(NULL); |
1290 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
1291 | const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(machine); | |
1292 | ||
aa570207 | 1293 | assert(machine->numa_state->num_nodes); |
60bed6a3 IM |
1294 | for (i = 0; i < possible_cpus->len; i++) { |
1295 | if (possible_cpus->cpus[i].props.has_node_id) { | |
1296 | break; | |
1297 | } | |
1298 | } | |
1299 | default_mapping = (i == possible_cpus->len); | |
1300 | ||
ec78f811 IM |
1301 | for (i = 0; i < possible_cpus->len; i++) { |
1302 | const CPUArchId *cpu_slot = &possible_cpus->cpus[i]; | |
1303 | ||
ec78f811 | 1304 | if (!cpu_slot->props.has_node_id) { |
d41f3e75 IM |
1305 | /* fetch default mapping from board and enable it */ |
1306 | CpuInstanceProperties props = cpu_slot->props; | |
1307 | ||
79e07936 | 1308 | props.node_id = mc->get_default_cpu_node_id(machine, i); |
d41f3e75 | 1309 | if (!default_mapping) { |
60bed6a3 IM |
1310 | /* record slots with not set mapping, |
1311 | * TODO: make it hard error in future */ | |
1312 | char *cpu_str = cpu_slot_to_string(cpu_slot); | |
1313 | g_string_append_printf(s, "%sCPU %d [%s]", | |
1314 | s->len ? ", " : "", i, cpu_str); | |
1315 | g_free(cpu_str); | |
d41f3e75 IM |
1316 | |
1317 | /* non mapped cpus used to fallback to node 0 */ | |
1318 | props.node_id = 0; | |
60bed6a3 | 1319 | } |
d41f3e75 IM |
1320 | |
1321 | props.has_node_id = true; | |
1322 | machine_set_cpu_numa_node(machine, &props, &error_fatal); | |
ec78f811 IM |
1323 | } |
1324 | } | |
244b3f44 TX |
1325 | |
1326 | if (machine->numa_state->hmat_enabled) { | |
1327 | numa_validate_initiator(machine->numa_state); | |
1328 | } | |
1329 | ||
c6ff347c | 1330 | if (s->len && !qtest_enabled()) { |
3dc6f869 AF |
1331 | warn_report("CPU(s) not present in any NUMA nodes: %s", |
1332 | s->str); | |
1333 | warn_report("All CPU(s) up to maxcpus should be described " | |
1334 | "in NUMA config, ability to start up with partial NUMA " | |
1335 | "mappings is obsoleted and will be removed in future"); | |
ec78f811 IM |
1336 | } |
1337 | g_string_free(s, true); | |
1338 | } | |
1339 | ||
a494fdb7 GS |
1340 | static void validate_cpu_cluster_to_numa_boundary(MachineState *ms) |
1341 | { | |
1342 | MachineClass *mc = MACHINE_GET_CLASS(ms); | |
1343 | NumaState *state = ms->numa_state; | |
1344 | const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); | |
1345 | const CPUArchId *cpus = possible_cpus->cpus; | |
1346 | int i, j; | |
1347 | ||
393d5c5b | 1348 | if (qtest_enabled() || state->num_nodes <= 1 || possible_cpus->len <= 1) { |
a494fdb7 GS |
1349 | return; |
1350 | } | |
1351 | ||
1352 | /* | |
1353 | * The Linux scheduling domain can't be parsed when the multiple CPUs | |
1354 | * in one cluster have been associated with different NUMA nodes. However, | |
1355 | * it's fine to associate one NUMA node with CPUs in different clusters. | |
1356 | */ | |
1357 | for (i = 0; i < possible_cpus->len; i++) { | |
1358 | for (j = i + 1; j < possible_cpus->len; j++) { | |
1359 | if (cpus[i].props.has_socket_id && | |
1360 | cpus[i].props.has_cluster_id && | |
1361 | cpus[i].props.has_node_id && | |
1362 | cpus[j].props.has_socket_id && | |
1363 | cpus[j].props.has_cluster_id && | |
1364 | cpus[j].props.has_node_id && | |
1365 | cpus[i].props.socket_id == cpus[j].props.socket_id && | |
1366 | cpus[i].props.cluster_id == cpus[j].props.cluster_id && | |
1367 | cpus[i].props.node_id != cpus[j].props.node_id) { | |
1368 | warn_report("CPU-%d and CPU-%d in socket-%" PRId64 "-cluster-%" PRId64 | |
1369 | " have been associated with node-%" PRId64 " and node-%" PRId64 | |
1370 | " respectively. It can cause OSes like Linux to" | |
1371 | " misbehave", i, j, cpus[i].props.socket_id, | |
1372 | cpus[i].props.cluster_id, cpus[i].props.node_id, | |
1373 | cpus[j].props.node_id); | |
1374 | } | |
1375 | } | |
1376 | } | |
1377 | } | |
1378 | ||
82b911aa IM |
1379 | MemoryRegion *machine_consume_memdev(MachineState *machine, |
1380 | HostMemoryBackend *backend) | |
1381 | { | |
1382 | MemoryRegion *ret = host_memory_backend_get_memory(backend); | |
1383 | ||
eef3a7ab | 1384 | if (host_memory_backend_is_mapped(backend)) { |
7a309cc9 MA |
1385 | error_report("memory backend %s can't be used multiple times.", |
1386 | object_get_canonical_path_component(OBJECT(backend))); | |
82b911aa IM |
1387 | exit(EXIT_FAILURE); |
1388 | } | |
1389 | host_memory_backend_set_mapped(backend, true); | |
1390 | vmstate_register_ram_global(ret); | |
1391 | return ret; | |
1392 | } | |
1393 | ||
26f88d84 PB |
1394 | static bool create_default_memdev(MachineState *ms, const char *path, Error **errp) |
1395 | { | |
1396 | Object *obj; | |
1397 | MachineClass *mc = MACHINE_GET_CLASS(ms); | |
1398 | bool r = false; | |
1399 | ||
1400 | obj = object_new(path ? TYPE_MEMORY_BACKEND_FILE : TYPE_MEMORY_BACKEND_RAM); | |
1401 | if (path) { | |
1402 | if (!object_property_set_str(obj, "mem-path", path, errp)) { | |
1403 | goto out; | |
1404 | } | |
1405 | } | |
1406 | if (!object_property_set_int(obj, "size", ms->ram_size, errp)) { | |
1407 | goto out; | |
1408 | } | |
1409 | object_property_add_child(object_get_objects_root(), mc->default_ram_id, | |
1410 | obj); | |
1411 | /* Ensure backend's memory region name is equal to mc->default_ram_id */ | |
1412 | if (!object_property_set_bool(obj, "x-use-canonical-path-for-ramblock-id", | |
1413 | false, errp)) { | |
1414 | goto out; | |
1415 | } | |
1416 | if (!user_creatable_complete(USER_CREATABLE(obj), errp)) { | |
1417 | goto out; | |
1418 | } | |
1419 | r = object_property_set_link(OBJECT(ms), "memory-backend", obj, errp); | |
1420 | ||
1421 | out: | |
1422 | object_unref(obj); | |
1423 | return r; | |
1424 | } | |
1425 | ||
62b4a227 PMD |
1426 | const char *machine_class_default_cpu_type(MachineClass *mc) |
1427 | { | |
1428 | if (mc->valid_cpu_types && !mc->valid_cpu_types[1]) { | |
1429 | /* Only a single CPU type allowed: use it as default. */ | |
1430 | return mc->valid_cpu_types[0]; | |
1431 | } | |
1432 | return mc->default_cpu_type; | |
1433 | } | |
26f88d84 | 1434 | |
acbadc5a GS |
1435 | static bool is_cpu_type_supported(const MachineState *machine, Error **errp) |
1436 | { | |
1437 | MachineClass *mc = MACHINE_GET_CLASS(machine); | |
1438 | ObjectClass *oc = object_class_by_name(machine->cpu_type); | |
1439 | CPUClass *cc; | |
1440 | int i; | |
1441 | ||
1442 | /* | |
1443 | * Check if the user specified CPU type is supported when the valid | |
1444 | * CPU types have been determined. Note that the user specified CPU | |
1445 | * type is provided through '-cpu' option. | |
1446 | */ | |
1447 | if (mc->valid_cpu_types) { | |
e702cbc1 | 1448 | assert(mc->valid_cpu_types[0] != NULL); |
acbadc5a GS |
1449 | for (i = 0; mc->valid_cpu_types[i]; i++) { |
1450 | if (object_class_dynamic_cast(oc, mc->valid_cpu_types[i])) { | |
1451 | break; | |
1452 | } | |
1453 | } | |
1454 | ||
1455 | /* The user specified CPU type isn't valid */ | |
1456 | if (!mc->valid_cpu_types[i]) { | |
5422d2a8 GS |
1457 | g_autofree char *requested = cpu_model_from_type(machine->cpu_type); |
1458 | error_setg(errp, "Invalid CPU model: %s", requested); | |
e702cbc1 | 1459 | if (!mc->valid_cpu_types[1]) { |
5422d2a8 GS |
1460 | g_autofree char *model = cpu_model_from_type( |
1461 | mc->valid_cpu_types[0]); | |
1462 | error_append_hint(errp, "The only valid type is: %s\n", model); | |
e702cbc1 | 1463 | } else { |
5422d2a8 | 1464 | error_append_hint(errp, "The valid models are: "); |
e702cbc1 | 1465 | for (i = 0; mc->valid_cpu_types[i]; i++) { |
5422d2a8 GS |
1466 | g_autofree char *model = cpu_model_from_type( |
1467 | mc->valid_cpu_types[i]); | |
e702cbc1 | 1468 | error_append_hint(errp, "%s%s", |
5422d2a8 | 1469 | model, |
e702cbc1 GS |
1470 | mc->valid_cpu_types[i + 1] ? ", " : ""); |
1471 | } | |
1472 | error_append_hint(errp, "\n"); | |
acbadc5a GS |
1473 | } |
1474 | ||
acbadc5a GS |
1475 | return false; |
1476 | } | |
1477 | } | |
1478 | ||
1479 | /* Check if CPU type is deprecated and warn if so */ | |
1480 | cc = CPU_CLASS(oc); | |
e702cbc1 GS |
1481 | assert(cc != NULL); |
1482 | if (cc->deprecation_note) { | |
acbadc5a GS |
1483 | warn_report("CPU model %s is deprecated -- %s", |
1484 | machine->cpu_type, cc->deprecation_note); | |
1485 | } | |
1486 | ||
1487 | return true; | |
1488 | } | |
1489 | ||
26f88d84 | 1490 | void machine_run_board_init(MachineState *machine, const char *mem_path, Error **errp) |
482dfe9a | 1491 | { |
41ddcd23 | 1492 | ERRP_GUARD(); |
482dfe9a | 1493 | MachineClass *machine_class = MACHINE_GET_CLASS(machine); |
ec78f811 | 1494 | |
a3ef9bfb PB |
1495 | /* This checkpoint is required by replay to separate prior clock |
1496 | reading from the other reads, because timer polling functions query | |
1497 | clock values from the log. */ | |
1498 | replay_checkpoint(CHECKPOINT_INIT); | |
1499 | ||
fb56b7a0 PB |
1500 | if (!xen_enabled()) { |
1501 | /* On 32-bit hosts, QEMU is limited by virtual address space */ | |
1502 | if (machine->ram_size > (2047 << 20) && HOST_LONG_BITS == 32) { | |
1503 | error_setg(errp, "at most 2047 MB RAM can be simulated"); | |
1504 | return; | |
1505 | } | |
1506 | } | |
1507 | ||
1508 | if (machine->memdev) { | |
1509 | ram_addr_t backend_size = object_property_get_uint(OBJECT(machine->memdev), | |
1510 | "size", &error_abort); | |
1511 | if (backend_size != machine->ram_size) { | |
1512 | error_setg(errp, "Machine memory size does not match the size of the memory backend"); | |
1513 | return; | |
1514 | } | |
1515 | } else if (machine_class->default_ram_id && machine->ram_size && | |
1516 | numa_uses_legacy_mem()) { | |
a37531f2 IM |
1517 | if (object_property_find(object_get_objects_root(), |
1518 | machine_class->default_ram_id)) { | |
41ddcd23 DH |
1519 | error_setg(errp, "object's id '%s' is reserved for the default" |
1520 | " RAM backend, it can't be used for any other purposes", | |
1521 | machine_class->default_ram_id); | |
1522 | error_append_hint(errp, | |
1523 | "Change the object's 'id' to something else or disable" | |
1524 | " automatic creation of the default RAM backend by setting" | |
1525 | " 'memory-backend=%s' with '-machine'.\n", | |
a37531f2 IM |
1526 | machine_class->default_ram_id); |
1527 | return; | |
1528 | } | |
26f88d84 PB |
1529 | if (!create_default_memdev(current_machine, mem_path, errp)) { |
1530 | return; | |
1531 | } | |
82b911aa IM |
1532 | } |
1533 | ||
fcd3f2cc | 1534 | if (machine->numa_state) { |
aa570207 TX |
1535 | numa_complete_configuration(machine); |
1536 | if (machine->numa_state->num_nodes) { | |
1537 | machine_numa_finish_cpu_init(machine); | |
a494fdb7 GS |
1538 | if (machine_class->cpu_cluster_has_numa_boundary) { |
1539 | validate_cpu_cluster_to_numa_boundary(machine); | |
1540 | } | |
aa570207 | 1541 | } |
3aeaac8f | 1542 | } |
c9cf636d | 1543 | |
26f88d84 PB |
1544 | if (!machine->ram && machine->memdev) { |
1545 | machine->ram = machine_consume_memdev(machine, machine->memdev); | |
1546 | } | |
1547 | ||
acbadc5a GS |
1548 | /* Check if the CPU type is supported */ |
1549 | if (machine->cpu_type && !is_cpu_type_supported(machine, errp)) { | |
1550 | return; | |
61ad65d0 RH |
1551 | } |
1552 | ||
e0292d7c | 1553 | if (machine->cgs) { |
6e6a6ca7 | 1554 | /* |
e0292d7c | 1555 | * With confidential guests, the host can't see the real |
6e6a6ca7 DG |
1556 | * contents of RAM, so there's no point in it trying to merge |
1557 | * areas. | |
1558 | */ | |
1559 | machine_set_mem_merge(OBJECT(machine), false, &error_abort); | |
9f88a7a3 DG |
1560 | |
1561 | /* | |
1562 | * Virtio devices can't count on directly accessing guest | |
1563 | * memory, so they need iommu_platform=on to use normal DMA | |
1564 | * mechanisms. That requires also disabling legacy virtio | |
1565 | * support for those virtio pci devices which allow it. | |
1566 | */ | |
1567 | object_register_sugar_prop(TYPE_VIRTIO_PCI, "disable-legacy", | |
1568 | "on", true); | |
1569 | object_register_sugar_prop(TYPE_VIRTIO_DEVICE, "iommu_platform", | |
1570 | "on", false); | |
6e6a6ca7 DG |
1571 | } |
1572 | ||
92242f34 | 1573 | accel_init_interfaces(ACCEL_GET_CLASS(machine->accelerator)); |
482dfe9a | 1574 | machine_class->init(machine); |
2f181fbd | 1575 | phase_advance(PHASE_MACHINE_INITIALIZED); |
482dfe9a IM |
1576 | } |
1577 | ||
6b21670c PB |
1578 | static NotifierList machine_init_done_notifiers = |
1579 | NOTIFIER_LIST_INITIALIZER(machine_init_done_notifiers); | |
1580 | ||
6b21670c PB |
1581 | void qemu_add_machine_init_done_notifier(Notifier *notify) |
1582 | { | |
1583 | notifier_list_add(&machine_init_done_notifiers, notify); | |
2f181fbd | 1584 | if (phase_check(PHASE_MACHINE_READY)) { |
6b21670c PB |
1585 | notify->notify(notify, NULL); |
1586 | } | |
1587 | } | |
1588 | ||
1589 | void qemu_remove_machine_init_done_notifier(Notifier *notify) | |
1590 | { | |
1591 | notifier_remove(notify); | |
1592 | } | |
1593 | ||
f66dc873 | 1594 | void qdev_machine_creation_done(void) |
6b21670c | 1595 | { |
f66dc873 PB |
1596 | cpu_synchronize_all_post_init(); |
1597 | ||
fe8ac1fa | 1598 | if (current_machine->boot_config.once) { |
97ec4d21 PB |
1599 | qemu_boot_set(current_machine->boot_config.once, &error_fatal); |
1600 | qemu_register_reset(restore_boot_order, g_strdup(current_machine->boot_config.order)); | |
f66dc873 PB |
1601 | } |
1602 | ||
1603 | /* | |
1604 | * ok, initial machine setup is done, starting from now we can | |
1605 | * only create hotpluggable devices | |
1606 | */ | |
2f181fbd | 1607 | phase_advance(PHASE_MACHINE_READY); |
f66dc873 PB |
1608 | qdev_assert_realized_properly(); |
1609 | ||
1610 | /* TODO: once all bus devices are qdevified, this should be done | |
1611 | * when bus is created by qdev.c */ | |
1612 | /* | |
0441e35f PM |
1613 | * This is where we arrange for the sysbus to be reset when the |
1614 | * whole simulation is reset. In turn, resetting the sysbus will cause | |
f66dc873 PB |
1615 | * all devices hanging off it (and all their child buses, recursively) |
1616 | * to be reset. Note that this will *not* reset any Device objects | |
1617 | * which are not attached to some part of the qbus tree! | |
1618 | */ | |
0441e35f | 1619 | qemu_register_resettable(OBJECT(sysbus_get_default())); |
f66dc873 | 1620 | |
6b21670c | 1621 | notifier_list_notify(&machine_init_done_notifiers, NULL); |
f66dc873 PB |
1622 | |
1623 | if (rom_check_and_register_reset() != 0) { | |
f66dc873 PB |
1624 | exit(1); |
1625 | } | |
1626 | ||
1627 | replay_start(); | |
1628 | ||
1629 | /* This checkpoint is required by replay to separate prior clock | |
1630 | reading from the other reads, because timer polling functions query | |
1631 | clock values from the log. */ | |
1632 | replay_checkpoint(CHECKPOINT_RESET); | |
1633 | qemu_system_reset(SHUTDOWN_CAUSE_NONE); | |
1634 | register_global_state(); | |
6b21670c PB |
1635 | } |
1636 | ||
36d20cb2 MA |
1637 | static const TypeInfo machine_info = { |
1638 | .name = TYPE_MACHINE, | |
1639 | .parent = TYPE_OBJECT, | |
1640 | .abstract = true, | |
1641 | .class_size = sizeof(MachineClass), | |
076b35b5 | 1642 | .class_init = machine_class_init, |
dcb3d601 | 1643 | .class_base_init = machine_class_base_init, |
36d20cb2 | 1644 | .instance_size = sizeof(MachineState), |
6b1b1440 MA |
1645 | .instance_init = machine_initfn, |
1646 | .instance_finalize = machine_finalize, | |
36d20cb2 MA |
1647 | }; |
1648 | ||
1649 | static void machine_register_types(void) | |
1650 | { | |
1651 | type_register_static(&machine_info); | |
1652 | } | |
1653 | ||
1654 | type_init(machine_register_types) |