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Commit | Line | Data |
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5fafdf24 | 1 | /* |
423f0742 PB |
2 | * General purpose implementation of a simple periodic countdown timer. |
3 | * | |
4 | * Copyright (c) 2007 CodeSourcery. | |
5 | * | |
8e31bf38 | 6 | * This code is licensed under the GNU LGPL. |
423f0742 | 7 | */ |
d6454270 | 8 | |
18c86e2b | 9 | #include "qemu/osdep.h" |
83c9f4ca | 10 | #include "hw/ptimer.h" |
d6454270 | 11 | #include "migration/vmstate.h" |
1de7afc9 | 12 | #include "qemu/host-utils.h" |
8a354bd9 | 13 | #include "sysemu/replay.h" |
740b1759 | 14 | #include "sysemu/cpu-timers.h" |
2a8b5870 | 15 | #include "sysemu/qtest.h" |
072bdb07 | 16 | #include "block/aio.h" |
d2528bdc | 17 | #include "sysemu/cpus.h" |
ad140dad | 18 | #include "hw/clock.h" |
423f0742 | 19 | |
22471b8a DO |
20 | #define DELTA_ADJUST 1 |
21 | #define DELTA_NO_ADJUST -1 | |
2b5c0322 | 22 | |
423f0742 PB |
23 | struct ptimer_state |
24 | { | |
852f771e | 25 | uint8_t enabled; /* 0 = disabled, 1 = periodic, 2 = oneshot. */ |
8d05ea8a BS |
26 | uint64_t limit; |
27 | uint64_t delta; | |
423f0742 PB |
28 | uint32_t period_frac; |
29 | int64_t period; | |
30 | int64_t last_event; | |
31 | int64_t next_event; | |
e7ea81c3 | 32 | uint8_t policy_mask; |
423f0742 | 33 | QEMUTimer *timer; |
78b6eaa6 PM |
34 | ptimer_cb callback; |
35 | void *callback_opaque; | |
36 | /* | |
37 | * These track whether we're in a transaction block, and if we | |
38 | * need to do a timer reload when the block finishes. They don't | |
39 | * need to be migrated because migration can never happen in the | |
40 | * middle of a transaction block. | |
41 | */ | |
42 | bool in_transaction; | |
43 | bool need_reload; | |
423f0742 PB |
44 | }; |
45 | ||
46 | /* Use a bottom-half routine to avoid reentrancy issues. */ | |
47 | static void ptimer_trigger(ptimer_state *s) | |
48 | { | |
af2a580f | 49 | s->callback(s->callback_opaque); |
423f0742 PB |
50 | } |
51 | ||
2b5c0322 | 52 | static void ptimer_reload(ptimer_state *s, int delta_adjust) |
423f0742 | 53 | { |
78b6eaa6 PM |
54 | uint32_t period_frac; |
55 | uint64_t period; | |
56 | uint64_t delta; | |
086ede32 | 57 | bool suppress_trigger = false; |
e91171e3 | 58 | |
086ede32 PM |
59 | /* |
60 | * Note that if delta_adjust is 0 then we must be here because of | |
61 | * a count register write or timer start, not because of timer expiry. | |
62 | * In that case the policy might require us to suppress the timer trigger | |
63 | * that we would otherwise generate for a zero delta. | |
64 | */ | |
65 | if (delta_adjust == 0 && | |
66 | (s->policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT)) { | |
67 | suppress_trigger = true; | |
68 | } | |
78b6eaa6 | 69 | if (s->delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER) |
086ede32 | 70 | && !suppress_trigger) { |
423f0742 | 71 | ptimer_trigger(s); |
22471b8a DO |
72 | } |
73 | ||
78b6eaa6 PM |
74 | /* |
75 | * Note that ptimer_trigger() might call the device callback function, | |
76 | * which can then modify timer state, so we must not cache any fields | |
77 | * from ptimer_state until after we have called it. | |
78 | */ | |
79 | delta = s->delta; | |
80 | period = s->period; | |
81 | period_frac = s->period_frac; | |
82 | ||
3f6e6a13 | 83 | if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_RELOAD)) { |
2b5c0322 | 84 | delta = s->delta = s->limit; |
423f0742 | 85 | } |
ef0a9984 DO |
86 | |
87 | if (s->period == 0) { | |
2a8b5870 DO |
88 | if (!qtest_enabled()) { |
89 | fprintf(stderr, "Timer with period zero, disabling\n"); | |
90 | } | |
780d23e5 | 91 | timer_del(s->timer); |
423f0742 PB |
92 | s->enabled = 0; |
93 | return; | |
94 | } | |
95 | ||
2b5c0322 | 96 | if (s->policy_mask & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD) { |
22471b8a DO |
97 | if (delta_adjust != DELTA_NO_ADJUST) { |
98 | delta += delta_adjust; | |
99 | } | |
2b5c0322 DO |
100 | } |
101 | ||
ef0a9984 DO |
102 | if (delta == 0 && (s->policy_mask & PTIMER_POLICY_CONTINUOUS_TRIGGER)) { |
103 | if (s->enabled == 1 && s->limit == 0) { | |
104 | delta = 1; | |
105 | } | |
106 | } | |
107 | ||
22471b8a DO |
108 | if (delta == 0 && (s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)) { |
109 | if (delta_adjust != DELTA_NO_ADJUST) { | |
110 | delta = 1; | |
111 | } | |
112 | } | |
113 | ||
3f6e6a13 DO |
114 | if (delta == 0 && (s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_RELOAD)) { |
115 | if (s->enabled == 1 && s->limit != 0) { | |
116 | delta = 1; | |
117 | } | |
118 | } | |
119 | ||
ef0a9984 | 120 | if (delta == 0) { |
68d59c6d PM |
121 | if (s->enabled == 0) { |
122 | /* trigger callback disabled the timer already */ | |
123 | return; | |
124 | } | |
ef0a9984 DO |
125 | if (!qtest_enabled()) { |
126 | fprintf(stderr, "Timer with delta zero, disabling\n"); | |
127 | } | |
128 | timer_del(s->timer); | |
129 | s->enabled = 0; | |
130 | return; | |
131 | } | |
132 | ||
e91171e3 DO |
133 | /* |
134 | * Artificially limit timeout rate to something | |
135 | * achievable under QEMU. Otherwise, QEMU spends all | |
136 | * its time generating timer interrupts, and there | |
137 | * is no forward progress. | |
138 | * About ten microseconds is the fastest that really works | |
139 | * on the current generation of host machines. | |
140 | */ | |
141 | ||
740b1759 CF |
142 | if (s->enabled == 1 && (delta * period < 10000) && |
143 | !icount_enabled() && !qtest_enabled()) { | |
2b5c0322 | 144 | period = 10000 / delta; |
e91171e3 DO |
145 | period_frac = 0; |
146 | } | |
147 | ||
423f0742 | 148 | s->last_event = s->next_event; |
2b5c0322 | 149 | s->next_event = s->last_event + delta * period; |
e91171e3 | 150 | if (period_frac) { |
2b5c0322 | 151 | s->next_event += ((int64_t)period_frac * delta) >> 32; |
423f0742 | 152 | } |
bc72ad67 | 153 | timer_mod(s->timer, s->next_event); |
423f0742 PB |
154 | } |
155 | ||
156 | static void ptimer_tick(void *opaque) | |
157 | { | |
158 | ptimer_state *s = (ptimer_state *)opaque; | |
3f6e6a13 DO |
159 | bool trigger = true; |
160 | ||
78b6eaa6 PM |
161 | /* |
162 | * We perform all the tick actions within a begin/commit block | |
163 | * because the callback function that ptimer_trigger() calls | |
164 | * might make calls into the ptimer APIs that provoke another | |
165 | * trigger, and we want that to cause the callback function | |
166 | * to be called iteratively, not recursively. | |
167 | */ | |
168 | ptimer_transaction_begin(s); | |
169 | ||
423f0742 | 170 | if (s->enabled == 2) { |
3f6e6a13 | 171 | s->delta = 0; |
423f0742 PB |
172 | s->enabled = 0; |
173 | } else { | |
ef0a9984 DO |
174 | int delta_adjust = DELTA_ADJUST; |
175 | ||
3f6e6a13 | 176 | if (s->delta == 0 || s->limit == 0) { |
ef0a9984 | 177 | /* If a "continuous trigger" policy is not used and limit == 0, |
3f6e6a13 DO |
178 | we should error out. delta == 0 means that this tick is |
179 | caused by a "no immediate reload" policy, so it shouldn't | |
180 | be adjusted. */ | |
22471b8a | 181 | delta_adjust = DELTA_NO_ADJUST; |
ef0a9984 DO |
182 | } |
183 | ||
3f6e6a13 DO |
184 | if (!(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)) { |
185 | /* Avoid re-trigger on deferred reload if "no immediate trigger" | |
186 | policy isn't used. */ | |
187 | trigger = (delta_adjust == DELTA_ADJUST); | |
188 | } | |
189 | ||
190 | s->delta = s->limit; | |
191 | ||
ef0a9984 | 192 | ptimer_reload(s, delta_adjust); |
423f0742 | 193 | } |
3f6e6a13 DO |
194 | |
195 | if (trigger) { | |
196 | ptimer_trigger(s); | |
197 | } | |
78b6eaa6 PM |
198 | |
199 | ptimer_transaction_commit(s); | |
423f0742 PB |
200 | } |
201 | ||
8d05ea8a | 202 | uint64_t ptimer_get_count(ptimer_state *s) |
423f0742 | 203 | { |
8d05ea8a | 204 | uint64_t counter; |
423f0742 | 205 | |
ef0a9984 | 206 | if (s->enabled && s->delta != 0) { |
5a50307b DO |
207 | int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
208 | int64_t next = s->next_event; | |
2b5c0322 | 209 | int64_t last = s->last_event; |
5a50307b DO |
210 | bool expired = (now - next >= 0); |
211 | bool oneshot = (s->enabled == 2); | |
212 | ||
423f0742 | 213 | /* Figure out the current counter value. */ |
56215da3 | 214 | if (expired) { |
423f0742 PB |
215 | /* Prevent timer underflowing if it should already have |
216 | triggered. */ | |
217 | counter = 0; | |
218 | } else { | |
8d05ea8a BS |
219 | uint64_t rem; |
220 | uint64_t div; | |
d0a981b2 PB |
221 | int clz1, clz2; |
222 | int shift; | |
e91171e3 DO |
223 | uint32_t period_frac = s->period_frac; |
224 | uint64_t period = s->period; | |
225 | ||
740b1759 CF |
226 | if (!oneshot && (s->delta * period < 10000) && |
227 | !icount_enabled() && !qtest_enabled()) { | |
e91171e3 DO |
228 | period = 10000 / s->delta; |
229 | period_frac = 0; | |
230 | } | |
d0a981b2 PB |
231 | |
232 | /* We need to divide time by period, where time is stored in | |
233 | rem (64-bit integer) and period is stored in period/period_frac | |
234 | (64.32 fixed point). | |
2b5c0322 | 235 | |
d0a981b2 PB |
236 | Doing full precision division is hard, so scale values and |
237 | do a 64-bit division. The result should be rounded down, | |
238 | so that the rounding error never causes the timer to go | |
239 | backwards. | |
240 | */ | |
423f0742 | 241 | |
56215da3 | 242 | rem = next - now; |
e91171e3 | 243 | div = period; |
d0a981b2 PB |
244 | |
245 | clz1 = clz64(rem); | |
246 | clz2 = clz64(div); | |
247 | shift = clz1 < clz2 ? clz1 : clz2; | |
248 | ||
249 | rem <<= shift; | |
250 | div <<= shift; | |
251 | if (shift >= 32) { | |
e91171e3 | 252 | div |= ((uint64_t)period_frac << (shift - 32)); |
d0a981b2 PB |
253 | } else { |
254 | if (shift != 0) | |
e91171e3 | 255 | div |= (period_frac >> (32 - shift)); |
d0a981b2 PB |
256 | /* Look at remaining bits of period_frac and round div up if |
257 | necessary. */ | |
e91171e3 | 258 | if ((uint32_t)(period_frac << shift)) |
d0a981b2 PB |
259 | div += 1; |
260 | } | |
423f0742 | 261 | counter = rem / div; |
2b5c0322 DO |
262 | |
263 | if (s->policy_mask & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD) { | |
264 | /* Before wrapping around, timer should stay with counter = 0 | |
265 | for a one period. */ | |
266 | if (!oneshot && s->delta == s->limit) { | |
267 | if (now == last) { | |
268 | /* Counter == delta here, check whether it was | |
269 | adjusted and if it was, then right now it is | |
270 | that "one period". */ | |
271 | if (counter == s->limit + DELTA_ADJUST) { | |
272 | return 0; | |
273 | } | |
274 | } else if (counter == s->limit) { | |
275 | /* Since the counter is rounded down and now != last, | |
276 | the counter == limit means that delta was adjusted | |
277 | by +1 and right now it is that adjusted period. */ | |
278 | return 0; | |
279 | } | |
280 | } | |
281 | } | |
423f0742 | 282 | } |
5580ea45 DO |
283 | |
284 | if (s->policy_mask & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN) { | |
285 | /* If now == last then delta == limit, i.e. the counter already | |
286 | represents the correct value. It would be rounded down a 1ns | |
287 | later. */ | |
288 | if (now != last) { | |
289 | counter += 1; | |
290 | } | |
291 | } | |
423f0742 PB |
292 | } else { |
293 | counter = s->delta; | |
294 | } | |
295 | return counter; | |
296 | } | |
297 | ||
8d05ea8a | 298 | void ptimer_set_count(ptimer_state *s, uint64_t count) |
423f0742 | 299 | { |
af2a580f | 300 | assert(s->in_transaction); |
423f0742 PB |
301 | s->delta = count; |
302 | if (s->enabled) { | |
af2a580f | 303 | s->need_reload = true; |
423f0742 PB |
304 | } |
305 | } | |
306 | ||
307 | void ptimer_run(ptimer_state *s, int oneshot) | |
308 | { | |
869e92b5 DO |
309 | bool was_disabled = !s->enabled; |
310 | ||
af2a580f | 311 | assert(s->in_transaction); |
78b6eaa6 | 312 | |
869e92b5 | 313 | if (was_disabled && s->period == 0) { |
2a8b5870 DO |
314 | if (!qtest_enabled()) { |
315 | fprintf(stderr, "Timer with period zero, disabling\n"); | |
316 | } | |
423f0742 PB |
317 | return; |
318 | } | |
319 | s->enabled = oneshot ? 2 : 1; | |
869e92b5 | 320 | if (was_disabled) { |
af2a580f | 321 | s->need_reload = true; |
869e92b5 | 322 | } |
423f0742 PB |
323 | } |
324 | ||
8d05ea8a | 325 | /* Pause a timer. Note that this may cause it to "lose" time, even if it |
423f0742 PB |
326 | is immediately restarted. */ |
327 | void ptimer_stop(ptimer_state *s) | |
328 | { | |
af2a580f | 329 | assert(s->in_transaction); |
78b6eaa6 | 330 | |
423f0742 PB |
331 | if (!s->enabled) |
332 | return; | |
333 | ||
334 | s->delta = ptimer_get_count(s); | |
bc72ad67 | 335 | timer_del(s->timer); |
423f0742 | 336 | s->enabled = 0; |
af2a580f | 337 | s->need_reload = false; |
423f0742 PB |
338 | } |
339 | ||
340 | /* Set counter increment interval in nanoseconds. */ | |
341 | void ptimer_set_period(ptimer_state *s, int64_t period) | |
342 | { | |
af2a580f | 343 | assert(s->in_transaction); |
7ef6e3cf | 344 | s->delta = ptimer_get_count(s); |
423f0742 PB |
345 | s->period = period; |
346 | s->period_frac = 0; | |
8d05ea8a | 347 | if (s->enabled) { |
ad140dad PM |
348 | s->need_reload = true; |
349 | } | |
350 | } | |
351 | ||
352 | /* Set counter increment interval from a Clock */ | |
353 | void ptimer_set_period_from_clock(ptimer_state *s, const Clock *clk, | |
354 | unsigned int divisor) | |
355 | { | |
356 | /* | |
357 | * The raw clock period is a 64-bit value in units of 2^-32 ns; | |
358 | * put another way it's a 32.32 fixed-point ns value. Our internal | |
359 | * representation of the period is 64.32 fixed point ns, so | |
360 | * the conversion is simple. | |
361 | */ | |
362 | uint64_t raw_period = clock_get(clk); | |
363 | uint64_t period_frac; | |
364 | ||
365 | assert(s->in_transaction); | |
366 | s->delta = ptimer_get_count(s); | |
367 | s->period = extract64(raw_period, 32, 32); | |
368 | period_frac = extract64(raw_period, 0, 32); | |
369 | /* | |
370 | * divisor specifies a possible frequency divisor between the | |
371 | * clock and the timer, so it is a multiplier on the period. | |
372 | * We do the multiply after splitting the raw period out into | |
373 | * period and frac to avoid having to do a 32*64->96 multiply. | |
374 | */ | |
375 | s->period *= divisor; | |
376 | period_frac *= divisor; | |
377 | s->period += extract64(period_frac, 32, 32); | |
378 | s->period_frac = (uint32_t)period_frac; | |
379 | ||
380 | if (s->enabled) { | |
af2a580f | 381 | s->need_reload = true; |
8d05ea8a | 382 | } |
423f0742 PB |
383 | } |
384 | ||
385 | /* Set counter frequency in Hz. */ | |
386 | void ptimer_set_freq(ptimer_state *s, uint32_t freq) | |
387 | { | |
af2a580f | 388 | assert(s->in_transaction); |
7ef6e3cf | 389 | s->delta = ptimer_get_count(s); |
423f0742 PB |
390 | s->period = 1000000000ll / freq; |
391 | s->period_frac = (1000000000ll << 32) / freq; | |
8d05ea8a | 392 | if (s->enabled) { |
af2a580f | 393 | s->need_reload = true; |
8d05ea8a | 394 | } |
423f0742 PB |
395 | } |
396 | ||
397 | /* Set the initial countdown value. If reload is nonzero then also set | |
398 | count = limit. */ | |
8d05ea8a | 399 | void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload) |
423f0742 | 400 | { |
af2a580f | 401 | assert(s->in_transaction); |
423f0742 PB |
402 | s->limit = limit; |
403 | if (reload) | |
404 | s->delta = limit; | |
62ea5b0b | 405 | if (s->enabled && reload) { |
af2a580f | 406 | s->need_reload = true; |
8d05ea8a BS |
407 | } |
408 | } | |
409 | ||
578c4b2f DO |
410 | uint64_t ptimer_get_limit(ptimer_state *s) |
411 | { | |
412 | return s->limit; | |
413 | } | |
414 | ||
78b6eaa6 PM |
415 | void ptimer_transaction_begin(ptimer_state *s) |
416 | { | |
af2a580f | 417 | assert(!s->in_transaction); |
78b6eaa6 PM |
418 | s->in_transaction = true; |
419 | s->need_reload = false; | |
420 | } | |
421 | ||
422 | void ptimer_transaction_commit(ptimer_state *s) | |
423 | { | |
424 | assert(s->in_transaction); | |
425 | /* | |
426 | * We must loop here because ptimer_reload() can call the callback | |
427 | * function, which might then update ptimer state in a way that | |
428 | * means we need to do another reload and possibly another callback. | |
429 | * A disabled timer never needs reloading (and if we don't check | |
430 | * this then we loop forever if ptimer_reload() disables the timer). | |
431 | */ | |
432 | while (s->need_reload && s->enabled) { | |
433 | s->need_reload = false; | |
434 | s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | |
435 | ptimer_reload(s, 0); | |
436 | } | |
437 | /* Now we've finished reload we can leave the transaction block. */ | |
438 | s->in_transaction = false; | |
439 | } | |
440 | ||
852f771e | 441 | const VMStateDescription vmstate_ptimer = { |
55a6e51f | 442 | .name = "ptimer", |
852f771e JQ |
443 | .version_id = 1, |
444 | .minimum_version_id = 1, | |
35d08458 | 445 | .fields = (VMStateField[]) { |
852f771e JQ |
446 | VMSTATE_UINT8(enabled, ptimer_state), |
447 | VMSTATE_UINT64(limit, ptimer_state), | |
448 | VMSTATE_UINT64(delta, ptimer_state), | |
449 | VMSTATE_UINT32(period_frac, ptimer_state), | |
450 | VMSTATE_INT64(period, ptimer_state), | |
451 | VMSTATE_INT64(last_event, ptimer_state), | |
452 | VMSTATE_INT64(next_event, ptimer_state), | |
e720677e | 453 | VMSTATE_TIMER_PTR(timer, ptimer_state), |
852f771e JQ |
454 | VMSTATE_END_OF_LIST() |
455 | } | |
55a6e51f BS |
456 | }; |
457 | ||
78b6eaa6 PM |
458 | ptimer_state *ptimer_init(ptimer_cb callback, void *callback_opaque, |
459 | uint8_t policy_mask) | |
460 | { | |
461 | ptimer_state *s; | |
462 | ||
af2a580f | 463 | /* The callback function is mandatory. */ |
78b6eaa6 PM |
464 | assert(callback); |
465 | ||
466 | s = g_new0(ptimer_state, 1); | |
467 | s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ptimer_tick, s); | |
468 | s->policy_mask = policy_mask; | |
469 | s->callback = callback; | |
470 | s->callback_opaque = callback_opaque; | |
471 | ||
472 | /* | |
473 | * These two policies are incompatible -- trigger-on-decrement implies | |
474 | * a timer trigger when the count becomes 0, but no-immediate-trigger | |
475 | * implies a trigger when the count stops being 0. | |
476 | */ | |
477 | assert(!((policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) && | |
478 | (policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER))); | |
479 | return s; | |
480 | } | |
481 | ||
072bdb07 MAL |
482 | void ptimer_free(ptimer_state *s) |
483 | { | |
072bdb07 MAL |
484 | timer_free(s->timer); |
485 | g_free(s); | |
486 | } |