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5fafdf24 1/*
423f0742
PB
2 * General purpose implementation of a simple periodic countdown timer.
3 *
4 * Copyright (c) 2007 CodeSourcery.
5 *
8e31bf38 6 * This code is licensed under the GNU LGPL.
423f0742 7 */
d6454270 8
18c86e2b 9#include "qemu/osdep.h"
1de7afc9 10#include "qemu/timer.h"
83c9f4ca 11#include "hw/ptimer.h"
d6454270 12#include "migration/vmstate.h"
1de7afc9 13#include "qemu/host-utils.h"
8a354bd9 14#include "sysemu/replay.h"
2a8b5870 15#include "sysemu/qtest.h"
072bdb07 16#include "block/aio.h"
d2528bdc 17#include "sysemu/cpus.h"
423f0742 18
22471b8a
DO
19#define DELTA_ADJUST 1
20#define DELTA_NO_ADJUST -1
2b5c0322 21
423f0742
PB
22struct ptimer_state
23{
852f771e 24 uint8_t enabled; /* 0 = disabled, 1 = periodic, 2 = oneshot. */
8d05ea8a
BS
25 uint64_t limit;
26 uint64_t delta;
423f0742
PB
27 uint32_t period_frac;
28 int64_t period;
29 int64_t last_event;
30 int64_t next_event;
e7ea81c3 31 uint8_t policy_mask;
423f0742
PB
32 QEMUBH *bh;
33 QEMUTimer *timer;
34};
35
36/* Use a bottom-half routine to avoid reentrancy issues. */
37static void ptimer_trigger(ptimer_state *s)
38{
39 if (s->bh) {
8a354bd9 40 replay_bh_schedule_event(s->bh);
423f0742
PB
41 }
42}
43
2b5c0322 44static void ptimer_reload(ptimer_state *s, int delta_adjust)
423f0742 45{
e91171e3
DO
46 uint32_t period_frac = s->period_frac;
47 uint64_t period = s->period;
2b5c0322 48 uint64_t delta = s->delta;
086ede32 49 bool suppress_trigger = false;
e91171e3 50
086ede32
PM
51 /*
52 * Note that if delta_adjust is 0 then we must be here because of
53 * a count register write or timer start, not because of timer expiry.
54 * In that case the policy might require us to suppress the timer trigger
55 * that we would otherwise generate for a zero delta.
56 */
57 if (delta_adjust == 0 &&
58 (s->policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT)) {
59 suppress_trigger = true;
60 }
61 if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)
62 && !suppress_trigger) {
423f0742 63 ptimer_trigger(s);
22471b8a
DO
64 }
65
3f6e6a13 66 if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_RELOAD)) {
2b5c0322 67 delta = s->delta = s->limit;
423f0742 68 }
ef0a9984
DO
69
70 if (s->period == 0) {
2a8b5870
DO
71 if (!qtest_enabled()) {
72 fprintf(stderr, "Timer with period zero, disabling\n");
73 }
780d23e5 74 timer_del(s->timer);
423f0742
PB
75 s->enabled = 0;
76 return;
77 }
78
2b5c0322 79 if (s->policy_mask & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD) {
22471b8a
DO
80 if (delta_adjust != DELTA_NO_ADJUST) {
81 delta += delta_adjust;
82 }
2b5c0322
DO
83 }
84
ef0a9984
DO
85 if (delta == 0 && (s->policy_mask & PTIMER_POLICY_CONTINUOUS_TRIGGER)) {
86 if (s->enabled == 1 && s->limit == 0) {
87 delta = 1;
88 }
89 }
90
22471b8a
DO
91 if (delta == 0 && (s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)) {
92 if (delta_adjust != DELTA_NO_ADJUST) {
93 delta = 1;
94 }
95 }
96
3f6e6a13
DO
97 if (delta == 0 && (s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_RELOAD)) {
98 if (s->enabled == 1 && s->limit != 0) {
99 delta = 1;
100 }
101 }
102
ef0a9984
DO
103 if (delta == 0) {
104 if (!qtest_enabled()) {
105 fprintf(stderr, "Timer with delta zero, disabling\n");
106 }
107 timer_del(s->timer);
108 s->enabled = 0;
109 return;
110 }
111
e91171e3
DO
112 /*
113 * Artificially limit timeout rate to something
114 * achievable under QEMU. Otherwise, QEMU spends all
115 * its time generating timer interrupts, and there
116 * is no forward progress.
117 * About ten microseconds is the fastest that really works
118 * on the current generation of host machines.
119 */
120
2b5c0322
DO
121 if (s->enabled == 1 && (delta * period < 10000) && !use_icount) {
122 period = 10000 / delta;
e91171e3
DO
123 period_frac = 0;
124 }
125
423f0742 126 s->last_event = s->next_event;
2b5c0322 127 s->next_event = s->last_event + delta * period;
e91171e3 128 if (period_frac) {
2b5c0322 129 s->next_event += ((int64_t)period_frac * delta) >> 32;
423f0742 130 }
bc72ad67 131 timer_mod(s->timer, s->next_event);
423f0742
PB
132}
133
134static void ptimer_tick(void *opaque)
135{
136 ptimer_state *s = (ptimer_state *)opaque;
3f6e6a13
DO
137 bool trigger = true;
138
423f0742 139 if (s->enabled == 2) {
3f6e6a13 140 s->delta = 0;
423f0742
PB
141 s->enabled = 0;
142 } else {
ef0a9984
DO
143 int delta_adjust = DELTA_ADJUST;
144
3f6e6a13 145 if (s->delta == 0 || s->limit == 0) {
ef0a9984 146 /* If a "continuous trigger" policy is not used and limit == 0,
3f6e6a13
DO
147 we should error out. delta == 0 means that this tick is
148 caused by a "no immediate reload" policy, so it shouldn't
149 be adjusted. */
22471b8a 150 delta_adjust = DELTA_NO_ADJUST;
ef0a9984
DO
151 }
152
3f6e6a13
DO
153 if (!(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)) {
154 /* Avoid re-trigger on deferred reload if "no immediate trigger"
155 policy isn't used. */
156 trigger = (delta_adjust == DELTA_ADJUST);
157 }
158
159 s->delta = s->limit;
160
ef0a9984 161 ptimer_reload(s, delta_adjust);
423f0742 162 }
3f6e6a13
DO
163
164 if (trigger) {
165 ptimer_trigger(s);
166 }
423f0742
PB
167}
168
8d05ea8a 169uint64_t ptimer_get_count(ptimer_state *s)
423f0742 170{
8d05ea8a 171 uint64_t counter;
423f0742 172
ef0a9984 173 if (s->enabled && s->delta != 0) {
5a50307b
DO
174 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
175 int64_t next = s->next_event;
2b5c0322 176 int64_t last = s->last_event;
5a50307b
DO
177 bool expired = (now - next >= 0);
178 bool oneshot = (s->enabled == 2);
179
423f0742 180 /* Figure out the current counter value. */
56215da3 181 if (expired) {
423f0742
PB
182 /* Prevent timer underflowing if it should already have
183 triggered. */
184 counter = 0;
185 } else {
8d05ea8a
BS
186 uint64_t rem;
187 uint64_t div;
d0a981b2
PB
188 int clz1, clz2;
189 int shift;
e91171e3
DO
190 uint32_t period_frac = s->period_frac;
191 uint64_t period = s->period;
192
5a50307b 193 if (!oneshot && (s->delta * period < 10000) && !use_icount) {
e91171e3
DO
194 period = 10000 / s->delta;
195 period_frac = 0;
196 }
d0a981b2
PB
197
198 /* We need to divide time by period, where time is stored in
199 rem (64-bit integer) and period is stored in period/period_frac
200 (64.32 fixed point).
2b5c0322 201
d0a981b2
PB
202 Doing full precision division is hard, so scale values and
203 do a 64-bit division. The result should be rounded down,
204 so that the rounding error never causes the timer to go
205 backwards.
206 */
423f0742 207
56215da3 208 rem = next - now;
e91171e3 209 div = period;
d0a981b2
PB
210
211 clz1 = clz64(rem);
212 clz2 = clz64(div);
213 shift = clz1 < clz2 ? clz1 : clz2;
214
215 rem <<= shift;
216 div <<= shift;
217 if (shift >= 32) {
e91171e3 218 div |= ((uint64_t)period_frac << (shift - 32));
d0a981b2
PB
219 } else {
220 if (shift != 0)
e91171e3 221 div |= (period_frac >> (32 - shift));
d0a981b2
PB
222 /* Look at remaining bits of period_frac and round div up if
223 necessary. */
e91171e3 224 if ((uint32_t)(period_frac << shift))
d0a981b2
PB
225 div += 1;
226 }
423f0742 227 counter = rem / div;
2b5c0322
DO
228
229 if (s->policy_mask & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD) {
230 /* Before wrapping around, timer should stay with counter = 0
231 for a one period. */
232 if (!oneshot && s->delta == s->limit) {
233 if (now == last) {
234 /* Counter == delta here, check whether it was
235 adjusted and if it was, then right now it is
236 that "one period". */
237 if (counter == s->limit + DELTA_ADJUST) {
238 return 0;
239 }
240 } else if (counter == s->limit) {
241 /* Since the counter is rounded down and now != last,
242 the counter == limit means that delta was adjusted
243 by +1 and right now it is that adjusted period. */
244 return 0;
245 }
246 }
247 }
423f0742 248 }
5580ea45
DO
249
250 if (s->policy_mask & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN) {
251 /* If now == last then delta == limit, i.e. the counter already
252 represents the correct value. It would be rounded down a 1ns
253 later. */
254 if (now != last) {
255 counter += 1;
256 }
257 }
423f0742
PB
258 } else {
259 counter = s->delta;
260 }
261 return counter;
262}
263
8d05ea8a 264void ptimer_set_count(ptimer_state *s, uint64_t count)
423f0742
PB
265{
266 s->delta = count;
267 if (s->enabled) {
bc72ad67 268 s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
2b5c0322 269 ptimer_reload(s, 0);
423f0742
PB
270 }
271}
272
273void ptimer_run(ptimer_state *s, int oneshot)
274{
869e92b5
DO
275 bool was_disabled = !s->enabled;
276
277 if (was_disabled && s->period == 0) {
2a8b5870
DO
278 if (!qtest_enabled()) {
279 fprintf(stderr, "Timer with period zero, disabling\n");
280 }
423f0742
PB
281 return;
282 }
283 s->enabled = oneshot ? 2 : 1;
869e92b5
DO
284 if (was_disabled) {
285 s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
2b5c0322 286 ptimer_reload(s, 0);
869e92b5 287 }
423f0742
PB
288}
289
8d05ea8a 290/* Pause a timer. Note that this may cause it to "lose" time, even if it
423f0742
PB
291 is immediately restarted. */
292void ptimer_stop(ptimer_state *s)
293{
294 if (!s->enabled)
295 return;
296
297 s->delta = ptimer_get_count(s);
bc72ad67 298 timer_del(s->timer);
423f0742
PB
299 s->enabled = 0;
300}
301
302/* Set counter increment interval in nanoseconds. */
303void ptimer_set_period(ptimer_state *s, int64_t period)
304{
7ef6e3cf 305 s->delta = ptimer_get_count(s);
423f0742
PB
306 s->period = period;
307 s->period_frac = 0;
8d05ea8a 308 if (s->enabled) {
bc72ad67 309 s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
2b5c0322 310 ptimer_reload(s, 0);
8d05ea8a 311 }
423f0742
PB
312}
313
314/* Set counter frequency in Hz. */
315void ptimer_set_freq(ptimer_state *s, uint32_t freq)
316{
7ef6e3cf 317 s->delta = ptimer_get_count(s);
423f0742
PB
318 s->period = 1000000000ll / freq;
319 s->period_frac = (1000000000ll << 32) / freq;
8d05ea8a 320 if (s->enabled) {
bc72ad67 321 s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
2b5c0322 322 ptimer_reload(s, 0);
8d05ea8a 323 }
423f0742
PB
324}
325
326/* Set the initial countdown value. If reload is nonzero then also set
327 count = limit. */
8d05ea8a 328void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload)
423f0742 329{
423f0742
PB
330 s->limit = limit;
331 if (reload)
332 s->delta = limit;
62ea5b0b 333 if (s->enabled && reload) {
bc72ad67 334 s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
2b5c0322 335 ptimer_reload(s, 0);
8d05ea8a
BS
336 }
337}
338
578c4b2f
DO
339uint64_t ptimer_get_limit(ptimer_state *s)
340{
341 return s->limit;
342}
343
852f771e 344const VMStateDescription vmstate_ptimer = {
55a6e51f 345 .name = "ptimer",
852f771e
JQ
346 .version_id = 1,
347 .minimum_version_id = 1,
35d08458 348 .fields = (VMStateField[]) {
852f771e
JQ
349 VMSTATE_UINT8(enabled, ptimer_state),
350 VMSTATE_UINT64(limit, ptimer_state),
351 VMSTATE_UINT64(delta, ptimer_state),
352 VMSTATE_UINT32(period_frac, ptimer_state),
353 VMSTATE_INT64(period, ptimer_state),
354 VMSTATE_INT64(last_event, ptimer_state),
355 VMSTATE_INT64(next_event, ptimer_state),
e720677e 356 VMSTATE_TIMER_PTR(timer, ptimer_state),
852f771e
JQ
357 VMSTATE_END_OF_LIST()
358 }
55a6e51f
BS
359};
360
e7ea81c3 361ptimer_state *ptimer_init(QEMUBH *bh, uint8_t policy_mask)
423f0742
PB
362{
363 ptimer_state *s;
364
7267c094 365 s = (ptimer_state *)g_malloc0(sizeof(ptimer_state));
423f0742 366 s->bh = bh;
bc72ad67 367 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ptimer_tick, s);
e7ea81c3 368 s->policy_mask = policy_mask;
086ede32
PM
369
370 /*
371 * These two policies are incompatible -- trigger-on-decrement implies
372 * a timer trigger when the count becomes 0, but no-immediate-trigger
373 * implies a trigger when the count stops being 0.
374 */
375 assert(!((policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) &&
376 (policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)));
423f0742
PB
377 return s;
378}
072bdb07
MAL
379
380void ptimer_free(ptimer_state *s)
381{
382 qemu_bh_delete(s->bh);
383 timer_free(s->timer);
384 g_free(s);
385}