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Commit | Line | Data |
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5fafdf24 | 1 | /* |
423f0742 PB |
2 | * General purpose implementation of a simple periodic countdown timer. |
3 | * | |
4 | * Copyright (c) 2007 CodeSourcery. | |
5 | * | |
8e31bf38 | 6 | * This code is licensed under the GNU LGPL. |
423f0742 | 7 | */ |
d6454270 | 8 | |
18c86e2b | 9 | #include "qemu/osdep.h" |
83c9f4ca | 10 | #include "hw/ptimer.h" |
d6454270 | 11 | #include "migration/vmstate.h" |
1de7afc9 | 12 | #include "qemu/host-utils.h" |
8a354bd9 | 13 | #include "sysemu/replay.h" |
740b1759 | 14 | #include "sysemu/cpu-timers.h" |
2a8b5870 | 15 | #include "sysemu/qtest.h" |
072bdb07 | 16 | #include "block/aio.h" |
d2528bdc | 17 | #include "sysemu/cpus.h" |
423f0742 | 18 | |
22471b8a DO |
19 | #define DELTA_ADJUST 1 |
20 | #define DELTA_NO_ADJUST -1 | |
2b5c0322 | 21 | |
423f0742 PB |
22 | struct ptimer_state |
23 | { | |
852f771e | 24 | uint8_t enabled; /* 0 = disabled, 1 = periodic, 2 = oneshot. */ |
8d05ea8a BS |
25 | uint64_t limit; |
26 | uint64_t delta; | |
423f0742 PB |
27 | uint32_t period_frac; |
28 | int64_t period; | |
29 | int64_t last_event; | |
30 | int64_t next_event; | |
e7ea81c3 | 31 | uint8_t policy_mask; |
423f0742 | 32 | QEMUTimer *timer; |
78b6eaa6 PM |
33 | ptimer_cb callback; |
34 | void *callback_opaque; | |
35 | /* | |
36 | * These track whether we're in a transaction block, and if we | |
37 | * need to do a timer reload when the block finishes. They don't | |
38 | * need to be migrated because migration can never happen in the | |
39 | * middle of a transaction block. | |
40 | */ | |
41 | bool in_transaction; | |
42 | bool need_reload; | |
423f0742 PB |
43 | }; |
44 | ||
45 | /* Use a bottom-half routine to avoid reentrancy issues. */ | |
46 | static void ptimer_trigger(ptimer_state *s) | |
47 | { | |
af2a580f | 48 | s->callback(s->callback_opaque); |
423f0742 PB |
49 | } |
50 | ||
2b5c0322 | 51 | static void ptimer_reload(ptimer_state *s, int delta_adjust) |
423f0742 | 52 | { |
78b6eaa6 PM |
53 | uint32_t period_frac; |
54 | uint64_t period; | |
55 | uint64_t delta; | |
086ede32 | 56 | bool suppress_trigger = false; |
e91171e3 | 57 | |
086ede32 PM |
58 | /* |
59 | * Note that if delta_adjust is 0 then we must be here because of | |
60 | * a count register write or timer start, not because of timer expiry. | |
61 | * In that case the policy might require us to suppress the timer trigger | |
62 | * that we would otherwise generate for a zero delta. | |
63 | */ | |
64 | if (delta_adjust == 0 && | |
65 | (s->policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT)) { | |
66 | suppress_trigger = true; | |
67 | } | |
78b6eaa6 | 68 | if (s->delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER) |
086ede32 | 69 | && !suppress_trigger) { |
423f0742 | 70 | ptimer_trigger(s); |
22471b8a DO |
71 | } |
72 | ||
78b6eaa6 PM |
73 | /* |
74 | * Note that ptimer_trigger() might call the device callback function, | |
75 | * which can then modify timer state, so we must not cache any fields | |
76 | * from ptimer_state until after we have called it. | |
77 | */ | |
78 | delta = s->delta; | |
79 | period = s->period; | |
80 | period_frac = s->period_frac; | |
81 | ||
3f6e6a13 | 82 | if (delta == 0 && !(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_RELOAD)) { |
2b5c0322 | 83 | delta = s->delta = s->limit; |
423f0742 | 84 | } |
ef0a9984 DO |
85 | |
86 | if (s->period == 0) { | |
2a8b5870 DO |
87 | if (!qtest_enabled()) { |
88 | fprintf(stderr, "Timer with period zero, disabling\n"); | |
89 | } | |
780d23e5 | 90 | timer_del(s->timer); |
423f0742 PB |
91 | s->enabled = 0; |
92 | return; | |
93 | } | |
94 | ||
2b5c0322 | 95 | if (s->policy_mask & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD) { |
22471b8a DO |
96 | if (delta_adjust != DELTA_NO_ADJUST) { |
97 | delta += delta_adjust; | |
98 | } | |
2b5c0322 DO |
99 | } |
100 | ||
ef0a9984 DO |
101 | if (delta == 0 && (s->policy_mask & PTIMER_POLICY_CONTINUOUS_TRIGGER)) { |
102 | if (s->enabled == 1 && s->limit == 0) { | |
103 | delta = 1; | |
104 | } | |
105 | } | |
106 | ||
22471b8a DO |
107 | if (delta == 0 && (s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)) { |
108 | if (delta_adjust != DELTA_NO_ADJUST) { | |
109 | delta = 1; | |
110 | } | |
111 | } | |
112 | ||
3f6e6a13 DO |
113 | if (delta == 0 && (s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_RELOAD)) { |
114 | if (s->enabled == 1 && s->limit != 0) { | |
115 | delta = 1; | |
116 | } | |
117 | } | |
118 | ||
ef0a9984 DO |
119 | if (delta == 0) { |
120 | if (!qtest_enabled()) { | |
121 | fprintf(stderr, "Timer with delta zero, disabling\n"); | |
122 | } | |
123 | timer_del(s->timer); | |
124 | s->enabled = 0; | |
125 | return; | |
126 | } | |
127 | ||
e91171e3 DO |
128 | /* |
129 | * Artificially limit timeout rate to something | |
130 | * achievable under QEMU. Otherwise, QEMU spends all | |
131 | * its time generating timer interrupts, and there | |
132 | * is no forward progress. | |
133 | * About ten microseconds is the fastest that really works | |
134 | * on the current generation of host machines. | |
135 | */ | |
136 | ||
740b1759 CF |
137 | if (s->enabled == 1 && (delta * period < 10000) && |
138 | !icount_enabled() && !qtest_enabled()) { | |
2b5c0322 | 139 | period = 10000 / delta; |
e91171e3 DO |
140 | period_frac = 0; |
141 | } | |
142 | ||
423f0742 | 143 | s->last_event = s->next_event; |
2b5c0322 | 144 | s->next_event = s->last_event + delta * period; |
e91171e3 | 145 | if (period_frac) { |
2b5c0322 | 146 | s->next_event += ((int64_t)period_frac * delta) >> 32; |
423f0742 | 147 | } |
bc72ad67 | 148 | timer_mod(s->timer, s->next_event); |
423f0742 PB |
149 | } |
150 | ||
151 | static void ptimer_tick(void *opaque) | |
152 | { | |
153 | ptimer_state *s = (ptimer_state *)opaque; | |
3f6e6a13 DO |
154 | bool trigger = true; |
155 | ||
78b6eaa6 PM |
156 | /* |
157 | * We perform all the tick actions within a begin/commit block | |
158 | * because the callback function that ptimer_trigger() calls | |
159 | * might make calls into the ptimer APIs that provoke another | |
160 | * trigger, and we want that to cause the callback function | |
161 | * to be called iteratively, not recursively. | |
162 | */ | |
163 | ptimer_transaction_begin(s); | |
164 | ||
423f0742 | 165 | if (s->enabled == 2) { |
3f6e6a13 | 166 | s->delta = 0; |
423f0742 PB |
167 | s->enabled = 0; |
168 | } else { | |
ef0a9984 DO |
169 | int delta_adjust = DELTA_ADJUST; |
170 | ||
3f6e6a13 | 171 | if (s->delta == 0 || s->limit == 0) { |
ef0a9984 | 172 | /* If a "continuous trigger" policy is not used and limit == 0, |
3f6e6a13 DO |
173 | we should error out. delta == 0 means that this tick is |
174 | caused by a "no immediate reload" policy, so it shouldn't | |
175 | be adjusted. */ | |
22471b8a | 176 | delta_adjust = DELTA_NO_ADJUST; |
ef0a9984 DO |
177 | } |
178 | ||
3f6e6a13 DO |
179 | if (!(s->policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER)) { |
180 | /* Avoid re-trigger on deferred reload if "no immediate trigger" | |
181 | policy isn't used. */ | |
182 | trigger = (delta_adjust == DELTA_ADJUST); | |
183 | } | |
184 | ||
185 | s->delta = s->limit; | |
186 | ||
ef0a9984 | 187 | ptimer_reload(s, delta_adjust); |
423f0742 | 188 | } |
3f6e6a13 DO |
189 | |
190 | if (trigger) { | |
191 | ptimer_trigger(s); | |
192 | } | |
78b6eaa6 PM |
193 | |
194 | ptimer_transaction_commit(s); | |
423f0742 PB |
195 | } |
196 | ||
8d05ea8a | 197 | uint64_t ptimer_get_count(ptimer_state *s) |
423f0742 | 198 | { |
8d05ea8a | 199 | uint64_t counter; |
423f0742 | 200 | |
ef0a9984 | 201 | if (s->enabled && s->delta != 0) { |
5a50307b DO |
202 | int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
203 | int64_t next = s->next_event; | |
2b5c0322 | 204 | int64_t last = s->last_event; |
5a50307b DO |
205 | bool expired = (now - next >= 0); |
206 | bool oneshot = (s->enabled == 2); | |
207 | ||
423f0742 | 208 | /* Figure out the current counter value. */ |
56215da3 | 209 | if (expired) { |
423f0742 PB |
210 | /* Prevent timer underflowing if it should already have |
211 | triggered. */ | |
212 | counter = 0; | |
213 | } else { | |
8d05ea8a BS |
214 | uint64_t rem; |
215 | uint64_t div; | |
d0a981b2 PB |
216 | int clz1, clz2; |
217 | int shift; | |
e91171e3 DO |
218 | uint32_t period_frac = s->period_frac; |
219 | uint64_t period = s->period; | |
220 | ||
740b1759 CF |
221 | if (!oneshot && (s->delta * period < 10000) && |
222 | !icount_enabled() && !qtest_enabled()) { | |
e91171e3 DO |
223 | period = 10000 / s->delta; |
224 | period_frac = 0; | |
225 | } | |
d0a981b2 PB |
226 | |
227 | /* We need to divide time by period, where time is stored in | |
228 | rem (64-bit integer) and period is stored in period/period_frac | |
229 | (64.32 fixed point). | |
2b5c0322 | 230 | |
d0a981b2 PB |
231 | Doing full precision division is hard, so scale values and |
232 | do a 64-bit division. The result should be rounded down, | |
233 | so that the rounding error never causes the timer to go | |
234 | backwards. | |
235 | */ | |
423f0742 | 236 | |
56215da3 | 237 | rem = next - now; |
e91171e3 | 238 | div = period; |
d0a981b2 PB |
239 | |
240 | clz1 = clz64(rem); | |
241 | clz2 = clz64(div); | |
242 | shift = clz1 < clz2 ? clz1 : clz2; | |
243 | ||
244 | rem <<= shift; | |
245 | div <<= shift; | |
246 | if (shift >= 32) { | |
e91171e3 | 247 | div |= ((uint64_t)period_frac << (shift - 32)); |
d0a981b2 PB |
248 | } else { |
249 | if (shift != 0) | |
e91171e3 | 250 | div |= (period_frac >> (32 - shift)); |
d0a981b2 PB |
251 | /* Look at remaining bits of period_frac and round div up if |
252 | necessary. */ | |
e91171e3 | 253 | if ((uint32_t)(period_frac << shift)) |
d0a981b2 PB |
254 | div += 1; |
255 | } | |
423f0742 | 256 | counter = rem / div; |
2b5c0322 DO |
257 | |
258 | if (s->policy_mask & PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD) { | |
259 | /* Before wrapping around, timer should stay with counter = 0 | |
260 | for a one period. */ | |
261 | if (!oneshot && s->delta == s->limit) { | |
262 | if (now == last) { | |
263 | /* Counter == delta here, check whether it was | |
264 | adjusted and if it was, then right now it is | |
265 | that "one period". */ | |
266 | if (counter == s->limit + DELTA_ADJUST) { | |
267 | return 0; | |
268 | } | |
269 | } else if (counter == s->limit) { | |
270 | /* Since the counter is rounded down and now != last, | |
271 | the counter == limit means that delta was adjusted | |
272 | by +1 and right now it is that adjusted period. */ | |
273 | return 0; | |
274 | } | |
275 | } | |
276 | } | |
423f0742 | 277 | } |
5580ea45 DO |
278 | |
279 | if (s->policy_mask & PTIMER_POLICY_NO_COUNTER_ROUND_DOWN) { | |
280 | /* If now == last then delta == limit, i.e. the counter already | |
281 | represents the correct value. It would be rounded down a 1ns | |
282 | later. */ | |
283 | if (now != last) { | |
284 | counter += 1; | |
285 | } | |
286 | } | |
423f0742 PB |
287 | } else { |
288 | counter = s->delta; | |
289 | } | |
290 | return counter; | |
291 | } | |
292 | ||
8d05ea8a | 293 | void ptimer_set_count(ptimer_state *s, uint64_t count) |
423f0742 | 294 | { |
af2a580f | 295 | assert(s->in_transaction); |
423f0742 PB |
296 | s->delta = count; |
297 | if (s->enabled) { | |
af2a580f | 298 | s->need_reload = true; |
423f0742 PB |
299 | } |
300 | } | |
301 | ||
302 | void ptimer_run(ptimer_state *s, int oneshot) | |
303 | { | |
869e92b5 DO |
304 | bool was_disabled = !s->enabled; |
305 | ||
af2a580f | 306 | assert(s->in_transaction); |
78b6eaa6 | 307 | |
869e92b5 | 308 | if (was_disabled && s->period == 0) { |
2a8b5870 DO |
309 | if (!qtest_enabled()) { |
310 | fprintf(stderr, "Timer with period zero, disabling\n"); | |
311 | } | |
423f0742 PB |
312 | return; |
313 | } | |
314 | s->enabled = oneshot ? 2 : 1; | |
869e92b5 | 315 | if (was_disabled) { |
af2a580f | 316 | s->need_reload = true; |
869e92b5 | 317 | } |
423f0742 PB |
318 | } |
319 | ||
8d05ea8a | 320 | /* Pause a timer. Note that this may cause it to "lose" time, even if it |
423f0742 PB |
321 | is immediately restarted. */ |
322 | void ptimer_stop(ptimer_state *s) | |
323 | { | |
af2a580f | 324 | assert(s->in_transaction); |
78b6eaa6 | 325 | |
423f0742 PB |
326 | if (!s->enabled) |
327 | return; | |
328 | ||
329 | s->delta = ptimer_get_count(s); | |
bc72ad67 | 330 | timer_del(s->timer); |
423f0742 | 331 | s->enabled = 0; |
af2a580f | 332 | s->need_reload = false; |
423f0742 PB |
333 | } |
334 | ||
335 | /* Set counter increment interval in nanoseconds. */ | |
336 | void ptimer_set_period(ptimer_state *s, int64_t period) | |
337 | { | |
af2a580f | 338 | assert(s->in_transaction); |
7ef6e3cf | 339 | s->delta = ptimer_get_count(s); |
423f0742 PB |
340 | s->period = period; |
341 | s->period_frac = 0; | |
8d05ea8a | 342 | if (s->enabled) { |
af2a580f | 343 | s->need_reload = true; |
8d05ea8a | 344 | } |
423f0742 PB |
345 | } |
346 | ||
347 | /* Set counter frequency in Hz. */ | |
348 | void ptimer_set_freq(ptimer_state *s, uint32_t freq) | |
349 | { | |
af2a580f | 350 | assert(s->in_transaction); |
7ef6e3cf | 351 | s->delta = ptimer_get_count(s); |
423f0742 PB |
352 | s->period = 1000000000ll / freq; |
353 | s->period_frac = (1000000000ll << 32) / freq; | |
8d05ea8a | 354 | if (s->enabled) { |
af2a580f | 355 | s->need_reload = true; |
8d05ea8a | 356 | } |
423f0742 PB |
357 | } |
358 | ||
359 | /* Set the initial countdown value. If reload is nonzero then also set | |
360 | count = limit. */ | |
8d05ea8a | 361 | void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload) |
423f0742 | 362 | { |
af2a580f | 363 | assert(s->in_transaction); |
423f0742 PB |
364 | s->limit = limit; |
365 | if (reload) | |
366 | s->delta = limit; | |
62ea5b0b | 367 | if (s->enabled && reload) { |
af2a580f | 368 | s->need_reload = true; |
8d05ea8a BS |
369 | } |
370 | } | |
371 | ||
578c4b2f DO |
372 | uint64_t ptimer_get_limit(ptimer_state *s) |
373 | { | |
374 | return s->limit; | |
375 | } | |
376 | ||
78b6eaa6 PM |
377 | void ptimer_transaction_begin(ptimer_state *s) |
378 | { | |
af2a580f | 379 | assert(!s->in_transaction); |
78b6eaa6 PM |
380 | s->in_transaction = true; |
381 | s->need_reload = false; | |
382 | } | |
383 | ||
384 | void ptimer_transaction_commit(ptimer_state *s) | |
385 | { | |
386 | assert(s->in_transaction); | |
387 | /* | |
388 | * We must loop here because ptimer_reload() can call the callback | |
389 | * function, which might then update ptimer state in a way that | |
390 | * means we need to do another reload and possibly another callback. | |
391 | * A disabled timer never needs reloading (and if we don't check | |
392 | * this then we loop forever if ptimer_reload() disables the timer). | |
393 | */ | |
394 | while (s->need_reload && s->enabled) { | |
395 | s->need_reload = false; | |
396 | s->next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); | |
397 | ptimer_reload(s, 0); | |
398 | } | |
399 | /* Now we've finished reload we can leave the transaction block. */ | |
400 | s->in_transaction = false; | |
401 | } | |
402 | ||
852f771e | 403 | const VMStateDescription vmstate_ptimer = { |
55a6e51f | 404 | .name = "ptimer", |
852f771e JQ |
405 | .version_id = 1, |
406 | .minimum_version_id = 1, | |
35d08458 | 407 | .fields = (VMStateField[]) { |
852f771e JQ |
408 | VMSTATE_UINT8(enabled, ptimer_state), |
409 | VMSTATE_UINT64(limit, ptimer_state), | |
410 | VMSTATE_UINT64(delta, ptimer_state), | |
411 | VMSTATE_UINT32(period_frac, ptimer_state), | |
412 | VMSTATE_INT64(period, ptimer_state), | |
413 | VMSTATE_INT64(last_event, ptimer_state), | |
414 | VMSTATE_INT64(next_event, ptimer_state), | |
e720677e | 415 | VMSTATE_TIMER_PTR(timer, ptimer_state), |
852f771e JQ |
416 | VMSTATE_END_OF_LIST() |
417 | } | |
55a6e51f BS |
418 | }; |
419 | ||
78b6eaa6 PM |
420 | ptimer_state *ptimer_init(ptimer_cb callback, void *callback_opaque, |
421 | uint8_t policy_mask) | |
422 | { | |
423 | ptimer_state *s; | |
424 | ||
af2a580f | 425 | /* The callback function is mandatory. */ |
78b6eaa6 PM |
426 | assert(callback); |
427 | ||
428 | s = g_new0(ptimer_state, 1); | |
429 | s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ptimer_tick, s); | |
430 | s->policy_mask = policy_mask; | |
431 | s->callback = callback; | |
432 | s->callback_opaque = callback_opaque; | |
433 | ||
434 | /* | |
435 | * These two policies are incompatible -- trigger-on-decrement implies | |
436 | * a timer trigger when the count becomes 0, but no-immediate-trigger | |
437 | * implies a trigger when the count stops being 0. | |
438 | */ | |
439 | assert(!((policy_mask & PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT) && | |
440 | (policy_mask & PTIMER_POLICY_NO_IMMEDIATE_TRIGGER))); | |
441 | return s; | |
442 | } | |
443 | ||
072bdb07 MAL |
444 | void ptimer_free(ptimer_state *s) |
445 | { | |
072bdb07 MAL |
446 | timer_free(s->timer); |
447 | g_free(s); | |
448 | } |