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f7c70325 PB |
1 | /* |
2 | * Cortex-A9MPCore internal peripheral emulation. | |
3 | * | |
4 | * Copyright (c) 2009 CodeSourcery. | |
b12080cd PM |
5 | * Copyright (c) 2011 Linaro Limited. |
6 | * Written by Paul Brook, Peter Maydell. | |
f7c70325 | 7 | * |
8e31bf38 | 8 | * This code is licensed under the GPL. |
f7c70325 PB |
9 | */ |
10 | ||
83c9f4ca | 11 | #include "hw/sysbus.h" |
9b5f952b | 12 | #include "hw/intc/arm_gic.h" |
fc719d77 | 13 | #include "hw/misc/a9scu.h" |
b12080cd | 14 | |
5126fec7 AF |
15 | #define TYPE_A9MPCORE_PRIV "a9mpcore_priv" |
16 | #define A9MPCORE_PRIV(obj) \ | |
17 | OBJECT_CHECK(A9MPPrivState, (obj), TYPE_A9MPCORE_PRIV) | |
18 | ||
845769fc | 19 | typedef struct A9MPPrivState { |
5126fec7 AF |
20 | /*< private >*/ |
21 | SysBusDevice parent_obj; | |
22 | /*< public >*/ | |
23 | ||
b12080cd | 24 | uint32_t num_cpu; |
b12080cd PM |
25 | MemoryRegion container; |
26 | DeviceState *mptimer; | |
cde4577f | 27 | DeviceState *wdt; |
a32134aa | 28 | uint32_t num_irq; |
9b5f952b AF |
29 | |
30 | GICState gic; | |
fc719d77 | 31 | A9SCUState scu; |
845769fc | 32 | } A9MPPrivState; |
b12080cd | 33 | |
ddd76165 PM |
34 | static void a9mp_priv_set_irq(void *opaque, int irq, int level) |
35 | { | |
845769fc | 36 | A9MPPrivState *s = (A9MPPrivState *)opaque; |
9b5f952b AF |
37 | |
38 | qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); | |
ddd76165 PM |
39 | } |
40 | ||
753bc6e9 AF |
41 | static void a9mp_priv_initfn(Object *obj) |
42 | { | |
43 | A9MPPrivState *s = A9MPCORE_PRIV(obj); | |
44 | ||
45 | memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000); | |
46 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); | |
9b5f952b AF |
47 | |
48 | object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); | |
49 | qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); | |
fc719d77 AF |
50 | |
51 | object_initialize(&s->scu, sizeof(s->scu), TYPE_A9_SCU); | |
52 | qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default()); | |
753bc6e9 AF |
53 | } |
54 | ||
b12080cd PM |
55 | static int a9mp_priv_init(SysBusDevice *dev) |
56 | { | |
5126fec7 | 57 | A9MPPrivState *s = A9MPCORE_PRIV(dev); |
fc719d77 | 58 | DeviceState *gicdev, *scudev; |
353575f0 | 59 | SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev, *scubusdev; |
b12080cd PM |
60 | int i; |
61 | ||
9b5f952b AF |
62 | gicdev = DEVICE(&s->gic); |
63 | qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); | |
64 | qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); | |
65 | qdev_init_nofail(gicdev); | |
66 | gicbusdev = SYS_BUS_DEVICE(&s->gic); | |
ddd76165 PM |
67 | |
68 | /* Pass through outbound IRQ lines from the GIC */ | |
69 | sysbus_pass_irq(dev, gicbusdev); | |
70 | ||
71 | /* Pass through inbound GPIO lines to the GIC */ | |
5126fec7 | 72 | qdev_init_gpio_in(DEVICE(dev), a9mp_priv_set_irq, s->num_irq - 32); |
b12080cd | 73 | |
fc719d77 AF |
74 | scudev = DEVICE(&s->scu); |
75 | qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); | |
76 | qdev_init_nofail(scudev); | |
77 | scubusdev = SYS_BUS_DEVICE(&s->scu); | |
353575f0 | 78 | |
b12080cd PM |
79 | s->mptimer = qdev_create(NULL, "arm_mptimer"); |
80 | qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu); | |
81 | qdev_init_nofail(s->mptimer); | |
cde4577f PC |
82 | timerbusdev = SYS_BUS_DEVICE(s->mptimer); |
83 | ||
84 | s->wdt = qdev_create(NULL, "arm_mptimer"); | |
85 | qdev_prop_set_uint32(s->wdt, "num-cpu", s->num_cpu); | |
86 | qdev_init_nofail(s->wdt); | |
87 | wdtbusdev = SYS_BUS_DEVICE(s->wdt); | |
b12080cd PM |
88 | |
89 | /* Memory map (addresses are offsets from PERIPHBASE): | |
90 | * 0x0000-0x00ff -- Snoop Control Unit | |
91 | * 0x0100-0x01ff -- GIC CPU interface | |
92 | * 0x0200-0x02ff -- Global Timer | |
93 | * 0x0300-0x05ff -- nothing | |
94 | * 0x0600-0x06ff -- private timers and watchdogs | |
95 | * 0x0700-0x0fff -- nothing | |
96 | * 0x1000-0x1fff -- GIC Distributor | |
97 | * | |
98 | * We should implement the global timer but don't currently do so. | |
99 | */ | |
353575f0 PC |
100 | memory_region_add_subregion(&s->container, 0, |
101 | sysbus_mmio_get_region(scubusdev, 0)); | |
b12080cd | 102 | /* GIC CPU interface */ |
ddd76165 PM |
103 | memory_region_add_subregion(&s->container, 0x100, |
104 | sysbus_mmio_get_region(gicbusdev, 1)); | |
b12080cd PM |
105 | /* Note that the A9 exposes only the "timer/watchdog for this core" |
106 | * memory region, not the "timer/watchdog for core X" ones 11MPcore has. | |
107 | */ | |
108 | memory_region_add_subregion(&s->container, 0x600, | |
cde4577f | 109 | sysbus_mmio_get_region(timerbusdev, 0)); |
b12080cd | 110 | memory_region_add_subregion(&s->container, 0x620, |
cde4577f | 111 | sysbus_mmio_get_region(wdtbusdev, 0)); |
ddd76165 PM |
112 | memory_region_add_subregion(&s->container, 0x1000, |
113 | sysbus_mmio_get_region(gicbusdev, 0)); | |
b12080cd | 114 | |
ddd76165 PM |
115 | /* Wire up the interrupt from each watchdog and timer. |
116 | * For each core the timer is PPI 29 and the watchdog PPI 30. | |
117 | */ | |
118 | for (i = 0; i < s->num_cpu; i++) { | |
119 | int ppibase = (s->num_irq - 32) + i * 32; | |
cde4577f | 120 | sysbus_connect_irq(timerbusdev, i, |
9b5f952b | 121 | qdev_get_gpio_in(gicdev, ppibase + 29)); |
cde4577f | 122 | sysbus_connect_irq(wdtbusdev, i, |
9b5f952b | 123 | qdev_get_gpio_in(gicdev, ppibase + 30)); |
b12080cd PM |
124 | } |
125 | return 0; | |
126 | } | |
127 | ||
39bffca2 | 128 | static Property a9mp_priv_properties[] = { |
845769fc | 129 | DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), |
39bffca2 AL |
130 | /* The Cortex-A9MP may have anything from 0 to 224 external interrupt |
131 | * IRQ lines (with another 32 internal). We default to 64+32, which | |
132 | * is the number provided by the Cortex-A9MP test chip in the | |
133 | * Realview PBX-A9 and Versatile Express A9 development boards. | |
134 | * Other boards may differ and should set this property appropriately. | |
135 | */ | |
845769fc | 136 | DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), |
39bffca2 AL |
137 | DEFINE_PROP_END_OF_LIST(), |
138 | }; | |
139 | ||
999e12bb AL |
140 | static void a9mp_priv_class_init(ObjectClass *klass, void *data) |
141 | { | |
39bffca2 | 142 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
143 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
144 | ||
145 | k->init = a9mp_priv_init; | |
39bffca2 | 146 | dc->props = a9mp_priv_properties; |
999e12bb AL |
147 | } |
148 | ||
8c43a6f0 | 149 | static const TypeInfo a9mp_priv_info = { |
5126fec7 | 150 | .name = TYPE_A9MPCORE_PRIV, |
39bffca2 | 151 | .parent = TYPE_SYS_BUS_DEVICE, |
845769fc | 152 | .instance_size = sizeof(A9MPPrivState), |
753bc6e9 | 153 | .instance_init = a9mp_priv_initfn, |
39bffca2 | 154 | .class_init = a9mp_priv_class_init, |
f7c70325 PB |
155 | }; |
156 | ||
83f7d43a | 157 | static void a9mp_register_types(void) |
f7c70325 | 158 | { |
39bffca2 | 159 | type_register_static(&a9mp_priv_info); |
f7c70325 PB |
160 | } |
161 | ||
83f7d43a | 162 | type_init(a9mp_register_types) |