]>
Commit | Line | Data |
---|---|---|
f7c70325 PB |
1 | /* |
2 | * Cortex-A9MPCore internal peripheral emulation. | |
3 | * | |
4 | * Copyright (c) 2009 CodeSourcery. | |
b12080cd PM |
5 | * Copyright (c) 2011 Linaro Limited. |
6 | * Written by Paul Brook, Peter Maydell. | |
f7c70325 | 7 | * |
8e31bf38 | 8 | * This code is licensed under the GPL. |
f7c70325 PB |
9 | */ |
10 | ||
17b7f2db | 11 | #include "qemu/osdep.h" |
de4c2dcf | 12 | #include "hw/cpu/a9mpcore.h" |
b12080cd | 13 | |
ddd76165 PM |
14 | static void a9mp_priv_set_irq(void *opaque, int irq, int level) |
15 | { | |
845769fc | 16 | A9MPPrivState *s = (A9MPPrivState *)opaque; |
9b5f952b AF |
17 | |
18 | qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); | |
ddd76165 PM |
19 | } |
20 | ||
753bc6e9 AF |
21 | static void a9mp_priv_initfn(Object *obj) |
22 | { | |
23 | A9MPPrivState *s = A9MPCORE_PRIV(obj); | |
24 | ||
25 | memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000); | |
26 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); | |
9b5f952b | 27 | |
fc719d77 AF |
28 | object_initialize(&s->scu, sizeof(s->scu), TYPE_A9_SCU); |
29 | qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default()); | |
eb110bd8 | 30 | |
4c25f365 PC |
31 | object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); |
32 | qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); | |
33 | ||
57e72f2a FL |
34 | object_initialize(&s->gtimer, sizeof(s->gtimer), TYPE_A9_GTIMER); |
35 | qdev_set_parent_bus(DEVICE(&s->gtimer), sysbus_get_default()); | |
36 | ||
eb110bd8 AF |
37 | object_initialize(&s->mptimer, sizeof(s->mptimer), TYPE_ARM_MPTIMER); |
38 | qdev_set_parent_bus(DEVICE(&s->mptimer), sysbus_get_default()); | |
39 | ||
40 | object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ARM_MPTIMER); | |
41 | qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default()); | |
753bc6e9 AF |
42 | } |
43 | ||
837cf101 | 44 | static void a9mp_priv_realize(DeviceState *dev, Error **errp) |
b12080cd | 45 | { |
837cf101 | 46 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
5126fec7 | 47 | A9MPPrivState *s = A9MPCORE_PRIV(dev); |
57e72f2a FL |
48 | DeviceState *scudev, *gicdev, *gtimerdev, *mptimerdev, *wdtdev; |
49 | SysBusDevice *scubusdev, *gicbusdev, *gtimerbusdev, *mptimerbusdev, | |
50 | *wdtbusdev; | |
837cf101 | 51 | Error *err = NULL; |
b12080cd | 52 | int i; |
4182bbb1 PM |
53 | bool has_el3; |
54 | Object *cpuobj; | |
b12080cd | 55 | |
4c25f365 PC |
56 | scudev = DEVICE(&s->scu); |
57 | qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); | |
58 | object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); | |
59 | if (err != NULL) { | |
60 | error_propagate(errp, err); | |
61 | return; | |
62 | } | |
63 | scubusdev = SYS_BUS_DEVICE(&s->scu); | |
64 | ||
9b5f952b AF |
65 | gicdev = DEVICE(&s->gic); |
66 | qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); | |
67 | qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); | |
4182bbb1 PM |
68 | |
69 | /* Make the GIC's TZ support match the CPUs. We assume that | |
70 | * either all the CPUs have TZ, or none do. | |
71 | */ | |
72 | cpuobj = OBJECT(qemu_get_cpu(0)); | |
6533a1fc | 73 | has_el3 = object_property_find(cpuobj, "has_el3", NULL) && |
4182bbb1 PM |
74 | object_property_get_bool(cpuobj, "has_el3", &error_abort); |
75 | qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); | |
76 | ||
837cf101 AF |
77 | object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); |
78 | if (err != NULL) { | |
79 | error_propagate(errp, err); | |
80 | return; | |
81 | } | |
9b5f952b | 82 | gicbusdev = SYS_BUS_DEVICE(&s->gic); |
ddd76165 PM |
83 | |
84 | /* Pass through outbound IRQ lines from the GIC */ | |
837cf101 | 85 | sysbus_pass_irq(sbd, gicbusdev); |
ddd76165 PM |
86 | |
87 | /* Pass through inbound GPIO lines to the GIC */ | |
837cf101 | 88 | qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32); |
b12080cd | 89 | |
57e72f2a FL |
90 | gtimerdev = DEVICE(&s->gtimer); |
91 | qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu); | |
92 | object_property_set_bool(OBJECT(&s->gtimer), true, "realized", &err); | |
93 | if (err != NULL) { | |
94 | error_propagate(errp, err); | |
95 | return; | |
96 | } | |
97 | gtimerbusdev = SYS_BUS_DEVICE(&s->gtimer); | |
98 | ||
eb110bd8 AF |
99 | mptimerdev = DEVICE(&s->mptimer); |
100 | qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); | |
837cf101 AF |
101 | object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err); |
102 | if (err != NULL) { | |
103 | error_propagate(errp, err); | |
104 | return; | |
105 | } | |
d3053e6b | 106 | mptimerbusdev = SYS_BUS_DEVICE(&s->mptimer); |
cde4577f | 107 | |
eb110bd8 AF |
108 | wdtdev = DEVICE(&s->wdt); |
109 | qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu); | |
837cf101 AF |
110 | object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err); |
111 | if (err != NULL) { | |
112 | error_propagate(errp, err); | |
113 | return; | |
114 | } | |
eb110bd8 | 115 | wdtbusdev = SYS_BUS_DEVICE(&s->wdt); |
b12080cd PM |
116 | |
117 | /* Memory map (addresses are offsets from PERIPHBASE): | |
118 | * 0x0000-0x00ff -- Snoop Control Unit | |
119 | * 0x0100-0x01ff -- GIC CPU interface | |
120 | * 0x0200-0x02ff -- Global Timer | |
121 | * 0x0300-0x05ff -- nothing | |
122 | * 0x0600-0x06ff -- private timers and watchdogs | |
123 | * 0x0700-0x0fff -- nothing | |
124 | * 0x1000-0x1fff -- GIC Distributor | |
b12080cd | 125 | */ |
353575f0 PC |
126 | memory_region_add_subregion(&s->container, 0, |
127 | sysbus_mmio_get_region(scubusdev, 0)); | |
b12080cd | 128 | /* GIC CPU interface */ |
ddd76165 PM |
129 | memory_region_add_subregion(&s->container, 0x100, |
130 | sysbus_mmio_get_region(gicbusdev, 1)); | |
57e72f2a FL |
131 | memory_region_add_subregion(&s->container, 0x200, |
132 | sysbus_mmio_get_region(gtimerbusdev, 0)); | |
b12080cd PM |
133 | /* Note that the A9 exposes only the "timer/watchdog for this core" |
134 | * memory region, not the "timer/watchdog for core X" ones 11MPcore has. | |
135 | */ | |
136 | memory_region_add_subregion(&s->container, 0x600, | |
d3053e6b | 137 | sysbus_mmio_get_region(mptimerbusdev, 0)); |
b12080cd | 138 | memory_region_add_subregion(&s->container, 0x620, |
cde4577f | 139 | sysbus_mmio_get_region(wdtbusdev, 0)); |
ddd76165 PM |
140 | memory_region_add_subregion(&s->container, 0x1000, |
141 | sysbus_mmio_get_region(gicbusdev, 0)); | |
b12080cd | 142 | |
ddd76165 | 143 | /* Wire up the interrupt from each watchdog and timer. |
57e72f2a FL |
144 | * For each core the global timer is PPI 27, the private |
145 | * timer is PPI 29 and the watchdog PPI 30. | |
ddd76165 PM |
146 | */ |
147 | for (i = 0; i < s->num_cpu; i++) { | |
148 | int ppibase = (s->num_irq - 32) + i * 32; | |
57e72f2a FL |
149 | sysbus_connect_irq(gtimerbusdev, i, |
150 | qdev_get_gpio_in(gicdev, ppibase + 27)); | |
d3053e6b | 151 | sysbus_connect_irq(mptimerbusdev, i, |
9b5f952b | 152 | qdev_get_gpio_in(gicdev, ppibase + 29)); |
cde4577f | 153 | sysbus_connect_irq(wdtbusdev, i, |
9b5f952b | 154 | qdev_get_gpio_in(gicdev, ppibase + 30)); |
b12080cd | 155 | } |
b12080cd PM |
156 | } |
157 | ||
39bffca2 | 158 | static Property a9mp_priv_properties[] = { |
845769fc | 159 | DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), |
39bffca2 AL |
160 | /* The Cortex-A9MP may have anything from 0 to 224 external interrupt |
161 | * IRQ lines (with another 32 internal). We default to 64+32, which | |
162 | * is the number provided by the Cortex-A9MP test chip in the | |
163 | * Realview PBX-A9 and Versatile Express A9 development boards. | |
164 | * Other boards may differ and should set this property appropriately. | |
165 | */ | |
845769fc | 166 | DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), |
39bffca2 AL |
167 | DEFINE_PROP_END_OF_LIST(), |
168 | }; | |
169 | ||
999e12bb AL |
170 | static void a9mp_priv_class_init(ObjectClass *klass, void *data) |
171 | { | |
39bffca2 | 172 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 173 | |
837cf101 | 174 | dc->realize = a9mp_priv_realize; |
39bffca2 | 175 | dc->props = a9mp_priv_properties; |
999e12bb AL |
176 | } |
177 | ||
8c43a6f0 | 178 | static const TypeInfo a9mp_priv_info = { |
5126fec7 | 179 | .name = TYPE_A9MPCORE_PRIV, |
39bffca2 | 180 | .parent = TYPE_SYS_BUS_DEVICE, |
845769fc | 181 | .instance_size = sizeof(A9MPPrivState), |
753bc6e9 | 182 | .instance_init = a9mp_priv_initfn, |
39bffca2 | 183 | .class_init = a9mp_priv_class_init, |
f7c70325 PB |
184 | }; |
185 | ||
83f7d43a | 186 | static void a9mp_register_types(void) |
f7c70325 | 187 | { |
39bffca2 | 188 | type_register_static(&a9mp_priv_info); |
f7c70325 PB |
189 | } |
190 | ||
83f7d43a | 191 | type_init(a9mp_register_types) |