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f7c70325 PB |
1 | /* |
2 | * Cortex-A9MPCore internal peripheral emulation. | |
3 | * | |
4 | * Copyright (c) 2009 CodeSourcery. | |
b12080cd PM |
5 | * Copyright (c) 2011 Linaro Limited. |
6 | * Written by Paul Brook, Peter Maydell. | |
f7c70325 | 7 | * |
8e31bf38 | 8 | * This code is licensed under the GPL. |
f7c70325 PB |
9 | */ |
10 | ||
de4c2dcf | 11 | #include "hw/cpu/a9mpcore.h" |
b12080cd | 12 | |
ddd76165 PM |
13 | static void a9mp_priv_set_irq(void *opaque, int irq, int level) |
14 | { | |
845769fc | 15 | A9MPPrivState *s = (A9MPPrivState *)opaque; |
9b5f952b AF |
16 | |
17 | qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); | |
ddd76165 PM |
18 | } |
19 | ||
753bc6e9 AF |
20 | static void a9mp_priv_initfn(Object *obj) |
21 | { | |
22 | A9MPPrivState *s = A9MPCORE_PRIV(obj); | |
23 | ||
24 | memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000); | |
25 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); | |
9b5f952b | 26 | |
fc719d77 AF |
27 | object_initialize(&s->scu, sizeof(s->scu), TYPE_A9_SCU); |
28 | qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default()); | |
eb110bd8 | 29 | |
4c25f365 PC |
30 | object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); |
31 | qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); | |
32 | ||
57e72f2a FL |
33 | object_initialize(&s->gtimer, sizeof(s->gtimer), TYPE_A9_GTIMER); |
34 | qdev_set_parent_bus(DEVICE(&s->gtimer), sysbus_get_default()); | |
35 | ||
eb110bd8 AF |
36 | object_initialize(&s->mptimer, sizeof(s->mptimer), TYPE_ARM_MPTIMER); |
37 | qdev_set_parent_bus(DEVICE(&s->mptimer), sysbus_get_default()); | |
38 | ||
39 | object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ARM_MPTIMER); | |
40 | qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default()); | |
753bc6e9 AF |
41 | } |
42 | ||
837cf101 | 43 | static void a9mp_priv_realize(DeviceState *dev, Error **errp) |
b12080cd | 44 | { |
837cf101 | 45 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
5126fec7 | 46 | A9MPPrivState *s = A9MPCORE_PRIV(dev); |
57e72f2a FL |
47 | DeviceState *scudev, *gicdev, *gtimerdev, *mptimerdev, *wdtdev; |
48 | SysBusDevice *scubusdev, *gicbusdev, *gtimerbusdev, *mptimerbusdev, | |
49 | *wdtbusdev; | |
837cf101 | 50 | Error *err = NULL; |
b12080cd | 51 | int i; |
4182bbb1 PM |
52 | bool has_el3; |
53 | Object *cpuobj; | |
b12080cd | 54 | |
4c25f365 PC |
55 | scudev = DEVICE(&s->scu); |
56 | qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); | |
57 | object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); | |
58 | if (err != NULL) { | |
59 | error_propagate(errp, err); | |
60 | return; | |
61 | } | |
62 | scubusdev = SYS_BUS_DEVICE(&s->scu); | |
63 | ||
9b5f952b AF |
64 | gicdev = DEVICE(&s->gic); |
65 | qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); | |
66 | qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); | |
4182bbb1 PM |
67 | |
68 | /* Make the GIC's TZ support match the CPUs. We assume that | |
69 | * either all the CPUs have TZ, or none do. | |
70 | */ | |
71 | cpuobj = OBJECT(qemu_get_cpu(0)); | |
72 | has_el3 = object_property_find(cpuobj, "has_el3", &error_abort) && | |
73 | object_property_get_bool(cpuobj, "has_el3", &error_abort); | |
74 | qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); | |
75 | ||
837cf101 AF |
76 | object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); |
77 | if (err != NULL) { | |
78 | error_propagate(errp, err); | |
79 | return; | |
80 | } | |
9b5f952b | 81 | gicbusdev = SYS_BUS_DEVICE(&s->gic); |
ddd76165 PM |
82 | |
83 | /* Pass through outbound IRQ lines from the GIC */ | |
837cf101 | 84 | sysbus_pass_irq(sbd, gicbusdev); |
ddd76165 PM |
85 | |
86 | /* Pass through inbound GPIO lines to the GIC */ | |
837cf101 | 87 | qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32); |
b12080cd | 88 | |
57e72f2a FL |
89 | gtimerdev = DEVICE(&s->gtimer); |
90 | qdev_prop_set_uint32(gtimerdev, "num-cpu", s->num_cpu); | |
91 | object_property_set_bool(OBJECT(&s->gtimer), true, "realized", &err); | |
92 | if (err != NULL) { | |
93 | error_propagate(errp, err); | |
94 | return; | |
95 | } | |
96 | gtimerbusdev = SYS_BUS_DEVICE(&s->gtimer); | |
97 | ||
eb110bd8 AF |
98 | mptimerdev = DEVICE(&s->mptimer); |
99 | qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); | |
837cf101 AF |
100 | object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err); |
101 | if (err != NULL) { | |
102 | error_propagate(errp, err); | |
103 | return; | |
104 | } | |
d3053e6b | 105 | mptimerbusdev = SYS_BUS_DEVICE(&s->mptimer); |
cde4577f | 106 | |
eb110bd8 AF |
107 | wdtdev = DEVICE(&s->wdt); |
108 | qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu); | |
837cf101 AF |
109 | object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err); |
110 | if (err != NULL) { | |
111 | error_propagate(errp, err); | |
112 | return; | |
113 | } | |
eb110bd8 | 114 | wdtbusdev = SYS_BUS_DEVICE(&s->wdt); |
b12080cd PM |
115 | |
116 | /* Memory map (addresses are offsets from PERIPHBASE): | |
117 | * 0x0000-0x00ff -- Snoop Control Unit | |
118 | * 0x0100-0x01ff -- GIC CPU interface | |
119 | * 0x0200-0x02ff -- Global Timer | |
120 | * 0x0300-0x05ff -- nothing | |
121 | * 0x0600-0x06ff -- private timers and watchdogs | |
122 | * 0x0700-0x0fff -- nothing | |
123 | * 0x1000-0x1fff -- GIC Distributor | |
b12080cd | 124 | */ |
353575f0 PC |
125 | memory_region_add_subregion(&s->container, 0, |
126 | sysbus_mmio_get_region(scubusdev, 0)); | |
b12080cd | 127 | /* GIC CPU interface */ |
ddd76165 PM |
128 | memory_region_add_subregion(&s->container, 0x100, |
129 | sysbus_mmio_get_region(gicbusdev, 1)); | |
57e72f2a FL |
130 | memory_region_add_subregion(&s->container, 0x200, |
131 | sysbus_mmio_get_region(gtimerbusdev, 0)); | |
b12080cd PM |
132 | /* Note that the A9 exposes only the "timer/watchdog for this core" |
133 | * memory region, not the "timer/watchdog for core X" ones 11MPcore has. | |
134 | */ | |
135 | memory_region_add_subregion(&s->container, 0x600, | |
d3053e6b | 136 | sysbus_mmio_get_region(mptimerbusdev, 0)); |
b12080cd | 137 | memory_region_add_subregion(&s->container, 0x620, |
cde4577f | 138 | sysbus_mmio_get_region(wdtbusdev, 0)); |
ddd76165 PM |
139 | memory_region_add_subregion(&s->container, 0x1000, |
140 | sysbus_mmio_get_region(gicbusdev, 0)); | |
b12080cd | 141 | |
ddd76165 | 142 | /* Wire up the interrupt from each watchdog and timer. |
57e72f2a FL |
143 | * For each core the global timer is PPI 27, the private |
144 | * timer is PPI 29 and the watchdog PPI 30. | |
ddd76165 PM |
145 | */ |
146 | for (i = 0; i < s->num_cpu; i++) { | |
147 | int ppibase = (s->num_irq - 32) + i * 32; | |
57e72f2a FL |
148 | sysbus_connect_irq(gtimerbusdev, i, |
149 | qdev_get_gpio_in(gicdev, ppibase + 27)); | |
d3053e6b | 150 | sysbus_connect_irq(mptimerbusdev, i, |
9b5f952b | 151 | qdev_get_gpio_in(gicdev, ppibase + 29)); |
cde4577f | 152 | sysbus_connect_irq(wdtbusdev, i, |
9b5f952b | 153 | qdev_get_gpio_in(gicdev, ppibase + 30)); |
b12080cd | 154 | } |
b12080cd PM |
155 | } |
156 | ||
39bffca2 | 157 | static Property a9mp_priv_properties[] = { |
845769fc | 158 | DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), |
39bffca2 AL |
159 | /* The Cortex-A9MP may have anything from 0 to 224 external interrupt |
160 | * IRQ lines (with another 32 internal). We default to 64+32, which | |
161 | * is the number provided by the Cortex-A9MP test chip in the | |
162 | * Realview PBX-A9 and Versatile Express A9 development boards. | |
163 | * Other boards may differ and should set this property appropriately. | |
164 | */ | |
845769fc | 165 | DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), |
39bffca2 AL |
166 | DEFINE_PROP_END_OF_LIST(), |
167 | }; | |
168 | ||
999e12bb AL |
169 | static void a9mp_priv_class_init(ObjectClass *klass, void *data) |
170 | { | |
39bffca2 | 171 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 172 | |
837cf101 | 173 | dc->realize = a9mp_priv_realize; |
39bffca2 | 174 | dc->props = a9mp_priv_properties; |
999e12bb AL |
175 | } |
176 | ||
8c43a6f0 | 177 | static const TypeInfo a9mp_priv_info = { |
5126fec7 | 178 | .name = TYPE_A9MPCORE_PRIV, |
39bffca2 | 179 | .parent = TYPE_SYS_BUS_DEVICE, |
845769fc | 180 | .instance_size = sizeof(A9MPPrivState), |
753bc6e9 | 181 | .instance_init = a9mp_priv_initfn, |
39bffca2 | 182 | .class_init = a9mp_priv_class_init, |
f7c70325 PB |
183 | }; |
184 | ||
83f7d43a | 185 | static void a9mp_register_types(void) |
f7c70325 | 186 | { |
39bffca2 | 187 | type_register_static(&a9mp_priv_info); |
f7c70325 PB |
188 | } |
189 | ||
83f7d43a | 190 | type_init(a9mp_register_types) |