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f7c70325 PB |
1 | /* |
2 | * ARM11MPCore internal peripheral emulation. | |
3 | * | |
4 | * Copyright (c) 2006-2007 CodeSourcery. | |
5 | * Written by Paul Brook | |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL. |
f7c70325 PB |
8 | */ |
9 | ||
83c9f4ca | 10 | #include "hw/sysbus.h" |
1de7afc9 | 11 | #include "qemu/timer.h" |
2a6ab1e3 | 12 | |
2a6ab1e3 PM |
13 | /* MPCore private memory region. */ |
14 | ||
845769fc | 15 | typedef struct ARM11MPCorePriveState { |
2e9dfe20 | 16 | SysBusDevice busdev; |
2a6ab1e3 PM |
17 | uint32_t scu_control; |
18 | int iomemtype; | |
19 | uint32_t old_timer_status[8]; | |
20 | uint32_t num_cpu; | |
2a6ab1e3 PM |
21 | MemoryRegion iomem; |
22 | MemoryRegion container; | |
23 | DeviceState *mptimer; | |
cde4577f | 24 | DeviceState *wdtimer; |
2e9dfe20 | 25 | DeviceState *gic; |
a32134aa | 26 | uint32_t num_irq; |
845769fc | 27 | } ARM11MPCorePriveState; |
2a6ab1e3 PM |
28 | |
29 | /* Per-CPU private memory mapped IO. */ | |
30 | ||
a8170e5e | 31 | static uint64_t mpcore_scu_read(void *opaque, hwaddr offset, |
2a6ab1e3 PM |
32 | unsigned size) |
33 | { | |
845769fc | 34 | ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; |
2a6ab1e3 | 35 | int id; |
2a6ab1e3 PM |
36 | /* SCU */ |
37 | switch (offset) { | |
38 | case 0x00: /* Control. */ | |
39 | return s->scu_control; | |
40 | case 0x04: /* Configuration. */ | |
41 | id = ((1 << s->num_cpu) - 1) << 4; | |
42 | return id | (s->num_cpu - 1); | |
43 | case 0x08: /* CPU status. */ | |
44 | return 0; | |
45 | case 0x0c: /* Invalidate all. */ | |
46 | return 0; | |
47 | default: | |
f9fe7bda PM |
48 | qemu_log_mask(LOG_GUEST_ERROR, |
49 | "mpcore_priv_read: Bad offset %x\n", (int)offset); | |
50 | return 0; | |
2a6ab1e3 PM |
51 | } |
52 | } | |
53 | ||
a8170e5e | 54 | static void mpcore_scu_write(void *opaque, hwaddr offset, |
2a6ab1e3 PM |
55 | uint64_t value, unsigned size) |
56 | { | |
845769fc | 57 | ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; |
2a6ab1e3 PM |
58 | /* SCU */ |
59 | switch (offset) { | |
60 | case 0: /* Control register. */ | |
61 | s->scu_control = value & 1; | |
62 | break; | |
63 | case 0x0c: /* Invalidate all. */ | |
64 | /* This is a no-op as cache is not emulated. */ | |
65 | break; | |
66 | default: | |
f9fe7bda PM |
67 | qemu_log_mask(LOG_GUEST_ERROR, |
68 | "mpcore_priv_read: Bad offset %x\n", (int)offset); | |
2a6ab1e3 PM |
69 | } |
70 | } | |
71 | ||
72 | static const MemoryRegionOps mpcore_scu_ops = { | |
73 | .read = mpcore_scu_read, | |
74 | .write = mpcore_scu_write, | |
75 | .endianness = DEVICE_NATIVE_ENDIAN, | |
76 | }; | |
77 | ||
2e9dfe20 | 78 | static void mpcore_priv_set_irq(void *opaque, int irq, int level) |
2a6ab1e3 | 79 | { |
845769fc | 80 | ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque; |
2e9dfe20 | 81 | qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); |
2a6ab1e3 PM |
82 | } |
83 | ||
845769fc | 84 | static void mpcore_priv_map_setup(ARM11MPCorePriveState *s) |
2a6ab1e3 PM |
85 | { |
86 | int i; | |
1356b98d | 87 | SysBusDevice *gicbusdev = SYS_BUS_DEVICE(s->gic); |
cde4577f PC |
88 | SysBusDevice *timerbusdev = SYS_BUS_DEVICE(s->mptimer); |
89 | SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(s->wdtimer); | |
2c9b15ca PB |
90 | memory_region_init(&s->container, NULL, "mpcode-priv-container", 0x2000); |
91 | memory_region_init_io(&s->iomem, NULL, &mpcore_scu_ops, s, "mpcore-scu", 0x100); | |
2a6ab1e3 PM |
92 | memory_region_add_subregion(&s->container, 0, &s->iomem); |
93 | /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs | |
94 | * at 0x200, 0x300... | |
95 | */ | |
96 | for (i = 0; i < (s->num_cpu + 1); i++) { | |
a8170e5e | 97 | hwaddr offset = 0x100 + (i * 0x100); |
2e9dfe20 PM |
98 | memory_region_add_subregion(&s->container, offset, |
99 | sysbus_mmio_get_region(gicbusdev, i + 1)); | |
2a6ab1e3 PM |
100 | } |
101 | /* Add the regions for timer and watchdog for "current CPU" and | |
102 | * for each specific CPU. | |
103 | */ | |
cde4577f | 104 | for (i = 0; i < (s->num_cpu + 1); i++) { |
2a6ab1e3 | 105 | /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */ |
cde4577f | 106 | hwaddr offset = 0x600 + i * 0x100; |
2a6ab1e3 | 107 | memory_region_add_subregion(&s->container, offset, |
cde4577f PC |
108 | sysbus_mmio_get_region(timerbusdev, i)); |
109 | memory_region_add_subregion(&s->container, offset + 0x20, | |
110 | sysbus_mmio_get_region(wdtbusdev, i)); | |
2a6ab1e3 | 111 | } |
2e9dfe20 PM |
112 | memory_region_add_subregion(&s->container, 0x1000, |
113 | sysbus_mmio_get_region(gicbusdev, 0)); | |
114 | /* Wire up the interrupt from each watchdog and timer. | |
115 | * For each core the timer is PPI 29 and the watchdog PPI 30. | |
116 | */ | |
117 | for (i = 0; i < s->num_cpu; i++) { | |
118 | int ppibase = (s->num_irq - 32) + i * 32; | |
cde4577f | 119 | sysbus_connect_irq(timerbusdev, i, |
2e9dfe20 | 120 | qdev_get_gpio_in(s->gic, ppibase + 29)); |
cde4577f | 121 | sysbus_connect_irq(wdtbusdev, i, |
2e9dfe20 | 122 | qdev_get_gpio_in(s->gic, ppibase + 30)); |
2a6ab1e3 PM |
123 | } |
124 | } | |
125 | ||
126 | static int mpcore_priv_init(SysBusDevice *dev) | |
127 | { | |
845769fc | 128 | ARM11MPCorePriveState *s = FROM_SYSBUS(ARM11MPCorePriveState, dev); |
2e9dfe20 PM |
129 | |
130 | s->gic = qdev_create(NULL, "arm_gic"); | |
131 | qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); | |
132 | qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); | |
306a571a PM |
133 | /* Request the legacy 11MPCore GIC behaviour: */ |
134 | qdev_prop_set_uint32(s->gic, "revision", 0); | |
2e9dfe20 PM |
135 | qdev_init_nofail(s->gic); |
136 | ||
137 | /* Pass through outbound IRQ lines from the GIC */ | |
1356b98d | 138 | sysbus_pass_irq(dev, SYS_BUS_DEVICE(s->gic)); |
2e9dfe20 PM |
139 | |
140 | /* Pass through inbound GPIO lines to the GIC */ | |
141 | qdev_init_gpio_in(&s->busdev.qdev, mpcore_priv_set_irq, s->num_irq - 32); | |
2a6ab1e3 | 142 | |
2a6ab1e3 PM |
143 | s->mptimer = qdev_create(NULL, "arm_mptimer"); |
144 | qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu); | |
145 | qdev_init_nofail(s->mptimer); | |
cde4577f PC |
146 | |
147 | s->wdtimer = qdev_create(NULL, "arm_mptimer"); | |
148 | qdev_prop_set_uint32(s->wdtimer, "num-cpu", s->num_cpu); | |
149 | qdev_init_nofail(s->wdtimer); | |
150 | ||
2a6ab1e3 PM |
151 | mpcore_priv_map_setup(s); |
152 | sysbus_init_mmio(dev, &s->container); | |
153 | return 0; | |
154 | } | |
f7c70325 PB |
155 | |
156 | /* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ | |
157 | controllers. The output of these, plus some of the raw input lines | |
158 | are fed into a single SMP-aware interrupt controller on the CPU. */ | |
159 | typedef struct { | |
160 | SysBusDevice busdev; | |
161 | SysBusDevice *priv; | |
162 | qemu_irq cpuic[32]; | |
163 | qemu_irq rvic[4][64]; | |
164 | uint32_t num_cpu; | |
165 | } mpcore_rirq_state; | |
166 | ||
167 | /* Map baseboard IRQs onto CPU IRQ lines. */ | |
168 | static const int mpcore_irq_map[32] = { | |
169 | -1, -1, -1, -1, 1, 2, -1, -1, | |
170 | -1, -1, 6, -1, 4, 5, -1, -1, | |
171 | -1, 14, 15, 0, 7, 8, -1, -1, | |
172 | -1, -1, -1, -1, 9, 3, -1, -1, | |
173 | }; | |
174 | ||
175 | static void mpcore_rirq_set_irq(void *opaque, int irq, int level) | |
176 | { | |
177 | mpcore_rirq_state *s = (mpcore_rirq_state *)opaque; | |
178 | int i; | |
179 | ||
180 | for (i = 0; i < 4; i++) { | |
181 | qemu_set_irq(s->rvic[i][irq], level); | |
182 | } | |
183 | if (irq < 32) { | |
184 | irq = mpcore_irq_map[irq]; | |
185 | if (irq >= 0) { | |
186 | qemu_set_irq(s->cpuic[irq], level); | |
187 | } | |
188 | } | |
189 | } | |
190 | ||
f7c70325 PB |
191 | static int realview_mpcore_init(SysBusDevice *dev) |
192 | { | |
193 | mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev); | |
194 | DeviceState *gic; | |
195 | DeviceState *priv; | |
196 | int n; | |
197 | int i; | |
198 | ||
199 | priv = qdev_create(NULL, "arm11mpcore_priv"); | |
200 | qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu); | |
201 | qdev_init_nofail(priv); | |
1356b98d | 202 | s->priv = SYS_BUS_DEVICE(priv); |
f7c70325 PB |
203 | sysbus_pass_irq(dev, s->priv); |
204 | for (i = 0; i < 32; i++) { | |
205 | s->cpuic[i] = qdev_get_gpio_in(priv, i); | |
206 | } | |
207 | /* ??? IRQ routing is hardcoded to "normal" mode. */ | |
208 | for (n = 0; n < 4; n++) { | |
209 | gic = sysbus_create_simple("realview_gic", 0x10040000 + n * 0x10000, | |
210 | s->cpuic[10 + n]); | |
211 | for (i = 0; i < 64; i++) { | |
212 | s->rvic[n][i] = qdev_get_gpio_in(gic, i); | |
213 | } | |
214 | } | |
215 | qdev_init_gpio_in(&dev->qdev, mpcore_rirq_set_irq, 64); | |
750ecd44 | 216 | sysbus_init_mmio(dev, sysbus_mmio_get_region(s->priv, 0)); |
f7c70325 PB |
217 | return 0; |
218 | } | |
219 | ||
999e12bb | 220 | static Property mpcore_rirq_properties[] = { |
0f58a188 | 221 | DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1), |
999e12bb | 222 | DEFINE_PROP_END_OF_LIST(), |
f7c70325 PB |
223 | }; |
224 | ||
999e12bb AL |
225 | static void mpcore_rirq_class_init(ObjectClass *klass, void *data) |
226 | { | |
39bffca2 | 227 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
228 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
229 | ||
230 | k->init = realview_mpcore_init; | |
39bffca2 | 231 | dc->props = mpcore_rirq_properties; |
999e12bb AL |
232 | } |
233 | ||
8c43a6f0 | 234 | static const TypeInfo mpcore_rirq_info = { |
39bffca2 AL |
235 | .name = "realview_mpcore", |
236 | .parent = TYPE_SYS_BUS_DEVICE, | |
237 | .instance_size = sizeof(mpcore_rirq_state), | |
238 | .class_init = mpcore_rirq_class_init, | |
999e12bb AL |
239 | }; |
240 | ||
241 | static Property mpcore_priv_properties[] = { | |
845769fc | 242 | DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1), |
0f58a188 PM |
243 | /* The ARM11 MPCORE TRM says the on-chip controller may have |
244 | * anything from 0 to 224 external interrupt IRQ lines (with another | |
245 | * 32 internal). We default to 32+32, which is the number provided by | |
246 | * the ARM11 MPCore test chip in the Realview Versatile Express | |
247 | * coretile. Other boards may differ and should set this property | |
248 | * appropriately. Some Linux kernels may not boot if the hardware | |
249 | * has more IRQ lines than the kernel expects. | |
250 | */ | |
845769fc | 251 | DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64), |
999e12bb AL |
252 | DEFINE_PROP_END_OF_LIST(), |
253 | }; | |
254 | ||
255 | static void mpcore_priv_class_init(ObjectClass *klass, void *data) | |
256 | { | |
39bffca2 | 257 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
258 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
259 | ||
260 | k->init = mpcore_priv_init; | |
39bffca2 | 261 | dc->props = mpcore_priv_properties; |
999e12bb AL |
262 | } |
263 | ||
8c43a6f0 | 264 | static const TypeInfo mpcore_priv_info = { |
39bffca2 AL |
265 | .name = "arm11mpcore_priv", |
266 | .parent = TYPE_SYS_BUS_DEVICE, | |
845769fc | 267 | .instance_size = sizeof(ARM11MPCorePriveState), |
39bffca2 | 268 | .class_init = mpcore_priv_class_init, |
f7c70325 PB |
269 | }; |
270 | ||
83f7d43a | 271 | static void arm11mpcore_register_types(void) |
f7c70325 | 272 | { |
39bffca2 AL |
273 | type_register_static(&mpcore_rirq_info); |
274 | type_register_static(&mpcore_priv_info); | |
f7c70325 PB |
275 | } |
276 | ||
83f7d43a | 277 | type_init(arm11mpcore_register_types) |