[mirror_qemu.git] / hw / cris / axis_dev88.c

/*
 * QEMU model for the AXIS devboard 88.
 *
 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/sysbus.h"
#include "net/net.h"
#include "hw/block/flash.h"
#include "hw/boards.h"
#include "hw/cris/etraxfs.h"
#include "hw/loader.h"
#include "elf.h"
#include "boot.h"
#include "sysemu/block-backend.h"
#include "exec/address-spaces.h"
#include "sysemu/qtest.h"

#define D(x)
#define DNAND(x)

struct nand_state_t
{
    DeviceState *nand;
    MemoryRegion iomem;
    unsigned int rdy:1;
    unsigned int ale:1;
    unsigned int cle:1;
    unsigned int ce:1;
};

static struct nand_state_t nand_state;
static uint64_t nand_read(void *opaque, hwaddr addr, unsigned size)
{
    struct nand_state_t *s = opaque;
    uint32_t r;
    int rdy;

    r = nand_getio(s->nand);
    nand_getpins(s->nand, &rdy);
    s->rdy = rdy;

    DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
    return r;
}

static void
nand_write(void *opaque, hwaddr addr, uint64_t value,
           unsigned size)
{
    struct nand_state_t *s = opaque;
    int rdy;

    DNAND(printf("%s addr=%x v=%x\n", __func__, addr, (unsigned)value));
    nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
    nand_setio(s->nand, value);
    nand_getpins(s->nand, &rdy);
    s->rdy = rdy;
}

static const MemoryRegionOps nand_ops = {
    .read = nand_read,
    .write = nand_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

struct tempsensor_t
{
    unsigned int shiftreg;
    unsigned int count;
    enum {
        ST_OUT, ST_IN, ST_Z
    } state;

    uint16_t regs[3];
};

static void tempsensor_clkedge(struct tempsensor_t *s,
                               unsigned int clk, unsigned int data_in)
{
    D(printf("%s clk=%d state=%d sr=%x\n", __func__,
             clk, s->state, s->shiftreg));
    if (s->count == 0) {
        s->count = 16;
        s->state = ST_OUT;
    }
    switch (s->state) {
        case ST_OUT:
            /* Output reg is clocked at negedge.  */
            if (!clk) {
                s->count--;
                s->shiftreg <<= 1;
                if (s->count == 0) {
                    s->shiftreg = 0;
                    s->state = ST_IN;
                    s->count = 16;
                }
            }
            break;
        case ST_Z:
            if (clk) {
                s->count--;
                if (s->count == 0) {
                    s->shiftreg = 0;
                    s->state = ST_OUT;
                    s->count = 16;
                }
            }
            break;
        case ST_IN:
            /* Indata is sampled at posedge.  */
            if (clk) {
                s->count--;
                s->shiftreg <<= 1;
                s->shiftreg |= data_in & 1;
                if (s->count == 0) {
                    D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
                    s->regs[0] = s->shiftreg;
                    s->state = ST_OUT;
                    s->count = 16;

                    if ((s->regs[0] & 0xff) == 0) {
                        /* 25 degrees celsius.  */
                        s->shiftreg = 0x0b9f;
                    } else if ((s->regs[0] & 0xff) == 0xff) {
                        /* Sensor ID, 0x8100 LM70.  */
                        s->shiftreg = 0x8100;
                    } else
                        printf("Invalid tempsens state %x\n", s->regs[0]);
                }
            }
            break;
    }
}


#define RW_PA_DOUT    0x00
#define R_PA_DIN      0x01
#define RW_PA_OE      0x02
#define RW_PD_DOUT    0x10
#define R_PD_DIN      0x11
#define RW_PD_OE      0x12

static struct gpio_state_t
{
    MemoryRegion iomem;
    struct nand_state_t *nand;
    struct tempsensor_t tempsensor;
    uint32_t regs[0x5c / 4];
} gpio_state;

static uint64_t gpio_read(void *opaque, hwaddr addr, unsigned size)
{
    struct gpio_state_t *s = opaque;
    uint32_t r = 0;

    addr >>= 2;
    switch (addr)
    {
        case R_PA_DIN:
            r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE];

            /* Encode pins from the nand.  */
            r |= s->nand->rdy << 7;
            break;
        case R_PD_DIN:
            r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE];

            /* Encode temp sensor pins.  */
            r |= (!!(s->tempsensor.shiftreg & 0x10000)) << 4;
            break;

        default:
            r = s->regs[addr];
            break;
    }
    return r;
    D(printf("%s %x=%x\n", __func__, addr, r));
}

static void gpio_write(void *opaque, hwaddr addr, uint64_t value,
                       unsigned size)
{
    struct gpio_state_t *s = opaque;
    D(printf("%s %x=%x\n", __func__, addr, (unsigned)value));

    addr >>= 2;
    switch (addr)
    {
        case RW_PA_DOUT:
            /* Decode nand pins.  */
            s->nand->ale = !!(value & (1 << 6));
            s->nand->cle = !!(value & (1 << 5));
            s->nand->ce  = !!(value & (1 << 4));

            s->regs[addr] = value;
            break;

        case RW_PD_DOUT:
            /* Temp sensor clk.  */
            if ((s->regs[addr] ^ value) & 2)
                tempsensor_clkedge(&s->tempsensor, !!(value & 2),
                                   !!(value & 16));
            s->regs[addr] = value;
            break;

        default:
            s->regs[addr] = value;
            break;
    }
}

static const MemoryRegionOps gpio_ops = {
    .read = gpio_read,
    .write = gpio_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

#define INTMEM_SIZE (128 * 1024)

static struct cris_load_info li;

static
void axisdev88_init(MachineState *machine)
{
    ram_addr_t ram_size = machine->ram_size;
    const char *cpu_model = machine->cpu_model;
    const char *kernel_filename = machine->kernel_filename;
    const char *kernel_cmdline = machine->kernel_cmdline;
    CRISCPU *cpu;
    CPUCRISState *env;
    DeviceState *dev;
    SysBusDevice *s;
    DriveInfo *nand;
    qemu_irq irq[30], nmi[2];
    void *etraxfs_dmac;
    struct etraxfs_dma_client *dma_eth;
    int i;
    MemoryRegion *address_space_mem = get_system_memory();
    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
    MemoryRegion *phys_intmem = g_new(MemoryRegion, 1);

    /* init CPUs */
    if (cpu_model == NULL) {
        cpu_model = "crisv32";
    }
    cpu = cpu_cris_init(cpu_model);
    env = &cpu->env;

    /* allocate RAM */
    memory_region_allocate_system_memory(phys_ram, NULL, "axisdev88.ram",
                                         ram_size);
    memory_region_add_subregion(address_space_mem, 0x40000000, phys_ram);

    /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the 
       internal memory.  */
    memory_region_init_ram(phys_intmem, NULL, "axisdev88.chipram", INTMEM_SIZE,
                           &error_fatal);
    vmstate_register_ram_global(phys_intmem);
    memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem);

      /* Attach a NAND flash to CS1.  */
    nand = drive_get(IF_MTD, 0, 0);
    nand_state.nand = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL,
                                NAND_MFR_STMICRO, 0x39);
    memory_region_init_io(&nand_state.iomem, NULL, &nand_ops, &nand_state,
                          "nand", 0x05000000);
    memory_region_add_subregion(address_space_mem, 0x10000000,
                                &nand_state.iomem);

    gpio_state.nand = &nand_state;
    memory_region_init_io(&gpio_state.iomem, NULL, &gpio_ops, &gpio_state,
                          "gpio", 0x5c);
    memory_region_add_subregion(address_space_mem, 0x3001a000,
                                &gpio_state.iomem);


    dev = qdev_create(NULL, "etraxfs,pic");
    /* FIXME: Is there a proper way to signal vectors to the CPU core?  */
    qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
    qdev_init_nofail(dev);
    s = SYS_BUS_DEVICE(dev);
    sysbus_mmio_map(s, 0, 0x3001c000);
    sysbus_connect_irq(s, 0, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_IRQ));
    sysbus_connect_irq(s, 1, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_NMI));
    for (i = 0; i < 30; i++) {
        irq[i] = qdev_get_gpio_in(dev, i);
    }
    nmi[0] = qdev_get_gpio_in(dev, 30);
    nmi[1] = qdev_get_gpio_in(dev, 31);

    etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10);
    for (i = 0; i < 10; i++) {
        /* On ETRAX, odd numbered channels are inputs.  */
        etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1);
    }

    /* Add the two ethernet blocks.  */
    dma_eth = g_malloc0(sizeof dma_eth[0] * 4); /* Allocate 4 channels.  */
    etraxfs_eth_init(&nd_table[0], 0x30034000, 1, &dma_eth[0], &dma_eth[1]);
    if (nb_nics > 1) {
        etraxfs_eth_init(&nd_table[1], 0x30036000, 2, &dma_eth[2], &dma_eth[3]);
    }

    /* The DMA Connector block is missing, hardwire things for now.  */
    etraxfs_dmac_connect_client(etraxfs_dmac, 0, &dma_eth[0]);
    etraxfs_dmac_connect_client(etraxfs_dmac, 1, &dma_eth[1]);
    if (nb_nics > 1) {
        etraxfs_dmac_connect_client(etraxfs_dmac, 6, &dma_eth[2]);
        etraxfs_dmac_connect_client(etraxfs_dmac, 7, &dma_eth[3]);
    }

    /* 2 timers.  */
    sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL);
    sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL);

    for (i = 0; i < 4; i++) {
        sysbus_create_simple("etraxfs,serial", 0x30026000 + i * 0x2000,
                             irq[0x14 + i]);
    }

    if (kernel_filename) {
        li.image_filename = kernel_filename;
        li.cmdline = kernel_cmdline;
        cris_load_image(cpu, &li);
    } else if (!qtest_enabled()) {
        fprintf(stderr, "Kernel image must be specified\n");
        exit(1);
    }
}

static void axisdev88_machine_init(MachineClass *mc)
{
    mc->desc = "AXIS devboard 88";
    mc->init = axisdev88_init;
    mc->is_default = 1;
}

DEFINE_MACHINE("axis-dev88", axisdev88_machine_init)
Commit	Line	Data
10c144e2 EI	1	/*
	2	* QEMU model for the AXIS devboard 88.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
4b816985	24
23b0d7df	25	#include "qemu/osdep.h"
da34e65c	26	#include "qapi/error.h"
83c9f4ca	27	#include "hw/sysbus.h"
1422e32d	28	#include "net/net.h"
0d09e41a	29	#include "hw/block/flash.h"
83c9f4ca	30	#include "hw/boards.h"
0d09e41a	31	#include "hw/cris/etraxfs.h"
83c9f4ca	32	#include "hw/loader.h"
ca20cf32	33	#include "elf.h"
47b43a1f	34	#include "boot.h"
fa1d36df	35	#include "sysemu/block-backend.h"
022c62cb	36	#include "exec/address-spaces.h"
5efe843a	37	#include "sysemu/qtest.h"
10c144e2 EI	38
	39	#define D(x)
	40	#define DNAND(x)
	41
	42	struct nand_state_t
	43	{
d4220389	44	DeviceState *nand;
838335ec	45	MemoryRegion iomem;
10c144e2 EI	46	unsigned int rdy:1;
	47	unsigned int ale:1;
	48	unsigned int cle:1;
	49	unsigned int ce:1;
	50	};
	51
	52	static struct nand_state_t nand_state;
a8170e5e	53	static uint64_t nand_read(void *opaque, hwaddr addr, unsigned size)
10c144e2 EI	54	{
	55	struct nand_state_t *s = opaque;
	56	uint32_t r;
	57	int rdy;
	58
	59	r = nand_getio(s->nand);
	60	nand_getpins(s->nand, &rdy);
	61	s->rdy = rdy;
	62
	63	DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
	64	return r;
	65	}
	66
	67	static void
a8170e5e	68	nand_write(void *opaque, hwaddr addr, uint64_t value,
838335ec	69	unsigned size)
10c144e2 EI	70	{
	71	struct nand_state_t *s = opaque;
	72	int rdy;
	73
838335ec	74	DNAND(printf("%s addr=%x v=%x\n", __func__, addr, (unsigned)value));
10c144e2 EI	75	nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
	76	nand_setio(s->nand, value);
	77	nand_getpins(s->nand, &rdy);
	78	s->rdy = rdy;
	79	}
	80
838335ec AK	81	static const MemoryRegionOps nand_ops = {
	82	.read = nand_read,
	83	.write = nand_write,
	84	.endianness = DEVICE_NATIVE_ENDIAN,
10c144e2 EI	85	};
10c144e2 EI	86
4a1e6bea EI	87	struct tempsensor_t
	88	{
	89	unsigned int shiftreg;
	90	unsigned int count;
	91	enum {
	92	ST_OUT, ST_IN, ST_Z
	93	} state;
	94
	95	uint16_t regs[3];
	96	};
	97
	98	static void tempsensor_clkedge(struct tempsensor_t *s,
	99	unsigned int clk, unsigned int data_in)
	100	{
	101	D(printf("%s clk=%d state=%d sr=%x\n", __func__,
	102	clk, s->state, s->shiftreg));
	103	if (s->count == 0) {
	104	s->count = 16;
	105	s->state = ST_OUT;
	106	}
	107	switch (s->state) {
	108	case ST_OUT:
	109	/* Output reg is clocked at negedge. */
	110	if (!clk) {
	111	s->count--;
	112	s->shiftreg <<= 1;
	113	if (s->count == 0) {
	114	s->shiftreg = 0;
	115	s->state = ST_IN;
	116	s->count = 16;
	117	}
	118	}
	119	break;
	120	case ST_Z:
	121	if (clk) {
	122	s->count--;
	123	if (s->count == 0) {
	124	s->shiftreg = 0;
	125	s->state = ST_OUT;
	126	s->count = 16;
	127	}
	128	}
	129	break;
	130	case ST_IN:
	131	/* Indata is sampled at posedge. */
	132	if (clk) {
	133	s->count--;
	134	s->shiftreg <<= 1;
	135	s->shiftreg \|= data_in & 1;
	136	if (s->count == 0) {
	137	D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
	138	s->regs[0] = s->shiftreg;
	139	s->state = ST_OUT;
	140	s->count = 16;
	141
	142	if ((s->regs[0] & 0xff) == 0) {
67cc32eb	143	/* 25 degrees celsius. */
4a1e6bea EI	144	s->shiftreg = 0x0b9f;
	145	} else if ((s->regs[0] & 0xff) == 0xff) {
	146	/* Sensor ID, 0x8100 LM70. */
	147	s->shiftreg = 0x8100;
	148	} else
	149	printf("Invalid tempsens state %x\n", s->regs[0]);
	150	}
	151	}
	152	break;
	153	}
	154	}
	155
	156
	157	#define RW_PA_DOUT 0x00
	158	#define R_PA_DIN 0x01
	159	#define RW_PA_OE 0x02
	160	#define RW_PD_DOUT 0x10
	161	#define R_PD_DIN 0x11
	162	#define RW_PD_OE 0x12
	163
	164	static struct gpio_state_t
10c144e2	165	{
838335ec	166	MemoryRegion iomem;
10c144e2	167	struct nand_state_t *nand;
4a1e6bea	168	struct tempsensor_t tempsensor;
10c144e2 EI	169	uint32_t regs[0x5c / 4];
	170	} gpio_state;
	171
a8170e5e	172	static uint64_t gpio_read(void *opaque, hwaddr addr, unsigned size)
10c144e2 EI	173	{
	174	struct gpio_state_t *s = opaque;
	175	uint32_t r = 0;
	176
	177	addr >>= 2;
	178	switch (addr)
	179	{
	180	case R_PA_DIN:
	181	r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE];
	182
	183	/* Encode pins from the nand. */
	184	r \|= s->nand->rdy << 7;
	185	break;
4a1e6bea EI	186	case R_PD_DIN:
	187	r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE];
	188
	189	/* Encode temp sensor pins. */
	190	r \|= (!!(s->tempsensor.shiftreg & 0x10000)) << 4;
	191	break;
	192
10c144e2 EI	193	default:
	194	r = s->regs[addr];
	195	break;
	196	}
	197	return r;
	198	D(printf("%s %x=%x\n", __func__, addr, r));
	199	}
	200
a8170e5e	201	static void gpio_write(void *opaque, hwaddr addr, uint64_t value,
838335ec	202	unsigned size)
10c144e2 EI	203	{
10c144e2 EI	204	struct gpio_state_t *s = opaque;
838335ec	205	D(printf("%s %x=%x\n", __func__, addr, (unsigned)value));
10c144e2 EI	206
	207	addr >>= 2;
	208	switch (addr)
	209	{
	210	case RW_PA_DOUT:
	211	/* Decode nand pins. */
	212	s->nand->ale = !!(value & (1 << 6));
	213	s->nand->cle = !!(value & (1 << 5));
	214	s->nand->ce = !!(value & (1 << 4));
	215
	216	s->regs[addr] = value;
	217	break;
4a1e6bea EI	218
	219	case RW_PD_DOUT:
	220	/* Temp sensor clk. */
	221	if ((s->regs[addr] ^ value) & 2)
	222	tempsensor_clkedge(&s->tempsensor, !!(value & 2),
	223	!!(value & 16));
	224	s->regs[addr] = value;
	225	break;
	226
10c144e2 EI	227	default:
	228	s->regs[addr] = value;
	229	break;
	230	}
	231	}
	232
838335ec AK	233	static const MemoryRegionOps gpio_ops = {
	234	.read = gpio_read,
	235	.write = gpio_write,
	236	.endianness = DEVICE_NATIVE_ENDIAN,
	237	.valid = {
	238	.min_access_size = 4,
	239	.max_access_size = 4,
	240	},
10c144e2 EI	241	};
	242
	243	#define INTMEM_SIZE (128 * 1024)
	244
77d4f95e	245	static struct cris_load_info li;
409dbce5	246
10c144e2	247	static
3ef96221	248	void axisdev88_init(MachineState *machine)
10c144e2	249	{
3ef96221 MA	250	ram_addr_t ram_size = machine->ram_size;
	251	const char *cpu_model = machine->cpu_model;
	252	const char *kernel_filename = machine->kernel_filename;
	253	const char *kernel_cmdline = machine->kernel_cmdline;
ddeb9ae5	254	CRISCPU *cpu;
fc9bb176	255	CPUCRISState *env;
fd6dc90b EI	256	DeviceState *dev;
fd6dc90b EI	257	SysBusDevice *s;
522f253c	258	DriveInfo *nand;
4a6da670	259	qemu_irq irq[30], nmi[2];
10c144e2	260	void *etraxfs_dmac;
1da005b3	261	struct etraxfs_dma_client *dma_eth;
10c144e2	262	int i;
b0e3d5ac AK	263	MemoryRegion *address_space_mem = get_system_memory();
	264	MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
	265	MemoryRegion *phys_intmem = g_new(MemoryRegion, 1);
10c144e2 EI	266
	267	/* init CPUs */
	268	if (cpu_model == NULL) {
	269	cpu_model = "crisv32";
	270	}
ddeb9ae5 AF	271	cpu = cpu_cris_init(cpu_model);
ddeb9ae5 AF	272	env = &cpu->env;
10c144e2 EI	273
10c144e2 EI	274	/* allocate RAM */
c0c85841 DM	275	memory_region_allocate_system_memory(phys_ram, NULL, "axisdev88.ram",
c0c85841 DM	276	ram_size);
b0e3d5ac	277	memory_region_add_subregion(address_space_mem, 0x40000000, phys_ram);
10c144e2 EI	278
	279	/* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
	280	internal memory. */
49946538	281	memory_region_init_ram(phys_intmem, NULL, "axisdev88.chipram", INTMEM_SIZE,
f8ed85ac	282	&error_fatal);
c5705a77	283	vmstate_register_ram_global(phys_intmem);
b0e3d5ac	284	memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem);
10c144e2 EI	285
10c144e2 EI	286	/* Attach a NAND flash to CS1. */
522f253c	287	nand = drive_get(IF_MTD, 0, 0);
4be74634	288	nand_state.nand = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL,
522f253c	289	NAND_MFR_STMICRO, 0x39);
2c9b15ca	290	memory_region_init_io(&nand_state.iomem, NULL, &nand_ops, &nand_state,
838335ec AK	291	"nand", 0x05000000);
	292	memory_region_add_subregion(address_space_mem, 0x10000000,
	293	&nand_state.iomem);
10c144e2 EI	294
10c144e2 EI	295	gpio_state.nand = &nand_state;
2c9b15ca	296	memory_region_init_io(&gpio_state.iomem, NULL, &gpio_ops, &gpio_state,
838335ec AK	297	"gpio", 0x5c);
	298	memory_region_add_subregion(address_space_mem, 0x3001a000,
	299	&gpio_state.iomem);
10c144e2 EI	300
10c144e2 EI	301
fd6dc90b EI	302	dev = qdev_create(NULL, "etraxfs,pic");
fd6dc90b EI	303	/* FIXME: Is there a proper way to signal vectors to the CPU core? */
ee6847d1	304	qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
e23a1b33	305	qdev_init_nofail(dev);
1356b98d	306	s = SYS_BUS_DEVICE(dev);
fd6dc90b	307	sysbus_mmio_map(s, 0, 0x3001c000);
4a6da670 EI	308	sysbus_connect_irq(s, 0, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_IRQ));
4a6da670 EI	309	sysbus_connect_irq(s, 1, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_NMI));
fd6dc90b	310	for (i = 0; i < 30; i++) {
067a3ddc	311	irq[i] = qdev_get_gpio_in(dev, i);
fd6dc90b	312	}
067a3ddc PB	313	nmi[0] = qdev_get_gpio_in(dev, 30);
067a3ddc PB	314	nmi[1] = qdev_get_gpio_in(dev, 31);
73cfd29f	315
ba494313	316	etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10);
10c144e2 EI	317	for (i = 0; i < 10; i++) {
10c144e2 EI	318	/* On ETRAX, odd numbered channels are inputs. */
73cfd29f	319	etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1);
10c144e2 EI	320	}
	321
	322	/* Add the two ethernet blocks. */
7267c094	323	dma_eth = g_malloc0(sizeof dma_eth[0] * 4); /* Allocate 4 channels. */
1da005b3 EI	324	etraxfs_eth_init(&nd_table[0], 0x30034000, 1, &dma_eth[0], &dma_eth[1]);
	325	if (nb_nics > 1) {
	326	etraxfs_eth_init(&nd_table[1], 0x30036000, 2, &dma_eth[2], &dma_eth[3]);
	327	}
10c144e2 EI	328
10c144e2 EI	329	/* The DMA Connector block is missing, hardwire things for now. */
1da005b3 EI	330	etraxfs_dmac_connect_client(etraxfs_dmac, 0, &dma_eth[0]);
	331	etraxfs_dmac_connect_client(etraxfs_dmac, 1, &dma_eth[1]);
	332	if (nb_nics > 1) {
	333	etraxfs_dmac_connect_client(etraxfs_dmac, 6, &dma_eth[2]);
	334	etraxfs_dmac_connect_client(etraxfs_dmac, 7, &dma_eth[3]);
10c144e2 EI	335	}
	336
	337	/* 2 timers. */
3b1fd90e EI	338	sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL);
3b1fd90e EI	339	sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL);
10c144e2 EI	340
10c144e2 EI	341	for (i = 0; i < 4; i++) {
4b816985	342	sysbus_create_simple("etraxfs,serial", 0x30026000 + i * 0x2000,
3b1fd90e	343	irq[0x14 + i]);
10c144e2 EI	344	}
10c144e2 EI	345
5efe843a AF	346	if (kernel_filename) {
	347	li.image_filename = kernel_filename;
	348	li.cmdline = kernel_cmdline;
	349	cris_load_image(cpu, &li);
	350	} else if (!qtest_enabled()) {
77d4f95e EI	351	fprintf(stderr, "Kernel image must be specified\n");
77d4f95e EI	352	exit(1);
10c144e2	353	}
10c144e2 EI	354	}
10c144e2 EI	355
e264d29d	356	static void axisdev88_machine_init(MachineClass *mc)
f80f9ec9	357	{
e264d29d EH	358	mc->desc = "AXIS devboard 88";
	359	mc->init = axisdev88_init;
	360	mc->is_default = 1;
f80f9ec9 AL	361	}
f80f9ec9 AL	362
e264d29d	363	DEFINE_MACHINE("axis-dev88", axisdev88_machine_init)