[mirror_qemu.git] / hw / cuda.c

/*
 * QEMU CUDA support
 *
 * Copyright (c) 2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

/* XXX: implement all timer modes */

//#define DEBUG_CUDA
//#define DEBUG_CUDA_PACKET

/* Bits in B data register: all active low */
#define TREQ		0x08		/* Transfer request (input) */
#define TACK		0x10		/* Transfer acknowledge (output) */
#define TIP		0x20		/* Transfer in progress (output) */

/* Bits in ACR */
#define SR_CTRL		0x1c		/* Shift register control bits */
#define SR_EXT		0x0c		/* Shift on external clock */
#define SR_OUT		0x10		/* Shift out if 1 */

/* Bits in IFR and IER */
#define IER_SET		0x80		/* set bits in IER */
#define IER_CLR		0		/* clear bits in IER */
#define SR_INT		0x04		/* Shift register full/empty */
#define T1_INT          0x40            /* Timer 1 interrupt */
#define T2_INT          0x20            /* Timer 2 interrupt */

/* Bits in ACR */
#define T1MODE          0xc0            /* Timer 1 mode */
#define T1MODE_CONT     0x40            /*  continuous interrupts */

/* commands (1st byte) */
#define ADB_PACKET	0
#define CUDA_PACKET	1
#define ERROR_PACKET	2
#define TIMER_PACKET	3
#define POWER_PACKET	4
#define MACIIC_PACKET	5
#define PMU_PACKET	6


/* CUDA commands (2nd byte) */
#define CUDA_WARM_START			0x0
#define CUDA_AUTOPOLL			0x1
#define CUDA_GET_6805_ADDR		0x2
#define CUDA_GET_TIME			0x3
#define CUDA_GET_PRAM			0x7
#define CUDA_SET_6805_ADDR		0x8
#define CUDA_SET_TIME			0x9
#define CUDA_POWERDOWN			0xa
#define CUDA_POWERUP_TIME		0xb
#define CUDA_SET_PRAM			0xc
#define CUDA_MS_RESET			0xd
#define CUDA_SEND_DFAC			0xe
#define CUDA_BATTERY_SWAP_SENSE		0x10
#define CUDA_RESET_SYSTEM		0x11
#define CUDA_SET_IPL			0x12
#define CUDA_FILE_SERVER_FLAG		0x13
#define CUDA_SET_AUTO_RATE		0x14
#define CUDA_GET_AUTO_RATE		0x16
#define CUDA_SET_DEVICE_LIST		0x19
#define CUDA_GET_DEVICE_LIST		0x1a
#define CUDA_SET_ONE_SECOND_MODE	0x1b
#define CUDA_SET_POWER_MESSAGES		0x21
#define CUDA_GET_SET_IIC		0x22
#define CUDA_WAKEUP			0x23
#define CUDA_TIMER_TICKLE		0x24
#define CUDA_COMBINED_FORMAT_IIC	0x25

#define CUDA_TIMER_FREQ (4700000 / 6)
#define CUDA_ADB_POLL_FREQ 50

/* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
#define RTC_OFFSET                      2082844800

typedef struct CUDATimer {
    int index;
    uint16_t latch;
    uint16_t counter_value; /* counter value at load time */
    int64_t load_time;
    int64_t next_irq_time;
    QEMUTimer *timer;
} CUDATimer;

typedef struct CUDAState {
    /* cuda registers */
    uint8_t b;      /* B-side data */
    uint8_t a;      /* A-side data */
    uint8_t dirb;   /* B-side direction (1=output) */
    uint8_t dira;   /* A-side direction (1=output) */
    uint8_t sr;     /* Shift register */
    uint8_t acr;    /* Auxiliary control register */
    uint8_t pcr;    /* Peripheral control register */
    uint8_t ifr;    /* Interrupt flag register */
    uint8_t ier;    /* Interrupt enable register */
    uint8_t anh;    /* A-side data, no handshake */

    CUDATimer timers[2];
   
    uint8_t last_b; /* last value of B register */
    uint8_t last_acr; /* last value of B register */
   
    int data_in_size;
    int data_in_index;
    int data_out_index;

    qemu_irq irq;
    uint8_t autopoll;
    uint8_t data_in[128];
    uint8_t data_out[16];
    QEMUTimer *adb_poll_timer;
} CUDAState;

static CUDAState cuda_state;
ADBBusState adb_bus;

static void cuda_update(CUDAState *s);
static void cuda_receive_packet_from_host(CUDAState *s,
                                          const uint8_t *data, int len);
static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
                              int64_t current_time);

static void cuda_update_irq(CUDAState *s)
{
    if (s->ifr & s->ier & (SR_INT | T1_INT)) {
        qemu_irq_raise(s->irq);
    } else {
        qemu_irq_lower(s->irq);
    }
}

static unsigned int get_counter(CUDATimer *s)
{
    int64_t d;
    unsigned int counter;

    d = muldiv64(qemu_get_clock(vm_clock) - s->load_time,
                 CUDA_TIMER_FREQ, ticks_per_sec);
    if (s->index == 0) {
        /* the timer goes down from latch to -1 (period of latch + 2) */
        if (d <= (s->counter_value + 1)) {
            counter = (s->counter_value - d) & 0xffff;
        } else {
            counter = (d - (s->counter_value + 1)) % (s->latch + 2);
            counter = (s->latch - counter) & 0xffff;
        }
    } else {
        counter = (s->counter_value - d) & 0xffff;
    }
    return counter;
}

static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val)
{
#ifdef DEBUG_CUDA
    printf("cuda: T%d.counter=%d\n",
           1 + (ti->timer == NULL), val);
#endif
    ti->load_time = qemu_get_clock(vm_clock);
    ti->counter_value = val;
    cuda_timer_update(s, ti, ti->load_time);
}

static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
{
    int64_t d, next_time;
    unsigned int counter;

    /* current counter value */
    d = muldiv64(current_time - s->load_time,
                 CUDA_TIMER_FREQ, ticks_per_sec);
    /* the timer goes down from latch to -1 (period of latch + 2) */
    if (d <= (s->counter_value + 1)) {
        counter = (s->counter_value - d) & 0xffff;
    } else {
        counter = (d - (s->counter_value + 1)) % (s->latch + 2);
        counter = (s->latch - counter) & 0xffff;
    }
   
    /* Note: we consider the irq is raised on 0 */
    if (counter == 0xffff) {
        next_time = d + s->latch + 1;
    } else if (counter == 0) {
        next_time = d + s->latch + 2;
    } else {
        next_time = d + counter;
    }
#if 0
#ifdef DEBUG_CUDA
    printf("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n",
           s->latch, d, next_time - d);
#endif
#endif
    next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) +
        s->load_time;
    if (next_time <= current_time)
        next_time = current_time + 1;
    return next_time;
}

static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
                              int64_t current_time)
{
    if (!ti->timer)
        return;
    if ((s->acr & T1MODE) != T1MODE_CONT) {
        qemu_del_timer(ti->timer);
    } else {
        ti->next_irq_time = get_next_irq_time(ti, current_time);
        qemu_mod_timer(ti->timer, ti->next_irq_time);
    }
}

static void cuda_timer1(void *opaque)
{
    CUDAState *s = opaque;
    CUDATimer *ti = &s->timers[0];

    cuda_timer_update(s, ti, ti->next_irq_time);
    s->ifr |= T1_INT;
    cuda_update_irq(s);
}

static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
{
    CUDAState *s = opaque;
    uint32_t val;

    addr = (addr >> 9) & 0xf;
    switch(addr) {
    case 0:
        val = s->b;
        break;
    case 1:
        val = s->a;
        break;
    case 2:
        val = s->dirb;
        break;
    case 3:
        val = s->dira;
        break;
    case 4:
        val = get_counter(&s->timers[0]) & 0xff;
        s->ifr &= ~T1_INT;
        cuda_update_irq(s);
        break;
    case 5:
        val = get_counter(&s->timers[0]) >> 8;
        cuda_update_irq(s);
        break;
    case 6:
        val = s->timers[0].latch & 0xff;
        break;
    case 7:
        /* XXX: check this */
        val = (s->timers[0].latch >> 8) & 0xff;
        break;
    case 8:
        val = get_counter(&s->timers[1]) & 0xff;
        s->ifr &= ~T2_INT;
        break;
    case 9:
        val = get_counter(&s->timers[1]) >> 8;
        break;
    case 10:
        val = s->sr;
        s->ifr &= ~SR_INT;
        cuda_update_irq(s);
        break;
    case 11:
        val = s->acr;
        break;
    case 12:
        val = s->pcr;
        break;
    case 13:
        val = s->ifr;
        if (s->ifr & s->ier)
            val |= 0x80;
        break;
    case 14:
        val = s->ier | 0x80;
        break;
    default:
    case 15:
        val = s->anh;
        break;
    }
#ifdef DEBUG_CUDA
    if (addr != 13 || val != 0)
        printf("cuda: read: reg=0x%x val=%02x\n", addr, val);
#endif
    return val;
}

static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    CUDAState *s = opaque;
   
    addr = (addr >> 9) & 0xf;
#ifdef DEBUG_CUDA
    printf("cuda: write: reg=0x%x val=%02x\n", addr, val);
#endif

    switch(addr) {
    case 0:
        s->b = val;
        cuda_update(s);
        break;
    case 1:
        s->a = val;
        break;
    case 2:
        s->dirb = val;
        break;
    case 3:
        s->dira = val;
        break;
    case 4:
        s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
        cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
        break;
    case 5:
        s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
        s->ifr &= ~T1_INT;
        set_counter(s, &s->timers[0], s->timers[0].latch);
        break;
    case 6:
        s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
        cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
        break;
    case 7:
        s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
        s->ifr &= ~T1_INT;
        cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
        break;
    case 8:
        s->timers[1].latch = val;
        set_counter(s, &s->timers[1], val);
        break;
    case 9:
        set_counter(s, &s->timers[1], (val << 8) | s->timers[1].latch);
        break;
    case 10:
        s->sr = val;
        break;
    case 11:
        s->acr = val;
        cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
        cuda_update(s);
        break;
    case 12:
        s->pcr = val;
        break;
    case 13:
        /* reset bits */
        s->ifr &= ~val;
        cuda_update_irq(s);
        break;
    case 14:
        if (val & IER_SET) {
            /* set bits */
            s->ier |= val & 0x7f;
        } else {
            /* reset bits */
            s->ier &= ~val;
        }
        cuda_update_irq(s);
        break;
    default:
    case 15:
        s->anh = val;
        break;
    }
}

/* NOTE: TIP and TREQ are negated */
static void cuda_update(CUDAState *s)
{
    int packet_received, len;

    packet_received = 0;
    if (!(s->b & TIP)) {
        /* transfer requested from host */

        if (s->acr & SR_OUT) {
            /* data output */
            if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
                if (s->data_out_index < sizeof(s->data_out)) {
#ifdef DEBUG_CUDA
                    printf("cuda: send: %02x\n", s->sr);
#endif
                    s->data_out[s->data_out_index++] = s->sr;
                    s->ifr |= SR_INT;
                    cuda_update_irq(s);
                }
            }
        } else {
            if (s->data_in_index < s->data_in_size) {
                /* data input */
                if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
                    s->sr = s->data_in[s->data_in_index++];
#ifdef DEBUG_CUDA
                    printf("cuda: recv: %02x\n", s->sr);
#endif
                    /* indicate end of transfer */
                    if (s->data_in_index >= s->data_in_size) {
                        s->b = (s->b | TREQ);
                    }
                    s->ifr |= SR_INT;
                    cuda_update_irq(s);
                }
            }
        }
    } else {
        /* no transfer requested: handle sync case */
        if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) {
            /* update TREQ state each time TACK change state */
            if (s->b & TACK)
                s->b = (s->b | TREQ);
            else
                s->b = (s->b & ~TREQ);
            s->ifr |= SR_INT;
            cuda_update_irq(s);
        } else {
            if (!(s->last_b & TIP)) {
                /* handle end of host to cuda transfer */
                packet_received = (s->data_out_index > 0);
                /* always an IRQ at the end of transfer */
                s->ifr |= SR_INT;
                cuda_update_irq(s);
            }
            /* signal if there is data to read */
            if (s->data_in_index < s->data_in_size) {
                s->b = (s->b & ~TREQ);
            }
        }
    }

    s->last_acr = s->acr;
    s->last_b = s->b;

    /* NOTE: cuda_receive_packet_from_host() can call cuda_update()
       recursively */
    if (packet_received) {
        len = s->data_out_index;
        s->data_out_index = 0;
        cuda_receive_packet_from_host(s, s->data_out, len);
    }
}

static void cuda_send_packet_to_host(CUDAState *s,
                                     const uint8_t *data, int len)
{
#ifdef DEBUG_CUDA_PACKET
    {
        int i;
        printf("cuda_send_packet_to_host:\n");
        for(i = 0; i < len; i++)
            printf(" %02x", data[i]);
        printf("\n");
    }
#endif
    memcpy(s->data_in, data, len);
    s->data_in_size = len;
    s->data_in_index = 0;
    cuda_update(s);
    s->ifr |= SR_INT;
    cuda_update_irq(s);
}

static void cuda_adb_poll(void *opaque)
{
    CUDAState *s = opaque;
    uint8_t obuf[ADB_MAX_OUT_LEN + 2];
    int olen;

    olen = adb_poll(&adb_bus, obuf + 2);
    if (olen > 0) {
        obuf[0] = ADB_PACKET;
        obuf[1] = 0x40; /* polled data */
        cuda_send_packet_to_host(s, obuf, olen + 2);
    }
    qemu_mod_timer(s->adb_poll_timer,
                   qemu_get_clock(vm_clock) +
                   (ticks_per_sec / CUDA_ADB_POLL_FREQ));
}

static void cuda_receive_packet(CUDAState *s,
                                const uint8_t *data, int len)
{
    uint8_t obuf[16];
    int ti, autopoll;

    switch(data[0]) {
    case CUDA_AUTOPOLL:
        autopoll = (data[1] != 0);
        if (autopoll != s->autopoll) {
            s->autopoll = autopoll;
            if (autopoll) {
                qemu_mod_timer(s->adb_poll_timer,
                               qemu_get_clock(vm_clock) +
                               (ticks_per_sec / CUDA_ADB_POLL_FREQ));
            } else {
                qemu_del_timer(s->adb_poll_timer);
            }
        }
        obuf[0] = CUDA_PACKET;
        obuf[1] = data[1];
        cuda_send_packet_to_host(s, obuf, 2);
        break;
    case CUDA_GET_TIME:
    case CUDA_SET_TIME:
        /* XXX: add time support ? */
        ti = time(NULL) + RTC_OFFSET;
        obuf[0] = CUDA_PACKET;
        obuf[1] = 0;
        obuf[2] = 0;
        obuf[3] = ti >> 24;
        obuf[4] = ti >> 16;
        obuf[5] = ti >> 8;
        obuf[6] = ti;
        cuda_send_packet_to_host(s, obuf, 7);
        break;
    case CUDA_FILE_SERVER_FLAG:
    case CUDA_SET_DEVICE_LIST:
    case CUDA_SET_AUTO_RATE:
    case CUDA_SET_POWER_MESSAGES:
        obuf[0] = CUDA_PACKET;
        obuf[1] = 0;
        cuda_send_packet_to_host(s, obuf, 2);
        break;
    case CUDA_POWERDOWN:
        obuf[0] = CUDA_PACKET;
        obuf[1] = 0;
        cuda_send_packet_to_host(s, obuf, 2);
	qemu_system_shutdown_request();
	break;
    default:
        break;
    }
}

static void cuda_receive_packet_from_host(CUDAState *s,
                                          const uint8_t *data, int len)
{
#ifdef DEBUG_CUDA_PACKET
    {
        int i;
        printf("cuda_receive_packet_from_host:\n");
        for(i = 0; i < len; i++)
            printf(" %02x", data[i]);
        printf("\n");
    }
#endif
    switch(data[0]) {
    case ADB_PACKET:
        {
            uint8_t obuf[ADB_MAX_OUT_LEN + 2];
            int olen;
            olen = adb_request(&adb_bus, obuf + 2, data + 1, len - 1);
            if (olen > 0) {
                obuf[0] = ADB_PACKET;
                obuf[1] = 0x00;
            } else {
                /* error */
                obuf[0] = ADB_PACKET;
                obuf[1] = -olen;
                olen = 0;
            }
            cuda_send_packet_to_host(s, obuf, olen + 2);
        }
        break;
    case CUDA_PACKET:
        cuda_receive_packet(s, data + 1, len - 1);
        break;
    }
}

static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
{
}

static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
}

static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr)
{
    return 0;
}

static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr)
{
    return 0;
}

static CPUWriteMemoryFunc *cuda_write[] = {
    &cuda_writeb,
    &cuda_writew,
    &cuda_writel,
};

static CPUReadMemoryFunc *cuda_read[] = {
    &cuda_readb,
    &cuda_readw,
    &cuda_readl,
};

int cuda_init(qemu_irq irq)
{
    CUDAState *s = &cuda_state;
    int cuda_mem_index;

    s->irq = irq;

    s->timers[0].index = 0;
    s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s);
    s->timers[0].latch = 0xffff;
    set_counter(s, &s->timers[0], 0xffff);

    s->timers[1].index = 1;
    s->timers[1].latch = 0;
    //    s->ier = T1_INT | SR_INT;
    s->ier = 0;
    set_counter(s, &s->timers[1], 0xffff);

    s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s);
    cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s);
    return cuda_mem_index;
}
Commit	Line	Data
267002cd FB	1	/*
267002cd FB	2	* QEMU CUDA support
5fafdf24	3	*
267002cd	4	* Copyright (c) 2004 Fabrice Bellard
5fafdf24	5	*
267002cd FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include "vl.h"
	25
61271e5c FB	26	/* XXX: implement all timer modes */
61271e5c FB	27
819e712b FB	28	//#define DEBUG_CUDA
	29	//#define DEBUG_CUDA_PACKET
	30
267002cd FB	31	/* Bits in B data register: all active low */
	32	#define TREQ 0x08 /* Transfer request (input) */
	33	#define TACK 0x10 /* Transfer acknowledge (output) */
	34	#define TIP 0x20 /* Transfer in progress (output) */
	35
	36	/* Bits in ACR */
	37	#define SR_CTRL 0x1c /* Shift register control bits */
	38	#define SR_EXT 0x0c /* Shift on external clock */
	39	#define SR_OUT 0x10 /* Shift out if 1 */
	40
	41	/* Bits in IFR and IER */
	42	#define IER_SET 0x80 /* set bits in IER */
	43	#define IER_CLR 0 /* clear bits in IER */
	44	#define SR_INT 0x04 /* Shift register full/empty */
	45	#define T1_INT 0x40 /* Timer 1 interrupt */
61271e5c	46	#define T2_INT 0x20 /* Timer 2 interrupt */
267002cd FB	47
	48	/* Bits in ACR */
	49	#define T1MODE 0xc0 /* Timer 1 mode */
	50	#define T1MODE_CONT 0x40 /* continuous interrupts */
	51
	52	/* commands (1st byte) */
	53	#define ADB_PACKET 0
	54	#define CUDA_PACKET 1
	55	#define ERROR_PACKET 2
	56	#define TIMER_PACKET 3
	57	#define POWER_PACKET 4
	58	#define MACIIC_PACKET 5
	59	#define PMU_PACKET 6
	60
	61
	62	/* CUDA commands (2nd byte) */
	63	#define CUDA_WARM_START 0x0
	64	#define CUDA_AUTOPOLL 0x1
	65	#define CUDA_GET_6805_ADDR 0x2
	66	#define CUDA_GET_TIME 0x3
	67	#define CUDA_GET_PRAM 0x7
	68	#define CUDA_SET_6805_ADDR 0x8
	69	#define CUDA_SET_TIME 0x9
	70	#define CUDA_POWERDOWN 0xa
	71	#define CUDA_POWERUP_TIME 0xb
	72	#define CUDA_SET_PRAM 0xc
	73	#define CUDA_MS_RESET 0xd
	74	#define CUDA_SEND_DFAC 0xe
	75	#define CUDA_BATTERY_SWAP_SENSE 0x10
	76	#define CUDA_RESET_SYSTEM 0x11
	77	#define CUDA_SET_IPL 0x12
	78	#define CUDA_FILE_SERVER_FLAG 0x13
	79	#define CUDA_SET_AUTO_RATE 0x14
	80	#define CUDA_GET_AUTO_RATE 0x16
	81	#define CUDA_SET_DEVICE_LIST 0x19
	82	#define CUDA_GET_DEVICE_LIST 0x1a
	83	#define CUDA_SET_ONE_SECOND_MODE 0x1b
	84	#define CUDA_SET_POWER_MESSAGES 0x21
	85	#define CUDA_GET_SET_IIC 0x22
	86	#define CUDA_WAKEUP 0x23
	87	#define CUDA_TIMER_TICKLE 0x24
	88	#define CUDA_COMBINED_FORMAT_IIC 0x25
	89
	90	#define CUDA_TIMER_FREQ (4700000 / 6)
e2733d20	91	#define CUDA_ADB_POLL_FREQ 50
267002cd	92
d7ce296f FB	93	/* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
	94	#define RTC_OFFSET 2082844800
	95
267002cd	96	typedef struct CUDATimer {
5fafdf24	97	int index;
61271e5c	98	uint16_t latch;
267002cd FB	99	uint16_t counter_value; /* counter value at load time */
	100	int64_t load_time;
	101	int64_t next_irq_time;
	102	QEMUTimer *timer;
	103	} CUDATimer;
	104
	105	typedef struct CUDAState {
	106	/* cuda registers */
	107	uint8_t b; /* B-side data */
	108	uint8_t a; /* A-side data */
	109	uint8_t dirb; /* B-side direction (1=output) */
	110	uint8_t dira; /* A-side direction (1=output) */
	111	uint8_t sr; /* Shift register */
	112	uint8_t acr; /* Auxiliary control register */
	113	uint8_t pcr; /* Peripheral control register */
	114	uint8_t ifr; /* Interrupt flag register */
	115	uint8_t ier; /* Interrupt enable register */
	116	uint8_t anh; /* A-side data, no handshake */
	117
	118	CUDATimer timers[2];
5fafdf24	119
267002cd FB	120	uint8_t last_b; /* last value of B register */
267002cd FB	121	uint8_t last_acr; /* last value of B register */
5fafdf24	122
267002cd FB	123	int data_in_size;
	124	int data_in_index;
	125	int data_out_index;
	126
d537cf6c	127	qemu_irq irq;
267002cd FB	128	uint8_t autopoll;
	129	uint8_t data_in[128];
	130	uint8_t data_out[16];
e2733d20	131	QEMUTimer *adb_poll_timer;
267002cd FB	132	} CUDAState;
	133
	134	static CUDAState cuda_state;
	135	ADBBusState adb_bus;
	136
	137	static void cuda_update(CUDAState *s);
5fafdf24	138	static void cuda_receive_packet_from_host(CUDAState *s,
267002cd	139	const uint8_t *data, int len);
5fafdf24	140	static void cuda_timer_update(CUDAState s, CUDATimer ti,
819e712b	141	int64_t current_time);
267002cd FB	142
	143	static void cuda_update_irq(CUDAState *s)
	144	{
819e712b	145	if (s->ifr & s->ier & (SR_INT \| T1_INT)) {
d537cf6c	146	qemu_irq_raise(s->irq);
267002cd	147	} else {
d537cf6c	148	qemu_irq_lower(s->irq);
267002cd FB	149	}
	150	}
	151
	152	static unsigned int get_counter(CUDATimer *s)
	153	{
	154	int64_t d;
	155	unsigned int counter;
	156
5fafdf24	157	d = muldiv64(qemu_get_clock(vm_clock) - s->load_time,
267002cd	158	CUDA_TIMER_FREQ, ticks_per_sec);
61271e5c FB	159	if (s->index == 0) {
	160	/* the timer goes down from latch to -1 (period of latch + 2) */
	161	if (d <= (s->counter_value + 1)) {
	162	counter = (s->counter_value - d) & 0xffff;
	163	} else {
	164	counter = (d - (s->counter_value + 1)) % (s->latch + 2);
5fafdf24	165	counter = (s->latch - counter) & 0xffff;
61271e5c	166	}
267002cd	167	} else {
61271e5c	168	counter = (s->counter_value - d) & 0xffff;
267002cd FB	169	}
	170	return counter;
	171	}
	172
819e712b	173	static void set_counter(CUDAState s, CUDATimer ti, unsigned int val)
267002cd	174	{
819e712b FB	175	#ifdef DEBUG_CUDA
	176	printf("cuda: T%d.counter=%d\n",
	177	1 + (ti->timer == NULL), val);
	178	#endif
	179	ti->load_time = qemu_get_clock(vm_clock);
	180	ti->counter_value = val;
	181	cuda_timer_update(s, ti, ti->load_time);
267002cd FB	182	}
	183
	184	static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
	185	{
61271e5c FB	186	int64_t d, next_time;
	187	unsigned int counter;
	188
267002cd	189	/* current counter value */
5fafdf24	190	d = muldiv64(current_time - s->load_time,
267002cd	191	CUDA_TIMER_FREQ, ticks_per_sec);
61271e5c FB	192	/* the timer goes down from latch to -1 (period of latch + 2) */
	193	if (d <= (s->counter_value + 1)) {
	194	counter = (s->counter_value - d) & 0xffff;
	195	} else {
	196	counter = (d - (s->counter_value + 1)) % (s->latch + 2);
5fafdf24	197	counter = (s->latch - counter) & 0xffff;
61271e5c	198	}
5fafdf24	199
61271e5c FB	200	/* Note: we consider the irq is raised on 0 */
	201	if (counter == 0xffff) {
	202	next_time = d + s->latch + 1;
	203	} else if (counter == 0) {
	204	next_time = d + s->latch + 2;
	205	} else {
	206	next_time = d + counter;
267002cd	207	}
dccfafc4	208	#if 0
819e712b	209	#ifdef DEBUG_CUDA
5fafdf24	210	printf("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n",
819e712b	211	s->latch, d, next_time - d);
dccfafc4	212	#endif
819e712b	213	#endif
5fafdf24	214	next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) +
267002cd FB	215	s->load_time;
	216	if (next_time <= current_time)
	217	next_time = current_time + 1;
	218	return next_time;
	219	}
	220
5fafdf24	221	static void cuda_timer_update(CUDAState s, CUDATimer ti,
819e712b FB	222	int64_t current_time)
	223	{
	224	if (!ti->timer)
	225	return;
	226	if ((s->acr & T1MODE) != T1MODE_CONT) {
	227	qemu_del_timer(ti->timer);
	228	} else {
	229	ti->next_irq_time = get_next_irq_time(ti, current_time);
	230	qemu_mod_timer(ti->timer, ti->next_irq_time);
	231	}
	232	}
	233
267002cd FB	234	static void cuda_timer1(void *opaque)
	235	{
	236	CUDAState *s = opaque;
	237	CUDATimer *ti = &s->timers[0];
	238
819e712b	239	cuda_timer_update(s, ti, ti->next_irq_time);
267002cd FB	240	s->ifr \|= T1_INT;
	241	cuda_update_irq(s);
	242	}
	243
	244	static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
	245	{
	246	CUDAState *s = opaque;
	247	uint32_t val;
	248
	249	addr = (addr >> 9) & 0xf;
	250	switch(addr) {
	251	case 0:
	252	val = s->b;
	253	break;
	254	case 1:
	255	val = s->a;
	256	break;
	257	case 2:
	258	val = s->dirb;
	259	break;
	260	case 3:
	261	val = s->dira;
	262	break;
	263	case 4:
	264	val = get_counter(&s->timers[0]) & 0xff;
	265	s->ifr &= ~T1_INT;
	266	cuda_update_irq(s);
	267	break;
	268	case 5:
	269	val = get_counter(&s->timers[0]) >> 8;
267002cd FB	270	cuda_update_irq(s);
	271	break;
	272	case 6:
	273	val = s->timers[0].latch & 0xff;
	274	break;
	275	case 7:
61271e5c	276	/* XXX: check this */
267002cd FB	277	val = (s->timers[0].latch >> 8) & 0xff;
	278	break;
	279	case 8:
	280	val = get_counter(&s->timers[1]) & 0xff;
61271e5c	281	s->ifr &= ~T2_INT;
267002cd FB	282	break;
	283	case 9:
	284	val = get_counter(&s->timers[1]) >> 8;
	285	break;
	286	case 10:
819e712b FB	287	val = s->sr;
	288	s->ifr &= ~SR_INT;
	289	cuda_update_irq(s);
267002cd FB	290	break;
	291	case 11:
	292	val = s->acr;
	293	break;
	294	case 12:
	295	val = s->pcr;
	296	break;
	297	case 13:
	298	val = s->ifr;
5fafdf24	299	if (s->ifr & s->ier)
b7c7b181	300	val \|= 0x80;
267002cd FB	301	break;
267002cd FB	302	case 14:
b7c7b181	303	val = s->ier \| 0x80;
267002cd FB	304	break;
	305	default:
	306	case 15:
	307	val = s->anh;
	308	break;
	309	}
	310	#ifdef DEBUG_CUDA
819e712b FB	311	if (addr != 13 \|\| val != 0)
819e712b FB	312	printf("cuda: read: reg=0x%x val=%02x\n", addr, val);
267002cd FB	313	#endif
	314	return val;
	315	}
	316
	317	static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
	318	{
	319	CUDAState *s = opaque;
5fafdf24	320
267002cd FB	321	addr = (addr >> 9) & 0xf;
	322	#ifdef DEBUG_CUDA
	323	printf("cuda: write: reg=0x%x val=%02x\n", addr, val);
	324	#endif
	325
	326	switch(addr) {
	327	case 0:
	328	s->b = val;
	329	cuda_update(s);
	330	break;
	331	case 1:
	332	s->a = val;
	333	break;
	334	case 2:
	335	s->dirb = val;
	336	break;
	337	case 3:
	338	s->dira = val;
	339	break;
	340	case 4:
61271e5c FB	341	s->timers[0].latch = (s->timers[0].latch & 0xff00) \| val;
61271e5c FB	342	cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
267002cd FB	343	break;
267002cd FB	344	case 5:
61271e5c FB	345	s->timers[0].latch = (s->timers[0].latch & 0xff) \| (val << 8);
	346	s->ifr &= ~T1_INT;
	347	set_counter(s, &s->timers[0], s->timers[0].latch);
267002cd FB	348	break;
	349	case 6:
	350	s->timers[0].latch = (s->timers[0].latch & 0xff00) \| val;
819e712b	351	cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
267002cd FB	352	break;
	353	case 7:
	354	s->timers[0].latch = (s->timers[0].latch & 0xff) \| (val << 8);
61271e5c	355	s->ifr &= ~T1_INT;
819e712b	356	cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
267002cd FB	357	break;
267002cd FB	358	case 8:
61271e5c	359	s->timers[1].latch = val;
819e712b	360	set_counter(s, &s->timers[1], val);
267002cd FB	361	break;
267002cd FB	362	case 9:
61271e5c	363	set_counter(s, &s->timers[1], (val << 8) \| s->timers[1].latch);
267002cd FB	364	break;
	365	case 10:
	366	s->sr = val;
	367	break;
	368	case 11:
	369	s->acr = val;
819e712b	370	cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
267002cd FB	371	cuda_update(s);
	372	break;
	373	case 12:
	374	s->pcr = val;
	375	break;
	376	case 13:
	377	/* reset bits */
	378	s->ifr &= ~val;
	379	cuda_update_irq(s);
	380	break;
	381	case 14:
	382	if (val & IER_SET) {
	383	/* set bits */
	384	s->ier \|= val & 0x7f;
	385	} else {
	386	/* reset bits */
	387	s->ier &= ~val;
	388	}
	389	cuda_update_irq(s);
	390	break;
	391	default:
	392	case 15:
	393	s->anh = val;
	394	break;
	395	}
	396	}
	397
	398	/* NOTE: TIP and TREQ are negated */
	399	static void cuda_update(CUDAState *s)
	400	{
819e712b FB	401	int packet_received, len;
	402
	403	packet_received = 0;
	404	if (!(s->b & TIP)) {
	405	/* transfer requested from host */
267002cd	406
819e712b FB	407	if (s->acr & SR_OUT) {
	408	/* data output */
	409	if ((s->b & (TACK \| TIP)) != (s->last_b & (TACK \| TIP))) {
	410	if (s->data_out_index < sizeof(s->data_out)) {
	411	#ifdef DEBUG_CUDA
	412	printf("cuda: send: %02x\n", s->sr);
	413	#endif
	414	s->data_out[s->data_out_index++] = s->sr;
	415	s->ifr \|= SR_INT;
	416	cuda_update_irq(s);
	417	}
	418	}
	419	} else {
	420	if (s->data_in_index < s->data_in_size) {
	421	/* data input */
	422	if ((s->b & (TACK \| TIP)) != (s->last_b & (TACK \| TIP))) {
	423	s->sr = s->data_in[s->data_in_index++];
	424	#ifdef DEBUG_CUDA
	425	printf("cuda: recv: %02x\n", s->sr);
	426	#endif
	427	/* indicate end of transfer */
	428	if (s->data_in_index >= s->data_in_size) {
	429	s->b = (s->b \| TREQ);
	430	}
	431	s->ifr \|= SR_INT;
	432	cuda_update_irq(s);
	433	}
267002cd	434	}
819e712b FB	435	}
	436	} else {
	437	/* no transfer requested: handle sync case */
	438	if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) {
	439	/* update TREQ state each time TACK change state */
	440	if (s->b & TACK)
	441	s->b = (s->b \| TREQ);
	442	else
	443	s->b = (s->b & ~TREQ);
267002cd FB	444	s->ifr \|= SR_INT;
267002cd FB	445	cuda_update_irq(s);
819e712b FB	446	} else {
819e712b FB	447	if (!(s->last_b & TIP)) {
e91c8a77	448	/* handle end of host to cuda transfer */
819e712b	449	packet_received = (s->data_out_index > 0);
e91c8a77	450	/* always an IRQ at the end of transfer */
819e712b FB	451	s->ifr \|= SR_INT;
	452	cuda_update_irq(s);
	453	}
	454	/* signal if there is data to read */
	455	if (s->data_in_index < s->data_in_size) {
	456	s->b = (s->b & ~TREQ);
	457	}
267002cd FB	458	}
	459	}
	460
267002cd FB	461	s->last_acr = s->acr;
267002cd FB	462	s->last_b = s->b;
819e712b FB	463
	464	/* NOTE: cuda_receive_packet_from_host() can call cuda_update()
	465	recursively */
	466	if (packet_received) {
	467	len = s->data_out_index;
	468	s->data_out_index = 0;
	469	cuda_receive_packet_from_host(s, s->data_out, len);
	470	}
267002cd FB	471	}
267002cd FB	472
5fafdf24	473	static void cuda_send_packet_to_host(CUDAState *s,
267002cd FB	474	const uint8_t *data, int len)
267002cd FB	475	{
819e712b FB	476	#ifdef DEBUG_CUDA_PACKET
	477	{
	478	int i;
	479	printf("cuda_send_packet_to_host:\n");
	480	for(i = 0; i < len; i++)
	481	printf(" %02x", data[i]);
	482	printf("\n");
	483	}
	484	#endif
267002cd FB	485	memcpy(s->data_in, data, len);
	486	s->data_in_size = len;
	487	s->data_in_index = 0;
	488	cuda_update(s);
	489	s->ifr \|= SR_INT;
	490	cuda_update_irq(s);
	491	}
	492
7db4eea6	493	static void cuda_adb_poll(void *opaque)
e2733d20 FB	494	{
	495	CUDAState *s = opaque;
	496	uint8_t obuf[ADB_MAX_OUT_LEN + 2];
	497	int olen;
	498
	499	olen = adb_poll(&adb_bus, obuf + 2);
	500	if (olen > 0) {
	501	obuf[0] = ADB_PACKET;
	502	obuf[1] = 0x40; /* polled data */
	503	cuda_send_packet_to_host(s, obuf, olen + 2);
	504	}
5fafdf24 TS	505	qemu_mod_timer(s->adb_poll_timer,
5fafdf24 TS	506	qemu_get_clock(vm_clock) +
e2733d20 FB	507	(ticks_per_sec / CUDA_ADB_POLL_FREQ));
	508	}
	509
5fafdf24	510	static void cuda_receive_packet(CUDAState *s,
267002cd FB	511	const uint8_t *data, int len)
	512	{
	513	uint8_t obuf[16];
e2733d20	514	int ti, autopoll;
267002cd FB	515
	516	switch(data[0]) {
	517	case CUDA_AUTOPOLL:
e2733d20 FB	518	autopoll = (data[1] != 0);
	519	if (autopoll != s->autopoll) {
	520	s->autopoll = autopoll;
	521	if (autopoll) {
5fafdf24 TS	522	qemu_mod_timer(s->adb_poll_timer,
5fafdf24 TS	523	qemu_get_clock(vm_clock) +
e2733d20 FB	524	(ticks_per_sec / CUDA_ADB_POLL_FREQ));
	525	} else {
	526	qemu_del_timer(s->adb_poll_timer);
	527	}
	528	}
267002cd FB	529	obuf[0] = CUDA_PACKET;
	530	obuf[1] = data[1];
	531	cuda_send_packet_to_host(s, obuf, 2);
	532	break;
	533	case CUDA_GET_TIME:
dccfafc4	534	case CUDA_SET_TIME:
267002cd	535	/* XXX: add time support ? */
d7ce296f	536	ti = time(NULL) + RTC_OFFSET;
267002cd FB	537	obuf[0] = CUDA_PACKET;
	538	obuf[1] = 0;
	539	obuf[2] = 0;
	540	obuf[3] = ti >> 24;
	541	obuf[4] = ti >> 16;
	542	obuf[5] = ti >> 8;
	543	obuf[6] = ti;
	544	cuda_send_packet_to_host(s, obuf, 7);
	545	break;
267002cd FB	546	case CUDA_FILE_SERVER_FLAG:
	547	case CUDA_SET_DEVICE_LIST:
	548	case CUDA_SET_AUTO_RATE:
	549	case CUDA_SET_POWER_MESSAGES:
	550	obuf[0] = CUDA_PACKET;
	551	obuf[1] = 0;
	552	cuda_send_packet_to_host(s, obuf, 2);
	553	break;
d7ce296f FB	554	case CUDA_POWERDOWN:
	555	obuf[0] = CUDA_PACKET;
	556	obuf[1] = 0;
	557	cuda_send_packet_to_host(s, obuf, 2);
	558	qemu_system_shutdown_request();
	559	break;
267002cd FB	560	default:
	561	break;
	562	}
	563	}
	564
5fafdf24	565	static void cuda_receive_packet_from_host(CUDAState *s,
267002cd FB	566	const uint8_t *data, int len)
267002cd FB	567	{
819e712b FB	568	#ifdef DEBUG_CUDA_PACKET
	569	{
	570	int i;
cadae95f	571	printf("cuda_receive_packet_from_host:\n");
819e712b FB	572	for(i = 0; i < len; i++)
	573	printf(" %02x", data[i]);
	574	printf("\n");
	575	}
	576	#endif
267002cd FB	577	switch(data[0]) {
267002cd FB	578	case ADB_PACKET:
e2733d20 FB	579	{
	580	uint8_t obuf[ADB_MAX_OUT_LEN + 2];
	581	int olen;
	582	olen = adb_request(&adb_bus, obuf + 2, data + 1, len - 1);
38f0b147	583	if (olen > 0) {
e2733d20 FB	584	obuf[0] = ADB_PACKET;
	585	obuf[1] = 0x00;
	586	} else {
38f0b147	587	/* error */
e2733d20	588	obuf[0] = ADB_PACKET;
38f0b147 FB	589	obuf[1] = -olen;
38f0b147 FB	590	olen = 0;
e2733d20 FB	591	}
	592	cuda_send_packet_to_host(s, obuf, olen + 2);
	593	}
267002cd FB	594	break;
	595	case CUDA_PACKET:
	596	cuda_receive_packet(s, data + 1, len - 1);
	597	break;
	598	}
	599	}
	600
	601	static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
	602	{
	603	}
	604
	605	static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
	606	{
	607	}
	608
	609	static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr)
	610	{
	611	return 0;
	612	}
	613
	614	static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr)
	615	{
	616	return 0;
	617	}
	618
	619	static CPUWriteMemoryFunc *cuda_write[] = {
	620	&cuda_writeb,
	621	&cuda_writew,
	622	&cuda_writel,
	623	};
	624
	625	static CPUReadMemoryFunc *cuda_read[] = {
	626	&cuda_readb,
	627	&cuda_readw,
	628	&cuda_readl,
	629	};
	630
d537cf6c	631	int cuda_init(qemu_irq irq)
267002cd FB	632	{
	633	CUDAState *s = &cuda_state;
	634	int cuda_mem_index;
	635
819e712b FB	636	s->irq = irq;
819e712b FB	637
61271e5c	638	s->timers[0].index = 0;
267002cd	639	s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s);
61271e5c	640	s->timers[0].latch = 0xffff;
819e712b	641	set_counter(s, &s->timers[0], 0xffff);
61271e5c FB	642
	643	s->timers[1].index = 1;
	644	s->timers[1].latch = 0;
cadae95f FB	645	// s->ier = T1_INT \| SR_INT;
cadae95f FB	646	s->ier = 0;
819e712b	647	set_counter(s, &s->timers[1], 0xffff);
e2733d20 FB	648
e2733d20 FB	649	s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s);
267002cd FB	650	cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s);
	651	return cuda_mem_index;
	652	}